A high-voltage electronic load system and an adaptive voltage-sharing control method thereof

Abstract

The application relates to a high-voltage electronic load system and an adaptive voltage-sharing control method thereof. The system part mainly comprises an FPGA control module, a DAC unit, an ADC unit, a power regulation unit and a signal conditioning unit; the FPGA control module collects an input voltage Vin through an operational amplifier OP5 and the ADC unit, and outputs a control signal to adjust an upper power tube Q1 through the DAC unit; the FPGA control module is configured with a wide-range adaptive voltage-sharing logic, which is used for automatically adjusting a voltage-sharing target value of the upper power tube Q1 according to a voltage interval where the input voltage Vin is located; the FPGA control module adopts a multi-instruction parallel processing architecture, and distributes voltage collection instructions, power tube state detection instructions, PID operation instructions, mode switching control instructions and fault protection instructions to different logic units for parallel execution. The application solves the technical problems that MOS tubes are prone to voltage-sharing imbalance in a high-voltage electronic load condition and it is difficult to dynamically share voltage.

Description

Technical Field

[0001] This application relates to the field of power load technology, and in particular to a high-voltage electronic load system and its adaptive voltage equalization control method. Background Technology

[0002] Electronic loads, as energy absorption devices that simulate various load characteristics, are core equipment for high-voltage DC power supply performance verification and aging tests. In high-voltage application scenarios (such as DC voltage levels ≥600V, and in some scenarios up to 1500V DC), the withstand voltage capability of a single MOSFET (for example, the withstand voltage of commonly used Si MOSFETs is mostly 600V~1500V, while SiC MOSFETs, although having higher withstand voltage, are more expensive) is limited by the voltage rating of power semiconductor devices and cannot directly meet the requirements of high-voltage systems.

[0003] To address the issue of insufficient voltage withstand capability of a single MOSFET, a topology using multiple MOSFETs connected in series is sometimes employed. However, this approach suffers from the following key technical challenges in practical applications: Voltage imbalance problem: The discreteness of device parameters of series MOSFETs (such as threshold voltage, on-resistance, parasitic capacitance) and the difference in drive signal delay can lead to uneven voltage across each MOSFET during the turn-on and turn-off process, and some MOSFETs may be damaged due to overvoltage. Dynamic voltage equalization is challenging: Under transient conditions of high-voltage electronic loads (such as load mode switching and current step changes), bus voltage fluctuations and differences in switching speeds of switching devices will further exacerbate voltage equalization imbalances. Traditional static voltage equalization schemes cannot meet the requirements of dynamic voltage equalization.

[0004] Based on the above, how to solve the technical problem of voltage imbalance caused by MOSFET series connection under high voltage electronic load conditions and the difficulty of dynamic voltage equalization is a problem to be solved in this technical field. Summary of the Invention

[0005] To address the aforementioned deficiencies or improvement needs of existing technologies, and to solve the technical problems of easy voltage equalization imbalance and difficulty in dynamic voltage equalization under high-voltage electronic load conditions caused by MOSFET series connection, this application provides a high-voltage electronic load system and its adaptive voltage equalization control method. It employs FPGA digital control combined with a dual-power transistor division of labor adjustment architecture, setting up an upper power transistor Q1 dedicated to dynamic constant voltage equalization and a lower power transistor Q2 dedicated to operating mode switching. Real-time voltage equalization control is achieved through a voltage equalization adjustment loop formed by operational amplifiers OP1 and OP2. A wide-range adaptive voltage equalization logic and a multi-instruction parallel processing architecture are configured in the FPGA, combined with a predictive algorithm and a dynamic voltage equalization compensation circuit. The system automatically adjusts the voltage equalization distribution ratio according to the input voltage range and performs acquisition, calculation, driving, and fault protection in parallel, achieving adaptive dynamic voltage equalization under a wide high-voltage input range of 500V~2000V. This effectively suppresses voltage equalization imbalance caused by device parameter dispersion, drive delay, and transient operating conditions, improving the dynamic stability and operational safety of the high-voltage electronic load.

[0006] The embodiments of this application adopt the following technical solutions: In a first aspect, this application provides a high-voltage electronic load system, including an FPGA control module, a DAC unit, an ADC unit, a power regulation unit, and a signal conditioning unit; The power regulation unit includes an upper power transistor Q1 and a lower power transistor Q2 connected in series. The upper power transistor Q1 is used for dynamic voltage equalization regulation, and the lower power transistor Q2 is used for mode switching control. The signal conditioning unit includes operational amplifiers OP1, OP2, OP3, OP4, and OP5, and corresponding peripheral circuits. Operational amplifiers OP1, OP2, and corresponding peripheral circuits form a voltage equalization closed-loop regulation loop, and operational amplifiers OP3, OP4, and corresponding peripheral circuits form a mode switching control loop. The FPGA control module acquires the input voltage Vin through operational amplifier OP5 and ADC unit, and adjusts the upper power transistor Q1 by outputting control signals through DAC unit. The FPGA control module is configured with wide-range adaptive voltage equalization logic to automatically adjust the voltage equalization target value of the upper power transistor Q1 according to the voltage range of the input voltage Vin. The FPGA control module adopts a multi-instruction parallel processing architecture, which distributes voltage acquisition instructions, power transistor status detection instructions, PID calculation instructions, mode switching control instructions, and fault protection instructions to different logic units for parallel execution.

[0007] The above technical solution realizes a high-voltage electronic load architecture with FPGA digital control and dual power transistors for division of labor adjustment. It can automatically complete the voltage equalization target value configuration according to the input voltage range, and improve the control response speed and fault protection real-time performance through multi-instruction parallel processing. It fundamentally solves the problems of voltage equalization imbalance and dynamic voltage equalization difficulty of series MOSFETs, and improves system stability, versatility and safety.

[0008] In some implementations, the FPGA control module has a built-in prediction algorithm that predicts voltage change trends in advance and achieves dynamic voltage equalization compensation through a voltage equalization closed-loop adjustment circuit.

[0009] Through the above technical solution, the FPGA control module uses a predictive algorithm to anticipate voltage change trends in advance, and can proactively adjust voltage equalization before voltage fluctuations or sudden changes in operating conditions, thereby achieving advanced dynamic voltage equalization compensation, avoiding voltage equalization imbalance under transient operating conditions, and further improving the dynamic stability of high-voltage loads.

[0010] In some implementations, the wide-range adaptive voltage equalization logic specifically includes: When the input voltage Vin is between 500V and 1000V, the voltage of the upper power transistor Q1 is controlled to be Vin / 2; When the input voltage Vin is between 1000V and 2000V, the voltage of the upper power transistor Q1 is automatically adjusted to the optimal value between Vin / 3 and Vin / 2.

[0011] Through the above technical solution, the voltage equalization ratio is automatically switched according to different input voltage ranges, so that the system can be adapted to a wide range of high voltage inputs from 500V to 2000V without replacing power transistors or manually adjusting parameters, which significantly improves the applicability and versatility of the equipment.

[0012] In some implementations, the FPGA control module automatically optimizes the loop compensation parameters of operational amplifiers OP1 and OP2 based on different input voltages Vin.

[0013] Through the above technical solution, the FPGA control module automatically optimizes the voltage equalization loop compensation parameters according to the input voltage, so that the voltage equalization closed-loop regulation loop maintains the best stability and response speed under different voltage levels, and avoids loop oscillation or excessive voltage equalization deviation under high voltage conditions.

[0014] In some implementations, the FPGA control module stores the optimal voltage equalization parameters corresponding to different input voltages Vin, and directly calls the corresponding optimal voltage equalization parameters when the same voltage is connected again.

[0015] Through the above technical solution, the FPGA control module stores and reuses the historical best voltage equalization parameters, so that the system can quickly enter a stable voltage equalization state without resetting the parameters when repeated voltage is applied, thereby improving the voltage equalization response speed and ease of use.

[0016] In some implementations, the fault protection instruction is set to the highest priority in the multi-instruction parallel processing architecture.

[0017] By setting the fault protection command to the highest priority through the above technical solution, the system can ensure that the protection action is executed first when an anomaly occurs, avoid the blockage of the control process that leads to untimely protection, and improve the safety of equipment operation.

[0018] In some implementations, the fault protection command includes one or more of overvoltage protection, overcurrent protection, and overtemperature protection. When a fault is triggered, the FPGA control module immediately shuts down the upper power transistor Q1 and the lower power transistor Q2.

[0019] Through the above technical solutions, the system has comprehensive overvoltage, overcurrent, and overtemperature protection capabilities. When a fault is triggered, the power transistor can be quickly shut down, effectively preventing damage to the power transistor and load circuit due to overvoltage, overcurrent, and overtemperature, thereby improving system reliability and service life.

[0020] In some implementations, both the upper power transistor Q1 and the lower power transistor Q2 are MOSFETs.

[0021] The above technical solution uses MOSFETs as power regulation devices to adapt to high-voltage and high-speed switching applications, meet the control requirements of series voltage equalization and mode switching, and ensure stable operation of the system under high-voltage conditions.

[0022] Secondly, this application provides an adaptive voltage equalization control method for a high-voltage electronic load system, applied to the high-voltage electronic load system described in the first aspect, comprising: The FPGA control module acquires the input voltage Vin in real time through operational amplifier OP5 and ADC unit; The FPGA control module automatically configures the voltage equalization target value of the power transistor Q1 according to the voltage range of the input voltage Vin; The FPGA control module adopts a multi-instruction parallel processing architecture, which executes voltage acquisition instructions, power transistor status detection instructions, PID calculation instructions, mode switching control instructions, and fault protection instructions in parallel. The fault protection instructions are set to the highest priority, and the upper power transistor Q1 and the lower power transistor Q2 are immediately turned off when a fault occurs.

[0023] The above technical solution realizes an integrated control method of wide-range adaptive voltage equalization + parallel control + high-priority fault protection, which can quickly and stably complete the voltage equalization adjustment and mode switching of series power transistors, while ensuring real-time protection under abnormal operating conditions, thereby improving control efficiency and system safety.

[0024] In some implementations, the FPGA control module also runs a prediction algorithm to anticipate voltage change trends and drive the equalization closed-loop adjustment loop to perform dynamic equalization compensation in advance.

[0025] By introducing a voltage trend prediction function into the control method through the above technical solution, we can realize early intervention-type dynamic voltage equalization, further suppress the voltage equalization imbalance caused by transient operating conditions, and make the dynamic voltage equalization response faster and the voltage equalization effect more stable.

[0026] In summary, this application includes at least the following beneficial technical effects: 1. A high-voltage electronic load architecture based on FPGA digital control and dual power transistor division of labor regulation has been implemented. It can automatically complete the configuration of the voltage equalization target value according to the input voltage range, and improve the control response speed and fault protection real-time performance through multi-instruction parallel processing. It fundamentally solves the problems of voltage equalization imbalance and dynamic voltage equalization difficulty of series MOSFETs, and improves system stability, versatility and safety. 2. The FPGA control module uses a predictive algorithm to anticipate voltage change trends in advance, and can proactively adjust voltage equalization before voltage fluctuations or sudden changes in operating conditions, thereby achieving advanced dynamic voltage equalization compensation, avoiding voltage equalization imbalance under transient operating conditions, and further improving the dynamic stability of high-voltage loads. 3. The voltage equalization ratio is automatically switched according to different input voltage ranges, so that the system can be adapted to a wide range of high voltage inputs from 500V to 2000V without replacing power transistors or manually adjusting parameters, which significantly improves the applicability and versatility of the equipment. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A structural block diagram of a high-voltage electronic load system provided in this application embodiment; Figure 2 A high-voltage electronic load circuit diagram provided for an embodiment of this application; Figure 3 A flowchart of an adaptive voltage equalization control method for a high-voltage electronic load system provided in this application embodiment. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0030] The present application will now be described in detail with reference to the accompanying drawings and embodiments. Example 1

[0031] like Figure 1 As shown in Embodiment 1 of this application, a high-voltage electronic load system is provided, including an FPGA (Field-Programmable Gate Array) control module, a DAC (Digital-to-Analog Converter) unit, an ADC (Analog-to-Digital Converter) unit, a power conditioning unit, and a signal conditioning unit. The FPGA control module, as the core of the system, acquires and receives signals through the ADC unit and outputs and drives control commands through the DAC unit. The signal conditioning unit is connected between the ADC unit, the DAC unit, and the power conditioning unit, completing signal matching and conditioning. Under the unified scheduling of the FPGA control module, the power conditioning unit performs power regulation and voltage equalization control based on the conditioned drive signal. All units cooperate and work together to form a complete high-voltage electronic load control system.

[0032] refer to Figure 2 In some embodiments, the power regulation unit includes an upper power transistor Q1 and a lower power transistor Q2 connected in series. The upper power transistor Q1 is used for dynamic voltage equalization regulation, and the lower power transistor Q2 is used for constant voltage, constant current, and constant resistance mode switching control. In this embodiment, both the upper power transistor Q1 and the lower power transistor Q2 are MOSFETs to adapt to high voltage and fast switching operating scenarios.

[0033] The signal conditioning unit includes operational amplifiers OP1, OP2, OP3, OP4, and OP5, along with corresponding peripheral resistors and capacitors, to amplify, filter, compensate for errors, and control the upper power transistor Q1 and the lower power transistor Q2. Specifically, operational amplifiers OP1 and OP2, along with their corresponding peripheral circuitry, form a voltage equalization closed-loop control circuit for real-time voltage equalization control of the series-connected power transistors. Specifically, the voltage equalization closed-loop control circuit acquires the terminal voltage of the upper power transistor Q1 to form a feedback signal, which is then input to the FPGA control module, forming a voltage equalization closed-loop control link of acquisition-comparison-adjustment. Operational amplifiers OP3 and OP4, along with their corresponding peripheral circuitry, form a mode switching control loop for switching and stabilizing constant voltage, constant current, and constant resistance modes. Specifically, the mode switching control loop acquires the loop current or output voltage to form a mode feedback signal, which is then input to the FPGA control module to achieve closed-loop adjustment for the corresponding mode.

[0034] The FPGA control module acquires the DC input voltage Vin in real time through operational amplifier OP5 and ADC unit (ADC3), and adjusts the conduction state of the power transistor Q1 by dynamically setting the output control signal of DAC unit (DAC1) to achieve voltage equalization.

[0035] The FPGA control module is configured with wide-range adaptive voltage equalization logic, enabling the circuit to adapt to different high-voltage input ranges (e.g., 500V~2000V) without the need for manual parameter adjustment. For example, the FPGA control module can dynamically adjust the voltage equalization target value of the upper power transistor Q1 according to the range of the input voltage Vin: when the input voltage Vin is in the low-high voltage range (500V~1000V), the FPGA control module controls the voltage of the upper power transistor Q1 to Vin / 2 to achieve voltage equalization; when the input voltage Vin is in the high voltage range (1000V~2000V), the FPGA control module automatically adjusts the voltage of the upper power transistor Q1 to the optimal value between Vin / 3 and Vin / 2 to avoid insufficient voltage withstand of the power transistor; at the same time, the FPGA control module automatically optimizes the loop compensation parameters of operational amplifiers OP1 and OP2 according to different input voltages Vin to avoid insufficient voltage withstand of Q1 due to excessively high Vin, ensuring that the voltage equalization closed-loop regulation loop is stable and oscillating within a wide voltage range.

[0036] Furthermore, the FPGA control module pre-stores a voltage equalization ratio parameter table and a loop compensation parameter table corresponding to different input voltages. When the input voltage Vin is detected to be in the range of 1000V to 2000V, the FPGA determines the optimal voltage equalization value between Vin / 3 and Vin / 2 based on the real-time Vin lookup table (this optimal value is a compromise between the power transistor's withstand voltage margin, dynamic voltage equalization stability, and losses), which serves as the target voltage equalization voltage for Q1. For example, when Vin = 1200V, the FPGA selects a voltage equalization ratio of 0.4, then the target voltage for Q1 is 480V; when Vin = 1500V, the FPGA selects a voltage equalization ratio of 0.35, then the target voltage for Q1 is 525V; when Vin = 1800V, the FPGA selects a voltage equalization ratio of 0.33, then the target voltage for Q1 is 594V. This ensures that Q1 always operates within a safe withstand voltage range while maintaining good dynamic voltage equalization performance.

[0037] Meanwhile, the FPGA automatically calls the corresponding loop compensation parameters according to the current voltage level, dynamically optimizing the response bandwidth and damping coefficient of the voltage equalization closed-loop adjustment loop composed of OP1 and OP2. This ensures that the loop remains stable and oscillating under different high-voltage conditions, improving the reliability of dynamic voltage equalization. For example, in the low voltage range (500V~1000V): the loop bandwidth is set wider, resulting in a faster response; in the high voltage range (1000V~2000V): the FPGA automatically increases the loop damping coefficient and reduces the bandwidth to avoid oscillations in the voltage equalization loop caused by high-voltage parasitic parameters; under transient conditions, the FPGA further fine-tunes the compensation parameters to make the voltage equalization response smooth and without overshoot.

[0038] Specifically, the upper power transistor Q1 is dedicated to dynamic voltage equalization regulation. Its implementation principle is as follows: The FPGA control module outputs a control signal matching the voltage equalization target value through the DAC unit based on the acquired input voltage Vin. After being conditioned by the signal conditioning unit, the signal equalization signal drives the conduction level of the upper power transistor Q1. At the same time, the voltage equalization closed-loop regulation circuit acquires the voltage across the upper power transistor Q1 in real time and feeds the actual voltage value back to the FPGA control module. This allows the FPGA control module to adjust the conduction voltage drop of Q1 in real time, ensuring that the voltage distribution between the series power transistors meets the preset voltage equalization rules. This prevents voltage equalization imbalance due to device parameter discrepancies, drive delays, or voltage fluctuations, thereby achieving dynamic, real-time, and closed-loop voltage equalization control.

[0039] The lower power transistor Q2 is dedicated to switching and closed-loop control of three operating modes: constant voltage, constant current, and constant resistance. Its implementation principle is as follows: the FPGA control module outputs a control signal corresponding to the target operating mode through a mode switching control loop, driving the lower power transistor Q2 to perform the corresponding closed-loop adjustment. Constant voltage mode: The lower power transistor Q2 maintains the output voltage stable at the target value, achieving constant voltage load characteristics; Constant current mode: The lower power transistor Q2 maintains the loop current stable at the target value, achieving constant current load characteristics; Constant resistance mode: The lower power transistor Q2 maintains the equivalent impedance stable at the target value, achieving constant resistance load characteristics.

[0040] The mode switching control loop is independent of the voltage equalization closed-loop regulation loop, so that the mode adjustment of the lower power transistor Q2 does not affect the voltage equalization control of the upper power transistor Q1. The two perform their respective functions and do not interfere with each other, thus realizing a dual power transistor division of labor architecture that decouples voltage equalization and mode control.

[0041] In some implementations, the FPGA control module stores the optimal voltage equalization parameters corresponding to different input voltages Vin. When the same voltage is connected again, the stored optimal voltage equalization parameters are directly called to quickly enter a stable working state and improve the voltage equalization response speed.

[0042] In some implementations, to address the control delay caused by the serial processing of "acquisition, calculation, driving, and protection" instructions in traditional FPGA control, this implementation adopts an FPGA multi-instruction parallel processing architecture to optimize control timing. Specifically, the FPGA control module uses a multi-instruction parallel processing architecture to distribute five types of instructions—voltage acquisition instructions (OP5+ADC3), power transistor status detection instructions, PID calculation instructions, mode switching control instructions, and fault protection instructions—to different logic units within the FPGA for parallel execution, avoiding control delays caused by serial processing. For example, while acquiring Vin, the status detection of Q1 / Q2 and PID parameter adjustment are performed simultaneously, without waiting for acquisition to complete before calculation, reducing the control delay from the original 1μs to less than 0.2μs. Furthermore, instruction priority allocation logic is added, setting the fault protection instruction as the highest priority. Fault protection includes one or more of overvoltage protection, overcurrent protection, and overtemperature protection. When a fault is triggered (overvoltage, overcurrent, overtemperature), the FPGA control module immediately shuts down the upper power transistor Q1 and the lower power transistor Q2, achieving rapid protection and further improving circuit safety. The above settings break through the timing limitations of traditional FPGA control and improve the overall control efficiency and response speed.

[0043] In some implementations, the FPGA control module has a built-in prediction algorithm that predicts the changing trends of the input voltage and the voltage across the power transistor in advance, and drives the voltage equalization closed-loop adjustment loop to perform adjustment actions in advance, thereby achieving dynamic voltage equalization compensation and effectively suppressing voltage equalization imbalance caused by transient operating conditions, mode switching, and current steps.

[0044] Specifically, the prediction algorithm built into the FPGA control module uses real-time collected input voltage Vin, voltage across the upper power transistor Q1, and current change rate as input quantities. Based on historical and real-time sampling data, it constructs a voltage change trend model to predict the direction and amplitude of voltage fluctuations within a set time period, obtaining a predicted voltage value. The FPGA control module uses this predicted voltage value as a basis for advance adjustment. Before actual voltage fluctuations occur, it drives the voltage equalization closed-loop adjustment loop to correct the conduction parameters of the upper power transistor Q1, pre-compensating for impending voltage deviations. This ensures that the series power transistors enter a stable voltage equalization state before transient conditions, mode switching, current steps, and other disturbances occur, thereby avoiding voltage imbalance. In this embodiment, the prediction algorithm can be implemented using linear prediction, incremental prediction, or model prediction based on historical data. Its core lies in predicting future voltage trends based on real-time electrical parameters and outputting voltage equalization adjustment commands in advance. As an example, this embodiment uses a first-order linear incremental prediction algorithm: the FPGA continuously stores the most recent k voltage sampling values ​​V. n-k …V n-1 V n Calculate the voltage increment ΔV between adjacent sampling points. n =V n -V n-1 The average value of multiple increments, avg(ΔV), is taken as the voltage change rate, and the predicted voltage V at the next moment is calculated based on this. n+1 =V n +avg(ΔV); The FPGA outputs the corresponding equalization adjustment amount in advance based on the predicted voltage, realizing advance compensation. It should be noted that the above prediction algorithm is an example, not a limitation.

[0045] In summary, the high-voltage electronic load system provided in this application embodiment can operate stably under a wide range of high-voltage input from 500V to 2000V without the need to replace the power transistor or perform manual adjustments. It is highly versatile, has a fast dynamic response, and is highly safe. Example 2

[0046] Based on the high-voltage electronic load system provided in Embodiment 1, this Embodiment 2 provides a specific circuit example applicable to the high-voltage electronic load system in Embodiment 1.

[0047] refer to Figure 2As shown, this high-voltage electronic load circuit includes three main loops: a voltage equalization closed-loop regulation loop, a mode switching control loop, and a voltage acquisition loop. The following is a detailed description of these three loops: Voltage equalization closed-loop regulation circuit (OP1, OP2 + Q1 + RC circuit, realizing dynamic voltage equalization closed-loop control): The voltage equalization closed-loop regulation circuit uses the upper power transistor Q1 as the control object. The drain (D) of Q1 is connected to the high-voltage input DC_IN, the source (S) is connected to the drain (D) of Q2, and the gate (G) receives the voltage equalization drive signal. The loop achieves closed-loop voltage equalization by sampling the voltage at the source (S) of Q1, ensuring balanced voltage distribution among the series power transistors.

[0048] The equalizing closed-loop regulation circuit includes resistive elements R1-R11 and capacitive elements C1-C2. R10 is connected between the output of OP1 and the gate G of Q1. A connection point is set between R10 and the output of OP1. One side of this connection point is connected to R9 and then grounded. The other side of this connection point is connected to R7, C1, and C2 between the inverting input of OP1. R7 and C1 are connected in series and in parallel with C2. The non-inverting input of OP1 is connected to R8 and then grounded. The inverting input of OP1 is connected to R5 and then to the connection point between the output of OP2 and ADC1. R11 is set between this connection point and ADC1. There is a connection point between the inverting input of OP1 and R5. This connection point is connected to R6 and then to DAC1. R3 is connected between the output of OP2 and the non-inverting input of OP2. The non-inverting input of OP2 is connected to R1 and then to the connection point between Q1 and DC_IN. The inverting input of OP2 is connected to R2 and then to the connection point between Q1 and Q2. The inverting input of OP2 is also connected to R4 and then grounded. ADC1 and DAC1 are both connected to the FPGA.

[0049] The functions of the above-mentioned resistors and capacitors are as follows: R1: Connects the non-inverting input terminal of OP2 to the drain D (DC_IN) of Q1, and is used to acquire the high-voltage side potential of Q1 to provide a high-voltage side reference for voltage equalization comparison; R2: Connects the inverting input terminal of OP2 to the source S of Q1 (Q1 and Q2 in series node), used to collect the low-voltage side potential of Q1 and form a voltage sampling feedback of Q1 terminal; R3: Connects the output terminal of OP2 and the non-inverting input terminal of OP2 to form the negative feedback branch of OP2, realizing error signal amplification and loop stability adjustment; R4: Connects the inverting input of OP2 to ground, providing DC bias for OP2 and stabilizing the quiescent operating point of the op-amp; R5: Connects the inverting input of OP1 to the output of OP2, and is used to send the equalization error signal output by OP2 into OP1 for secondary adjustment; R6: Connect the inverting input of OP1 to DAC1, and introduce the voltage equalization target value output by DAC1 into the inverting input of OP1 as the voltage equalization closed-loop setpoint; R7: Connected in series with C1 and in parallel with C2, it is connected between the inverting input terminal of OP1 and the output terminal of OP1 to form a loop phase compensation network to prevent the voltage equalization loop from oscillating. R8: Connects the non-inverting input of OP1 to ground, providing DC bias to the non-inverting input of OP1 to ensure that the op-amp operates in a suitable range; R9: Connects the OP1 output terminal to ground to discharge residual charge, stabilize the OP1 output potential, and prevent gate drive signal drift. R10: Connects the output of OP1 to the gate G of Q1, and sends the voltage equalization adjustment signal directly to the gate of Q1 to control the conduction degree of Q1 to achieve dynamic voltage equalization. R11: Connects the output of OP2 to ADC1, samples the equalization error signal and sends it back to the FPGA to realize digital monitoring and correction; C1 and C2, together with R7, form an RC compensation network to suppress high-frequency interference and improve the dynamic response and stability of the voltage equalization loop.

[0050] Voltage equalization closed-loop regulation logic: The FPGA outputs the voltage equalization target value through DAC1, which is sent to the inverting input of OP1 via R6; R1 collects the drain voltage of Q1 and R2 collects the source voltage of Q1, which are sent to OP2 for error comparison and feedback stabilization via R3; the error signal output by OP2 is sent to OP1 via R5, and OP1 outputs a drive signal after compensation by R7, C1, and C2, which controls the gate G of Q1 through R10 to adjust the on-state voltage drop of Q1 in real time, so that the voltage across Q1 is maintained at the target voltage equalization value, realizing dynamic voltage equalization of the series power transistors; at the same time, the output signal of OP2 is sent back to the FPGA via R11 and ADC1, forming a mixed digital-analog closed-loop control.

[0051] Mode switching control loop (OP3, OP4 + Q2 + RC circuit, achieving constant voltage / constant current / constant resistance control): The mode switching control loop uses the following power transistor Q2 as the control object. The drain (D) of Q2 is connected to the source (S) of Q1. The source (S) is connected to the sampling resistor RsN and then grounded. The gate (G) receives the mode drive signal. The loop collects the loop current through RsN to achieve closed-loop control of the three operating modes.

[0052] The mode switching control loop includes resistors R12-R22 and capacitors C3-C4. R14 is connected between the output of OP3 and the gate G of Q2. A connection point is set between R14 and the output of OP3. One side of this connection point is connected to R16 and then grounded. The other side of this connection point is connected to R21, C3, and C4 between the inverting input of OP3. R21 and C3 are connected in series and in parallel with C4. The non-inverting input of OP3 is connected to R15 and then grounded. The inverting input of OP3 is connected to R12 and then to the connection point between the output of OP4 and ADC2. R22 is set between this connection point and ADC2. There is a connection point between the inverting input of OP3 and R12. This connection point is connected to R13 and then to DAC2. R17 is connected between the output of OP4 and the non-inverting input of OP4. The non-inverting input of OP4 is connected to R18 and then to the connection point between Q2 and RsN. The inverting input of OP4 is connected to R19 and then to the grounded side of RsN. The inverting input of OP4 is also connected to R20 and then grounded. ADC2 and DAC2 are both connected to the FPGA.

[0053] The functions of the above-mentioned resistors and capacitors are as follows: R12: Connect the inverting input of OP3 to the output of OP4, and send the mode error adjustment signal to the inverting input of OP3 to realize mode closed-loop correction; R13: Connect the inverting input of OP3 to DAC2, and introduce the mode setpoint output by DAC2 into OP3 as the target command for constant voltage / constant current / constant resistance mode; R14: Connects the output of OP3 to the gate G of Q2, and sends the mode control signal to the gate of Q2 to control the conduction of Q2 and the switching of the working mode; R15: Connects the non-inverting input of OP3 to ground, providing bias to the non-inverting input of OP3 and stabilizing the operating point of the op-amp; R16: Connects the output terminal of OP3 to ground to stabilize the output potential of OP3 and suppress drive signal spikes; R17: Connects the output of OP4 to the non-inverting input of OP4 to form the negative feedback branch of OP4, thereby amplifying the mode error signal; R18: Connect the non-inverting input terminal of OP4 to the source S (upper end of RsN) of Q2 to collect the voltage signal corresponding to the operating current of Q2 as mode feedback; R19: Connect the inverting input terminal of OP4 to the ground terminal of RsN to acquire the reference potential of the acquisition circuit and form a current sampling differential comparison. R20: Connects the inverting input of OP4 to ground to provide DC bias for OP4 and ensure the static stability of the op-amp; R21: Connected in series with C3 and in parallel with C4, it is connected across the inverting input terminal of OP3 and the output terminal of OP3 to form a mode loop compensation and prevent oscillation. R22: Connect the output of OP4 to ADC2 to sample and transmit the mode error signal back to the FPGA to realize mode status monitoring; C3 and C4, together with R21, form an RC filter compensation network to filter out mode switching noise and improve the stability of mode control. RsN: Connected in series between the source S of Q2 and ground, it converts the load current into a voltage signal, which serves as the core sampling basis for the closed-loop mode.

[0054] Mode switching control loop collaborative logic: The FPGA outputs the mode target instruction through DAC2, which is sent to the inverting input of OP3 via R13; RsN samples the load current, which is sent to OP4 via R18 and R19 for current / voltage comparison, and the error signal output by OP4 is sent to OP3 via R12; OP3, after compensation by R21, C3, and C4, outputs a drive signal, which controls the gate G of Q2 via R14 to adjust the conduction state of Q2 to achieve constant voltage, constant current, or constant resistance modes; the output signal of OP4 is simultaneously sent back to the FPGA via R22 and ADC2 to form a mode closed-loop real-time correction, ensuring mode stability and fast switching.

[0055] Voltage acquisition loop (OP5 + resistor circuit, to realize input voltage Vin acquisition): The voltage acquisition loop is responsible for acquiring the high voltage input DC_IN, providing real-time Vin to the FPGA for adaptive voltage equalization and mode parameter calculation.

[0056] The voltage acquisition loop includes resistors R23-R26; the output of OP5 is connected to ADC3, R26 is connected between the output of OP5 and the non-inverting input of OP5, the inverting input of OP5 is connected to ground after being connected to R25, the inverting input of OP5 is also connected to R24 and then to the ground side of RsN, the non-inverting input of OP5 is connected to R23 and then to the connection point between Q1 and DC_IN; ADC3 is connected to the FPGA.

[0057] The functions of the above-mentioned resistive elements are as follows: R23: Connect the non-inverting input terminal of OP5 to the drain D (DC_IN) of Q1 to perform voltage division sampling on the high voltage input DC_IN and reduce the high voltage to the safe input range of the op-amp; R24: Connects the inverting input of OP5 to the ground terminal of RsN to provide the system ground reference potential and ensure that the voltage sampling reference is consistent; R25: Connects the inverting input of OP5 to ground, providing bias to the inverting input of OP5 and stabilizing the static operating point of the sampling circuit; R26: Connects the output terminal of OP5 to the non-inverting input terminal of OP5 to form the feedback branch of the voltage follower, realizing buffer isolation of high impedance input and low impedance output.

[0058] Voltage acquisition loop collaborative logic: R23 divides the high-voltage input DC_IN and sends the sampled voltage to the non-inverting input of OP5; OP5, under the voltage follower structure formed by R26, buffers and isolates the sampled signal to avoid the impact of the downstream load on the sampling accuracy; OP5 outputs a stable sampled voltage to ADC3, which converts it into a digital signal and inputs it to the FPGA, providing the real-time input voltage Vin for the FPGA to perform wide-range adaptive voltage equalization, loop parameter optimization, and prediction algorithms.

[0059] The three major loops work in synergy: the voltage acquisition loop accurately acquires the input voltage Vin in real time and transmits it to the FPGA, providing a unified high-voltage input reference for the adaptive voltage equalization ratio adjustment of the voltage equalization closed-loop regulation loop and the operating parameter matching of the mode switching control loop; the voltage equalization closed-loop regulation loop, with Q1 as its core, independently completes the dynamic voltage equalization control of the series power transistor, decoupled from the hardware link and signal conditioning of the mode switching control loop, and is not affected by the mode switching action; the mode switching control loop, with Q2 as its core, independently realizes the switching and stabilization control of constant voltage / constant current / constant resistance modes, and its regulation... The process will not affect the voltage distribution balance of the equalization closed-loop regulation loop. The FPGA, as the central control core, performs unified scheduling of the sampling, calculation, driving, and feedback actions of the three major loops based on a multi-instruction parallel processing architecture. At the same time, it combines prediction algorithms to predict voltage change trends and drive the equalization closed-loop regulation loop to perform dynamic equalization compensation in advance. This ensures that the entire high-voltage electronic load circuit maintains stable voltage equalization, accurate and reliable mode switching, and timely fault safety protection response under transient conditions such as a wide range of high-voltage input from 500V to 2000V, load mode switching, and current step jumps. Example 3

[0060] Based on the high-voltage electronic load system provided in Embodiment 1, this Embodiment 3 provides an adaptive voltage equalization control method for a high-voltage electronic load system, which is applied to the high-voltage electronic load system of Embodiment 1.

[0061] refer to Figure 3 The method includes the following steps: S1. Real-time acquisition of input voltage: The FPGA control module acquires the input voltage Vin in real time through the operational amplifier OP5 and the ADC unit, and completes the sampling and conversion of the high-voltage input signal.

[0062] S2, Wide-range adaptive voltage equalization configuration: The FPGA control module automatically configures the voltage equalization target value of the power transistor Q1 based on the voltage range of the input voltage Vin: If Vin is between 500V and 1000V, set the voltage of Q1 to Vin / 2; If Vin is between 1000V and 2000V, set the Q1 voltage to the optimal value between Vin / 3 and Vin / 2. Simultaneously, the FPGA control module automatically optimizes the loop compensation parameters of OP1 and OP2 based on the current Vin value to ensure the stability of the voltage equalization loop.

[0063] S3, Parallel control execution of multiple instructions: The FPGA control module employs a multi-instruction parallel processing architecture, executing in parallel the following instructions: voltage acquisition; power transistor status detection; PID calculation; mode switching control; and fault protection. This parallel execution significantly reduces control latency and improves system response speed. During this parallel control execution, the fault protection instruction can be set to the highest priority, and the fault types include one or more of overvoltage, overcurrent, and overtemperature. When a fault is detected, the FPGA control module immediately shuts down the upper power transistor Q1 and the lower power transistor Q2 to prevent damage to the power transistors.

[0064] Furthermore, the FPGA control module also runs a prediction algorithm to predict voltage change trends based on historical voltage data and real-time acquired values, and drives the voltage equalization closed-loop adjustment loop to perform dynamic voltage equalization compensation in advance. Under transient conditions such as load mode switching, current step, and bus fluctuation, the voltage equalization of the series power transistors remains stable, avoiding device damage due to voltage equalization imbalance.

[0065] Furthermore, the FPGA control module also stores the optimal voltage equalization parameters corresponding to different input voltages Vin. When the same voltage is connected again, the corresponding parameters are directly called to quickly enter a stable voltage equalization state, improving the system's ease of use and response speed.

[0066] The method provided in this application achieves stable, reliable, and efficient operation of high-voltage electronic loads under complex transient conditions in a wide voltage range through wide-range adaptive voltage equalization, multi-instruction parallel control, predictive algorithm prediction, and highest priority fault protection.

[0067] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A high-voltage electronic load system, characterized in that, It includes an FPGA control module, a DAC unit, an ADC unit, a power conditioning unit, and a signal conditioning unit; The power regulation unit includes an upper power transistor Q1 and a lower power transistor Q2 connected in series. The upper power transistor Q1 is used for dynamic voltage equalization regulation, and the lower power transistor Q2 is used for mode switching control. The signal conditioning unit includes operational amplifiers OP1, OP2, OP3, OP4, and OP5, and corresponding peripheral circuits. Operational amplifiers OP1, OP2, and corresponding peripheral circuits form a voltage equalization closed-loop regulation loop, and operational amplifiers OP3, OP4, and corresponding peripheral circuits form a mode switching control loop. The FPGA control module acquires the input voltage Vin through operational amplifier OP5 and ADC unit, and adjusts the upper power transistor Q1 by outputting control signals through DAC unit. The FPGA control module is configured with wide-range adaptive voltage equalization logic to automatically adjust the voltage equalization target value of the upper power transistor Q1 according to the voltage range of the input voltage Vin. The FPGA control module adopts a multi-instruction parallel processing architecture, which distributes voltage acquisition instructions, power transistor status detection instructions, PID calculation instructions, mode switching control instructions, and fault protection instructions to different logic units for parallel execution.

2. The high-voltage electronic load system according to claim 1, characterized in that, The FPGA control module has a built-in prediction algorithm that predicts voltage change trends in advance and achieves dynamic voltage equalization compensation through a voltage equalization closed-loop adjustment circuit.

3. The high-voltage electronic load system according to claim 1, characterized in that, The wide-range adaptive voltage equalization logic specifically includes: When the input voltage Vin is between 500V and 1000V, the voltage of the upper power transistor Q1 is controlled to be Vin / 2; When the input voltage Vin is between 1000V and 2000V, the voltage of the upper power transistor Q1 is automatically adjusted to the optimal value between Vin / 3 and Vin / 2.

4. The high-voltage electronic load system according to claim 3, characterized in that, The FPGA control module automatically optimizes the loop compensation parameters of operational amplifiers OP1 and OP2 based on different input voltages Vin.

5. The high-voltage electronic load system according to claim 3, characterized in that, The FPGA control module stores the optimal voltage equalization parameters corresponding to different input voltages Vin. When the same voltage is connected again, the corresponding optimal voltage equalization parameters are directly called.

6. The high-voltage electronic load system according to claim 1, characterized in that, In the multi-instruction parallel processing architecture, the fault protection instruction is set to the highest priority.

7. The high-voltage electronic load system according to claim 6, characterized in that, The fault protection command includes one or more of overvoltage protection, overcurrent protection and overtemperature protection. When a fault is triggered, the FPGA control module immediately shuts down the upper power transistor Q1 and the lower power transistor Q2.

8. The high-voltage electronic load system according to any one of claims 1-7, characterized in that, Both the upper power transistor Q1 and the lower power transistor Q2 are MOSFETs.

9. An adaptive voltage equalization control method for a high-voltage electronic load system, applied to the high-voltage electronic load system according to any one of claims 1-8, characterized in that, include: The FPGA control module acquires the input voltage Vin in real time through operational amplifier OP5 and ADC unit; The FPGA control module automatically configures the voltage equalization target value of the power transistor Q1 according to the voltage range of the input voltage Vin; The FPGA control module adopts a multi-instruction parallel processing architecture, which executes voltage acquisition instructions, power tube status detection instructions, PID calculation instructions, mode switching control instructions, and fault protection instructions in parallel. The fault protection command is set to the highest priority, and the upper power transistor Q1 and the lower power transistor Q2 are immediately shut down when a fault occurs.

10. The adaptive voltage equalization control method for a high-voltage electronic load system according to claim 9, characterized in that, The FPGA control module also runs a prediction algorithm to predict voltage change trends and drive the equalization closed-loop adjustment loop to perform dynamic equalization compensation in advance.

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