Power supply chip psrr parameter detection circuit and automatic test device

Abstract

This utility model discloses a power chip PSRR parameter detection circuit and automated testing device, including an MCU module, a signal generation module, a power operational amplifier module, a buffer circuit module, an electronic load module, a DAC module, and an ADC module. The input terminal of the signal generation module is connected to an SPI interface; the input terminal of the power operational amplifier module is connected to the output terminal of the signal generation module; the first input terminal of the buffer circuit module is used to acquire the first input signal of the power chip under test, and the second input terminal of the buffer circuit module is used to acquire the first output signal of the power chip under test; the input terminal of the electronic load module is connected to the current output terminal of the power chip under test; the input terminal of the DAC module is connected to an I2C interface; the first and second input terminals of the ADC module are respectively connected to the first and second output terminals of the buffer circuit module. This design simplifies the testing process, minimizes the impact on input and output signals, reduces testing costs, and improves measurement accuracy and testing efficiency.

Description

Technical Field

[0001] This utility model relates to the field of automated testing technology, and in particular to a power chip PSRR parameter detection circuit and automated testing device. Background Technology

[0002] PSRR (Power Supply Rejection Ratio) is a crucial parameter for evaluating the performance of power supply chips. It represents the chip's ability to suppress noise and ripple from the input power supply to the output. In electronic systems, power quality is paramount to circuit stability and reliability, especially in high-precision, low-noise applications such as communication systems, medical equipment, and high-performance ADCs / DACs. Therefore, PSRR testing is a key step in evaluating the performance of power supply chips.

[0003] Currently, the following problems exist in the PSRR parameter detection of power supply chips:

[0004] 1. Existing testing equipment is bulky and expensive, making it difficult to achieve automated batch testing. High-precision PSRR measurement requires expensive testing equipment, such as high-bandwidth oscilloscopes and spectrum analyzers, which increases testing costs.

[0005] 2. The parameters introduced by the existing test equipment itself have a significant impact on the input and output signals. For example, the bandwidth, attenuation and capacitive load of the test probe may have a significant impact on the measurement results, especially for PSRR measurement in the high-frequency band.

[0006] 3. The existing testing process is complex. PSRR testing requires complex signal injection, synchronous measurement and data analysis, which increases the complexity and time cost of the test.

[0007] 4. Low-frequency noise may be very low, while the background noise of existing test equipment may interfere with the measurement, resulting in a decrease in the measurement accuracy of PSRR in the low-frequency range. Utility Model Content

[0008] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a power supply chip PSRR parameter detection circuit and automated testing device, which simplifies the testing process, reduces interference, minimizes the impact on input and output signals, lowers testing costs, and improves measurement accuracy and testing efficiency.

[0009] On one hand, this utility model embodiment provides a power chip PSRR parameter detection circuit, including:

[0010] The MCU module is equipped with an SPI interface, an I2C interface, and an LVDS interface.

[0011] A signal generation module, wherein the input terminal of the signal generation module is connected to the SPI interface;

[0012] A power operational amplifier module, wherein the input terminal of the power operational amplifier module is connected to the output terminal of the signal generation module;

[0013] A buffer circuit module, wherein the first input terminal of the buffer circuit module is used to acquire the first input signal of the power chip under test, and the second input terminal of the buffer circuit module is used to acquire the first output signal of the power chip under test;

[0014] An electronic load module, the input terminal of which is connected to the current output terminal of the power supply chip under test, is used to adjust the load current to a preset value;

[0015] A DAC module, wherein the input terminal of the DAC module is connected to the I2C interface, and the output terminal of the DAC module is connected to the voltage setting terminal of the electronic load module;

[0016] An ADC module is provided, wherein its first input terminal and second input terminal are connected to the first output terminal and second output terminal of the buffer circuit module, respectively, and the output terminal of the ADC module is connected to the LVDS interface.

[0017] According to some embodiments of this utility model, the signal generation module uses a chip of model AD9834CRUZ, and the power operational amplifier module uses a chip of model ADA4870ACPZ.

[0018] According to some embodiments of the present invention, the electronic load module includes a first operational amplifier chip, a first NMOS transistor, and an instrumentation amplifier chip. The first operational amplifier chip is connected to the first NMOS transistor, the first NMOS transistor is an adjustment transistor, and the instrumentation amplifier chip is used to output a feedback signal.

[0019] According to some embodiments of this utility model, the DAC module uses a chip with the model number AD5696BRUZ.

[0020] According to some embodiments of this utility model, the ADC module is a high-speed ADC, using a chip with the model number ADC3682.

[0021] According to some embodiments of the present invention, the power chip PSRR parameter detection circuit further includes a power filtering module, which includes multiple filter capacitors connected in parallel for filtering out external power interference signals.

[0022] According to some embodiments of the present invention, the power chip PSRR parameter detection circuit further includes a positive voltage LDO power module. The positive voltage LDO power module includes a first voltage regulator chip, a first resistor, a second resistor, a first filter capacitor, and a second filter capacitor. The first resistor and the first filter capacitor are connected to the input terminal of the first voltage regulator chip, and the second resistor and the second filter capacitor are connected to the setting terminal of the first voltage regulator chip.

[0023] According to some embodiments of the present invention, the power chip PSRR parameter detection circuit further includes a negative voltage LDO power module. The negative voltage LDO power module includes a second voltage regulator chip, a third resistor, a fourth resistor, a third filter capacitor, and a fourth filter capacitor. The third resistor and the third filter capacitor are connected to the input terminal of the second voltage regulator chip, and the fourth resistor and the fourth filter capacitor are connected to the setting terminal of the second voltage regulator chip.

[0024] According to some embodiments of this utility model, the power chip PSRR parameter detection circuit further includes a reference voltage module. The reference voltage module includes a third voltage regulator chip, a fifth filter capacitor, a sixth filter capacitor, a seventh filter capacitor, and an eighth filter capacitor. The fifth filter capacitor and the sixth filter capacitor, which are connected in parallel, are connected to the input terminal of the third voltage regulator chip. The seventh filter capacitor and the eighth filter capacitor, which are connected in parallel, are connected to the output terminal of the third voltage regulator chip.

[0025] On the other hand, this utility model embodiment provides an automated testing device, including the above-mentioned power chip PSRR parameter detection circuit.

[0026] The embodiments of this utility model have at least the following beneficial effects:

[0027] The power chip PSRR parameter detection circuit of this embodiment includes an MCU module, a signal generation module, a power operational amplifier module, a buffer circuit module, and an electronic load module. The MCU module serves as the control center and is equipped with an SPI interface. It receives signals generated by the signal generation module 200 through the SPI interface and performs control and monitoring. A set electronic load voltage signal is output to the electronic load module via the DAC module. The electronic load module adjusts the load current to a preset value based on the received set signal. The signal generation module generates an AC test signal of a specific frequency. The power operational amplifier module amplifies the AC test signal output by the signal generation module, thereby outputting a power supply with a test signal to the power chip under test. The buffer circuit module collects the input and output signals of the power chip under test and performs signal buffering. The ADC module receives the buffered signal through its first and second input terminals and converts the analog signal into a digital signal, which is then transmitted to the MCU module for processing. The MCU module evaluates the PSRR parameter performance of the power chip under test, thereby achieving effective detection of the power chip's PSRR parameter. The overall testing circuit can be integrated into a single test board to achieve automated testing on the production line; it can directly send commands to test the PSRR parameters of the power supply chip at the corresponding frequency, simplifying the testing process, reducing testing costs, and improving measurement accuracy and testing efficiency.

[0028] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0029] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0030] Figure 1 This is a schematic block diagram of the power chip PSRR parameter detection circuit according to an embodiment of the present invention.

[0031] Figure 2 for Figure 1 The circuit diagram shown is of the PSRR parameter detection circuit for the power chip.

[0032] Figure 3 for Figure 1 The circuit diagram shown is of the signal generation module of the power chip PSRR parameter detection circuit.

[0033] Figure 4 for Figure 1 The circuit schematic of the power operational amplifier module of the PSRR parameter detection circuit of the power chip is shown.

[0034] Figure 5 for Figure 1 The circuit schematic of the buffer circuit module of the PSRR parameter detection circuit of the power chip is shown.

[0035] Figure 6 for Figure 1 One of the circuit schematics of the electronic load module of the power chip PSRR parameter detection circuit is shown.

[0036] Figure 7 for Figure 1 The second circuit schematic diagram of the electronic load module of the power chip PSRR parameter detection circuit is shown.

[0037] Figure 8 This is a circuit diagram of the power filtering module of the power chip PSRR parameter detection circuit in an embodiment of the present invention.

[0038] Figure 9 This is a circuit diagram of the positive voltage LDO power module of the power chip PSRR parameter detection circuit according to an embodiment of the present invention.

[0039] Figure 10 This is a circuit diagram of the negative voltage LDO power module of the power chip PSRR parameter detection circuit in an embodiment of this utility model.

[0040] Figure 11 This is a circuit diagram of the reference voltage module of the PSRR parameter detection circuit of the power chip in an embodiment of this utility model.

[0041] Figure label:

[0042] MCU module 100, signal generation module 200, power operational amplifier module 300, buffer circuit module 400, electronic load module 500, first load unit 510, second load unit 520, DAC module 600, ADC module 700, power supply filtering module 810, positive voltage LDO power supply module 820, negative voltage LDO power supply module 830, reference voltage module 840, and power supply chip under test 900. Detailed Implementation

[0043] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0044] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first," "second," etc., are used in the description, they are only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the sequential relationship of the indicated technical features.

[0045] In the description of this utility model, unless otherwise explicitly defined, the terms "setting" and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0046] Testing the PSRR parameter of power supply chips faces several technical challenges. First, the bandwidth and noise floor limitations of the test equipment can affect measurement accuracy, especially for high-frequency PSRR values. Second, the injection of input noise requires precise control to ensure that its waveform and spectrum are consistent with actual power supply noise. Furthermore, electromagnetic interference and circuit board layout in the test environment can introduce additional noise, interfering with test results. To overcome these challenges, high-bandwidth oscilloscopes, spectrum analyzers, and specialized signal injection equipment are typically used, and testing is conducted in a well-shielded environment. As electronic systems increasingly demand higher power quality, PSRR testing techniques are constantly being improved to more accurately reflect the actual performance of power supply chips. For example, dynamic PSRR testing methods have been introduced to evaluate the transient noise suppression capability of power supply chips under rapidly changing loads. These technological advancements provide crucial support for the design and optimization of power supply chips and also drive performance improvements in power management circuits.

[0047] This embodiment discloses a power supply chip PSRR parameter detection circuit, suitable for automated testing devices. Please refer to... Figures 1 to 7The power chip PSRR parameter detection circuit includes an MCU module 100, a signal generation module 200, a power operational amplifier module 300, a buffer circuit module 400, an electronic load module 500, a DAC module 600, and an ADC module 700. The MCU module 100 is equipped with an SPI interface, an I2C interface, and an LVDS interface. The input terminal of the signal generation module 200 is connected to the SPI interface. The input terminal of the power operational amplifier module 300 is connected to the output terminal of the signal generation module 200. The first input terminal of the buffer circuit module 400 is used to acquire the first input signal of the power chip under test 900, and the second input terminal of the buffer circuit module 400 is used to acquire the first output signal of the power chip under test 900. The input terminal of the electronic load module 500 is connected to the current output terminal of the power chip under test 900, and the electronic load module 500 is used to adjust the load current to a preset value. The input terminal of the DAC module 600 is connected to the I2C interface, and the output terminal of the DAC module 600 is connected to the voltage setting terminal of the electronic load module 500. The first input terminal and the second input terminal of the ADC module 700 are connected to the first output terminal and the second output terminal of the buffer circuit module 400, respectively, and the output terminal of the ADC module 700 is connected to the LVDS interface.

[0048] The basic principle of PSRR parameter detection for power supply chips is to input a noise signal of known amplitude and frequency at the input terminal of the power supply chip, while simultaneously measuring the noise amplitude at the output terminal, and calculating the ratio of input noise to output noise, usually expressed in dB. This parameter reflects the power supply chip's ability to suppress power supply noise. For example, in the high-frequency range, the output noise of the power supply chip is mainly determined by the high-frequency characteristics of the internal circuitry; while in the low-frequency range, PSRR depends more on the loop gain and compensation design of the power supply chip.

[0049] The MCU module 100 is equipped with an SPI interface, an I2C interface, and an LVDS (Low Voltage Differential Signaling) interface. As the control center, the MCU module 100 receives signals generated by the signal generation module 200 via the SPI interface and performs control and monitoring. The MCU module 100 outputs the electronic load voltage setting signal to the electronic load module 500 through the DAC module 600. The electronic load module 500 adjusts the load current to a preset value based on the received analog signal. The signal generation module 200 generates an AC test signal of a specific frequency. The power operational amplifier module 300 amplifies the AC test signal output by the signal generation module 200 and amplifies the DC voltage force signal output by the amplification circuit unit, thereby outputting a power supply with a test signal to the power supply chip 900 under test. The buffer circuit module 400 acquires the input and output signals of the power supply chip 900 under test and performs signal buffering processing. The ADC module 700 receives the buffered signal through its first and second input terminals and converts the analog signal into a digital signal, which is then transmitted to the MCU module 100 for processing. The MCU module 100 evaluates the PSRR parameter performance of the power supply chip 900 under test, thereby achieving effective detection of the PSRR parameter of the power supply chip. The PSRR parameter of the power supply chip at the corresponding frequency can be tested by directly sending commands, simplifying the test process. It has little impact on the input and output signals, reduces test costs, and improves measurement accuracy and test efficiency.

[0050] Please refer to Figure 3 and Figure 4 The signal generation module 200 uses an AD9834CRUZ chip, and the power operational amplifier module 300 uses an ADA4870ACPZ chip. During the PSRR parameter detection of the power chip, it is necessary to continuously generate test signals of different amplitudes at multiple frequencies. The signal generation module 200 uses the AD9834CRUZ chip as its core, which supports a maximum output signal of 75MHz, meeting the maximum 10MHz testing requirements in actual testing. During testing, the power chip under test 900 also needs sufficient power to superimpose the test signal; the power operational amplifier module 300 uses the ADA4870ACPZ chip as its core component. This chip has a maximum output current of 1.1A and features high bandwidth and high slew rate, meeting the current maximum 1A testing environment.

[0051] Please refer to Figure 2 and Figure 5Because the signal to be tested is very sensitive and cannot be directly measured using an ADC, an additional buffer circuit module 400 was designed. The core component used in the buffer circuit module 400 is the THS4551IDGKR chip, which features high bandwidth and high slew rate, enabling buffering and amplification of high-speed signals. A DC blocking capacitor C1600 is designed at the signal input to reduce the impact on the original signal.

[0052] Please refer to Figure 6 and Figure 7 The electronic load module 500 includes a first load unit 510 and a second load unit 520. The first load unit 510 includes a first operational amplifier chip U1101A and a second operational amplifier chip U1101B. The second load unit 520 includes a first NMOS transistor Q1100 and an instrumentation amplifier chip U1102. The first operational amplifier chip U1101A is connected to the first NMOS transistor, and the instrumentation amplifier chip U1102 is used to output a feedback signal. Using the first NMOS transistor Q1100 as an adjustment transistor, the voltage across resistor R1108 is continuously adjusted to ensure that the set load current is at a specified value. Simultaneously, the instrumentation amplifier chip U1102 is used as the feedback signal output to achieve closed-loop current control and adjust the load current to the preset value.

[0053] Please refer to Figure 1 and Figure 2 The DAC module 600 uses the AD5696BRUZ DAC chip. This DAC chip features four output channels, 16-bit data resolution, an external 2.5V reference source, and an IIC serial data communication interface, enabling various digital-to-analog conversion functions. The DAC module 600 is responsible for converting digital signals into analog signals for precise control of the electronic load module 500. As the core of the DAC module 600, the DAC chip provides four channels of high-resolution digital-to-analog conversion capability, ensuring signal conversion accuracy and meeting diverse needs. The converted analog signal is output from the DAC module 600 to the electronic load module 500. The electronic load module 500 adjusts the load current based on the received analog signal, making the entire circuit more stable and easier to control.

[0054] Please refer to Figure 1 and Figure 2The ADC module 700 is a high-speed ADC, employing the ADC3682 chip. This ADC chip features two input channels, 18-bit data resolution, an on-chip 1.6V reference source, SPI and LVDS interfaces, and a maximum sampling rate of 25 MSPS. The ADC module 700 receives buffered signals through its first and second input terminals and converts the analog signals into digital signals. The use of the high-speed ADC chip ADC3682 achieves fast and accurate signal conversion. Through buffering and high-speed conversion, it achieves high-quality signal transmission and processing, ensuring the reliability and efficiency of the detection results, and improving measurement accuracy and response speed.

[0055] Please refer to Figure 8 The PSRR parameter detection circuit also includes a power supply filtering module 810, which comprises multiple parallel-connected filter capacitors used to filter out external power supply interference signals. After the external power supply is input, it passes through a series of capacitors and inductors, filtering out most of the external interference signals and ensuring the stability of the power supply in the test section.

[0056] Please refer to Figure 9 The power chip PSRR parameter detection circuit also includes a positive voltage LDO power module 820. The positive voltage LDO power module 820 includes a first voltage regulator chip U800, a first resistor R806, a second resistor R809, a first filter capacitor C831, and a second filter capacitor C833. The first resistor R806 and the first filter capacitor C831 are connected to the input terminal of the first voltage regulator chip U800, and the second resistor R809 and the second filter capacitor C833 are connected to the output terminal of the first voltage regulator chip U800. The first resistor R806 and the first filter capacitor C831 form the input terminal filtering circuit. The model of the first voltage regulator chip U800 is LT3045EMSE#PBF. After the 3.3V power supply is input, it first passes through the input terminal filtering circuit to reduce input noise, then passes through the first voltage regulator chip U800, and then passes through the ninth filter capacitor C832 for filtering, outputting a stable 2V positive voltage.

[0057] Please refer to Figure 10The power chip PSRR parameter detection circuit also includes a negative voltage LDO power module 830. The negative voltage LDO power module 830 includes a second voltage regulator chip U801, a third resistor R810, a fourth resistor R813, a third filter capacitor C834, and a fourth filter capacitor C836. The third resistor R810 and the third filter capacitor C834 are connected to the input terminal of the second voltage regulator chip U801, and the fourth resistor R813 and the fourth filter capacitor C836 are connected to the setting terminal of the second voltage regulator chip. The first resistor R810 and the first filter capacitor C834 form the input terminal filtering circuit. The model of the first voltage regulator chip U800 is LT3094EMSE#PBF. After the negative 9V power supply is input, it first passes through the input terminal filtering circuit to reduce input noise, then passes through the second voltage regulator chip U801, and then passes through the tenth filter capacitor C835 for filtering, outputting a stable 2V negative voltage.

[0058] Please refer to Figure 11 The power supply chip's PSRR parameter detection circuit also includes a reference voltage module 840. The reference voltage module 840 includes a third voltage regulator chip U900, a fifth filter capacitor C900, a sixth filter capacitor C901, a seventh filter capacitor C902, and an eighth filter capacitor C903. The fifth and sixth filter capacitors, connected in parallel, are connected to the input terminal of the third voltage regulator chip, while the seventh and eighth filter capacitors, also connected in parallel, are connected to the output terminal of the third voltage regulator chip. The third voltage regulator chip U900 is model REF2025AIDDCR. After the 5V power supply is input, it first passes through the fifth filter capacitor C900 and the sixth filter capacitor C901 at the input terminal to reduce input noise. Then, it passes through the third voltage regulator chip U900 and is filtered by the seventh and eighth filter capacitors C902 and C903, outputting a stable 2.5V voltage. This voltage is used to bias the operational amplifier output to ensure that the operational amplifier can output a voltage of 0V or lower.

[0059] This embodiment also discloses an automated testing device, including the aforementioned power chip PSRR parameter detection circuit. The power chip PSRR parameter detection circuit can be integrated into a single test board, which can be easily embedded into an automated testing device to achieve automated batch testing on the production line. Through optimized selection of key signals, the impact on input and output signals is minimal; the testing process is simplified, and commands can be directly sent to test the PSRR parameters of the power chip at the corresponding frequency. Furthermore, FFT processing can be performed on the test data to extract the target signal, reducing the impact of external interference on the test data.

[0060] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present utility model.

Claims

1. A power supply chip PSRR parameter detection circuit, characterized in that, include: MCU module (100), the MCU module (100) is provided with SPI interface, I2C interface and LVDS interface; A signal generation module (200) is provided, the input of which is connected to the SPI interface; A power operational amplifier module (300) is provided, the input of which is connected to the output of the signal generation module (200). A buffer circuit module (400) is provided, wherein the first input terminal of the buffer circuit module (400) is used to acquire the first input signal of the power chip under test (900), and the second input terminal of the buffer circuit module (400) is used to acquire the first output signal of the power chip under test (900). An electronic load module (500) is provided, the input terminal of which is connected to the current output terminal of the power supply chip (900) under test. The electronic load module (500) is used to adjust the load current to a preset value. A DAC module (600) is provided, wherein the input terminal of the DAC module (600) is connected to the I2C interface, and the output terminal of the DAC module (600) is connected to the voltage setting terminal of the electronic load module (500). An ADC module (700) is provided, wherein the first input terminal and the second input terminal of the ADC module (700) are respectively connected to the first output terminal and the second output terminal of the buffer circuit module (400), and the output terminal of the ADC module (700) is connected to the LVDS interface.

2. The power chip PSRR parameter detection circuit according to claim 1, characterized in that, The signal generation module (200) uses a chip of model AD9834CRUZ, and the power operational amplifier module (300) uses a chip of model ADA4870ACPZ.

3. The power chip PSRR parameter detection circuit according to claim 1, characterized in that, The electronic load module (500) includes a first operational amplifier chip, a first NMOS transistor, and an instrumentation amplifier chip. The first operational amplifier chip is connected to the first NMOS transistor, which is a regulating transistor. The instrumentation amplifier chip is used to output a feedback signal.

4. The power chip PSRR parameter detection circuit according to claim 1, characterized in that, The DAC module (600) uses a chip with the model number AD5696BRUZ.

5. The power chip PSRR parameter detection circuit according to claim 4, characterized in that, The ADC module (700) is a high-speed ADC, using a chip with the model number ADC3682.

6. The power chip PSRR parameter detection circuit according to claim 1, characterized in that, The power chip PSRR parameter detection circuit also includes a power filtering module (810), which includes multiple parallel-connected filter capacitors for filtering out external power interference signals.

7. The power chip PSRR parameter detection circuit according to claim 1, characterized in that, The power chip PSRR parameter detection circuit also includes a positive voltage LDO power module (820). The positive voltage LDO power module (820) includes a first voltage regulator chip, a first resistor, a second resistor, a first filter capacitor, and a second filter capacitor. The first resistor and the first filter capacitor are connected to the input terminal of the first voltage regulator chip, and the second resistor and the second filter capacitor are connected to the setting terminal of the first voltage regulator chip.

8. The power chip PSRR parameter detection circuit according to claim 7, characterized in that, The power chip PSRR parameter detection circuit also includes a negative voltage LDO power module (830). The negative voltage LDO power module (830) includes a second voltage regulator chip, a third resistor, a fourth resistor, a third filter capacitor, and a fourth filter capacitor. The third resistor and the third filter capacitor are connected to the input terminal of the second voltage regulator chip, and the fourth resistor and the fourth filter capacitor are connected to the setting terminal of the second voltage regulator chip.

9. The power chip PSRR parameter detection circuit according to claim 8, characterized in that, The power chip PSRR parameter detection circuit also includes a reference voltage module (840). The reference voltage module (840) includes a third voltage regulator chip, a fifth filter capacitor, a sixth filter capacitor, a seventh filter capacitor, and an eighth filter capacitor. The fifth filter capacitor and the sixth filter capacitor, which are connected in parallel, are connected to the input terminal of the third voltage regulator chip. The seventh filter capacitor and the eighth filter capacitor, which are connected in parallel, are connected to the output terminal of the third voltage regulator chip.

10. An automated testing device, characterized in that, Includes the power chip PSRR parameter detection circuit as described in any one of claims 1 to 9.

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