Data caching apparatus, method, integrated circuit chip, computing apparatus and board
By using a data caching device composed of multi-dimensional read and write pointers, the problem of existing FIFO caches being unable to meet flexible access needs is solved, achieving efficient data access and flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CAMBRICON TECH CO LTD
- Filing Date
- 2020-12-22
- Publication Date
- 2026-07-24
AI Technical Summary
The existing FIFO buffer's access method cannot meet the needs of flexible data access, and cannot achieve arbitrary writing and reading of data.
A data caching device consisting of multiple read pointers and write pointers allows data to be stored and retrieved in multi-dimensional storage blocks. Arbitrary data storage and retrieval can be achieved through independent operation of the write pointer group and the read pointer group.
It improves the access speed and flexibility of the data caching device, supports arbitrary data storage and retrieval, and meets various data storage needs.
Smart Images
Figure CN114661634B_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to the field of data storage. More specifically, this disclosure relates to data caching devices, methods, integrated circuit chips, computing devices, and circuit boards. Background Technology
[0002] Currently, in system design, FIFO (First Input First Output) buffers are widely used to increase data transfer rates, handle large data streams, and match systems with different transfer rates, thereby improving system performance. A FIFO data buffer is a first-in, first-out data buffer where data is read from the buffer in the order it is written; that is, data written first is read from the buffer first, and data written later is read from the buffer last.
[0003] However, as the demands on buffers increase in various operations, the access methods of existing FIFO buffers cannot meet practical needs. Therefore, how to obtain a buffer with flexible access methods has become a problem that needs to be solved in the existing technology. Summary of the Invention
[0004] In order to at least partially solve the technical problems mentioned in the background art, the present disclosure provides a data caching device and method thereof, an integrated circuit chip including the data caching device, a computing device and a board.
[0005] In one aspect, this disclosure provides a data caching device, wherein the data caching device includes: a data caching unit comprising a plurality of storage blocks for storing data; the data caching unit storing data in storage blocks each pointed to by at least one set of write pointers; the data caching unit outputting data from read-read spaces each pointed to by a plurality of sets of read pointers; wherein each of the at least one set of write pointers includes write pointers in at least two dimensions, and each of the plurality of sets of read pointers includes read pointers in at least two dimensions.
[0006] In another aspect, this disclosure provides a data caching method for reading and writing data in a data caching device, the data caching device including a data caching unit, the data caching unit including a plurality of storage blocks for storing data, wherein the data caching method includes: storing data in storage blocks each pointed to by at least one group of write pointers each including at least two dimensions; and outputting data from read-read spaces each pointed to by a plurality of read pointer groups each including at least two dimensions.
[0007] In another aspect, this disclosure provides an integrated circuit chip that includes the aforementioned data cache device. In yet another embodiment, the data cache device of this disclosure can be configured as a standalone integrated circuit chip.
[0008] In another aspect, this disclosure provides a computing device that includes the aforementioned data cache device or the aforementioned integrated circuit chip.
[0009] In another aspect, this disclosure provides a board that includes the aforementioned computing device.
[0010] By utilizing the data caching device, corresponding caching method, integrated circuit chip, computing device, and board disclosed herein, arbitrary writing and reading of data can be achieved by employing multiple read pointers and write pointers. Therefore, the data caching device of this disclosure is flexible and can be widely applied to various data storage applications. Attached Figure Description
[0011] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:
[0012] Figure 1 This is a schematic block diagram illustrating a data caching apparatus according to an embodiment of the present disclosure;
[0013] Figure 2 This is a schematic diagram illustrating a data caching unit according to an embodiment of the present disclosure;
[0014] Figure 3 This is a schematic block diagram illustrating a data caching apparatus according to another embodiment of the present disclosure;
[0015] Figure 4 This is a schematic diagram illustrating an instruction cache unit according to an embodiment of the present disclosure;
[0016] Figure 5 This is a flowchart illustrating a data caching method according to an embodiment of the present disclosure;
[0017] Figure 6 This is a flowchart illustrating a data caching method according to another embodiment of the present disclosure;
[0018] Figure 7 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and
[0019] Figure 8 This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation
[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0021] The technical solution disclosed herein provides a data caching device, method, integrated circuit chip, computing device, and board as a whole. Unlike existing data caching devices, this disclosure provides a data caching device capable of multiple reads and writes, thereby improving access speed. Specifically, this disclosure allows for arbitrary storage and retrieval of data within the data caching device, with storage and retrieval occurring independently. Therefore, the data caching device of this disclosure features high access speed and high flexibility.
[0022] Figure 1 This is a schematic block diagram illustrating a data caching device 100 according to one embodiment of the present disclosure. Figure 1 As shown, the data caching device 100 may include a data caching unit 101. The data caching unit 101 includes multiple storage blocks for storing data. The data caching unit 101 stores data in storage blocks pointed to by at least one set of write pointers. The data caching unit 101 outputs data from read-read spaces pointed to by multiple sets of read pointers. Each of the at least one set of write pointers includes write pointers in at least two dimensions, and each of the multiple sets of read pointers includes read pointers in at least two dimensions.
[0023] In one embodiment, the data cache unit 101 may have multiple storage rows, each storage row comprising multiple storage blocks, and all storage blocks in the data cache unit 101 have the same storage space. Thus, these storage blocks can form a storage array. Therefore, the data cache unit 101 can constitute a two-dimensional data cache unit.
[0024] Furthermore, for this data cache unit 101, data writing is performed on storage blocks, meaning data can be written to any storage block; therefore, the storage block is the basic unit of writing. Data reading, on the other hand, is performed on the space to be read (a storage space of any size within a storage row); that is, data of any bit width within any storage row can be read. In other words, the space to be read can be located within a storage block, can be a single storage block, or can be a storage space larger than a single storage block; therefore, 1 bit is the basic unit of reading.
[0025] Therefore, one or more write pointer groups can write data to the memory blocks they point to, and multiple read pointer groups can read data from the memory spaces they point to. Each write pointer group includes two write pointers, and each read pointer group includes two read pointers. It should be noted that write pointer groups and read pointer groups can operate independently.
[0026] In another embodiment, the data cache unit 101 may include multiple storage slices, and each storage slice may include multiple storage rows, and each storage row may include multiple storage blocks. In this case, the data cache unit is a three-dimensional storage unit. Therefore, each write pointer group may each include three-dimensional write pointers, and each read pointer group may each include three-dimensional read pointers.
[0027] Similarly, the higher the dimension of the data cache unit, that is, the more storage layers there are, the larger the dimension of the pointer group.
[0028] Furthermore, when at least one write pointer group each includes write pointers in two dimensions and multiple read pointer groups each include read pointers in two dimensions, at least one write pointer group may each include a row write pointer and a column write pointer, the row write pointer and the column write pointer can jointly determine the memory block to which it points; multiple read pointer groups may each include a row read pointer and a column read pointer, the row read pointer and the column read pointer can jointly determine the start position of the read space to be read, and the read control signal corresponding to the read pointer group indicates the bit width of the space to be read.
[0029] Specifically, you can refer to Figure 2 , Figure 2 This is a schematic diagram illustrating a data caching unit 101 according to an embodiment of the present disclosure. Figure 2 The diagram illustrates, for example, that the data cache unit 101 is an N×4 storage matrix, where N is the number of storage rows. Furthermore, Figure 2 Two sets of write pointers are shown. One set includes a row write pointer Wr0 and a column write pointer Wc0, while the other set includes a row write pointer Wr1 and a column write pointer Wc1. The row write pointers Wr0 and Wr1 point to the row containing the data to be written, and the column write pointers Wc0 and Wc1 point to the column containing the data to be written. Therefore, the row write pointers Wr0 and Wr1 and the column write pointers Wc0 and Wc1 in each set can collectively determine the specific memory block they point to.
[0030] Furthermore, the data cache unit 101 can also be regarded as an N×M storage matrix, where N is the number of storage rows and M is the number of storage bits (bit width) in each storage row. Figure 2Two sets of read pointers are also shown: one set includes a row read pointer Rr0 and a column read pointer Rc0, and the other set includes a row read pointer Rr1 and a column read pointer Rc1. In each set, the row read pointers Rr0 and Rr1 point to the row containing the data to be read, and the column read pointers Rc0 and Rc1 point to the column containing the starting storage bit of the data to be read. Therefore, the row read pointers Rr0 and Rr1 and the column read pointers Rc0 and Rc1 in each set can jointly determine the starting position of the read space. Furthermore, the read control signal corresponding to the read pointer set can indicate the bit width of the read space, thereby determining the bit width of the data to be read.
[0031] It should be noted that Figure 2 The two write pointer groups and the two read pointer groups are shown only by way of example, and this disclosure is not limited thereto.
[0032] To enable more flexible reading and writing of data, multiple write pointer groups can each point to different storage blocks; the multiple read pointer groups can each point to a space to be read.
[0033] In this embodiment, when there are multiple write pointer groups, each write pointer group points to a different memory block. This allows for simultaneous writing of data to different memory blocks and avoids data loss caused by repeatedly writing different data to the same memory block under a single instruction. Multiple read pointer groups can each point to a different space to be read, meaning each read pointer group can point to a different space, or at least two read pointer groups can point to the same space. This allows at least two read pointer groups to read data from the same space, thus achieving data sharing. Figure 2 The data cache unit 101 shown has two write pointer groups pointing to different memory blocks and two read pointer groups pointing to different spaces to be read. Of course, the two read pointer groups can also point to the same space to be read.
[0034] When writing data to the storage block in the data cache unit, it should be noted that when the storage block pointed to by the write pointer group is empty, the data cache unit 101 can store data in the storage block; when the storage block pointed to by the write pointer group contains data, the data cache unit 101 can wait for the data in the storage block to be cleared.
[0035] In this embodiment, when writing data to the data cache unit 101, unused or still needed data should be avoided from being overwritten. In the data cache unit 101, data in a storage block that has been used up will be cleared. Therefore, for example, refer to... Figure 2If the memory block pointed to by the write pointer group is empty, data can be written to that memory block; if data exists in that memory block, it means that the data has not been used up or has not been cleared yet, so it is necessary to wait for the data in that memory block to be cleared before writing the data to that memory block.
[0036] When reading data from the data cache unit, it should be noted that when the space to be read pointed to by the read pointer is empty or has not been written, the data cache unit 101 waits for the space to be read to be written; when the space to be read pointed to by the read pointer group has been written, the data cache unit 101 outputs the data of the space to be read according to the number of reads indicated by the read control signal corresponding to the read pointer group.
[0037] In this embodiment, when reading data from the data cache unit, it should be ensured that the data in the space to be read is completely present. For example, refer to... Figure 2 If the space pointed to by the read pointer group does not contain data or is being written, the system must wait until the data is completely written into the space before reading it. If the space contains complete data, it can be read. It should be noted that the same read pointer group can read data from the same space multiple times based on the read control signal to reuse the same data. It should also be noted that when data in a memory block is no longer accessed in subsequent reads (i.e., no longer used), the data in that memory block should be cleared.
[0038] Furthermore, the data caching unit 101 may include a counting module. The data caching unit 101 can determine whether the read operation has been completed by counting the data from the counting module.
[0039] In this embodiment, to determine whether the read count is complete, the data cache unit 101 may include a counting module. This counting module can count the number of reads indicated by the read control signal. When the count is complete, the read count is considered complete.
[0040] In addition, when at least two read pointer groups point to the same space to be read, the counting module counts the number of reads indicated by the read control signals corresponding to each of the at least two read pointer groups.
[0041] In this embodiment, for example, refer to Figure 2 When the read pointer groups need to read data from the same read space, the counting module can count the number of reads indicated by the read control signal corresponding to each read pointer group.
[0042] In order to write data to any storage block in the data cache unit and to read data from any read space in the data cache unit, the write pointer group determines the storage block to be pointed to based on the row step size and column step size indicated by the corresponding write control signal; the read pointer group determines the read start position to be pointed to based on the row step size and column step size indicated by the corresponding read control signal.
[0043] In this embodiment, when the data cache unit initially operates, the write pointer group and the read pointer group can be initialized to point to the starting position of the data cache unit (e.g., the position of the first storage bit in the first storage block of the first row and first column). Subsequently, the write pointer group and the read pointer group can determine the storage block to be pointed to and the space to be read based on the step size indicated by the corresponding write control signal and read control signal. That is, the write pointer group and the read pointer group can determine the storage block to be pointed to and the space to be read based on the storage block to be pointed to and the step size indicated by the current write control signal and read control signal.
[0044] The range of the row step size for the row write pointer and the column step size for the column write pointer can be set according to the number of rows and columns of the storage matrix formed by the storage blocks. This ensures that the row write pointer and the column write pointer can point to any row and column according to the write control signal, thus jointly identifying any storage block. For example, the range of the row step size can be set to 0 to n-1, and the range of the column step size can be set to 0 to m-1, where n represents the number of rows in the storage matrix formed by the storage blocks, and m represents the number of columns in the storage matrix formed by the storage blocks.
[0045] For example, if the number of storage rows in the data cache unit is 100, and the row write pointer originally pointed to the 5th storage row, then if the row step size is 8, it will point to the 13th storage row. Furthermore, when the row step size is 0, it means the storage row pointed to by the row write pointer remains unchanged, i.e., it still points to the original storage row. When the row step size is n-1, it means the storage row the row write pointer will point to is the adjacent storage row above the original storage row. For example, if the number of storage rows in the data cache unit is 100, and the row write pointer originally pointed to the 5th storage row, then if the row step size is 99, it will point to the 4th storage row. Therefore, for each row step size, the counting of storage rows in the data cache unit proceeds cyclically from the first storage row to the last storage row; that is, when the index of the original storage row plus the row step size is greater than the index of the last storage row, the counting continues from the first storage row to the last storage row.
[0046] For example, if the number of storage columns in a data cache unit is 100, and the column write pointer originally pointed to column 5, then if the column step size is 8, the next storage column it will point to will be column 13. Furthermore, when the column step size is 0, it means the storage column pointed to by the column write pointer remains unchanged, i.e., it still points to the original storage column. When the column step size is m-1, it means the storage column the column write pointer will point to is the adjacent storage column above the original storage column. For example, if the number of storage columns in a data cache unit is 100, and the column write pointer originally pointed to column 5, then if the column step size is 99, the next storage column it will point to will be column 4. Therefore, for each column step size, the counting of storage columns in the data cache unit proceeds cyclically from the first storage column to the last storage column; that is, when the index of the originally pointed-to storage column plus the column step size is greater than the index of the last storage column, the counting continues from the first storage column to the last storage column.
[0047] The range of the row step size for the row read pointer and the column step size for the column read pointer can be set according to the number of rows and columns of the storage matrix formed by the storage bits. This ensures that the row read pointer and the column read pointer can point to any row and column according to the read control signal, thus jointly determining any space to be read. For example, the range of the row step size can be set to 0 to x-1, and the range of the column step size can be set to 0 to y-1, where x represents the number of rows in the storage matrix formed by the storage bits, and y represents the number of columns in the storage matrix formed by the storage bits. The specific description is similar to the description of the row write pointer and the column write pointer above, and will not be repeated here.
[0048] As can be seen from the above, there can be multiple write pointer groups and read pointer groups; however, the data buffer unit 101 may include at least one data input port and at least one data output port.
[0049] In one embodiment, the data cache unit 101 may include multiple data input ports and multiple data output ports. The data cache unit 101 can store data in parallel through the multiple data input ports according to the write control signal; the data cache unit 101 can output data in parallel through the multiple data output ports according to the read control signal.
[0050] In this embodiment, the data buffer unit 101 may have multiple data input ports and multiple data output ports. Therefore, the number of data input ports may correspond to the number of write pointer groups, and the number of data output ports may correspond to the number of read pointer groups. Thus, write pointer groups can write data in parallel through the data input ports, and read pointer groups can read data in parallel through the data output ports.
[0051] In another embodiment, the data buffer unit 101 may include a data input port and a data output port. The data buffer unit 101 can serially store data through a data input port according to a write control signal; the data buffer unit 101 can serially output data through a data output port according to a read control signal.
[0052] In this embodiment, the data cache unit 101 may have only one data input port and one data output port. Therefore, multiple write pointer groups share one data input port, and multiple read pointer groups share one data output port. Thus, data can be serially passed through the data input port and written into the memory blocks pointed to by the multiple write pointer groups, and data can be read from the read space pointed to by the multiple read pointer groups and output serially through the data output port.
[0053] Of course, the number of data input ports and data output ports may not correspond to the number of write pointer groups and may not be a single group. In this case, when the number of data input ports is less than the number of write pointer groups, some write pointer groups can share a single data input port, while others can each use a separate data input port. Similarly, when the number of data output ports is less than the number of read pointer groups, some read pointer groups can share a single data output port, while others can each use a separate data output port. Thus, a combination of serial and parallel methods can be used to store and output data through the data input and data output ports.
[0054] Reference Figure 3 , Figure 3 This is a schematic block diagram illustrating a data caching device 200 according to another embodiment of the present disclosure. Figure 3 The data cache device 200 shown is Figure 1 The difference between the data cache device 100 shown is that the data cache device 200 may further include an instruction cache unit 201. The instruction cache unit 201 can be used to receive external instructions and parse at least one write control signal and multiple read control signals according to the external instructions, wherein each write control signal includes a write pointer group and each read control signal includes a read pointer group.
[0055] In this embodiment, the data caching device 200 may further include an instruction cache unit 201 for caching external instructions. Specifically, the external instructions in the instruction cache unit 201 can control data reading and writing to the data cache unit 101. Specifically, the instruction cache unit 201 can receive and parse external instructions to obtain at least one write control signal and multiple read control signals for the data cache unit 101. Each write control signal includes a write pointer group, and each read control signal includes a read pointer group. Furthermore, each write control signal includes the aforementioned step size, and each read control signal includes the aforementioned step size and the number of reads.
[0056] Furthermore, the external instructions include write instructions and read instructions, and the instruction cache unit 201 includes at least one write instruction cache unit and multiple read instruction cache units; each write instruction cache unit is used to receive and store the write instructions, and parse a write control signal according to each write instruction; each read instruction cache unit is used to receive and store the read instructions, and parse a read control signal according to each read instruction.
[0057] Specifically, you can refer to Figure 4 , Figure 4 This is a schematic diagram illustrating an instruction cache unit 201 according to an embodiment of the present disclosure. Figure 4 As shown, external instructions can be divided into write instructions w_inst and read instructions r_inst. Instruction cache unit 201 can include multiple write instruction cache units and multiple read instruction cache units. Both the multiple write instruction cache units and the multiple read instruction cache units can be FIFO (First-In-First-Out) buffers. The write instruction cache unit can receive and store the write instruction w_inst, and the read instruction cache unit can receive and store the read instruction r_inst. The number of write instruction cache units corresponds to the number of write pointer groups, and the number of read instruction cache units corresponds to the number of read pointer groups. Each write instruction cache unit can parse the write control signals w_ctrl_0-w_ctrl_n from the top-ranked write instruction according to the first-in-first-out principle, and each read instruction cache unit can parse the read control signals r_ctrl_0-r_ctrl_n from the top-ranked read instruction according to the first-in-first-out principle. Among them, the write instruction and read instruction include a wait instruction. When the number of memory lines to be read or written is less than the number of write instruction cache units and read instruction cache units, the control signals parsed by some write instruction cache units and / or some read instruction cache units are wait signals, and no operation is performed.
[0058] This disclosure also provides a data caching method for reading and writing data in a data caching device. (See reference...) Figure 5 , Figure 5 This is a flowchart illustrating a data caching method according to an embodiment of the present disclosure. Figure 5 As shown, it can be understood that the data caching device used in this data caching method is the one mentioned above. Figures 1-4 The data caching device is described in detail, and therefore the preceding description of the data caching device and its internal components, functions and operations also apply to the description herein.
[0059] The data caching method disclosed herein is applied to the aforementioned data caching apparatus. The data caching apparatus includes a data caching unit, which comprises multiple storage blocks for storing data. Therefore, the data caching method includes the following steps S101-S102.
[0060] In step S101, data is stored in a storage block pointed to by at least one group of write pointers, each comprising at least two dimensions.
[0061] In step S102, data is output from the space to be read, which is pointed to by a plurality of read pointer groups, each of which includes read pointers in at least two dimensions.
[0062] According to embodiments of this disclosure, each of the at least one write pointer group includes a row write pointer and a column write pointer, the row write pointer and the column write pointer jointly determine the memory block to which it points; each of the plurality of read pointer groups includes a row read pointer and a column read pointer, the row read pointer and the column read pointer jointly determine the read start position of the space to be read, and the read control signal corresponding to the read pointer group indicates the bit width of the space to be read.
[0063] According to embodiments of this disclosure, multiple write pointer groups each point to different memory blocks; the multiple read pointer groups each point to a space to be read.
[0064] According to an embodiment of this disclosure, when the storage block pointed to by the write pointer group is empty, the data cache unit stores data in the storage block; when the storage block pointed to by the write pointer group contains data, the data cache unit waits for the data in the storage block to be cleared.
[0065] According to an embodiment of this disclosure, when the space to be read pointed to by the read pointer group is empty or has not been written with data, the data cache unit waits for the space to be written with data; when the space to be read pointed to by the read pointer group contains data that has been written with data, the data cache unit outputs the data of the space to be read according to the number of reads indicated by the read control signal corresponding to the read pointer group.
[0066] According to embodiments of this disclosure, the counting module of the data cache unit can be used to count the data cache unit to determine whether the reading count is complete.
[0067] According to an embodiment of this disclosure, when at least two of the read pointer groups point to the same space to be read, the counting module counts the number of reads indicated by the read control signal corresponding to each of the at least two read pointer groups.
[0068] According to embodiments of this disclosure, the write pointer group determines the memory block to which it points based on the row step size and column step size indicated by the corresponding write control signal; the read pointer group determines the read start position to which it points based on the row step size and column step size indicated by the corresponding read control signal.
[0069] According to embodiments of this disclosure, data is stored in parallel through multiple data input ports of the data buffer unit according to a write control signal; and data is output in parallel through multiple data output ports of the data buffer unit according to a read control signal.
[0070] According to embodiments of this disclosure, data is serially stored through a data input port of the data buffer unit according to a write control signal; and data is serially output through a data output port of the data buffer unit according to a read control signal.
[0071] Reference Figure 6 , Figure 6 This is a flowchart illustrating a data caching method according to another embodiment of the present disclosure. Figure 6 As shown, the data caching method may further include step S201 before step S101. In step S201, an external instruction is received using the instruction cache unit of the data caching device, and at least one write control signal, each including a write pointer group, and multiple read control signals, each including a read pointer group, are parsed according to the external instruction.
[0072] According to embodiments of this disclosure, the external instructions include write instructions and read instructions, and the instruction cache unit includes at least one write instruction cache unit and multiple read instruction cache units; each write instruction cache unit is used to receive and store the write instructions, and parse a write control signal according to each write instruction; each read instruction cache unit is used to receive and store the read instructions, and parse a read control signal according to each read instruction.
[0073] In the above embodiments of this disclosure, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.
[0074] Figure 7This is a structural diagram illustrating a combined processing apparatus 700 according to an embodiment of the present disclosure. As shown, the combined processing apparatus 700 includes a computing device 702, which may include the data caching device of the present disclosure as described above in conjunction with the accompanying drawings. Additionally, the combined processing apparatus includes a general interconnect interface 704 and other processing devices 706. The computing device according to the present disclosure interacts with other processing devices to jointly complete user-specified operations.
[0075] According to the scheme of this disclosure, the other processing device may include one or more types of processors such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a neural network processor, and other general-purpose and / or special-purpose processors, and the number is not limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the computing device of this disclosure (which may be embodied as a machine learning computing device) and external data and control, performing tasks including but not limited to data transfer, and completing basic control such as starting and stopping the machine learning computing device; the other processing device may also cooperate with the machine learning computing device to jointly complete computing tasks.
[0076] According to the present disclosure, the universal interconnect interface can be used to transfer data and control commands between a computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnect interface and write it to on-chip storage. Furthermore, the computing device can obtain control commands from other processing devices via the universal interconnect interface and write them to on-chip control cache. Alternatively or optionally, the universal interconnect interface can also read data from the computing device's storage module and transmit it to other processing devices.
[0077] Optionally, the combined processing apparatus may further include a storage device 708, which may be connected to the computing device and the other processing device respectively. In one or more embodiments, the storage device may be used to store data from the computing device and the other processing device, particularly suitable for data that cannot be fully stored in the internal storage of the computing device or other processing device, requiring computation.
[0078] Depending on the application scenario, the combined processing device disclosed herein can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, video capture equipment, and video surveillance equipment. This effectively reduces the core area of the control unit, increases processing speed, and lowers overall power consumption. In this case, the general-purpose interconnect interface of the combined processing device connects to certain components of the device. These components may include, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface.
[0079] In some embodiments, this disclosure also discloses a chip or integrated circuit chip that includes the aforementioned computing device, combined processing device, and data cache device. In other embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip.
[0080] In some embodiments, this disclosure also discloses a circuit board that includes the above-described chip packaging structure. See also... Figure 8 The aforementioned exemplary board is provided. In addition to the chip 802, the board may also include other supporting components, including but not limited to: storage device 804, interface device 806, and controller 808.
[0081] The storage device is connected to the chip within the chip package structure via a bus and is used to store data. The storage device may include multiple sets of storage cells 810. Each set of storage cells is connected to the chip via a bus. It can be understood that each set of storage cells may be DDR SDRAM (“Double Data Rate SDRAM”).
[0082] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include four groups of memory cells. Each group of memory cells may include multiple DDR4 chips. In one embodiment, the chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.
[0083] In one embodiment, each group of memory cells may include multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the chip for controlling the data transfer and data storage of each memory cell.
[0084] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to realize data transmission between the chip and an external device 812 (e.g., a server or computer). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the chip are still transmitted back to the external device (e.g., the server) by the interface device.
[0085] The controller is electrically connected to the chip to monitor its status. Specifically, the chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller ("MCU"). The chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Thus, the chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the chip.
[0086] In some embodiments, this disclosure also discloses an electronic device or apparatus that includes the aforementioned circuit board. Depending on the application scenario, the electronic device or apparatus may include a data processing device, robot, computer, printer, scanner, tablet computer, smart terminal, mobile phone, dashcam, navigator, sensor, camera, server, cloud server, camera, camcorder, projector, watch, earphone, mobile storage, wearable device, vehicle, home appliance, and / or medical device. The vehicle includes airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs.
[0087] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.
[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0089] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the circuit division is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple circuits or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections between devices or circuits through some interfaces, and may be electrical, optical, acoustic, magnetic, or other forms.
[0090] The circuit described as a separate component may or may not be physically separate. The components shown as circuits may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0091] Furthermore, the functional circuits in the various embodiments of this disclosure can be integrated into one processing unit, or each circuit can exist physically separately, or two or more circuits can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.
[0092] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, when the technical solution of this disclosure can be embodied in the form of a software product, the computer software product is stored in a storage device and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage device includes various media capable of storing program code, such as a USB flash drive, read-only memory ("ROM"), random access memory ("RAM"), portable hard drive, magnetic disk, or optical disk.
[0093] The foregoing can be better understood in accordance with the following terms:
[0094] Clause A1, a data caching device, wherein the data caching device comprises: a data caching unit including a plurality of storage blocks for storing data; the data caching unit storing data in storage blocks each pointed to by at least one set of write pointers; the data caching unit outputting data from read-read spaces each pointed to by a plurality of sets of read pointers; wherein each of the at least one set of write pointers includes write pointers in at least two dimensions, and each of the plurality of sets of read pointers includes read pointers in at least two dimensions.
[0095] Clause A2, the data caching device according to Clause A1, wherein each of the at least one write pointer group includes a row write pointer and a column write pointer, the row write pointer and the column write pointer jointly determining the memory block to which it points; each of the plurality of read pointer groups includes a row read pointer and a column read pointer, the row read pointer and the column read pointer jointly determining the read start position of the space to be read, and a read control signal corresponding to the read pointer group indicates the bit width of the space to be read.
[0096] Clause A3, the data caching device according to Clause A2, wherein a plurality of write pointer groups each point to a different memory block; and the plurality of read pointer groups each point to a space to be read.
[0097] Clause A4, the data caching device according to Clause A3, wherein when the memory block pointed to by the write pointer group is empty, the data caching unit stores data in the memory block; when the memory block pointed to by the write pointer group contains data, the data caching unit waits for the data in the memory block to be cleared.
[0098] Clause A5, the data caching device according to Clause A3, wherein when the space to be read pointed to by the read pointer group is empty or has not been written with data, the data caching unit waits for the space to be written with data; when the space to be read pointed to by the read pointer group contains data that has been written with data, the data caching unit outputs the data of the space to be read according to the number of reads indicated by the read control signal corresponding to the read pointer group.
[0099] Clause A6, the data caching device according to Clause A5, wherein the data caching unit includes: a counting module, the data caching unit determining whether the read count has been completed by counting the data in the counting module.
[0100] Clause A7, the data caching device according to Clause A6, wherein when at least two of the read pointer groups point to the same space to be read, the counting module counts the number of reads indicated by the read control signal corresponding to each of the at least two read pointer groups.
[0101] Clause A8, the data caching device according to Clause A3, wherein the write pointer group determines the memory block to which it points based on the row step size and column step size indicated by the corresponding write control signal; and the read pointer group determines the read start position to which it points based on the row step size and column step size indicated by the corresponding read control signal.
[0102] Clause A9, the data caching device according to Clause A3, wherein the data caching device further comprises: an instruction caching unit for receiving external instructions and parsing at least one write control signal and a plurality of read control signals according to the external instructions, wherein each write control signal includes a write pointer group and each read control signal includes a read pointer group.
[0103] Clause A10, the data caching device according to Clause A9, wherein the external instructions include write instructions and read instructions, the instruction caching unit includes at least one write instruction caching unit and a plurality of read instruction caching units; each write instruction caching unit is used to receive and store the write instructions, and parse a write control signal according to each write instruction; each read instruction caching unit is used to receive and store the read instructions, and parse a read control signal according to each read instruction.
[0104] Clause A11, the data caching device according to Clause A3, wherein the data caching unit includes at least one data input port and at least one data output port.
[0105] Clause A12, the data caching device according to Clause A11, wherein the data caching unit includes a plurality of data input ports and a plurality of data output ports, the data caching unit stores data in parallel through the plurality of data input ports according to the write control signal; the data caching unit outputs data in parallel through the plurality of data output ports according to the read control signal.
[0106] Clause A13, the data caching device according to Clause A12, wherein the data caching unit includes a data input port and a data output port, the data caching unit serially stores data through the data input port according to the write control signal; the data caching unit serially stores data through the data output port according to the read control signal.
[0107] Clause A14, a data caching method for reading and writing data in a data caching device, the data caching device including a data caching unit including a plurality of storage blocks for storing data, wherein the data caching method includes: storing data in storage blocks each pointed to by at least one group of write pointers each including at least two dimensions; and outputting data from read-read spaces each pointed to by a plurality of read pointer groups each including at least two dimensions.
[0108] Clause A15, an integrated circuit chip, including a data cache device according to any one of Clauses A1-A13.
[0109] Clause A16, a computing device including a data cache device according to any one of Clauses A1-A13 or an integrated circuit chip according to Clause A15.
[0110] Clause A17, a board including a computing device as described in Clause A16.
[0111] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.
[0112] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.
[0113] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.
[0114] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."
[0115] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.
Claims
1. A data caching device, wherein, The data caching device includes: A data caching unit, which includes multiple storage blocks for storing data; The data cache unit stores data simultaneously in different memory blocks pointed to by multiple write pointer groups; The data buffer unit outputs data from the read space pointed to by each of the multiple read pointer groups; The data cache unit is a storage array. Each of the multiple write pointer groups includes write pointers in at least two dimensions, and each of the multiple read pointer groups includes read pointers in at least two dimensions. The write pointers in each write pointer group are used to jointly determine the storage block to which the data is pointed. Each read pointer group includes read pointers in at least two dimensions to jointly determine the space to be read.
2. The data caching device according to claim 1, wherein, Each of the multiple write pointer groups includes a row write pointer and a column write pointer, and the row write pointer and the column write pointer together determine the memory block to which they point; Each of the multiple read pointer groups includes a row read pointer and a column read pointer. The row read pointer and the column read pointer together determine the starting position of the read space. The read control signal corresponding to the read pointer group indicates the bit width of the read space.
3. The data caching device according to claim 1, wherein, When the storage block pointed to by the plurality of write pointer groups is empty, the data cache unit stores data in the storage block; When the storage block pointed to by the plurality of write pointer groups contains data, the data cache unit waits for the data in the storage block to be cleared.
4. The data caching device according to claim 1, wherein, When the space to be read pointed to by the plurality of read pointer groups is empty or has not been written with data, the data cache unit waits for the space to be read to be written with data. When the space to be read pointed to by the plurality of read pointer groups contains data that has been written, the data cache unit outputs the data in the space to be read according to the number of reads indicated by the read control signal corresponding to the plurality of read pointer groups.
5. The data caching device according to claim 4, wherein, The data caching unit includes: The data cache unit uses the counting module to determine whether the read count has been completed.
6. The data caching device according to claim 5, wherein, When at least two of the read pointer groups point to the same space to be read, the counting module counts the number of reads indicated by the read control signal corresponding to each of the at least two read pointer groups.
7. The data caching device according to claim 1, wherein, The multiple write pointer groups determine the memory block they point to based on the row step size and column step size indicated by the corresponding write control signal; The multiple read pointer groups determine the starting position of the read space they point to based on the row step size and column step size indicated by the corresponding read control signal.
8. The data caching device according to claim 1, wherein, The data caching device further includes: An instruction cache unit is used to receive external instructions and parse multiple write control signals and multiple read control signals according to the external instructions. Each write control signal includes a write pointer group, and each read control signal includes a read pointer group.
9. The data caching device according to claim 8, wherein, The external instructions include write instructions and read instructions, and the instruction cache unit includes multiple write instruction cache units and multiple read instruction cache units; Each write instruction buffer unit is used to receive and store the write instruction, and parse out a write control signal based on each write instruction; Each read instruction buffer unit is used to receive and store the read instruction, and parse a read control signal according to each read instruction.
10. The data caching device according to claim 1, wherein, The data buffer unit includes at least one data input port and at least one data output port.
11. The data caching device according to claim 10, wherein, The data buffer unit includes multiple data input ports and multiple data output ports. The data cache unit stores data in parallel through the multiple data input ports according to the write control signal; The data buffer unit outputs data in parallel through the multiple data output ports according to the read control signal.
12. The data caching device according to claim 11, wherein, The data buffer unit includes a data input port and a data output port. The data cache unit serially stores data through the one data input port according to the write control signal; The data cache unit serially stores data through the one data output port according to the read control signal.
13. A data caching method for reading and writing data in a data caching device, the data caching device comprising a data caching unit, the data caching unit being a storage array, the data caching unit comprising multiple storage blocks for storing data, wherein, The data caching method includes: Data is stored in different memory blocks, each pointed to by a group of write pointers, each comprising a write pointer with at least two dimensions. Data is output from the space to be read, each pointed to by a group of read pointers, each comprising a read pointer with at least two dimensions. Each write pointer group contains at least two write pointers of different dimensions used to jointly determine the memory block to which it points; each read pointer group contains at least two read pointers of different dimensions used to jointly determine the space to be read.
14. An integrated circuit chip comprising the data cache device according to any one of claims 1-12.
15. A computing device comprising a data cache device according to any one of claims 1-12 or an integrated circuit chip according to claim 14.
16. A board comprising the computing device according to claim 15.