Igbt drive core, short circuit fault turn-off timing processing method and medium

Abstract

The application discloses an IGBT driving core, a short-circuit fault shutdown timing processing method and a medium. The IGBT driving core comprises a primary side and a secondary side. The primary side comprises a level conversion circuit, a PWMA signal driving circuit, a FaultA receiving circuit, a PWMB signal driving circuit, a FaultB receiving circuit and a primary side programmable logic device. The secondary side comprises an A channel programmable logic device, a PWMA signal receiving circuit, a FaultA driving circuit, an IGBT-A push-pull driving circuit, an A channel fault detection circuit, a B channel programmable logic device, a PWMB signal receiving circuit, a FaultB driving circuit, an IGBT-B push-pull driving circuit and a B channel fault detection circuit. The application can solve the problem of IGBT overvoltage damage caused by shutdown timing errors in the application of the traditional driving core scheme in a multi-level topology.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to an IGBT driver core suitable for multi-level topologies, a short-circuit fault turn-off timing processing method, and a dielectric. Background Technology

[0002] IGBTs possess excellent characteristics such as high withstand voltage, high current, high speed, and low saturation voltage drop, making them widely used in power electronic converters. The drive circuit, acting as a bridge between the control circuit and the power semiconductor device, plays a crucial role in fully utilizing the IGBT's performance and improving system reliability. Besides providing good drive performance and reliable protection, IGBT driver design must also address issues such as IGBT parasitic effects, electromagnetic compatibility, insulation voltage, switching speed optimization, cost, and integration. To adapt to most industrial applications, IGBT driver manufacturers offer general-purpose dual-channel IGBT driver cores, which customers can easily integrate into their products by configuring peripheral circuits. Currently, the mainstream IGBT driver solutions mainly include the following three approaches:

[0003] Option 1: ASIC Integrated Circuit Solution

[0004] The primary company using ASIC integrated circuit driver solutions is PI (formerly Concept Semiconductor) in the United States, with mainstream driver core products including 2SD315A and 2SC0435. The primary side of the driver core uses an LDI chip, and the secondary side uses an IGD chip. Communication between the front-end and rear-end chips is achieved through a pulse transformer. The LDI001 mainly performs tasks such as mode selection, logic control, dead-time generation, pulse modulation, and fault latching. The IGD001 mainly performs tasks such as pulse demodulation, amplification, overcurrent and short-circuit protection, undervoltage protection, fault latching, and fault confirmation. The application of ASIC technology significantly reduces the number of components in the driver module.

[0005] The driver does not have a shutdown timing processing function, but the literature claims that the advanced active clamping function based on SCALE-2 technology has been verified to simplify short-circuit management of multilevel converters without the need for specific shutdown timing.

[0006] Option 2: Pure Analog Circuit Solution

[0007] The main representative of analog circuit solutions is the 2ED300C17 half-bridge driver core manufactured by Infineon (formerly Euec) in Germany. Currently, most analog driver solutions in China are imitations of the 2ED300C17. This driver uses discrete components on both the primary and secondary sides to form an analog driver circuit, with pulse transformers used for magnetic isolation between the front and rear stages to achieve the transmission of PWM signals and fault signals. This driver also features mode selection, logic control, dead time generation, pulse modulation, and fault latching functions. However, it currently lacks shutdown timing processing capabilities and is only suitable for two-level applications.

[0008] Option 3: Digital drive circuit solution

[0009] The digital driver circuit solution primarily utilizes the 2FSC0435 driver core manufactured by Hangzhou Feishide Technology Co., Ltd. This driver employs a programmable CPLD on the primary side and a conventional push-pull circuit on the secondary side, with signal transmission via optocouplers. While retaining the "active clamping" function, the driver adds a "soft shutdown" function. The primary side also features fault management, outputting pulse widths of varying lengths for different faults. Currently, this driver lacks shutdown timing processing capabilities and is only suitable for two-level applications.

[0010] The three driver core solutions mentioned above represent the current mainstream solutions, and their primary-side interface circuits are basically the same. Currently, only PI officially claims that they are suitable for multi-level topologies; other driver core solutions will have short-circuit fault shutdown timing issues in multi-level applications. Therefore, for multi-level, especially three-level, applications, most manufacturers purchase or design dedicated driver circuits to solve the shutdown timing problem. Summary of the Invention

[0011] The main objective of this invention is to propose an IGBT driver core, a short-circuit fault turn-off timing processing method, and a medium suitable for multi-level topologies, aiming to solve the problem of IGBT overvoltage damage caused by turn-off timing errors in traditional driver core solutions in multi-level topology applications.

[0012] To achieve the above objectives, the present invention provides an IGBT driver core, comprising a primary side and a secondary side. The primary side includes a level conversion circuit, a PWMA signal driving circuit, a FaultA receiving circuit, a PWMB signal driving circuit, a FaultB receiving circuit, and a primary-side programmable logic device. The secondary side includes an A-channel programmable logic device, a PWMA signal receiving circuit, a FaultA driving circuit, an IGBT-A push-pull driving circuit, an A-channel fault detection circuit, a B-channel programmable logic device, a PWMB signal receiving circuit, a FaultB driving circuit, an IGBT-B push-pull driving circuit, and a B-channel fault detection circuit.

[0013] The primary-side programmable logic device is connected to the level conversion circuit, PWMA signal driving circuit, FaultA receiving circuit, PWMB signal driving circuit, and FaultB receiving circuit, respectively. The level conversion circuit is also connected to the main controller. The A-channel programmable logic device is connected to the PWMA signal receiving circuit, FaultA driving circuit, IGBT-A push-pull driving circuit, and A-channel fault detection circuit, respectively. The B-channel programmable logic device is connected to the PWMB signal receiving circuit, FaultB driving circuit, IGBT-B push-pull driving circuit, and B-channel fault detection circuit, respectively.

[0014] The IGBT driver core also includes an A-channel isolation device and a B-channel isolation device; the PWMA signal driving circuit, FaultA receiving circuit, PWMA signal receiving circuit, and FaultA driving circuit are respectively connected to the A-channel isolation device; the PWMB signal driving circuit, FaultB receiving circuit, PWMB signal receiving circuit, and FaultB driving circuit are respectively connected to the B-channel isolation device.

[0015] A further technical solution of the present invention is that the primary-side programmable device is configured with a PWMA pin, a PWMB pin, a working mode selection pin MOD1, a shutdown timing processing selection pin MOD2, a FOA pin, and a FOB pin connected to the main controller, wherein,

[0016] PWMA and PWMB are PWM switching signals transmitted from the main controller, and the primary-side programmable logic device selects to transmit PWMA and PWMB signals to the A-channel programmable logic device and the B-channel programmable logic device respectively according to the working mode of the MOD1 pin.

[0017] FOA and FOB are the fault output signals for the A-channel IGBT and B-channel IGBT, respectively.

[0018] A further technical solution of the present invention is that the A-channel programmable logic device and the B-channel programmable logic device are respectively configured with GHx, GLx, GNDx, Vccx, Veex, ACLx, REFx and VCEx pins, wherein,

[0019] The GHx and GLx pins are respectively connected to the turn-on and turn-off gate resistors of the A-channel IGBT and the B-channel IGBT;

[0020] REFx is the short-circuit detection reference voltage setting pin, which requires an external resistor; VCEx is the voltage between the collector and emitter of the IGBT after being attenuated by the resistor. When the voltage at the VCEx pin is greater than the REFx voltage, a short-circuit fault is considered to have occurred.

[0021] The ACLx is the active clamp input pin of the corresponding channel, used to clamp the overvoltage when the IGBT is turned off;

[0022] Vccx, Veex, and GNDx are generated by the driver board's built-in power supply and connected to a certain number of external capacitors.

[0023] A further technical solution of the present invention is that the A-channel isolation device and the B-channel isolation device are magnetically isolated, or optically isolated, or capacitively isolated.

[0024] To achieve the above objectives, the present invention also proposes a short-circuit fault turn-off timing processing method, which is applied to the IGBT driver core described above, and the method includes the following steps:

[0025] When the primary-side programmable logic device receives a fault signal FaultA or FaultB sent by the A-channel programmable logic device or the B-channel programmable logic device, it determines whether FaultA or FaultB is valid.

[0026] If FaultA or FaultB is valid, the shutdown signal is sent to the secondary A-channel programmable logic device or the B-channel programmable logic device after a delay or immediately according to the high or low level of the MOD2 pin, and the secondary programmable logic device shuts down the IGBT of the corresponding channel.

[0027] A further technical solution of the present invention is that, if FaultA or FaultB is valid, the step of sending a shutdown signal to the secondary-side A-channel programmable logic device or B-channel programmable logic device with a delay or immediately based on the high or low level of the MOD2 pin, and having the secondary-side programmable logic device shut down the IGBT of the corresponding channel, includes:

[0028] If FaultA is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel A. Then, the primary-side programmable logic device transmits the shutdown signal to the B-channel programmable logic device after a delay, and the B-channel programmable logic device shuts down channel B after a delay.

[0029] If FaultA is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel B. The primary-side programmable logic device will immediately transmit the shutdown signal to the B-channel programmable logic device to immediately shut down channel B.

[0030] If FaultB is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel B. Then, the primary-side programmable logic device transmits the shutdown signal to the A-channel programmable logic device after a delay, and the A-channel programmable logic device shuts down channel A after a delay.

[0031] If FaultB is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel A. The primary-side programmable logic device will immediately transmit the shutdown signal to the programmable logic device of channel A, and immediately shut down channel A.

[0032] A further technical solution of the present invention is that, after the step of preferentially shutting down channel A or channel B according to the high or low level of the MOD2 pin, the invention further includes:

[0033] Channel A outputs a fault signal FOA valid or Channel B outputs a fault signal FOB valid.

[0034] A further technical solution of the present invention is that, after the A-channel programmable logic device or the B-channel programmable logic device detects an IGBT short-circuit fault, it shall delay the shutdown of the corresponding IGBT for a period of time t. doff1 , and t doff1 The formula t needs to be satisfied. doff1 >t d1 +t d2 And t doff1 >t doff2 ;

[0035] Among them, t d1 The time t represents the transmission time of fault signals FaultA or FaultB from the A-channel programmable logic device or the B-channel programmable logic device to the primary-side programmable logic device. d2 t represents the time it takes for the PWMA or PWMB signal to be transmitted from the primary-side CPLD to the A-channel or B-channel programmable logic device. doff2 The time from when the programmable logic device in channel A or channel B detects an IGBT short-circuit fault to when the programmable logic device in the other channel immediately turns off.

[0036] When the primary-side programmable logic device detects that a fault signal FaultA or FaultB is valid in one of the secondary-side channels, it delays the shutdown of the other channel IGBT by a delay time t. doff3 The formula t should be satisfied. doff3 >t doff1 .

[0037] A further technical solution of the present invention is that, when the primary-side programmable logic device receives a fault signal FaultA or FaultB sent by the A-channel programmable logic device or the B-channel programmable logic device, the step of determining whether FaultA or FaultB is valid includes:

[0038] The A-channel programmable logic device or the B-channel programmable logic device receives the corresponding PWMA signal or PWMB signal and drives the corresponding A-channel IGBT or B-channel IGBT.

[0039] Determine whether a fault has occurred in channel A or channel B;

[0040] If so, a fault signal FaultA or FaultB is sent to the primary-side programmable logic device.

[0041] To achieve the above objectives, the present invention also proposes a computer-readable storage medium storing a short-circuit fault shutdown timing processing program, wherein the short-circuit fault shutdown timing processing program is executed by a processor to perform the steps described in the above embodiments.

[0042] The beneficial effects of this invention—the IGBT driver core, the short-circuit fault turn-off timing processing method, and the medium—are as follows: This invention is applicable to digital IGBT driver cores in multi-level topologies. Both the primary and secondary sides of the driver core utilize programmable devices such as CPLDs or FPGAs, and the primary-side interface circuit has a turn-off timing selection pin. By introducing a turn-off timing control pin on the primary side of the driver core, the high and low level states of this pin can control the turn-off order of the two IGBTs on the secondary side when encountering short-circuit or undervoltage faults. This solves the problem of IGBT overvoltage damage caused by incorrect turn-off timing in traditional driver core solutions in multi-level topology applications. This invention has a certain degree of versatility; users only need to simply configure the states of external pins based on this driver core to select the turn-off order of the two IGBTs on the secondary side, greatly simplifying the application. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0044] Figure 1 This is a circuit structure block diagram of a preferred embodiment of the IGBT driver core of the present invention;

[0045] Figure 2 This is a flowchart illustrating a preferred embodiment of the short-circuit fault shutdown timing processing method of the present invention;

[0046] Figure 3 This is a schematic diagram of the A-channel CPLD workflow;

[0047] Figure 4 This is a schematic diagram of the B-channel CPLD workflow;

[0048] Figure 5 This is a schematic diagram of the primary-side CPLD shutdown timing process;

[0049] Figure 6This is a schematic diagram of the three-level application of the driver core;

[0050] Figure 7 This is a three-level fault shutdown timing diagram.

[0051] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0053] Please refer to Figure 1 This invention proposes a digital IGBT driver core suitable for multi-level topologies. Both the primary and secondary sides of the driver core use programmable devices CPLD or FPGA, and the primary side interface circuit has a turn-off timing selection pin. By introducing a turn-off timing control pin on the primary side of the driver core, the high and low level states of this pin can control the turn-off order of the two IGBTs on the secondary side when they encounter short circuit or undervoltage faults. This can solve the problem of IGBT overvoltage damage caused by incorrect turn-off timing in traditional driver core solutions in multi-level topology applications.

[0054] Specifically, a preferred embodiment of the IGBT driver core of the present invention includes a primary side and a secondary side. The primary side includes a level conversion circuit, a PWMA signal driving circuit, a FaultA receiving circuit, a PWMB signal driving circuit, a FaultB receiving circuit, and a primary-side programmable logic device. The secondary side includes an A-channel programmable logic device, a PWMA signal receiving circuit, a FaultA driving circuit, an IGBT-A push-pull driving circuit, an A-channel fault detection circuit, a B-channel programmable logic device, a PWMB signal receiving circuit, a FaultB driving circuit, an IGBT-B push-pull driving circuit, and a B-channel fault detection circuit.

[0055] In this embodiment, the programmable logic controller can be a CPLD or an FPGA, and the A-channel isolation device and the B-channel isolation device can both be magnetically isolated, optocoupler isolated, or capacitively isolated.

[0056] In this embodiment, the primary-side programmable logic device is connected to the level conversion circuit, the PWMA signal driving circuit, the FaultA receiving circuit, the PWMB signal driving circuit, and the FaultB receiving circuit, respectively. The level conversion circuit is also connected to the main controller. The A-channel programmable logic device is connected to the PWMA signal receiving circuit, the FaultA driving circuit, the IGBT-A push-pull driving circuit, and the A-channel fault detection circuit, respectively. The B-channel programmable logic device is connected to the PWMB signal receiving circuit, the FaultB driving circuit, the IGBT-B push-pull driving circuit, and the B-channel fault detection circuit, respectively.

[0057] The IGBT driver core also includes an A-channel isolation device and a B-channel isolation device; the PWMA signal driving circuit, FaultA receiving circuit, PWMA signal receiving circuit, and FaultA driving circuit are respectively connected to the A-channel isolation device; the PWMB signal driving circuit, FaultB receiving circuit, PWMB signal receiving circuit, and FaultB driving circuit are respectively connected to the B-channel isolation device.

[0058] The primary-side programmable device is configured with PWMA pin, PWMB pin, operating mode selection pin MOD1, shutdown timing processing selection pin MOD2, FOA pin, and FOB pin connected to the main controller.

[0059] Wherein, PWMA and PWMB are PWM switching signals transmitted from the main controller, and the primary-side programmable logic device transmits PWMA and PWMB signals to the A-channel programmable logic device and the B-channel programmable logic device respectively according to the working mode of the MOD1 pin.

[0060] FOA and FOB are the fault output signals for the A-channel IGBT and B-channel IGBT, respectively.

[0061] The A-channel programmable logic device and the B-channel programmable logic device are respectively configured with GHx, GLx, GNDx, Vccx, Veex, ACLx, REFx and VCEx pins.

[0062] The GHx and GLx pins are connected to the turn-on and turn-off gate resistors of the A-channel IGBT and B-channel IGBT, respectively.

[0063] REFx is the short-circuit detection reference voltage setting pin, which requires an external resistor; VCEx is the voltage between the collector and emitter of the IGBT after being attenuated by the resistor. When the voltage at the VCEx pin is greater than the REFx voltage, a short-circuit fault is considered to have occurred.

[0064] The ACLx is the active clamp input pin of the corresponding channel, used to clamp the overvoltage when the IGBT is turned off.

[0065] Vccx, Veex, and GNDx are generated by the driver board's built-in power supply and connected to a certain number of external capacitors.

[0066] The following combination Figure 1 The overall hardware scheme of the IGBT driver core of this invention is described in detail.

[0067] The overall hardware scheme of the IGBT driver core proposed in this invention is as follows: Figure 1 As shown, both the primary and secondary sides use programmable logic devices (CPLDs) or FPGAs. PWM drive signals or fault signals are transmitted between the primary and secondary CPLDs through isolation devices, which can be magnetic isolation, optocoupler isolation, or capacitor isolation.

[0068] The primary-side CPLD is responsible for PWM signal processing, operating mode selection, shutdown timing management, and fault output. Its corresponding external interface pins are PWMA, PWMB, MOD1, MOD2, FOA, FOB, VDD, and GND. The functions of each pin are as follows:

[0069] 1. PWMA and PWMB are PWM switching signals transmitted from the main controller. The primary-side CPLD selects to transmit PWMA and PWMB signals to the secondary-side A-channel CPLD and B-channel CPLD according to the MOD1 working mode.

[0070] 2. MOD1 is the operating mode selection pin. Similar to traditional drivers, it offers two operating modes: "Direct Mode" and "Half-Bridge Mode." Direct Mode: Channels A and B operate independently without any connection and can be activated simultaneously. Direct mode is suitable for multi-level topologies. Half-Bridge Mode: In half-bridge mode, a dead time is generated between the two channels. Only one channel is active at any given time. The dead time between the two channels is set by software. Half-bridge mode is suitable for two-level topologies.

[0071] 3. MOD2 is the shutdown timing selection pin, which selects whether channel A or channel B is shut down first by using its high or low level state. When the primary-side CPLD detects a valid fault signal Faul tx transmitted from the secondary-side CPLD, it will decide, based on the state of MOD2, whether to immediately or delay for a certain period of time to transmit the shutdown signal to the other CPLD.

[0072] 4. FOA and FOB are the fault output signals of IGBT A and IGBT B, respectively. The primary-side CPLD sends the fault signal transmitted from the secondary-side CPLD to the main controller. The level can be active high or active low.

[0073] 5. VDD and GND are the power input pins of the driver board.

[0074] The secondary-side CPLD receives the PWM switching signals from the primary-side CPLD and sends them to the IGBT push-pull drive circuit to turn the IGBTs on or off. Simultaneously, it detects whether a short circuit or undervoltage fault has occurred in the corresponding IGBT channel. If a fault occurs, it transmits the fault signal to the primary-side CPLD and, after a certain delay, turns off the corresponding IGBT channel. The secondary-side external pins of the driver board mainly include GHx, GLx, GNDx, Vccx, Veex, ACLx, REFx, and VCEx. The main functions of these pins are as follows:

[0075] 1. GHx and GLx are connected to the turn-on and turn-off gate resistors of the A-channel or B-channel IGBT, respectively;

[0076] 2. REFx is the short-circuit detection reference voltage setting pin, which requires an external resistor. VCEx is the voltage between the collector and emitter of the IGBT after attenuation through the resistor. When the voltage at the VCEx pin is greater than the REFx voltage, a short-circuit fault is considered to have occurred.

[0077] 3. ACLx is the active clamp input pin for the corresponding channel, used to clamp the overvoltage when the IGBT is turned off;

[0078] 4. Vccx, Veex, and GNDx are generated by the driver board's built-in power supply and require an external number of capacitors.

[0079] The beneficial effects of this IGBT driver core are as follows: This invention is a digital IGBT driver core applicable to multi-level topologies. Both the primary and secondary sides of the driver core use programmable devices CPLD or FPGA, and the primary side interface circuit has a turn-off timing selection pin. By introducing a turn-off timing control pin on the primary side of the driver core, the high and low level states of this pin can control the turn-off order of the two IGBTs on the secondary side when encountering short circuit or undervoltage faults. This can solve the problem of IGBT overvoltage damage caused by incorrect turn-off timing in traditional driver core solutions in multi-level topology applications. This invention has a certain degree of versatility. Users only need to simply configure the state of the external pins based on this driver core to select the turn-off order of the two IGBTs on the secondary side, greatly simplifying the application.

[0080] To achieve the above objectives, this invention also proposes a short-circuit fault turn-off timing processing method. This method is applied to the IGBT driver core described in the above embodiments. Please refer to... Figure 2 A preferred embodiment of the short-circuit fault shutdown timing processing method of the present invention includes the following steps:

[0081] Step S10: When the primary-side programmable logic device receives a fault signal FaultA or FaultB sent by the secondary-side A-channel programmable logic device or the secondary-side B-channel programmable logic device, it determines whether FaultA or FaultB is valid.

[0082] Step S20: If FaultA or FaultB is valid, then the shutdown signal is sent to the secondary A-channel programmable logic device or the B-channel programmable logic device after a delay or immediately according to the high or low level of the MOD2 pin, and the secondary programmable logic device shuts down the IGBT of the corresponding channel.

[0083] Specifically, the step of sending a shutdown signal to the secondary-side A-channel programmable logic device or B-channel programmable logic device with a delay or immediately based on the high or low level of the MOD2 pin, and having the secondary-side programmable logic device shut down the corresponding channel's IGBT, includes:

[0084] If FaultA is valid, the level corresponding to the MOD2 pin prioritizes shutting down channel A. Then, the primary-side programmable logic device transmits the shutdown signal to the B-channel programmable logic device after a delay, and the B-channel programmable logic device shuts down channel B after a delay.

[0085] If FaultA is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel B. The primary-side programmable logic device will immediately transmit the shutdown signal to the B-channel programmable logic device to immediately shut down channel B.

[0086] If FaultB is valid, the level corresponding to the MOD2 pin prioritizes shutting down channel B. Then, the primary-side programmable logic device transmits the shutdown signal to the A-channel programmable logic device after a delay, and the A-channel programmable logic device shuts down channel A after a delay.

[0087] If FaultB is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel A. The primary-side programmable logic device will immediately transmit the shutdown signal to the programmable logic device of channel A, and immediately shut down channel A.

[0088] In this embodiment, after the step of preferentially shutting down channel A or channel B based on the high or low level of the MOD2 pin, the method further includes:

[0089] Channel A outputs a fault signal FOA valid or Channel B outputs a fault signal FOB valid.

[0090] In this embodiment, after the A-channel programmable logic device or the B-channel programmable logic device detects an IGBT short-circuit fault, it will delay the shutdown of the corresponding IGBT for a delay time of t.doff1 , and t doff1 The formula t needs to be satisfied. doff1 >t d1 +t d2 And t doff1 >t doff2 .

[0091] Among them, t d1 The time t represents the transmission time of fault signals FaultA or FaultB from the A-channel programmable logic device or the B-channel programmable logic device to the primary-side programmable logic device. d2 t represents the time it takes for the PWMA or PWMB signal to be transmitted from the primary-side CPLD to the A-channel or B-channel programmable logic device. doff2 The time from when the programmable logic device in channel A or channel B detects an IGBT short-circuit fault to when the programmable logic device in the other channel immediately turns off.

[0092] When the primary-side programmable logic device detects that a fault signal FaultA or FaultB is valid in one of the secondary-side channels, it delays the shutdown of the other channel IGBT by a delay time t. doff3 The formula t should be satisfied. doff3 >t doff1 .

[0093] In this embodiment, when the primary-side programmable logic device receives a fault signal FaultA or FaultB sent by the A-channel programmable logic device or the B-channel programmable logic device, the step prior to determining whether FaultA or FaultB is valid includes:

[0094] The A-channel programmable logic device or the B-channel programmable logic device receives the corresponding PWMA signal or PWMB signal and drives the corresponding A-channel IGBT or B-channel IGBT.

[0095] Determine whether a fault has occurred in channel A or channel B.

[0096] If so, a fault signal FaultA or FaultB is sent to the primary-side programmable logic device.

[0097] The following combination Figures 2 to 7 The short-circuit fault shutdown timing processing method of the present invention will be further described in detail.

[0098] The IGBT short-circuit fault turn-off timing processing method of this invention requires the cooperation of both the primary and secondary CPLDs. Figure 3 and Figure 4 This is a flowchart illustrating the shutdown process when the secondary-side CPLD encounters a short-circuit fault. Figure 3 This is the workflow diagram for the A-channel CPLD. Figure 4This is the B-channel CPLD workflow diagram. When a short-circuit fault occurs in any channel IGBT, the fault signal "Fault" is first transmitted to the primary-side CPLD, and then the IGBT is turned off after a certain delay.

[0099] The workflow of the primary-side CPLD is as follows: Figure 5 As shown. When the primary-side CPLD detects a valid fault signal FaultA or FaultB from the secondary side, it considers a short-circuit fault to have occurred in the corresponding IGBT of the secondary side channel. At this time, the primary-side CPLD determines whether to prioritize shutting down channel A or channel B based on the high or low level of the MOD2 pin. For example, if a short-circuit fault occurs in the IGBT of channel A, the fault signal FaultA is valid. If the level corresponding to the MOD2 pin prioritizes shutting down channel A, the primary-side CPLD will delay for a certain period before transmitting the shutdown signal to the CPLD of channel B; otherwise, it will immediately transmit the fault signal to channel B. Upon receiving the shutdown command from the primary-side CPLD, channel B will immediately shut down the IGBT.

[0100] Ignoring the primary and secondary CPLD logic processing time, the turn-off delay time t after the secondary CPLD detects an IGBT short-circuit fault is... off1 The formula t needs to be satisfied. doff1 >t d1 +t d2 And t doff1 >t doff2 Among them, t d1 t represents the time it takes for the fault signal Faultx to travel from the secondary CPLD to the primary CPLD. d2 t represents the time it takes for the PWM signal to travel from the primary-side CPLD to the secondary-side CPLD. d1 and t d2 The latency primarily depends on the isolation method of the driver board. Magnetic isolation has a shorter latency than optocoupler isolation; therefore, this invention recommends using magnetic isolation to achieve communication between the primary and secondary CPLDs. doff2 This refers to the time from when the secondary-side CPLD detects an IGBT short-circuit fault to when the other channel CPLD immediately shuts off. It also refers to the delay t between the primary-side CPLD detecting a valid fault signal Fautlx in one of the secondary channels and then shutting off the other channel's IGBT. doff3 The formula t should be satisfied. doff3 >t doff1 .

[0101] Diode-neutral-clamped three-level topologies are widely used in medium-voltage high-power converters; therefore, this implementation mainly uses the three-level topology as an example to illustrate the application of the driver core. Figure 6 and Figure 7As shown, the three-level single-phase bridge arm has a total of four IGBTs (S1, S2, S3, and S4) and two clamping diodes (D5 and D6), therefore requiring two driver cores. The driver board connection is as follows. Figure 6 As shown, driver core 1 and driver core 2 are mounted on the driver baseboard as core boards. The driver baseboard connects the main controller and the four IGBTs of the three-level power unit. The core of this invention is that the driver core has a fault timing management function, which determines the turn-off order of the two IGBTs on the secondary side by configuring the high and low level states of MOD2. Therefore, this embodiment mainly describes the selection of the MOD2 pin.

[0102] In three-level applications, the transistors must be turned off in the "outer first, inner last" order. That is, when an IGBT malfunctions, the outer transistor S1 or S4 should be turned off first, followed by the inner transistor S2 or S3. Otherwise, overvoltage damage to the inner transistor can easily occur. Assuming MOD2 is high, it prioritizes turning off the IGBT in channel A; conversely, a low MOD2 level prioritizes turning off the IGBT in channel B. Therefore, the MOD2 pin of driver core 1 should be connected to the power supply pin Vdd and kept high, while the MOD2 pin of driver core 2 should be connected to GND and kept low. The turn-off sequence for each transistor in a three-level application is shown in Figure 7.

[0103] When S1 fails, S1 first delays by t doff1 After a certain time, the IGBT is turned off. Based on the high level of MOD2, the primary-side CPLD of driver core 1 prioritizes turning off the IGBT of channel A, and then delays by t... doff3 Then turn off the B-channel IGBT, i.e., the S2 transistor.

[0104] When S2 fails, S2 first delays by t doff1 After a certain time, the IGBT is turned off. Based on the high level of MOD2, the primary-side CPLD of driver core 1 prioritizes turning off the IGBT of channel A, thus immediately turning off channel A, i.e., transistor S1, with a delay time of t. doff2 .

[0105] When S3 fails, S3 first delays t doff1 After a certain time, the IGBT is turned off. Based on the low level state of MOD2, the primary-side CPLD of driver core 2 prioritizes turning off the IGBT of channel B, so channel B, i.e., S4 transistor, is turned off immediately, with a delay time of tdoff2.

[0106] When S4 fails, S4 first delays t doff1 After a certain time, the IGBT is turned off. Based on the low level state of MOD2, the primary-side CPLD of driver core 2 prioritizes turning off the B-channel IGBT, and then delays by t... doff3 Then turn off the IGBT in channel A, i.e., the S3 transistor.

[0107] The beneficial effects of the short-circuit fault turn-off timing processing method of the present invention are as follows: The present invention is applicable to digital IGBT driver cores in multi-level topologies. Both the primary and secondary sides of the driver core adopt programmable devices CPLD or FPGA, and the primary side interface circuit has a turn-off timing selection pin. By introducing a turn-off timing control pin on the primary side of the driver core, the turn-off order of the two IGBTs on the secondary side can be controlled by the high and low level states of this pin when encountering short-circuit or undervoltage faults. This can solve the problem of IGBT overvoltage damage caused by incorrect turn-off timing in traditional driver core solutions in multi-level topology applications. The present invention has a certain degree of versatility. Users only need to simply configure the state of the external pins based on this driver core to select the turn-off order of the two IGBTs on the secondary side, which greatly simplifies the application.

[0108] To achieve the above objectives, the present invention also proposes a computer-readable storage medium storing a short-circuit fault shutdown timing processing program. When the short-circuit fault shutdown timing processing program is run by a processor, the steps described in the above embodiments are executed, and will not be repeated here.

[0109] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. An IGBT driver core, characterized in that, It includes a primary side and a secondary side. The primary side includes a level conversion circuit, a PWMA signal driving circuit, a FaultA receiving circuit, a PWMB signal driving circuit, a FaultB receiving circuit, and a primary-side programmable logic device. The secondary side includes an A-channel programmable logic device, a PWMA signal receiving circuit, a FaultA driving circuit, an IGBT-A push-pull driving circuit, an A-channel fault detection circuit, a B-channel programmable logic device, a PWMB signal receiving circuit, a FaultB driving circuit, an IGBT-B push-pull driving circuit, and a B-channel fault detection circuit. The primary-side programmable logic device is connected to the level conversion circuit, PWMA signal driving circuit, FaultA receiving circuit, PWMB signal driving circuit, and FaultB receiving circuit, respectively. The level conversion circuit is also connected to the main controller. The A-channel programmable logic device is connected to the PWMA signal receiving circuit, FaultA driving circuit, IGBT-A push-pull driving circuit, and A-channel fault detection circuit, respectively. The B-channel programmable logic device is connected to the PWMB signal receiving circuit, FaultB driving circuit, IGBT-B push-pull driving circuit, and B-channel fault detection circuit, respectively. The IGBT driver core also includes an A-channel isolation device and a B-channel isolation device; the PWMA signal driving circuit, FaultA receiving circuit, PWMA signal receiving circuit, and FaultA driving circuit are respectively connected to the A-channel isolation device; the PWMB signal driving circuit, FaultB receiving circuit, PWMB signal receiving circuit, and FaultB driving circuit are respectively connected to the B-channel isolation device. The primary-side programmable logic device is configured with PWMA pin, PWMB pin, operating mode selection pin MOD1, shutdown timing selection pin MOD2, FOA pin, and FOB pin, all connected to the main controller. PWMA and PWMB are PWM switching signals transmitted from the main controller, and the primary-side programmable logic device selects to transmit PWMA and PWMB signals to the A-channel programmable logic device and the B-channel programmable logic device respectively according to the working mode of the MOD1 pin. FOA and FOB are the fault output signals for the A-channel IGBT and B-channel IGBT, respectively.

2. The IGBT driver core according to claim 1, characterized in that... The IGBT-A push-pull drive circuit and the IGBT-B push-pull drive circuit are respectively configured with GHx, GLx, GNDx, Vccx, Veex, and ACLx pins, and the A-channel fault detection circuit and the B-channel fault detection circuit are respectively configured with REFx and VCEx pins, where x = A and B; The GHx and GLx pins are respectively connected to the turn-on and turn-off gate resistors of the A-channel IGBT and the B-channel IGBT; REFx is the short-circuit detection reference voltage setting pin, which requires an external resistor; VCEx is the voltage between the collector and emitter of the IGBT after being attenuated by the resistor. When the voltage at the VCEx pin is greater than the REFx voltage, a short-circuit fault is considered to have occurred. The ACLx is the active clamp input pin of the corresponding channel, used to clamp the overvoltage when the IGBT is turned off; Vccx, Veex, and GNDx are generated by the driver board's built-in power supply and connected to a certain number of external capacitors.

3. The IGBT driver core according to any one of claims 1 to 2, characterized in that, The A-channel isolation device and the B-channel isolation device are magnetically isolated, or optically isolated, or capacitively isolated.

4. A method for short-circuit fault turn-off timing processing, characterized in that, The method is applied to the IGBT driver core as described in any one of claims 1 to 3, and the method includes the following steps: When the primary-side programmable logic device receives a fault signal FaultA or FaultB sent by the secondary-side A-channel programmable logic device or the secondary-side B-channel programmable logic device, it determines whether FaultA or FaultB is valid. If FaultA or FaultB is valid, the shutdown signal is sent to the secondary A-channel programmable logic device or the B-channel programmable logic device after a delay or immediately according to the high or low level of the MOD2 pin, and the secondary programmable logic device shuts down the IGBT of the corresponding channel.

5. The short-circuit fault turn-off timing processing method according to claim 4, characterized in that, If FaultA or FaultB is valid, the step of sending a shutdown signal to the secondary-side A-channel programmable logic device or B-channel programmable logic device with a delay or immediately based on the high or low level of the MOD2 pin, and having the secondary-side programmable logic device shut down the corresponding channel's IGBT, includes: If FaultA is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel A. Then, the primary-side programmable logic device transmits the shutdown signal to the B-channel programmable logic device after a delay, and the B-channel programmable logic device shuts down channel B after a delay. If FaultA is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel B. The primary-side programmable logic device will immediately transmit the shutdown signal to the B-channel programmable logic device to immediately shut down channel B. If FaultB is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel B. Then, the primary-side programmable logic device transmits the shutdown signal to the A-channel programmable logic device after a delay, and the A-channel programmable logic device shuts down channel A after a delay. If FaultB is valid, the level corresponding to the MOD2 pin is to prioritize shutting down channel A. The primary-side programmable logic device will immediately transmit the shutdown signal to the programmable logic device of channel A, and immediately shut down channel A.

6. The short-circuit fault turn-off timing processing method according to claim 5, characterized in that, Following the step of preferentially shutting down channel A or channel B based on the high or low level of the MOD2 pin, the following is also included: Channel A outputs a fault signal FOA valid or Channel B outputs a fault signal FOB valid.

7. The short-circuit fault turn-off timing processing method according to claim 4, characterized in that, After detecting an IGBT short-circuit fault, the A-channel or B-channel programmable logic device must delay the shutdown of the corresponding IGBT for a delay time of t. doff1 , and t doff1 The formula t needs to be satisfied. doff1 >t d1 +t d2 And t doff1 >t doff2 ; Among them, t d1 The time t represents the transmission time of fault signals FaultA or FaultB from the A-channel programmable logic device or the B-channel programmable logic device to the primary-side programmable logic device. d2 t represents the time t takes for the PWMA or PWMB signal to be transmitted from the primary-side programmable logic device to the A-channel or B-channel programmable logic device. doff2 The time from when the programmable logic device in channel A or channel B detects an IGBT short-circuit fault to when the programmable logic device in the other channel immediately turns off. When the primary-side programmable logic device detects that a fault signal FaultA or FaultB is valid in one of the secondary-side channels, it delays the shutdown of the other channel IGBT by a delay time t. doff3 The formula t should be satisfied. doff3 >t doff1 .

8. The short-circuit fault turn-off timing processing method according to any one of claims 4 to 7, characterized in that, When the primary-side programmable logic device receives a fault signal FaultA or FaultB sent by the A-channel programmable logic device or the B-channel programmable logic device, the step prior to determining whether FaultA or FaultB is valid includes: The A-channel programmable logic device or the B-channel programmable logic device receives the corresponding PWMA signal or PWMB signal and drives the corresponding A-channel IGBT or B-channel IGBT. Determine whether a fault has occurred in channel A or channel B; If so, a fault signal FaultA or FaultB is sent to the primary-side programmable logic device.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a short-circuit fault shutdown timing processing program, which, when executed by a processor, performs the steps of the method as described in any one of claims 4 to 8.

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