Procedure testing method and apparatus

Abstract

This application provides a program detection method and apparatus that can help users quickly check if a program is running in a weak memory environment, thereby improving the efficiency of program detection and applicable to program testing. The method includes: receiving a program provided by a user, and obtaining the result of the program running in a weak memory environment based on query parameters and the program. The query parameters indicate the maximum interval between two operations of the program that require reordering.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a method and apparatus for program detection. Background Technology

[0002] Strong memory model and weak memory model are two memory models. The strong memory model describes a system where every instruction implicitly includes acquire and release semantics. Acquire semantics prevents out-of-order read-acquire and subsequent read / write operations, while release semantics prevents out-of-order write-release and preceding read / write operations. In other words, a sequence of write operations performed by one core on memory can be observed in the same order by other cores of the central processing unit (CPU). The weak memory model, on the other hand, describes a system where, within an independent thread, any read / write operation on memory can be swapped with other read / write operations without altering the thread's behavior.

[0003] Due to the lagging software ecosystem of weak memory models, programs developed on strong memory model platforms may experience crashes, restarts, or incorrect calculation results when ported to weak memory model platforms. This necessitates repeated testing and debugging by experienced developers to analyze whether the program will exhibit abnormalities on the weak memory model platform. However, the probability of reproducing these crashes, restarts, or incorrect calculation results is low, the cost of reproducing the problem is high due to limitations in test cases and testing environments, and it requires a high level of expertise from testers. Summary of the Invention

[0004] This application provides a program detection method and apparatus that can help users quickly check whether a program is running on a weak memory model platform, thereby improving the efficiency of program detection.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] Firstly, a program detection method is provided. This method includes: receiving a program provided by a user, and obtaining the result of the program running in a weak memory environment based on query parameters and the program. The query parameters indicate the maximum interval between two operations of the program that would be reordered.

[0007] Based on the program detection method described in the first aspect, the program detection device receives a program provided by the user and obtains the result of the program running in a weak memory environment based on the query parameter of the maximum interval between the two operations that indicate the reordering of the program and the program. This can help users quickly complete the check of the program running in a weak memory environment, improve the efficiency of program detection, and require less professional skills from the user.

[0008] In one possible design, obtaining the result of the program running in a weak memory environment based on query parameters and the program can include: obtaining the result of the program running in a weak memory environment based on query parameters, the interval between the first operation and the second operation in the first thread of the program, and the interval between the third operation and the fourth operation in the second thread of the program. Optionally, the first and third operations can be a pair of read-write operations on the same variable, the second and fourth operations can be a pair of read-write operations on the same variable, the first and second operations can be operations on different variables, and the third and fourth operations can be operations on different variables. This eliminates the need for user testing of the program, improving the efficiency of program detection.

[0009] In one possible design approach, the program detection method provided in the first aspect may further include: using memory read / write mode query rules to detect the first operation in the first thread, the second operation in the first thread, the third operation in the second thread, and the fourth operation in the second thread, to obtain the result that the program is running in a weak memory environment.

[0010] Optionally, the memory read / write pattern query rules can be determined based on query parameters. These rules can be used to determine whether the first thread and the second thread overlap in time. If the program satisfies the memory read / write pattern query rules, the result is incorrect, potentially leading to weak memory ordering issues. If the rules are not met, the result is correct, resulting in correct performance on a weak memory model platform. This eliminates the need for repeated testing by the user, allowing for quick access to results when the program is running in a weak memory environment.

[0011] Optionally, the memory read / write pattern query rules may include out-of-order read / write query rules, and / or out-of-order read / write and write / read query rules. This allows for the examination of the execution results of a program comprising at least two threads, one thread including read-read operations and the other thread including write-write operations, in a weak memory environment, and / or allows for the examination of the execution results of a program comprising at least two threads, one thread including read-write operations and the other thread including write-read operations, in a weak memory environment.

[0012] In one possible design approach, the query parameters can be user-defined and may include on-chip write operation latency. Optionally, the query parameters may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. Thus, memory read / write mode can be queried based on user-inputted query parameters.

[0013] In one possible design approach, the program detection method provided in the first aspect may further include: obtaining the numerical value corresponding to the query parameter. The numerical value corresponding to the query parameter may include the value corresponding to the on-chip write operation latency. Optionally, the numerical value corresponding to the query parameter may also include the value corresponding to the cross-NUMA write operation latency and / or the value corresponding to the cross-NUMA read operation latency.

[0014] Alternatively, a weak memory environment can be the runtime environment corresponding to a non-uniform memory access architecture (NUMA) running device.

[0015] In one possible design approach, the program detection method provided in the first aspect may further include: providing results to the user. These results may include modification suggestions. In this way, the user can manually modify the program based on the modification suggestions, thereby helping the user quickly locate the location in the program that causes the error, quickly complete the program modification, and improve the efficiency of program modification.

[0016] Optionally, the result may include: Correct. Alternatively, the result may include errors and / or suggested modifications.

[0017] Optionally, the modification suggestion may include the location information of the code that needs to be modified, such as the line number and / or program file name. The modification suggestion can be used by a program detection device to modify the program or by a user to manually modify the program.

[0018] In one possible design approach, the program detection method provided in the first aspect may further include: modifying the program according to modification suggestions in response to a user's confirmation instruction. This directly assists the user in completing the program modification, further improving the efficiency of program modification.

[0019] Secondly, a program detection device is provided. This device includes a receiving unit and an acquiring unit. The receiving unit receives a program provided by a user; the acquiring unit obtains the result of the program running in a weak memory environment based on query parameters and the program. The query parameters indicate the maximum interval between two operations of the program that would be reordered.

[0020] In one possible design, the acquisition unit is further configured to obtain the result of the program running in a weak memory environment based on query parameters, the interval between the first operation and the second operation in the first thread of the program, and the interval between the third operation and the fourth operation in the second thread of the program. Optionally, the first and third operations are a pair of read-write operations on the same variable, the second and fourth operations are a pair of read-write operations on the same variable, the first and second operations are operations on different variables, and the third and fourth operations are operations on different variables.

[0021] In one possible design approach, the acquisition unit is also used to query rules using memory read / write patterns to detect the first operation, the second operation, the third operation, and the fourth operation in the second thread of the program, thereby obtaining the result of the program running in a weak memory environment.

[0022] Optionally, the memory read / write pattern query rules can be determined based on the query parameters, and the memory read / write pattern query rules can be used to determine whether the first thread and the second thread overlap in time.

[0023] In one possible design approach, the memory read / write pattern query rules may include read-read, write-write out-of-order query rules, and / or read-write, write-read out-of-order query rules.

[0024] In one possible design approach, the query parameters can be user-defined and may include on-chip write operation latency. Optionally, the query parameters may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. Thus, memory read / write mode can be queried based on user-inputted query parameters.

[0025] In one possible design, the acquisition unit is further configured to acquire the numerical value corresponding to the query parameter. The numerical value corresponding to the query parameter may include the value corresponding to the on-chip write operation latency. Optionally, the numerical value corresponding to the query parameter may also include the value corresponding to the cross-NUMA write operation latency and / or the value corresponding to the cross-NUMA read operation latency.

[0026] Alternatively, a weak memory environment can be the runtime environment corresponding to a device running on a non-uniform memory access architecture (NUMA).

[0027] In one possible design, the program detection device described in the second aspect may further include an output unit. The output unit is used to provide results to the user. The results may include modification suggestions.

[0028] Optionally, the result may include: Correct. Alternatively, the result may include errors and / or suggested modifications.

[0029] Optionally, the modification suggestion may include the location information of the code that needs to be modified, such as the line number and / or program file name. The modification suggestion can be used by a program detection device to modify the program or by a user to manually modify the program.

[0030] In one possible design approach, the acquisition unit is also used to modify the program based on modification suggestions in response to a user's confirmation instruction.

[0031] In one possible design approach, the program detection device can be placed in a cloud server.

[0032] It should be noted that the receiving unit and the output unit can be set up separately, or they can be integrated into a single module, i.e., a transceiver module. This application does not impose specific limitations on the specific implementation methods of the receiving unit and the output unit.

[0033] Optionally, the program detection apparatus described in the second aspect may further include a storage module storing a program or instructions. When the acquisition unit executes the program or instructions, the program detection apparatus can perform the program detection method as described in any possible implementation of the first aspect.

[0034] It should be noted that the program detection device described in the second aspect can be a computer device, server or cloud server, or it can be a chip (system) or other component or part that can be set in a computer device, server or cloud server. This application does not limit it in this regard.

[0035] Furthermore, the technical effects of the program detection device described in the second aspect can be referred to the technical effects of the program detection method described in the first aspect, and will not be repeated here.

[0036] Thirdly, a program detection apparatus is provided. The program detection apparatus includes: a processor coupled to a memory for storing a computer program; the processor is configured to execute the computer program stored in the memory, such that the program detection apparatus performs the program detection method as described in any possible implementation of the first aspect.

[0037] In one possible design, the program detection device described in the third aspect may further include a transceiver. The transceiver may be a transceiver circuit or an input / output port. The transceiver can be used for communication between the program detection device and other devices.

[0038] In this application, the program detection device described in the third aspect can be a computer device, a server or a cloud server, or a chip or chip system disposed inside a computer device, server or cloud server.

[0039] Furthermore, the technical effects of the program detection device described in the third aspect can be referred to the technical effects of the program detection method described in any implementation of the first aspect, and will not be repeated here.

[0040] Fourthly, a chip system is provided, which has a weak memory environment. The chip system includes a processor and input / output ports. The processor is coupled to a memory containing instructions and is used to control the chip system to implement the processing functions involved in any implementation of the first aspect. The input / output ports are used to implement the transmit / receive functions involved in any implementation of the first aspect.

[0041] In one possible design, the chip system also includes a memory for storing program instructions and data that implement the functions involved in the first aspect.

[0042] This chip system can consist of chips or include chips and other discrete components.

[0043] Fifthly, a computer-readable storage medium is provided, comprising: computer instructions stored in the computer-readable storage medium; when the computer instructions are executed on a computer, causing the computer to perform the program detection method as described in any possible implementation of the first aspect.

[0044] In a sixth aspect, a computer program product comprising instructions is provided, including a computer program or instructions that, when executed on a computer, cause the computer to perform the program detection method as described in any possible implementation of the first aspect. Attached Figure Description

[0045] Figure 1 Flowchart of the program detection method provided in the embodiments of this application Figure 1 ;

[0046] Figure 2 This application illustrates the use of the program detection method provided in the embodiments of this application. Figure 1 ;

[0047] Figure 3 Flowchart of the program detection method provided in the embodiments of this application Figure 2 ;

[0048] Figure 4 A schematic diagram of the CPU structure provided in the embodiments of this application. Figure 1 ;

[0049] Figure 5 A schematic diagram of the interface of the program testing device provided in the embodiments of this application. Figure 1 ;

[0050] Figure 6 Example diagrams of the program provided in the embodiments of this application;

[0051] Figure 7 A schematic diagram of the interface of the program testing device provided in the embodiments of this application. Figure 2 ;

[0052] Figure 8 Analysis examples of the programs provided for embodiments of this application Figure 1 ;

[0053] Figure 9 Analysis examples of the programs provided for embodiments of this application Figure 2 ;

[0054] Figure 10 This application illustrates the use of the program detection method provided in the embodiments of this application. Figure 2 ;

[0055] Figure 11 Schematic diagram of the structure of the program testing device provided in the embodiments of this application Figure 1 ;

[0056] Figure 12 Schematic diagram of the structure of the program testing device provided in the embodiments of this application Figure 2 . Detailed Implementation

[0057] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0058] This application will present various aspects, embodiments, or features relating to systems that may include multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0059] Furthermore, in the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as an "example" in this application should not be construed as being better or more advantageous than other embodiments or designs. Rather, the use of the word "example" is intended to present the concept in a specific manner.

[0060] In the embodiments of this application, "operation instruction" and "operation" may sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, their intended meanings are consistent. Similarly, "statement," "program statement," and "code" may sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, their intended meanings are consistent.

[0061] In the description of this application, unless otherwise stated, "multiple" means two or more. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone.

[0062] First, for ease of understanding, the relevant terms and concepts that may be involved in the embodiments of this application will be introduced below.

[0063] (1) Total Store Ordering (TSO) Consistency Model

[0064] The TSO (Time-of-Stake) consistency model describes the order in which multiple cores in a central processing unit (CPU) perform one and only one global memory write operation. The TSO consistency model is a strong memory model.

[0065] This application provides a program detection method capable of detecting the correctness of a program running on a weak memory model platform, such as an Advanced Reduced Instruction Set Machine (ARM) platform. This program detection method can be used independently or integrated with third-party software. The program detection device provided in this application can be a computer device, server, or cloud server, or it can be a chip or other component with program detection functionality applied in a computer device, server, or cloud server.

[0066] The following will combine Figures 1-10 The program detection method provided in the embodiments of this application will be described in detail.

[0067] Figure 1 Flowchart of the program detection method provided in the embodiments of this application Figure 1 The program detection method provided in this application can be used to inspect software developed in compiled languages, such as C or C++.

[0068] like Figure 1 As shown, the detection method of this program includes the following steps:

[0069] S101 receives the program provided by the user.

[0070] Figure 2 This application illustrates the use of the program detection method provided in the embodiments of this application. Figure 1 .

[0071] like Figure 2As shown, the program detection device receives a program provided by the user. Taking C / C++ software as an example, the program can be C / C++ software source code. The program may include one or more threads.

[0072] Optionally, the program detection method provided in this application embodiment may include: using a compiler to convert the user-provided program into intermediate representation (IR) code.

[0073] For example, taking the Clang / LLVM compiler, suppose the user-provided program is XXX.c. The Clang / LLVM compiler compiles this program, generating intermediate code, for example, clang-emit-llvm-cg XXX.co XXX.bc. Optionally, the intermediate file XXX.bc is analyzed by the program detection device Weakmemcheck.

[0074] Combination Figure 3 (a) or Figure 3 In section (b), the compiler compiles the user-provided program to generate intermediate code (IR). The program detection device analyzes the intermediate code, which enables static analysis of the source code. It does not require running the user-provided program, thus avoiding intrusion into the user's software and ensuring the security and ease of operation of the user's program.

[0075] S102, based on the query parameters and the program, obtain the result of the program running in a weak memory environment.

[0076] Optionally, a weak memory environment refers to the operating environment of a device running on a non-uniform memory access architecture (NUMA).

[0077] For example, a weak memory environment can be the operating environment of a weak memory model device or a weak memory model platform.

[0078] For example, a query parameter is used to indicate the maximum interval between two operations of the program that would be reordered. Optionally, a query parameter may include a type of query parameter and / or a numerical value corresponding to the query parameter.

[0079] In some embodiments, the type of the query parameter may include on-chip write operation latency. For example, on-chip write operation latency may be used to indicate the maximum interval between two on-chip store instructions being reordered.

[0080] For example, memory instructions can be used to save data from registers to memory, and on-chip write operation latency can be used to detect whether reordering will occur between two or more memory instructions within a NUMA node. For more information on NUMA nodes, please refer to the following... Figure 4 A detailed explanation.

[0081] Optionally, the query parameter type may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. For example, cross-NUMA write operation latency can be used to indicate the maximum interval between two store instructions across NUMA nodes being reordered, and cross-NUMA read operation latency can be used to indicate the maximum interval between two load instructions across NUMA nodes being reordered, where cross-NUMA node instructions refer to instructions in which the processing of one NUMA node accesses the memory of another NUMA node.

[0082] For example, a load instruction can be used to read data from memory and place it into a register. Cross-NUMA write operation latency can be used to detect whether reordering occurs between two or more store instructions across two or more NUMA nodes. Cross-NUMA read operation latency can be used to detect whether reordering occurs between two or more load instructions across two or more NUMA nodes. For more information on cross-NUMA write operation latency and cross-NUMA read operation latency, please refer to the following... Figure 4 A detailed explanation.

[0083] In some embodiments, the value corresponding to the query parameter may include the value corresponding to the on-chip write operation latency.

[0084] For example, assuming the on-chip write operation latency is set to 8, the maximum interval between two memory operation instructions being reordered is 8 memory operation instructions. That is, if the interval between two memory operation instructions is less than or equal to 8 memory operation instructions, then these two memory operation instructions are considered to be reordered; if the interval between two memory operation instructions is greater than 8 memory operation instructions, then these two memory operation instructions are considered not to be reordered. Memory operation instructions can include store instructions and / or load instructions.

[0085] Optionally, the values ​​corresponding to the query parameters may also include values ​​corresponding to the latency of cross-NUMA write operations and / or the latency of cross-NUMA read operations.

[0086] For example, assuming the value corresponding to the cross-NUMA write operation latency is set to 8, the maximum interval between two memory instruction reordering is 8 memory operation instructions. That is, if the interval between two memory instructions is less than or equal to 8 memory operation instructions, it is considered that these two memory instructions will be reordered; if the interval between two memory instructions is greater than 8 memory operation instructions, it is considered that these two memory instructions will not be reordered.

[0087] Similarly, assuming the value corresponding to the cross-NUMA read operation latency is set to 8, the maximum interval between two load instructions being reordered is 8 memory operation instructions. That is, if the interval between two load instructions is less than or equal to 8 memory operation instructions, it is assumed that these two load instructions will not be reordered; if the interval between two load instructions exceeds 8 memory operation instructions, it is assumed that these two load instructions will not be reordered.

[0088] Optionally, the type of the query parameter may include the on-chip read operation latency, and the value corresponding to the query parameter may include the value corresponding to the on-chip read operation latency. For example, the on-chip read operation latency can be used to indicate the maximum interval between two load instructions being reordered, and the on-chip read operation latency can be used to detect whether reordering will occur between two or more load instructions within a NUMA node. The specific implementation of the on-chip read operation latency is similar to that of the on-chip write operation latency described above, and will not be repeated here.

[0089] It should be noted that, taking a program containing memory operation instructions 1 and 2 as an example, reordering refers to a change in the execution order of memory operation instructions 1 and 2. For instance, if the program file's code specifies that memory operation instruction 1 is executed before memory operation instruction 2, but the program is run in a weak memory environment, due to the characteristics of a weak memory environment, memory operation instruction 2 will be executed first, followed by memory operation instruction 1.

[0090] In some embodiments, memory read / write patterns can be queried based on query parameters. These query parameters describe the on-chip and off-chip memory read / write latency of different CPU cores and construct memory read / write pattern query rules.

[0091] Alternatively, the query parameters can be determined based on the CPU architecture.

[0092] Figure 4 A schematic diagram of the CPU structure provided in the embodiments of this application. Figure 1 .

[0093] like Figure 4As shown, the CPU includes two memory locations: memory0 and memory1. Each memory location corresponds to a core and a cache. Memory0 corresponds to core0, core1, cache0, and cache1. A store buffer exists between core0 and cache0, and between core1 and cache1. Memory1 corresponds to core2, core3, cache2, and cache3. A store buffer exists between core2 and cache2, and between core3 and cache3. Optionally, a NUMA load buffer and / or a NUMA store buffer may exist between memory0 and memory1. For example, core0 and core1 can read from memory1 through a cross-NUMA load cache, and core0 and core1 can write to memory1 through a cross-NUMA storage cache. Similarly, core2 and core3 can read from memory0 through a cross-NUMA load cache, and core2 and core3 can write to memory0 through a cross-NUMA storage cache.

[0094] Combination Figure 4 The architecture including memory0, core0, core1, cache0, and cache1, and their corresponding Store Buffers, can be referred to as NUMA node 0. Read operations performed by core0 or core1 within NUMA node 0 on the internal memory (memory0) or cache (cache0 and cache1, and their corresponding Store Buffers) of NUMA node 0 are called on-chip read operations. For example, a read operation from core0 to memory0 is called an on-chip read operation. Write operations performed by core0 or core1 within NUMA node 0 on the internal memory (memory0) or cache (cache0 and cache1, and their corresponding Store Buffers) of NUMA node 0 are called on-chip write operations. For example, a write operation from core0 to memory0 is called an on-chip write operation.

[0095] Similarly, the architecture including memory1, core2, core3, cache2, and cache3, and their corresponding Store Buffers, can be referred to as NUMA node 1. Read operations performed by core2 or core3 within NUMA node 1 on the internal memory (memory1) or cache (cache2, cache3, and their corresponding Store Buffers) of NUMA node 1 are called on-chip read operations. For example, a read operation by core2 on memory1 is called an on-chip read operation. Write operations performed by core2 or core3 within NUMA node 1 on the internal memory (memory1) or cache (cache2, cache3, and their corresponding Store Buffers) of NUMA node 1 are called on-chip write operations. For example, a write operation by core2 on memory1 is called an on-chip write operation.

[0096] For example, memory operations between NUMA node 0 and NUMA node 1 are referred to as cross-NUMA memory operations, which include read operations and / or write operations. For instance, a read operation from core0 in NUMA node 0 to memory1 in NUMA node 1 is called a cross-NUMA read operation, and a write operation from core0 in NUMA node 0 to memory1 in NUMA node 1 is called a cross-NUMA write operation. Similarly, a read operation from core2 in NUMA node 1 to memory0 in NUMA node 0 is called a cross-NUMA read operation, and a write operation from core2 in NUMA node 1 to memory0 in NUMA node 0 is called a cross-NUMA write operation, and so on.

[0097] For example, combined Figure 4 If the CPU includes a store buffer, the values ​​corresponding to the on-chip write operation latency and / or on-chip write operation latency can be determined. If the CPU includes a NUMA load buffer, the values ​​corresponding to the NUMA write operation latency and / or cross-NUMA write operation latency can be determined. If the CPU includes a NUMA store buffer, the values ​​corresponding to the NUMA read operation latency and / or cross-NUMA read operation latency can be determined. Optionally, if the CPU includes a load buffer, the values ​​corresponding to the on-chip read operation latency and / or on-chip read operation latency can be determined. Specifically, a load buffer can correspond to a core 0 and cache 0; similarly, load buffers can correspond to core 1 and cache 1, core 2 and cache 2, and core 3 and cache 3, respectively. Figure 4 (Not shown in the image).

[0098] In some embodiments, the query parameters may be determined by the program detection device.

[0099] For example, the program detection device can determine the type of query parameters, such as using on-chip write operation latency, or using cross-NUMA write operation latency and / or cross-NUMA read operation latency.

[0100] For example, the program detection device can determine the value corresponding to the query parameter. For instance, the program detection device measures the value corresponding to the query parameter based on a test set. The program detection device can determine the value corresponding to the on-chip write operation latency, and it can also determine the value corresponding to the cross-NUMA write operation latency and / or the value corresponding to the cross-NUMA read operation latency.

[0101] In some embodiments, the query parameters can be user-defined.

[0102] Combination Figure 2 The program detection device can analyze the program based on the query parameters determined by the user and obtain the results of the program running in a weak memory environment.

[0103] Optionally, users can specify the type of query parameters.

[0104] For example, users can enter query parameters on the display interface of the program detection device. Figure 5 A schematic diagram of the interface of the program testing device provided in the embodiments of this application. Figure 1 Combining Figure 5 In section (a), the user can enter the command corresponding to the query parameter in the input query parameter area of ​​the display interface. For example, the user can enter the command StoreBuffer corresponding to the on-chip write operation latency. Optionally, the user can also enter the command NUMAStoreSize corresponding to the cross-NUMA write operation latency and / or the command NUMALoadSize corresponding to the cross-NUMA read operation latency.

[0105] Alternatively, for example, the display interface of the program detection device may include a selection box for on-chip write operation latency, and may also include selection boxes for cross-NUMA write operation latency and / or cross-NUMA read operation latency. For example, a user can determine the type of query parameter to use by checking the selection box corresponding to the type of query parameter. Combined with... Figure 5 In section (b), users can check the checkboxes corresponding to on-chip write operation latency to confirm the use of on-chip write operation latency. Similarly, users can check the checkboxes corresponding to cross-NUMA write operation latency to confirm the use of cross-NUMA write operation latency. If cross-NUMA read operation latency is not to be used, the checkboxes corresponding to cross-NUMA read operation latency can be left unchecked.

[0106] Optionally, users can specify the numerical values ​​corresponding to the query parameters.

[0107] Combination Figure 5 (a) or Figure 5 In section (b), the user can enter the corresponding value in the input value area corresponding to the type of each query parameter. For example, the user can enter 8 in the input value area corresponding to the on-chip write operation latency. Similarly, the user can enter 8 in the input value area corresponding to the cross-NUMA write operation latency, and the user can enter 8 in the input value area corresponding to the cross-NUMA read operation latency.

[0108] It should be noted that the above are merely examples provided in the embodiments of this application, and the embodiments of this application do not limit how the query parameters are determined. For example, the type of the query parameter may be determined by the program detection device, and the value corresponding to the query parameter may be determined by the user. Alternatively, the type of the query parameter may be determined by the user, and the value of the query parameter may be determined by the program detection device. Alternatively, after the program detection device determines the type of the query parameter and / or the value corresponding to the query parameter, the user may modify the type of the query parameter and / or the value corresponding to the query parameter.

[0109] In one possible design approach, the program detection method provided in this application embodiment may further include: obtaining the numerical value corresponding to the query parameter.

[0110] Optionally, the value corresponding to the query parameter can be preset, and / or the value corresponding to the query parameter can be provided by the user through the input value area corresponding to the type of query parameter in the display interface.

[0111] In one possible design approach, the above S102 may include: obtaining the result of the program running in a weak memory environment based on the query parameters, the interval between the first operation and the second operation in the first thread of the program, and the interval between the third operation and the fourth operation in the second thread of the program.

[0112] Optionally, the first and third operations can be a pair of read and write operations on the same variable, the second and fourth operations can be a pair of read and write operations on the same variable, the first and second operations can be operations on different variables, and the third and fourth operations can be operations on different variables. For example, the variable can be a shared variable. A pair of operations can be: the first operation is a read operation on the first variable, and the third operation is a write operation on the first variable; or, the first operation is a write operation on the first variable, and the third operation is a read operation on the first variable. Similarly, the second operation is a read operation on the second variable, and the fourth operation is a write operation on the second variable; or, the second operation is a write operation on the second variable, and the fourth operation is a read operation on the second variable. The first variable can include global variables, shared variables, etc., and the second variable can include global variables, shared variables, etc.

[0113] Figure 6 Example diagrams of the program provided for embodiments of this application.

[0114] like Figure 6 As shown, the program includes a first thread (thread1) on line 14 and a second thread (thread2) on line 21. It can calculate the interval between the write operation on the variable `population` in thread1 (line 17) and the write operation on the variable `syn_flag` in thread1 (line 18). It can also calculate the interval between the read operation on the variable `syn_flag` in thread2 (line 23) and the read operation on the variable `population` in thread2 (line 24). Based on the query parameters and these two intervals, the program obtains the result of running in a weak memory environment.

[0115] In one possible design, the program detection method provided in this application embodiment may further include: using memory read / write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread of the program, to obtain the result that the program is running in a weak memory environment.

[0116] For example, the specific implementation methods of the first operation, the second operation, the third operation and the fourth operation can be referred to the above specific implementation methods, and will not be repeated here.

[0117] Optionally, the memory read / write pattern query rules can be determined based on the query parameters, and the memory read / write pattern query rules can be used to determine whether the first thread and the second thread overlap in time.

[0118] Combination Figure 6 Memory read / write mode query rules can be used to... Figure 6The program shown uses threads 1 and 2 to detect the results of the program running in a weak memory environment.

[0119] For example, memory read / write pattern query rules may include read-read and write-write out-of-order query rules, and / or read-write and write-read out-of-order query rules.

[0120] For example, the read-read, write-write out-of-order query rule may include one or more of the following conditions: the first and second operation instructions are two adjacent operation instructions in the first thread, the first operation instruction is a write operation instruction on the first variable, the second operation instruction is a write operation instruction on the second variable; the third and fourth operation instructions are two adjacent operation instructions in the second thread, the third operation instruction is a read operation instruction on the first variable, and the fourth operation instruction is a read operation instruction on the second variable; the first and third operation instructions are in a competitive relationship, and the second and fourth operation instructions are in a competitive relationship; the interval between the first and second operation instructions is less than the sum of the value corresponding to the on-chip write operation latency and the value corresponding to the cross-NUMA write operation latency; and the interval between the third and fourth operation instructions is less than the value corresponding to the cross-NUMA read operation latency. Thus, the read-read, write-write out-of-order query rule can be used to check the execution results of a program that includes at least two threads, with one thread including read-read operations and the other thread including write-write operations, in a weak memory environment.

[0121] For example, the read / write and write-read out-of-order query rules may include one or more of the following conditions: the fifth and sixth operation instructions are two adjacent operation instructions in the first thread, the fifth operation instruction is a write operation instruction on the third variable, and the sixth operation instruction is a read operation instruction on the fourth variable; the seventh and eighth operation instructions are two adjacent operation instructions in the second thread, the seventh operation instruction is a read operation instruction on the third variable, and the eighth operation instruction is a write operation instruction on the fourth variable; the fifth and seventh operation instructions are in a competitive relationship, and the sixth and eighth operation instructions are in a competitive relationship; the interval between the fifth and sixth operation instructions is less than the sum of the value corresponding to the on-chip write operation latency, the value corresponding to the cross-NUMA write operation latency, and the value corresponding to the cross-NUMA read operation latency; and the interval between the third and eighth operation instructions is less than the sum of the value corresponding to the on-chip write operation latency, the value corresponding to the cross-NUMA write operation latency, and the value corresponding to the cross-NUMA read operation latency. In this way, read-write and write-read out-of-order query rules can be used to check the running results of programs that include at least two threads, one of which includes read-write operations and the other of which includes write-read operations, in a weak memory environment.

[0122] Specifically, a competition relationship can occur when the execution order of two operation instructions affects the execution result. The third variable can include global variables, shared variables, etc., and the fourth variable can also include global variables, shared variables, etc.

[0123] Program statements that satisfy the above memory read / write pattern query rules can be identified as dangerous statements that may result in errors due to instruction reordering in a weak memory environment.

[0124] Thus, if the program meets the memory read / write pattern query rules, the result will be incorrect, which may easily lead to weak memory ordering problems; if the program does not meet the memory read / write pattern query rules, the result will be correct, which may result in correct operation on a weak memory model platform. Users do not need to repeatedly test the program, and the results of the program running in a weak memory environment can be obtained quickly.

[0125] In one possible design, the program detection method provided in this application embodiment may further include: providing results to the user. Optionally, the results may include: correct. Alternatively, the results may include errors and / or modification suggestions.

[0126] For example, "correct" indicates that the program can run correctly in a weak memory environment, while "incorrect" indicates that the program will crash, exit, or produce incorrect calculation results when running in a weak memory environment. Modification suggestions can include the location information of the code that needs to be modified, such as the line number and / or the program file name. These suggestions can be used by a program detection device to modify the program or by the user to manually modify the program to ensure it runs correctly in a weak memory environment. This helps users quickly locate the location in the program that causes errors, quickly complete program modifications, and improve the efficiency of program modification.

[0127] Optionally, if the result is correct, the test result can be displayed to the user through the display interface. If the result is incorrect, the test result and / or modification suggestions can be displayed to the user through the display interface.

[0128] Figure 7 A schematic diagram of the interface of the program testing device provided in the embodiments of this application. Figure 2 .like Figure 7 As shown, if the result is an error, the display interface can show the error result, the corresponding program file name, and the line number of the error statement.

[0129] In one possible design, the program detection method provided in this application embodiment may further include: modifying the program according to modification suggestions in response to a user's confirmation instruction.

[0130] Combination Figure 7When a user selects a specific area to repair in the display interface, the program detection device can respond to the user's confirmation and modify the program according to the suggested modifications. Alternatively, after selecting an area not to repair in the display interface, the user can manually modify the program according to the suggested modifications. This directly assists the user in completing the program modification, further improving the efficiency of program modification.

[0131] based on Figure 1 The program detection method described above involves a program detection device receiving a program provided by a user and obtaining the result of the program running in a weak memory environment based on query parameters and the program. This method can help users quickly check whether a program is running in a weak memory environment, improve the efficiency of program detection, and requires less professional skills from the user.

[0132] In some embodiments, combined with Figure 3 (a) or Figure 3 In step (b), the program checking method provided in the embodiments of this application may further include steps one through eight as described below. The following description uses an example where the program includes a first thread and a second thread.

[0133] Step 1: Analyze the alias relationships among all variables in the multiple variables included in the program.

[0134] Combination Figure 6 and Figure 8 ,analyze Figure 6 The alias relationships of all variables in the program shown can be obtained as follows: Figure 8 The alias relationships shown are {Beijing.Population Alias ​​my_city->population} and {Beijing.sync_flag Alias ​​my_city->sync_flag}.

[0135] Step two: Perform variable dependency analysis on the program.

[0136] For example, the function relationships and variable dependencies in the user-provided program are analyzed, and relevant thread relationship graphs and function call relationship graphs are constructed. The multithreading-related application programming interfaces (APIs) used in the program are analyzed, and a thread data structure based on thread call context and function call context is constructed to distinguish the context of different thread operations and analyze variable dependencies. The multithreading-related APIs may include thread-related functions such as `pthread_create` and `pthread_mutex_lock`.

[0137] Combination Figure 6 and Figure 8 ,right Figure 6The procedure shown can be used to perform variable dependency analysis to obtain the following results: Figure 8 The main function (including its functions and instructions), the first thread (thread1) (including its functions and instructions), and the second thread (thread2) are shown.

[0138] By decomposing the program, we can identify the function call context of the first thread and the function call context of the second thread, thus enabling a thread analysis method based on thread call context and function call context.

[0139] Step 3: Analyze the first variable in the program.

[0140] For example, one or more first variables in the program are analyzed, and the thread call context and function call context accessed by each of the one or more first variables are distinguished. The first variable can be a variable included in both the first thread and the second thread, and the first variable can include shared variables, global variables, etc. In this way, a method for identifying shared variable access points based on thread call context and function call context can be implemented. For example, the search for shared variables can be completed based on an alias analysis algorithm to improve efficiency, and context encoding technology can be used to analyze shared variables in the program to improve computational accuracy.

[0141] Combination Figure 6 and Figure 8 ,right Figure 6 The procedure shown can be used to perform shared variable analysis to obtain, for example... Figure 8 The search results for the variables shown are: my_city->population: {line 17, 24, 31} and my_city->sync_flag: {line 18, 23, 30}.

[0142] Step four: Analyze the lock variables in the program.

[0143] For example, analyze whether any statement in the program uses a lock variable. Analyze one or more mutexes used by both the first and second threads, and distinguish the thread call context and function call context of each mutex. Context encoding techniques can be used to analyze lock variables in the program to improve calculation accuracy.

[0144] Combination Figure 6 and Figure 8 ,right Figure 6 The program shown performs lock variable analysis because Figure 6 The program shown does not include lock variables, therefore, Figure 8 The analysis results do not include locking variables.

[0145] Step 5: Analyze the possibility of the basic program blocks, including the first variable, occurring in parallel.

[0146] For example, a static vector time algorithm can be used to analyze the possibility of parallel occurrence (MHP) of each statement in each basic block (BB) containing the first variable. By constructing vector timestamps for basic blocks that include read or write operations on the first variable, the relative logical time of execution of this basic block within the program or thread can be simulated. This allows for parallel analysis at the basic block level, based on the overall program thread call context and function call context.

[0147] Combination Figure 6 and Figure 8 ,right Figure 6 The procedure shown can be used to perform MHP analysis to obtain results such as... Figure 8 The vector timestamp construction results of the first thread (thread1) and the second thread (thread2) shown indicate that the execution time of the statements in thread1 and thread2 overlaps, and the statements in thread1 and thread2 may be executed concurrently.

[0148] Figure 9 Analysis examples of the programs provided for embodiments of this application Figure 2 . Figure 9 To Figure 6 The analysis results of the program shown (e.g., the file name is weekConsistency.c).

[0149] like Figure 9 As shown, Note 1: ST is an abbreviation for Static Thread. Note 2: We precisely record the call string of each variable. Note 3: In call string types such as A(b)->C(d), A represents the caller, and b represents the call instruction. Note 4: A(b)->C means that A calls C by instruction b.

[0150] Use the above five steps to... Figure 6 Analyzing the program shown (e.g., filename weekConsistency.c), the following information can be obtained: The group includes: a write operation to the global variable `population` in thread1 (line 17 of the source code weekConsistency.c), and a read operation to the global variable `population` in thread2 (line 24 of the source code weekConsistency.c); the group also includes: a write operation to the global variable `syrn_flag` in thread1 (line 18 of the source code weekConsistency.c), and a read operation to the global variable `syrn_flag` in thread2 (line 23 of the source code weekConsistency.c). The time interval between statements on lines 17 and 18 of thread1 overlaps with the time interval between statements on lines 23 and 24 of thread2, indicating that the statements in thread1 and thread2 may execute concurrently.

[0151] It should be noted that steps three to five above describe the internal analysis of a single thread. These steps can be executed on both the first and second threads within the program. This application does not limit the specific implementation method. For example, steps three to five can be executed on the first thread first, and then on the second thread. Alternatively, step three can be executed on the first thread first, and then on the second thread. Similarly, step four can be executed on the first thread first, and then on the second thread.

[0152] It should be noted that the embodiments of this application do not limit the order of steps three to five described above. (In conjunction with...) Figure 3 In (b), steps three, four, and five can be parallel. The execution order of steps three, four, and five does not affect the corresponding execution results of each step.

[0153] Step 6: Query the memory read / write mode of the program.

[0154] Regarding the specific implementation of step six, please refer to the above-mentioned query rules using memory read / write mode to detect the first operation, the second operation, the third operation, and the fourth operation in the first thread of the program to obtain the results of the program running in a weak memory environment. This will not be elaborated here.

[0155] For example, combined Figure 3In step (b), based on the results of steps three to five above, the statements in the program can be queried to obtain the first statement. The first statement includes read and write operations on the same variable, and the read and write operations on the variable are not write-protected, and the read and write operations on the variable may be executed concurrently by the first thread and the second thread at the same time, and the read and write operations on the variable may constitute a race relationship.

[0156] Combination Figure 6 and Figure 8 ,right Figure 6 The program shown performs a memory read / write mode query, because Figure 6 The program shown does not contain dangerous statements, therefore, Figure 8 The results shown can include correct ones.

[0157] Step 7: Obtain the results of the program running in a weak memory environment.

[0158] For example, the first statement is marked as a dangerous statement, which can also be called a dangerous code. Modification suggestions can be determined based on the dangerous code and the type of operation included within it. These modification suggestions may include the line number of the dangerous code and / or the program file name, and the operation type may include a write operation or a read operation.

[0159] Step 8: Provide the results to the user.

[0160] Optionally, the result may include: correct. Alternatively, the result may include errors and / or suggested modifications. For details on the specific implementation of S706, please refer to the above description; it will not be repeated here.

[0161] Optionally, the font color of dangerous code can be changed to a different color than the font color of other code in the program, and displayed to the user through the display interface.

[0162] Figure 10 This application illustrates the use of the program detection method provided in the embodiments of this application. Figure 2 .like Figure 10 As shown, assuming the user-provided program A runs on a strong memory model platform, the program detection device provided in this embodiment uses the program detection method provided in this embodiment to detect program A, and the result is an error. The user can manually or the program detection device can automatically modify program A, such as by inserting memory masking instructions to fix existing problems. After compilation by the compiler, the obtained program A' can run correctly on a weak memory model platform, which can improve the efficiency of program detection and modification.

[0163] based on Figure 3 (a) or Figure 3The program detection method shown in (b) can statically analyze the read and write operations of global variables and their relative timing relationships in the user-provided program, determine whether the program will have problems running in a weak memory environment, identify the location of problematic code, and help users perform automatic or manual repairs, thereby improving the efficiency of program detection and repair.

[0164] The above combination Figures 1-10 The program detection method provided in the embodiments of this application is described in detail below. Figures 11-12 This application provides a detailed description of the program testing device provided in its embodiments.

[0165] Figure 11 This is a schematic diagram of the structure of the program testing device provided in the embodiments of this application. Figure 1 This detection device is suitable for performing... Figure 1 The program detection device in the program detection method shown is functional. For ease of explanation, Figure 11 Only the main components of the detection device for this procedure are shown.

[0166] like Figure 11 As shown, the program detection device 1100 includes a receiving unit 1101 and an acquiring unit 1102. The receiving unit 1101 receives a program provided by a user. The acquiring unit 1102 obtains the result of the program running in a weak memory environment based on query parameters and the program. The query parameters indicate the maximum interval between two operations of the program that would be reordered.

[0167] In one possible design, the acquisition unit 1102 is further configured to obtain the result of the program running in a weak memory environment based on query parameters, the interval between the first operation and the second operation in the first thread of the program, and the interval between the third operation and the fourth operation in the second thread of the program. Optionally, the first operation and the third operation are a pair of read-write operations on the same variable, the second operation and the fourth operation are a pair of read-write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on different variables.

[0168] In one possible design, the acquisition unit 1102 is also used to use memory read / write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread of the program, so as to obtain the result of the program running in a weak memory environment.

[0169] Optionally, the memory read / write pattern query rules can be determined based on the query parameters, and the memory read / write pattern query rules can be used to determine whether the first thread and the second thread overlap in time.

[0170] In one possible design approach, the memory read / write pattern query rules may include read-read, write-write out-of-order query rules, and / or read-write, write-read out-of-order query rules.

[0171] In one possible design approach, the query parameters can be user-defined and may include on-chip write operation latency.

[0172] Optionally, the query parameters may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. This allows for memory read / write pattern queries based on user-inputted parameters.

[0173] In one possible design, the acquisition unit 1102 is also used to acquire the value corresponding to the query parameter. The value corresponding to the query parameter may include the value corresponding to the on-chip write operation latency.

[0174] Optionally, the values ​​corresponding to the query parameters may also include values ​​corresponding to the latency of cross-NUMA write operations and / or the latency of cross-NUMA read operations.

[0175] Alternatively, a weak memory environment can be the runtime environment corresponding to a device running on a non-uniform memory access architecture (NUMA).

[0176] In one possible design, the program testing device 1100 may further include an output unit 1103. The output unit 1103 is used to provide results to the user. The results may include modification suggestions.

[0177] Optionally, the result may include: Correct. Alternatively, the result may include errors and / or suggested modifications.

[0178] Optionally, the modification suggestion may include the location information of the code that needs to be modified, such as the line number and / or program file name. The modification suggestion can be used by a program detection device to modify the program or by a user to manually modify the program.

[0179] In one possible design, the acquisition unit 1102 is also used to modify the program according to the modification suggestion in response to the user's confirmation instruction.

[0180] In one possible design, the program detection device 1100 can be placed in a cloud server.

[0181] It should be noted that the receiving unit 1101 and the output unit 1103 can be set separately or integrated into one module, i.e., a transceiver module. Figure 11 (Not shown in the image). This application does not specifically limit the specific implementation of the receiving unit 1101 and the output unit 1103.

[0182] Optionally, the program detection device 1100 may further include a storage module ( Figure 11 (Not shown in the image), this storage module stores programs or instructions. When the acquisition unit 1102 executes the program or instructions, the program detection device 1100 can execute. Figure 1 The program detection device in the program detection method shown has the following function.

[0183] It should be noted that the program detection device 1100 may be a computer device, server or cloud server, or a chip (system) or other component or part that can be set in a computer device, server or cloud server. This application does not limit this.

[0184] also, Figure 11 The technical effects of the program testing device 1100 shown can be referenced. Figure 1 The technical effects of the detection method shown are not elaborated here.

[0185] Figure 12 This is a schematic diagram of the structure of the program testing device provided in the embodiments of this application. Figure 2 The detection device can be a computer device, server, or cloud server, or it can be a chip (system) or other component or part that can be installed in a computer device, server, or cloud server. This application does not limit this.

[0186] like Figure 12 As shown, the program detection device 1200 may include a processor 1201. Optionally, the program detection device 1200 may also include a memory 1202 and a transceiver 1203. The processor 1201 is coupled to the memory 1202 and the transceiver 1203, for example, they can be connected via a communication bus.

[0187] The following is combined Figure 12 A detailed description of each component of the program testing device 1200 is provided below:

[0188] Processor 1201 is the control center of program detection device 1200. It can be a single processor or a collective term for multiple processing elements. For example, processor 1201 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of this application, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0189] The processor 1201 can execute various functions of the program detection device 1200 by running or executing software programs stored in the memory 1202 and calling data stored in the memory 1202.

[0190] In a specific implementation, as one example, the processor 1201 may include one or more CPUs, for example... Figure 12 CPU0 and CPU1 are shown in the diagram.

[0191] In a specific implementation, as one example, the program detection device 1200 may also include multiple processors, for example... Figure 12 The processors 1201 and 1204 are shown. Each of these processors can be a single-core processor (CPU) or a multi-core processor (CPU). Here, "processor" can refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0192] The memory 1202 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 1202 may be integrated with the processor 1201 or exist independently, and may be accessed via the input / output port of the program detection device 1200. Figure 12 (Not shown in the image) is coupled to the processor 1201, and this embodiment of the application does not specifically limit this.

[0193] The memory 1202 is used to store the software program that executes the solution of this application, and its execution is controlled by the processor 1201. Specific implementation methods described above can be found in the above method embodiments, and will not be repeated here.

[0194] Transceiver 1203 is used for communication with other devices. Furthermore, transceiver 1203 may include a receiver and a transmitter. Figure 12 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function. The transceiver 1203 can be integrated with the processor 1201 or exist independently, and is connected via the input / output port of the program detection device 1200 (…). Figure 12 (Not shown in the image) is coupled to the processor 1201, and this embodiment of the application does not specifically limit this.

[0195] It should be noted that, Figure 12 The structure of the program testing device 1200 shown does not constitute a limitation on the program testing device. The actual program testing device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0196] This application provides a chip system. The chip system includes a processor and input / output ports. The processor is used to implement the processing functions involved in the above-described method embodiments, and the input / output ports are used to implement the transmit / receive functions involved in the above-described method embodiments.

[0197] In one possible design, the chip system also includes a memory for storing program instructions and data that implement the functions involved in the above method embodiments.

[0198] This chip system can consist of chips or include chips and other discrete components.

[0199] This application provides a computer-readable storage medium, comprising: computer instructions stored in the computer-readable storage medium; when the computer instructions are executed on a computer, the computer causes the computer to perform the program detection method described in the above method embodiments.

[0200] This application provides a computer program product containing instructions, including a computer program or instructions, which, when run on a computer, cause the computer to execute the program detection method described in the above method embodiments.

[0201] It should be understood that the processor in the embodiments of this application can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0202] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0203] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0204] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0205] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0206] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0207] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0208] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0209] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0210] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0211] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0212] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0213] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A program detection method, characterized in that, include: Receive programs provided by users; Based on the query parameters and the program, the result of the program running in a weak memory environment is obtained; wherein, the result includes: correct, or, the result includes: error and / or modification suggestion, and the query parameters are used to indicate the maximum interval between two operations of the program being reordered, wherein reordering refers to a change in the execution order of two operations of the program; The step of obtaining the result of the program running in a weak memory environment based on the query parameters and the program includes: obtaining the result of the program running in the weak memory environment based on the query parameters, the interval between the first operation and the second operation in the first thread of the program, and the interval between the third operation and the fourth operation in the second thread of the program.

2. The procedure detection method according to claim 1, characterized in that, The first operation and the third operation are a pair of read and write operations on the same variable, the second operation and the fourth operation are a pair of read and write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on different variables.

3. The procedure detection method according to claim 2, characterized in that, Also includes: The memory read / write mode query rules are used to detect the first operation, the second operation, the third operation, and the fourth operation in the first thread of the program, to obtain the result of the program running in the weak memory environment.

4. The procedure detection method according to claim 3, characterized in that, The memory read / write mode query rule is determined based on the query parameters, and the memory read / write mode query rule is used to determine whether the first thread and the second thread overlap in time.

5. The procedure detection method according to any one of claims 1-4, characterized in that, The query parameters are determined by the user, and the query parameters include the on-chip write operation latency.

6. The procedure detection method according to any one of claims 1-4, characterized in that, The weak memory environment refers to the operating environment of devices running on a Non-Unified Memory Access Architecture (NUMA).

7. The procedure detection method according to any one of claims 1-4, characterized in that, Also includes: The results are provided to the user, wherein the results include suggested modifications.

8. The procedure detection method according to claim 7, characterized in that, Also includes: In response to the user's confirmation instruction, the program is modified according to the modification suggestion.

9. A program detection device, characterized in that, include: Receiving unit and acquiring unit; wherein, The receiving unit is used to receive programs provided by the user; The acquisition unit is used to obtain the result of the program running in a weak memory environment based on the query parameters and the program; wherein, the result includes: correct, or, the result includes: error and / or modification suggestion, and the query parameters are used to indicate the maximum interval between two operations of the program being reordered, wherein reordering refers to a change in the execution order of two operations of the program; The acquisition unit is further configured to obtain the result of the program running on the weak memory environment based on the query parameters, the interval between the first operation and the second operation in the first thread of the program, and the interval between the third operation and the fourth operation in the second thread of the program.

10. The procedure detection device according to claim 9, characterized in that, The first operation and the third operation are a pair of read and write operations on the same variable, the second operation and the fourth operation are a pair of read and write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on different variables.

11. The procedure detection device according to claim 9, characterized in that, The acquisition unit is further configured to use memory read / write mode query rules to detect the first operation, the second operation, the third operation, and the fourth operation in the first thread of the program, and to obtain the result of the program running in the weak memory environment.

12. The procedure detection device according to claim 11, characterized in that, The memory read / write mode query rule is determined based on the query parameters, and the memory read / write mode query rule is used to determine whether the first thread and the second thread overlap in time.

13. The procedure testing apparatus according to any one of claims 9-12, characterized in that, The query parameters are determined by the user, and the query parameters include the on-chip write operation latency.

14. The procedure testing apparatus according to any one of claims 9-12, characterized in that, The weak memory environment refers to the operating environment of devices running on a Non-Unified Memory Access Architecture (NUMA).

15. The procedure testing apparatus according to any one of claims 9-12, characterized in that, Also includes: Output unit; where, The output unit is used to provide the results to the user; wherein the results include modification suggestions.

16. The procedure detection device according to claim 15, characterized in that, The acquisition unit is further configured to modify the program according to the modification suggestion in response to the user's confirmation instruction.

17. The procedure testing apparatus according to any one of claims 9-12, characterized in that, The program detection device is located in a cloud server.

18. A program detection device, characterized in that, The device includes: a processor coupled to a memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory, so that the apparatus performs the program detection method as described in any one of claims 1-8.

19. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the program detection method as described in any one of claims 1-8.

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