Compressed ftl table and accelerator thereof

Abstract

Provided are compressed FTL tables and accelerators thereof. The provided FTL accelerator includes a read address calculation unit, a read data selection unit, a read address sending unit, and a read data receiving unit. The read address calculation unit calculates, according to an index (L) of an entry of a logical FTL table to be read, an address of an entry of a physical FTL table corresponding to the entry of the logical FTL table to be accessed. The read address calculation unit also indicates to the read data selection unit a portion of data read from a memory that belongs to the entry of the physical FTL table to be accessed. The read data selection unit obtains, according to the indication of the read address calculation unit, the portion of the data read from the memory that belongs to the entry of the physical FTL table to be accessed, and expands the entry of the physical FTL table to be accessed to obtain the entry of the logical FTL table to be accessed.

Description

Technical Field

[0001] This application relates to storage technology, and in particular to compressed FTL tables, methods of using them, and hardware accelerators that provide compressed FTLs. Background Technology

[0002] See Figure 1 The diagram illustrates a block diagram of a storage device. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and storage device 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the aforementioned methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] Common types of NVMs include NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), and XPoint memory.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, mapping host logical addresses to NVM chip physical addresses, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 140 and can access the data in the DRAM 110. The DRAM stores the FTL table and / or caches the I / O command data.

[0006] The control unit 104 includes a flash interface controller (or media interface, media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] NVM storage media typically store and retrieve data in pages, while erasing data in blocks. A block (also called a physical block) on an NVM storage medium contains multiple pages. A page (called a physical page) on the storage medium has a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0008] In storage devices, the FTL (Flash Translation Layer) is used to maintain the mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the solid-state storage device. In existing technologies, address mapping can also be implemented using intermediate address formats. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address. Optionally, the host accessing the storage device provides the FTL.

[0009] A table structure that stores mapping information from logical addresses to physical addresses is called an FTL table (also known as an L2P table). Typically, the data items in an FTL table record the address mapping relationships in storage devices in units of specified storage units (e.g., 512 bytes, 2KB, 4KB, etc.). Summary of the Invention

[0010] As storage device capacity increases, the size of the FTL (Framework Time Table) increases to record more storage units, requiring more memory to house it. To address updated storage units, the size of each entry in the FTL also needs to increase. For example, a 32-bit FTL entry can address 2^32 data units. If each data unit is 4KB, 2^32 data units correspond to a 16TB storage capacity, meaning the FTL itself would be 16GB, requiring at least 16GB of memory. However, storage devices come in various capacities; for example, if a user's storage device is 4TB, the FTL could be 4GB. However, to provide 4TB of storage, if each data unit is 4KB, the FTL needs to manage 2^30 data units, requiring only 30 bits per entry, resulting in a FTL size of 30 * 2^30 bits (3.75GB, less than 4GB). However, due to limitations imposed by memory chips and CPU addressing methods, CPU addressing channels typically use data widths that are multiples of 32 bits or bytes per address, and memory chips also generally use data widths that are multiples of bytes. Therefore, if the FTL table entry size is, for example, 30 bits, although this reduces the overall size of the FTL table, entries that cross byte boundaries require, for example, two or more bus accesses or memory accesses to load into the CPU. This significantly increases the time required to load FTL table entries, limiting the performance of the storage device.

[0011] To reduce the memory space occupied by the FTL table when providing storage devices of various capacities, and to reduce or eliminate the impact of non-byte-aligned FTL table entries on CPU or other devices within the chip accessing FTL table entries, embodiments of this application provide a compressed FTL table. The size of entries in the provided compressed FTL table may not be an integer multiple of bytes. Furthermore, the compressed FTL table entries are tightly packed in memory without leaving unused memory space between entries for byte alignment. Embodiments of this application also suggest that the CPU or other devices access the FTL table in their existing manner, either byte-aligned or aligned to integer multiples of bytes, thereby eliminating the impact of using a compressed FTL table on the CPU or other devices. It is also desirable to use hardware accelerators to process the FTL table, thereby offloading the burden introduced to the CPU by software access to the FTL table and improving FTL table access performance.

[0012] According to a first aspect of this application, a first FTL accelerator according to the first aspect of this application is provided, including a read address calculation unit, a read data selection unit, a read address sending unit, and a read data receiving unit; the read address calculation unit calculates the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be accessed based on the index (L) of the entry of the logical FTL table to be read, wherein the size of the logical FTL table entry is M bits, the size of the physical FTL table entry is N bits, M and N are positive integers, and M>N, and wherein there is a one-to-one correspondence between the entries of the logical FTL table and the entries of the physical FTL table; The address calculation unit is coupled to the read address sending unit. The read address sending unit accesses the memory using the address provided by the read address calculation unit. The read data receiving unit receives data provided by the memory and provides it to the read data selection unit. The read address calculation unit also indicates to the read data selection unit the portion of the data read from the memory that belongs to the entry of the physical FTL table to be accessed. The read data selection unit obtains the portion of the data read from the memory that belongs to the entry of the physical FTL table to be accessed based on the data indicated by the read address calculation unit, and expands the entries of the physical FTL table to be accessed to obtain the entries of the logical FTL table to be accessed.

[0013] According to the first FTL accelerator of the first aspect of this application, a second FTL accelerator according to the first aspect of this application is provided, further comprising: a read address cache unit and a read data cache unit; the read address cache unit stores an index (L) of an entry of a logical FTL table to be accessed; the read data cache unit stores an entry of a logical FTL table to be accessed; a read address calculation unit is coupled to the read address cache unit and obtains the index (L) from the read address cache unit; a read data selection unit stores a portion of the data read from the memory that belongs to an entry of a physical FTL table to be accessed in the read data cache; the entries of the physical FTL table to be accessed stored in the read data cache are expanded to the size of an entry of a logical FTL table to be accessed, so as to obtain an entry of a logical FTL table to be accessed.

[0014] According to the first or second FTL accelerator of the first aspect of this application, a third FTL accelerator according to the first aspect of this application is provided, wherein the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be accessed, calculated by the read address calculation unit according to the index (L), is the address of one or more bytes in the storage space of the physical FTL table, starting from the Nmod 8th bit of the byte address ⌊L / 8⌋, which stores N bits of data.

[0015] According to one of the first to third FTL accelerators of the first aspect of this application, a fourth FTL accelerator according to the first aspect of this application is provided, wherein if N mod 8 is 0, the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be accessed, calculated by the read address calculation unit according to the index (L), is the address of the N / 8⌋th byte starting from the N mod 8th bit of the byte address ⌊L / 8⌋; if L*N mod 8 is not 0, and (N mod 8) – (8-L*N mod 8) <= 0, the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be accessed, calculated by the read address calculation unit according to the index (L), is the address of the N / 8⌋+1th byte starting from the N mod 8th bit of the byte address ⌊L / 8⌋; if L*N mod 8 is not 0, and (N mod 8) – (8-L*N mod 8) If the value is greater than 0, then the address of the physical FTL table entry corresponding to the logical FTL table entry to be accessed, calculated by the read address calculation unit according to the index (L), is the address of the N mod 8th bit of the byte address ⌊L / 8⌋+2 bytes.

[0016] According to one of the first to fourth FTL accelerators of the first aspect of this application, a fifth FTL accelerator according to the first aspect of this application is provided, wherein if N mod 8 is 0, the portion of the data read from memory by the read address calculation unit to the read data selection unit that belongs to the entry of the physical FTL table to be accessed includes the complete data of the address of the ⌊N / 8⌋th byte starting from the N mod 8th bit of the byte address ⌊L / 8⌋; if L*N mod 8 is not 0, the portion of the data read from memory by the read address calculation unit to the read data selection unit that belongs to the entry of the physical FTL table to be accessed includes the L*N mod 8th bit to the last bit of the byte with byte address L*N / 8; if (L+1)*N mod 8 is not 0, the portion of the data read from memory by the read address calculation unit to the read data selection unit that belongs to the entry of the physical FTL table to be accessed includes the first (L+1)*N mod 8th bits of the byte with byte address (L+1)*N / 8.

[0017] According to one of the first to fifth FTL accelerators of the first aspect of this application, a sixth FTL accelerator according to the first aspect of this application is provided, further comprising: a write address calculation unit, a write command processing unit, and a write data concatenation unit; the write address calculation unit calculates the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be updated based on the index (L) of the entry of the logical FTL table to be updated; the write data concatenation unit obtains the corresponding N-bit physical FTL table entry from the entry of the logical FTL table to be updated; the write command processing unit is coupled to the write address calculation unit and writes the N-bit physical FTL table entry obtained by the write data concatenation unit into the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be updated provided by the write address calculation unit.

[0018] According to the sixth FTL acceleration of the first aspect of this application, a seventh FTL accelerator according to the first aspect of this application is provided, wherein the write address calculation unit further calculates one or two addresses to be read from the physical FTL table based on the index (L) of the entry of the logical FTL table to be updated, and provides the one or two addresses to be read from the physical FTL table to the write command processing unit; the write command processing unit reads data from the memory based on the one or two addresses to be read from the physical FTL table; the write address calculation unit further indicates to the write data selection unit the portion of the data read from the memory that does not belong to the entry of the physical FTL table to be updated; the write data selection unit obtains the portion of the data read from the memory that does not belong to the entry of the physical FTL table to be updated based on the instruction of the write address calculation unit. The write data concatenation unit provides the write data to the logical FTL table entries and the write data selection unit to the write data concatenation unit. The write data concatenation unit then concatenates the corresponding N-bit physical FTL table entries obtained from the logical FTL table entries to be updated with the write data selection unit's portion of the physical FTL table entries obtained from the memory that do not belong to the physical FTL table entries to be updated. The write command processing unit then writes the N-bit physical FTL table entries provided by the write data concatenation unit and the portion of the physical FTL table entries obtained from the memory that do not belong to the physical FTL table entries to be updated into the address of the physical FTL table entries corresponding to the logical FTL table entries to be updated, provided by the write address calculation unit.

[0019] According to the sixth or seventh FTL accelerator of the first aspect of this application, an eighth FTL accelerator according to the first aspect of this application is provided, wherein if N mod 8 is 0, the address of the physical FTL table entry calculated by the write address calculation unit according to the index (L) is the address of the ⌊N / 8⌋th byte starting from the N mod 8th bit of the byte address ⌊L / 8⌋; if L*N mod 8 is not 0, and (N mod 8) – (8-L*N mod 8) <= 0, the address of the physical FTL table entry calculated by the write address calculation unit according to the index (L) is the address of the ⌊N / 8⌋+1th byte starting from the N mod 8th bit of the byte address ⌊L / 8⌋; if L*N mod 8 is not 0, and (N mod 8) – (8-L*N mod 8) If the value is greater than 0, then the address of the physical FTL table entry calculated by the write address calculation unit according to the index (L) is the address of the Nth mod 8th bit of the byte address ⌊L / 8⌋ + 2 bytes.

[0020] According to the seventh or eighth FTL accelerator of the first aspect of this application, a ninth FTL accelerator according to the first aspect of this application is provided, wherein if L*N mod 8 is not 0, the portion of the data read from memory by the write address calculation unit that does not belong to the entry of the physical FTL table to be updated includes the first L*N mod 8 bits of the byte with byte address L*N / 8; if (L+1)*N mod 8 is not 0, the portion of the data read from memory by the write address calculation unit that does not belong to the entry of the physical FTL table to be updated includes the (L+1)*N mod 8 bits to the last bit of the byte with byte address (L+1)*N / 8.

[0021] According to one of the sixth to ninth FTL accelerators of the first aspect of this application, a tenth FTL accelerator according to the first aspect of this application is provided, further comprising a write address sending unit; the write command processing unit includes a read address generation unit and a write address generation unit; the read address generation unit uses one or two addresses to be read from the physical FTL table to read data from the memory through the read address sending unit; the read data receiving unit receives the data read from the memory; the write address generation unit sends the address of the physical FTL table entry corresponding to the entry of the logical FTL table to be updated, provided by the write address calculation unit, through the write address sending unit.

[0022] According to one of the first to tenth FTL accelerators of the first aspect of this application, an eleventh FTL accelerator according to the first aspect of this application is provided, further comprising: a master device interface for coupling a bus; a read address sending unit sending a read address to the bus through the master device interface; a read data receiving unit obtaining read data from the bus through the master device interface; a write address sending unit sending a write address to the bus through the master device interface; and a write data sending unit sending data to be written to the bus through the master device interface.

[0023] According to one of the first to eleventh FTL accelerators of the first aspect of this application, a twelfth FTL accelerator according to the first aspect of this application is provided, further comprising: a slave device interface for coupling a bus; a read address cache storing an index (L) of entries of a logical FTL table to be read obtained through the slave device interface; a read data cache storing entries of a logical FTL table to be read to be sent through the slave device interface; a write address cache storing an index (L) of entries of a logical FTL table to be written obtained through the slave device interface; and a write data cache storing entries of a logical FTL table to be written obtained through the slave device interface.

[0024] According to a second aspect of this application, a first control component according to the second aspect of this application is provided, comprising: a first master device, an FTL accelerator, a memory controller, and a bus; the FTL accelerator is coupled to the bus via a master device interface; the memory controller is coupled to the bus via a slave device interface, and the memory controller is also coupled to a memory; the aforementioned FTL accelerator is one of the first to twelfth FTL accelerators according to the first aspect of this application.

[0025] According to the first control component of the second aspect of this application, a second control component according to the second aspect of this application is provided, wherein the first master device provides the FTL accelerator with an index (L) of an entry of a logical FTL table to be read; the FTL accelerator, in response to the index (L) provided by the first master device, accesses the entry of the same index (L) of the physical FTL table in the memory through a master device interface.

[0026] According to the second control component of the second aspect of this application, a third control component according to the second aspect of this application is provided, wherein the FTL accelerator obtains the entry corresponding to the same index (L) of the physical FTL table obtained by accessing the memory through the master device interface, and generates the entry corresponding to the same index (L) of the logical FTL table and provides it to the first master device.

[0027] According to one of the first to third control components of the second aspect of this application, a fourth control component according to the second aspect of this application is provided, wherein the FTL accelerator is further coupled to the bus via a slave device interface; the first master device accesses a first address space using an index (L); the bus forwards the index (L) provided by the first master device to the FTL accelerator via the slave device interface according to the first address space; and the bus forwards the first master device's access to a second address space to the memory controller.

[0028] According to one of the first to third control components of the second aspect of this application, a fifth control component according to the second aspect of this application is provided, wherein the first master device is directly coupled to the FTL accelerator; the first master device directly provides the index (L) to the FTL accelerator based on the index (L) being located in the first address space; the first master device sends access to the second address space to the bus; and the bus forwards access to the second address space to the memory controller based on the second address space.

[0029] According to one of the first to fifth control components of the second aspect of this application, a sixth control component according to the second aspect of this application is provided, wherein the first master device is a CPU. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0031] Figure 1 A block diagram showing a storage device using existing technology;

[0032] Figure 2A A schematic diagram illustrating the logical FTL table and the physical FTL table according to an embodiment of this application is shown;

[0033] Figure 2B A schematic diagram of a compressed FTL table in memory according to an embodiment of this application is shown;

[0034] Figure 3 A block diagram showing a control component including an FTL accelerator according to an embodiment of this application is illustrated;

[0035] Figure 4 A block diagram of an FTL accelerator according to an embodiment of this application is shown;

[0036] Figure 5A A flowchart illustrating the process of an FTL accelerator handling read requests for a logical FTL table according to an embodiment of this application is shown.

[0037] Figure 5B A flowchart illustrating the process of writing requests to a logical FTL table by an FTL accelerator according to an embodiment of this application is shown.

[0038] Figure 6A and Figure 6B A schematic diagram showing the corresponding entries of the logical FTL read from the physical FTL table;

[0039] Figure 6C and Figure 6D A schematic diagram showing the writing of the corresponding entry into the logical FTL table to the physical FTL table;

[0040] Figure 7 A block diagram of control components including an FTL accelerator is shown according to yet another embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] Figure 2A A schematic diagram of the logical FTL table and the physical FTL table according to an embodiment of this application is shown.

[0043] According to embodiments of this application, a logical FTL table and a physical FTL table are provided. The logical FTL table is an FTL table perceived by the device accessing the FTL table. The device accessing the FTL table is, for example, a CPU or control unit (see also...). Figure 1 Other bus devices (control unit 104). The physical FTL table is in memory (e.g., Figure 1 The FTL table is stored in DRAM 104.

[0044] As an example, both the logical FTL table and the physical FTL table contain multiple entries, addressed by logical addresses (denoted as LBAs). The entries in the logical FTL table and the physical FTL table correspond one-to-one, thus having the same number of entries. The number of entries in each table is denoted as MaxLBA. The size of an entry in the logical FTL table is M bits, and the size of an entry in the physical FTL table is N bits, where M and N are both positive integers.

[0045] Optionally, to facilitate, for example, CPU access to the logical FTL table, the size of M is an integer multiple of, for example, 8 or 32, so that entries in the logical FTL table are aligned by byte or DWORD (double word). See also Figure 2A From the perspective of the CPU accessing the logical FTL table, the logical FTL table consists of MaxLBA entries, each entry being M bits in size. Figure 2A In the example, M=64), the entries of the logical FTL table are arranged sequentially in the storage space, one end to the other. The corresponding FTL table entry is obtained by indexing the storage space of the logical FTL table using a logical address (LBA). The FTL table entries record the addresses used for the NVM chip (called physical addresses, denoted as PBAs). Because the logical FTL table entries are aligned to bytes or double words, the starting address of each entry in the storage space is located at the beginning of a byte or double word, and the end of the entry is located at the end of a byte or double word. Figure 2A In the example, when the CPU accesses the corresponding entry in the FTL table using the logical address (LBA) as an index, it obtains the address of the corresponding entry in the FTL table by, for example, LBA*8 (64 bits correspond to 8 bytes).

[0046] For the physical FTL table, each entry is N bits in size, where N is any positive integer less than M. The value of N is determined by the number of data units provided by the NVM chip that the FTL table entry addresses. For example, to address 2^30 data units, then N is 30. Generally, if an entry in the physical FTL table can address one of 2^n data units, then N = n. As an example, Figure 2A In this case, N=33. In the physical FTL table, each entry is stored in the memory space provided by the memory with its first and last entries grounded. Therefore, the start and / or end positions of some entries are not located at byte boundaries.

[0047] Figure 2B A schematic diagram of a compressed FTL table in memory according to an embodiment of this application is shown.

[0048] For example, a compressed FTL table is stored starting at address 0 in memory. The memory width is, for example, 64 bits, meaning that 64 bits (8 bytes) of data are read from memory at a time. The entries in the compressed FTL table are stored contiguously in memory, with no unused storage space between adjacent entries, so that the start and / or end addresses of the entries are not located at byte boundaries of the storage space.

[0049] Figure 2B In this context, a marker of the form PBA(i) represents one of the entries in the compressed FTL table (its value is the i-th physical address (PBA) of the FTL table, where i is, for example, an integer). See also Figure 2BThe compressed FTL table entry PBA(0) is stored in the first 33 bits starting from the 0-byte address of memory. The first 31 bits of the compressed FTL table entry PBA(1) are stored in the first 34 bits to the 64-byte address of memory. The remaining 2 bits of the compressed FTL table entry PBA(1) are stored in the first 8-byte address of memory. Next, the compressed FTL table entry PBA(2) is stored in the first 3-byte address of memory. The first 29 bits of the compressed FTL table entry PBA(3) are stored in the first 36-byte address of memory. The remaining 4 bits of the compressed FTL table entry PBA(4) are stored in the first 12-byte address of memory. The compressed FTL table entry PBA(5) is stored in the first 5-byte address of memory. And then comes the compressed FTL table entry PBA(6).

[0050] Therefore, one or more entries in the physical FTL table are not aligned to byte boundaries or to the read data bit width in memory. Consequently, the storage space occupied by the physical FTL table in memory is smaller than the size of the logical FTL table perceived by the CPU.

[0051] According to an embodiment of this application, the CPU accesses the logical FTL table using the logical address LBA as an index, while the FTL accelerator calculates the address in memory of the corresponding entry in the physical FTL table based on the logical address LBA, and obtains the entry of the FTL table to be accessed through one or more memory accesses in response to the CPU's access to the logical FTL table.

[0052] According to an embodiment of this application, the storage location of the corresponding entry in the physical FTL table relative to the starting address of the physical FTL table is calculated based on the entries in the logical FTL table indexed by LBA: if LBA*N mod 8 is 0 (mod represents modulo operation), then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting from the byte address LBA *N / 8, which occupies N / 8 or N / 8+1 bytes; if LBA*N mod 8 is not 0, then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting from LBA*N mod 8 bits after the byte address LBA * / 8, which occupies N / 8+1 or N / 8+2 bytes. For example, if LBA*N mod 8 is not 0 and (N mod 8) – (8-LBA*N mod 8)<= 0, the corresponding N-bit storage space occupies N / 8 (rounded down)+1 bytes; if LBA*N mod 8 is not 0 and (N mod 8) – (8-LBA*N mod 8) > 0, the corresponding N-bit storage space occupies N / 8 (rounded down)+2 bytes.

[0053] Figure 3 A block diagram of control components including an FTL accelerator is shown according to an embodiment of this application.

[0054] The control unit includes, for example, a CPU, a media interface controller (NFI), an FTL accelerator, and a memory controller. The CPU, NFI, FTL accelerator, and / or memory controller are coupled, for example, via a bus. The control unit is also coupled to external memory. Figure 3 The memory controller is used to access external memory (DRAM). Optionally, each device on the bus is assigned an address space on the bus. Thus, when a bus access request requests the address accessed, the bus forwards the access request to the device corresponding to the accessed address. For example, the FTL accelerator is assigned a 0-8GB bus address space, the memory controller is assigned a 16GB-32GB bus address space, and the NFI is assigned, for example, a 1MB address space starting at 8GB. From the CPU's perspective, the logical FTL table is contained in the 0-8GB address space occupied by the FTL accelerator. The physical FTL table is contained in the 16GB-32GB bus address space occupied by the memory controller. Access requests from the CPU to the 0-8GB bus address space are forwarded to the FTL accelerator for processing, while requests from the CPU to the 16GB-32GB bus address space are forwarded to the memory controller for processing.

[0055] According to embodiments of this application, the FTL accelerator includes a slave interface and a master interface. The FTL accelerator is coupled to a bus via the slave interface and the master interface, respectively. Thus, one or more devices of the control unit (e.g., CPU, NFI) can access the FTL accelerator as a bus slave via the slave interface, while the FTL accelerator can access one or more devices of the control unit (e.g., memory controller) as a master via the master interface.

[0056] As an example, from the CPU's perspective, the logical FTL table resides in a designated memory space, such as an 8GB memory space starting from byte 0. Each entry in the logical FTL table is M = 64 bits (8 bytes). Each entry in the physical FTL table is N = 33 bits.

[0057] Therefore, the CPU sends an access request to the logical FTL table (indexed as LBA) via the bus. Figure 3 In the middle, as indicated by (1), the address accessed is LBA*8, with a length of 8 bytes. The bus sends the access request to the FTL accelerator for processing based on the address range of 0 to 8GB indicated by the memory space access request from the CPU. The bus provides the access request to the FTL accelerator through the slave interface of the FTL accelerator ( Figure 3 In the middle, as indicated by (2). The FTL accelerator determines the storage location of the corresponding 33-bit entry in the physical FTL table based on the address (LBA*8) indicated in the received access, and sends one or more memory access requests to the memory controller via the bus through its master device interface to obtain the 33-bit physical FTL table entry from DRAM ( Figure 3 In the middle, as indicated by (3). The FTL accelerator sends the access request to the bus through its master device interface, and the bus sends the access request to the memory controller for processing based on the address range accessed by the bus request, which is, for example, 16GB to 32GB. Figure 3 In the middle, it is also indicated by (3). Thus, the starting address of the address space range of the memory controller on the bus is 16GB, and the storage location of the 33-bit entry determined by the FTL accelerator in the physical FTL table is also subject to an offset value of, for example, 16GB from the address space range of the memory controller on the bus. The memory controller responds to the access request from the FTL accelerator, accesses the DRAM, and provides the processing result of the access request to the FTL accelerator through the FTL accelerator's master device interface. Based on the processing result provided by the memory controller, the FTL accelerator completes its access to the entries of the logical FTL table to the CPU through its slave device interface ( Figure 3In the context of (4), for example, if the CPU wants to read a logical FTL table entry, the FTL accelerator provides the CPU with a 64-bit entry in response to its access request, based on the size of the logical FTL table entry. Understandably, the physical FTL table entries recorded in DRAM are, for example, 33 bits in size, and the FTL accelerator fills the 33-bit entry obtained from DRAM with data and provides the CPU with a 64-bit entry.

[0058] Access to DRAM is byte-aligned. The FTL accelerator accesses multiple bytes of DRAM to access entries in the physical FTL table, some of which are bits that do not belong to the physical FTL table entries being accessed. The FTL accelerator must also prevent these bits that do not belong to the physical FTL table entries from being corrupted.

[0059] Figure 4 A block diagram of an FTL accelerator according to an embodiment of this application is shown.

[0060] The FTL accelerator includes a write address buffer, a write data buffer, a read address buffer, a read data buffer, a write address calculation unit, a write data concatenation unit, a read address calculation unit, a read data selection unit, a write command processing unit, a write data concatenation unit, a read address sending unit, a write address sending unit, a read data receiving unit, and a write data sending unit. The FTL accelerator also includes a slave interface and a master interface. The slave interface and master interface are each coupled to the bus.

[0061] The FTL accelerator's write address cache, write data cache, write address calculation unit, write data concatenation unit, write command processing unit, write data selection unit, write address sending unit, and write data sending unit are used to process update requests to the logical FTL table. The FTL accelerator's read address cache, read data cache, read address calculation unit, read data selection unit, read address sending unit, and read data receiving unit are used to process read requests to the logical FTL table. The read address sending unit and read data receiving unit are used in both processing update and read requests to the logical FTL table.

[0062] The write address cache, write data cache, read address cache, and read data cache are each coupled to the slave device interface to receive and cache logical FTL table update / read requests sent to the FTL accelerator by other bus master devices such as the CPU. For logical FTL table update requests, the write address cache records the address to be accessed by the update request; the cached address is, for example, the address used to access an entry in the logical FTL table (e.g., the logical address LBA). The FTL accelerator is configured with the starting address of the physical FTL table in memory, the memory bus address, and the size of the physical FTL table entries (N bits, see also...). Figure 2A) and the size of entries in the logical FTL table (M bits, see also Figure 2A The write data cache records the entries in the logical FTL table indicated by the update request. The size of the logical FTL table entries recorded in the write data cache is, for example, M bits.

[0063] For example, an FTL table update request indicates that the logical address LBA corresponds to entry E in the logical FTL table. For example, the first M bits of entry E have the same width as the corresponding entry in the physical FTL table and need to be written to the physical FTL table, while the other bits of entry E are discarded.

[0064] The write address calculation unit calculates the memory address of the entry in the physical FTL table corresponding to the logical address LBA to be updated, based on the logical address LBA obtained from the write address cache, the configured physical FTL table entry size N, and the address of the physical FTL table in memory.

[0065] If LBA*N mod 8 is 0 and N mod 8 is 0, then the corresponding entry in the physical FTL table is stored in N bits of storage space starting at byte address LBA *N / 8. The write address calculation unit calculates the byte address of ⌈N / 8⌉ consecutive bytes starting from byte address LBA *N / 8. All bits of these bytes will be updated, where ⌈⌉ represents rounding up. If LBA*N mod 8 is 0 and N mod 8 is not 0, then for the byte at byte address (LBA+1)*N / 8, only the first (LBA+1)*N mod 8 bits need to be updated.

[0066] If LBA*N mod 8 is not 0, then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting from LBA*N mod 8 bits after the byte address LBA*N / 8 (rounded down). This N-bit storage space occupies N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2 bytes. The write address calculation unit calculates the byte address of N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2 consecutive bytes starting from the byte address LBA*N / 8. All or some bits of these bytes will be updated. The write address calculation unit also determines the number of bytes (N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2) of the physical FTL table entry to be updated stored in memory.

[0067] The write data concatenation unit concatenates N bits from the M-bit logical FTL table entries in the write buffer, which are used for entries in the physical FTL table, with a portion of the bits from the byte containing the entry to be updated in the physical FTL table, to obtain the complete content of each byte of the entry to be updated in the FTL table. For example, if LBA*N mod 8 is 0, then the length of the concatenated data by the write data concatenation unit is LBA*N / 8 bytes. The first N bits of this data come from the N bits in the buffer used for physical FTL table entries, and the optional remaining bits come from a portion of the bits from the byte containing the entry to be updated in the physical FTL table, which is read from the physical FTL table. The byte address of this portion of bits in the physical FTL table is (LBA+1)*N / 8 (rounded down), and it is located in the last 8 - (LBA+1)*N mod 8 bits of that byte. If LBA*N mod 8 is not 0, then the size of the data concatenated by the write data concatenation unit is N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2 bytes. The first LBA*N mod 8 bits come from the first LBA*N mod 8 bits of the byte at memory address LBA*N / 8, the next N bits come from the N bits cached for the physical FTL table entry, and optionally the remaining bits. If (LBA*N+N) mod 8 is not 0, then the remaining bits come from the last part of the byte to be updated in memory (byte address (LBA*N+N) / 8, rounded down) (its last 8 - (LBA*N+N) mod 8 bits). If (LBA*N+N) mod 8 is 0, then the remaining bits do not exist.

[0068] Understandably, for various storage methods of the physical FTL table, and / or the interface width of the memory storing the physical FTL table (e.g., byte-based or double-word-based access), the write address calculation unit calculates the address in memory of the corresponding entry in the physical FTL table based on the index (logical address LBA) of the logical FTL table entry. The write address calculation unit also calculates and indicates the position of the bits to be concatenated to the write data concatenation unit.

[0069] Since data concatenation is required, the write command processing unit reads a portion of the physical FTL table from memory based on 0, 1, or 2 byte addresses containing the data to be concatenated, provided by the write address calculation unit. If LBA * N mod 8 is 0, and if (LBA+1) * N mod 8 is 0, then there is no need to read the physical FTL table from memory. If LBA * N mod 8 is 0, the byte address containing the data to be concatenated is (LBA*N+N) / 8 (rounded down), where the bits used for concatenation are the last 8 - (LBA*N+N) mod 8 bits (i.e., 8 - N mod 8 bits). If LBA * N mod 8 is not 0, and (LBA * N + N) mod 8 is 0, then the byte address containing the data to be concatenated is LBA*N / 8 (rounded down), where the bits used for concatenation are the first LBA*N mod 8 bits. If LBA * N mod 8 is not 0, and (LBA * N + N) mod 8 is also not 0, then the byte address storing the data to be concatenated is (LBA * N) / 8 (rounded down) and (LBA * N + N) / 8 (rounded down) (a total of 2 bytes). The first byte's concatenation bits are the first (LBA * N) mod 8 bits, and the second byte's concatenation bits are the last 8 - (LBA * N + N) mod 8 bits. Due to memory interface limitations, the write command processing unit must read the complete byte containing the data to be concatenated from memory. Optionally, the write address calculation unit indicates to the write command processing unit the byte address storing one or two bytes of the data to be concatenated.

[0070] The write command processing unit includes a read address generation unit and a write address generation unit. The read address generation unit generates a byte address storing one or two bytes of data to be concatenated, so that these one or two bytes can be read from memory. The read address generation unit provides the read address to the read address sending unit. The read address sending unit sends the read address to the bus through the master device interface according to the bus protocol. For example, if the bus is an AXI bus, the read address sending unit sends the read address on the read address channel of the AXI bus, and the slave device on the bus acting as the receiver is, for example, a memory controller (see also...). Figure 3 ).

[0071] After retrieving the bits to be concatenated from memory and concatenating them with an entry (N bits) in the physical FTL table provided by the write data cache, the write address generation unit generates a write address to write the concatenated data into memory.

[0072] For bits to be concatenated read from memory, the memory controller provides the byte containing the bits to be concatenated, read from memory, to the read data receiving unit via a bus (e.g., via the read data channel of the AXI bus). The write data selection unit selects the bits to be concatenated from the byte containing the bits to be concatenated provided by the read data receiving unit and provides it to the write data concatenation unit. Optionally, the write address calculation unit provides the position of the data to be concatenated to the write data selection unit.

[0073] The write data concatenation unit retrieves the entry (N bits) of the physical FTL table to be updated (indexed by the logical address LBA) from the write data cache, along with optional bits to be concatenated, to form a complete N / 8 (rounded down) bytes, N / 8 (rounded down) + 1 bytes, or N / 8 (rounded down) + 2 bytes, and provides them to the write data sending unit. Correspondingly, the write address generation unit of the write command processing unit generates the address for these bytes and provides it to the write address sending unit. According to the bus protocol, the write address sending unit sends the write address to the memory controller via the bus (see also...). Figure 3 The write data sending unit sends these bytes of data to the memory controller via the bus. For example, if the bus is an AXI bus, the write address sending unit sends the write address through the write address channel, while the write data sending unit sends these bytes through the write data channel. Thus, a complete set of N / 8 (rounded down), N / 8 (rounded down) + 1, or N / 8 (rounded down) + 2 bytes containing the entry (N bits) of the physical FTL table to be updated and the bits to be concatenated is written to memory.

[0074] Therefore, from the perspective of the CPU updating the logical FTL table entry, it appears to have written an M-bit entry to the logical FTL table entry indexed by the logical address LBA. Furthermore, the CPU can also read the M-bit entry from the logical FTL table using the logical address LBA. The FTL acceleration unit according to an embodiment of this application also handles requests from the CPU to read entries from the logical FTL table.

[0075] Continue reading Figure 4 For example, a logical FTL table read request from the CPU indicates a logical address LBA. The FTL accelerator is configured with a logical FTL table entry size of M bits and a physical FTL table entry size of N bits. For an FTL table read request, the address to be accessed by the logical FTL table read request is recorded in the read address cache. The cached address is, for example, the address used to read an entry of the logical FTL table (e.g., logical address LBA).

[0076] The read address calculation unit calculates the memory address of the entry in the physical FTL table corresponding to the logical address LBA to be read, based on the logical address LBA obtained from the read address cache, the configured physical FTL table entry size N, and the address of the physical FTL table in memory. The read address calculation unit calculates the memory address of the entry in the physical FTL table corresponding to the logical address LBA in a manner similar to that of the write address calculation unit.

[0077] For example, if LBA*N mod 8 is 0, then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting at byte address LBA *N / 8. The read address calculation unit calculates the byte address of ⌈N / 8⌉ consecutive bytes starting from byte address LBA *N / 8. All bits of these bytes will be read.

[0078] If LBA*N mod 8 is not 0, then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting from the LBA*N mod 8 bits after the byte address LBA*N / 8 (rounded down). This N-bit storage space occupies N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2 bytes. The read address calculation unit calculates the byte address of N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2 consecutive bytes starting from the byte address LBA*N / 8. All or part of the bits of these bytes will be read. The read address calculation unit also determines the number of bytes in memory that store the physical FTL table entry to be read (N / 8 (rounded down), N / 8 (rounded down) + 1, or N / 8 (rounded down) + 2).

[0079] The byte address generated by the read address calculation unit is provided to the read address sending unit. The read address sending unit sends the read address to, for example, the memory controller via the bus through the FTL accelerator's master device interface. In response to the read address, the memory controller provides the corresponding data to the FTL accelerator's read data receiving unit via the bus.

[0080] The read data selection unit selects N bits corresponding to the physical FTL table entry to be read from N / 8 (rounded down), N / 8 (rounded down) + 1, or N / 8 (rounded down) + 2 bytes of data read from memory provided by the read data receiving unit, and records them in the read data buffer. Optionally, the read address calculation unit indicates to the read data selection unit which bits in each byte of data read belong to the entry in the physical FTL table indexed by the logical address LBA.

[0081] The read data selection unit or read data cache also expands the N-bit entries of the read physical FTL table to M bits. For example, it fills the N-bit data with a specified number of bits (e.g., MN bits) of specified data (e.g., all 0s, all 1s, or random data) before or after the read N-bit data to obtain M-bit logical FTL table entries. The M-bit logical FTL table entries from the read data cache are then provided to the CPU via the FTL accelerator's slave interface as a response to the logical FTL table read request.

[0082] Optionally, the FTL accelerator according to the embodiments of this application, in response to an update request for a logical FTL table entry received from a CPU, not only writes the entry to be updated into the physical FTL table to update the corresponding entry therein, but also provides a response to the CPU from the device interface with the processing result of the update result to meet, for example, the requirements of the bus protocol.

[0083] Figure 5A A flowchart illustrating the process of an FTL accelerator handling read requests for a logical FTL table according to an embodiment of this application is shown.

[0084] For example, when a master device, such as the CPU, issues a read request for an entry in the logical FTL table, the bus forwards the read request as an FTL accelerator for the slave device (see also...). Figure 4 In response to an FTL table read request (510), the read request indicates the logical address LBA to be accessed as the index of the logical FTL table, and the logical address LBA is recorded in the read address cache. The read address calculation unit calculates the address and length of the corresponding entry in the physical FTL table based on the index of the logical FTL table (e.g., the logical address LBA) indicated by the read request (515).

[0085] For example, if LBA*N mod 8 is 0, the corresponding entry in the physical FTL table is stored in N / 8 (rounded up) bytes starting from byte address LBA *N / 8 (rounded down). If N mod 8 is not 0, the last byte of the N / 8 (rounded up) bytes storing the entry also includes some bits from other entries. If LBA*N mod 8 is not 0, and (N mod 8) – (8-LBA*N mod 8) <= 0, the corresponding entry in the physical FTL table is stored in N / 8 (rounded down) + 1 bytes starting from byte address LBA *N / 8 (rounded down). If LBA*N mod 8 is not 0, and (N mod 8) – (8-LBA*N mod 8) > 0, the corresponding entry in the physical FTL table is stored in N / 8 (rounded down) + 2 bytes starting from byte address LBA *N / 8 (rounded down).

[0086] Optionally, the read address calculation unit may also adjust the address and / or length of the corresponding entry in the physical FTL table based on the memory bus address and the starting address of the physical FTL table in the memory.

[0087] Based on the address and length obtained by the read address calculation unit, the FTL accelerator accesses the memory via the bus through the slave device interface to read data from the memory (520). The read data selection unit of the FTL accelerator selects an N-bit entry (525) from the read data, indexed by the logical address LBA in the physical FTL table. The N-bit physical FTL table entry is expanded to the size of the logical FTL table entry (M bits) required for the read request (530), and the M bits of data are stored in the read data cache. The access request for the logical FTL table entry is then responded to via the slave device interface with the expanded M-bit data.

[0088] Figure 5B A flowchart illustrating the process of writing requests to a logical FTL table by an FTL accelerator according to an embodiment of this application is shown.

[0089] The host device, such as the CPU, issues a write request for an entry in the logical FTL table to update the logical FTL table entry. In response to the FTL table write request (550), the write request indicates the logical address LBA to be accessed as the index of the logical FTL table, and the logical FTL table entry (M bits) to be written. The logical address LBA is recorded in the write address cache. The M-bit logical FTL table entry is recorded in the write data cache. The write address calculation unit calculates the address and length (555) of the corresponding entry in the physical FTL table based on the logical FTL table index (e.g., the logical address LBA) indicated by the write request. N bits of the M-bit logical FTL table entry correspond to the physical FTL table entry to be updated.

[0090] For example, if LBA*N mod 8 is 0, the corresponding entry in the physical FTL table is stored in N / 8 (rounded up) bytes starting from byte address LBA *N / 8 (rounded down). If N mod 8 is not 0, the last byte of the N / 8 (rounded up) bytes storing the entry also includes some bits from other entries. If LBA*N mod 8 is not 0, and (N mod 8) – (8-LBA*N mod 8) <= 0, the corresponding entry in the physical FTL table is stored in N / 8 (rounded down) + 1 bytes starting from byte address LBA *N / 8 (rounded down). If LBA*N mod 8 is not 0, and (N mod 8) – (8-LBA*N mod 8) > 0, the corresponding entry in the physical FTL table is stored in N / 8 (rounded down) + 2 bytes starting from byte address LBA *N / 8 (rounded down).

[0091] If the entries in the physical FTL table to be updated are not byte-bounded (i.e., LBA*N mod 8 is not 0, and / or (LBA+1)*N mod 8 is not 0), 1 or 2 bytes of data must be read from memory, and a portion of the read data bits are concatenated with the N bits of data to be written. Steps 560 to 570 are then executed to complete the data concatenation. If the entries in the physical FTL table to be updated are byte-bounded (i.e., LBA*N mod 8 is 0, and (LBA+1)*N mod 8 is 0), then steps 560 to 570 do not need to be executed.

[0092] The write address calculation unit also indicates that 0, 1, or 2 bits of the calculated write address need to be read. The read address generation unit of the write command processing unit reads data from the memory through the master device interface (560) according to the write address to be read. The write data selection unit selects valid data (bits to be concatenated) from the read data (565). For example, if LBA*N mod 8 is 0 and N mod 8 is not 0, then the byte address of the read 1 byte of data is (LBA+1)*N / 8, and the last 8-(LBA+1)*N mod 8 bits are the data to be concatenated; if LBA*N mod 8 is not 0, then the first LBA*N mod 8 bits of the 1 byte of data read from the byte address LBA*N / 8 are the data to be concatenated, and / or the last 8-(LBA+1)*N mod 8 bits of the 1 byte of data read from the byte address (LBA+1)*N / 8 are the data to be concatenated.

[0093] If steps 560 to 570 are executed, the write data concatenation unit concatenates the bits to be concatenated provided by the write data selection unit with the N-bit data of the corresponding entry in the physical FTL table to be updated in the write data cache (570), resulting in N / 8 (rounded down) + 1 or N / 8 (rounded down) + 2 bytes of data. If steps 560 to 570 are not required, the write data concatenation unit directly obtains the N-bit data (size N / 8 (rounded down) bytes) of the entry to be written to the physical FTL table from the write data cache. The N / 8 (rounded down) byte, N / 8 (rounded down) + 1 byte, or N / 8 (rounded down) + 2 byte of data provided by the write data concatenation unit is then written to the memory via the master device interface (580).

[0094] Figure 6A and Figure 6B This diagram illustrates the process of reading the corresponding entry of the logical FTL from the physical FTL table.

[0095] Figures 6A to 6DIn the example, the logical FTL table entry size is 64 bits, while the physical FTL table entry size is 33 bits.

[0096] See Figure 6A To read the entries in the logical FTL table indexed by logical address 0. Figure 6A The first 16 bytes (denoted as bytes 0 to 15) of the space storing the physical FTL table are shown. The entry of the physical FTL table indexed by logical address 0 is denoted as PBA(0), which occupies 33 bits starting from byte 0, occupying the complete bytes 0 to 3 and the first bit of byte 4. According to an embodiment of this application, in order to read the entry PBA(0), it is necessary to read the complete bytes 0 to 4, a total of 5 bytes, from memory, and select all the data of bytes 0 to 3 and the first bit of byte 4 to obtain PBA(0). Then, the 33-bit PBA(0) is filled with, for example, 31 bits of 0 to obtain the logical FTL table entry to be read (denoted as LBA(0)).

[0097] See Figure 6B To read the entry of the logical FTL table indexed by logical address 1, the entry of the physical FTL table indexed by logical address 1 is denoted as PBA(1). It is located in 33 bits starting from the 2nd bit of byte 4, occupying bits 2 to 8 of byte 4, the complete bytes 5 to 7, and the first 2 bits of byte 7. According to an embodiment of this application, in order to read the entry PBA(1), it is necessary to read the complete bytes 4 to 8, a total of 5 bytes, from memory, and select bits 2 to 8 of byte 4, all data of bytes 5 to 7, and the first 2 bits of byte 8 to obtain PBA(1). Then, the 33-bit PBA(1) is filled with, for example, 31 bits of 0 to obtain the logical FTL table entry to be read (denoted as LBA(1)).

[0098] Figure 6C and Figure 6D This diagram illustrates the writing of the corresponding entry from the logical FTL table to the physical FTL table.

[0099] See Figure 6C To update the entry in the logical FTL table indexed by logical address 0 (denoted as LBA(0)), select the specified N bits from entry LBA(0), which is PBA(0). The entry in the physical FTL table indexed by logical address 0 is denoted as PBA(0), which occupies the first bit of the complete bytes 0 to 3 and 4 in the 33 bits starting from byte 0 in the physical FTL table.

[0100] According to an embodiment of this application, in order to write entry PBA(0), byte 4 needs to be read from memory. After PBA(0) is updated, the first bit of byte 4 is the last bit of the updated PBA(0), while the second to eighth bits of byte 4 belong to PBA(1) and should not be updated. Therefore, the N bits of LBA(0) are concatenated with the second to eighth bits of the read byte 4 to form the content of bytes 0 to 4. This content is then written into bytes 0 to 4 of the physical FTL table to complete the update of LBA(0) and PBA(0).

[0101] See Figure 6D To update the entry in the logical FTL table indexed by logical address 1 (denoted as LBA(1)), select the specified N bits from entry LBA(1), which is PBA(1). The entry in the physical FTL table indexed by logical address 1 is denoted as PBA(1), which occupies 33 bits in the physical FTL table starting from the 2nd bit of byte 4, occupying bits 2 to 8 of byte 4, the complete bytes 5 to 7, and the first 2 bits of byte 7.

[0102] According to an embodiment of this application, in order to write entry PBA(1), bytes 4 and 8 need to be read from memory. After updating PBA(1), the first bit of byte 4 is the last bit of PBA(0) (and should not be updated), while the second to eighth bits of byte 4 are the first 7 bits of PBA(1). After updating PBA(1), the first 2 bits of byte 8 are the last 2 bits of PBA(1). The third to eighth bits of byte 8 belong to PBA(2) and should not be updated.

[0103] Therefore, the N bits of LBA(1) are concatenated with the first 1 bit of the read byte 4 and the last 6 bits of the read byte 8 to form the content of bytes 4 to 8. This content is then written into bytes 4 to 8 of the physical FTL table to complete the update of LBA(1) and PBA(1).

[0104] Figure 7 A block diagram of control components including an FTL accelerator is shown according to yet another embodiment of this application.

[0105] The control components include, for example, a CPU, a Media Interface Controller (NFI), an FTL accelerator, and a memory controller. The CPU, NFI, FTL accelerator, and / or memory controller are coupled, for example, via a bus. The CPU is also directly coupled to the FTL accelerator. The CPU determines whether to send an access request to the FTL accelerator or the bus based on the address space to be accessed. For example, the FTL accelerator is allocated a 0-8GB address space, while the device coupled to the bus is allocated an 8GB-32GB address space, the NFI is allocated, for example, a 1MB address space starting from 8GB, and the memory controller is allocated a 16GB-32GB address space. From the CPU's perspective, the logical FTL table is contained in the 0-8GB address space occupied by the FTL accelerator. The physical FTL table is contained in the 16GB-32GB address space occupied by the memory controller. Access requests from the CPU to the 0-8GB address space are sent directly to the FTL accelerator for processing, while requests to access the 16GB-32GB address space are forwarded by the bus to the memory controller for processing.

[0106] According to embodiments of this application, the FTL accelerator includes a master device interface. The FTL accelerator is coupled to a bus via the master device interface. This allows the CPU of the control unit to directly access the FTL accelerator. The FTL accelerator, in turn, can access one or more devices of the control unit (e.g., a memory controller) as a master device via the master device interface.

[0107] Therefore, the CPU sends an access request to the FTL accelerator for an entry in the logical FTL table (indexed as LBA). The accessed address is LBA*8, and the length is 8 bytes. The FTL accelerator determines the storage location of the corresponding physical FTL table entry in the physical FTL table based on the address (LBA*8) indicated in the received access request, and then sends one or more memory access requests to the memory controller via the bus through its master device interface to access the physical FTL table entry in DRAM.

[0108] Although the examples referred to in the present invention are described, they are for illustrative purposes only and not for limiting the scope of this application. Changes, additions and / or deletions to the implementation may be made without departing from the scope of this application.

[0109] Those skilled in the art who benefit from the teachings presented in the above description and associated drawings will recognize many modifications and other embodiments of the present application described herein. Therefore, it should be understood that the present application is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in its general and descriptive sense and not for limiting purposes.

Claims

1. An FTL accelerator, comprising a read address calculation unit, a read data selection unit, a read address transmission unit, and a read data receiving unit; The read address calculation unit calculates the address of the physical FTL table entry corresponding to the logical FTL table entry to be accessed based on the index (L) of the logical FTL table entry to be read. The read address calculation unit also indicates to the read data selection unit the portion of the data read from the memory that belongs to the entry of the physical FTL table to be accessed; The read data selection unit obtains the portion of the physical FTL table to be accessed from the data read from the memory as instructed by the read address calculation unit, and expands the physical FTL table to obtain the logical FTL table to be accessed. The logical FTL table has an entry size of M bits, and the physical FTL table has an entry size of N bits, where M and N are positive integers and M > N. The entries in the logical FTL table correspond one-to-one with the entries in the physical FTL table. If N mod 8 is 0, then the address of the physical FTL table entry corresponding to the logical FTL table entry to be accessed, calculated by the read address calculation unit based on the index (L), is a byte address. Starting from the Nth mod 8th bit An address of 1 byte; If L*N mod 8 is not 0, and (N mod 8) – (8-L*N mod 8) <= 0, then the address of the physical FTL table entry corresponding to the logical FTL table entry to be accessed, calculated by the read address calculation unit based on the index (L), is a byte address. Starting from the N mod 8th bit The address is a byte address; if L*Nmod 8 is not 0, and (N mod 8) – (8-L*N mod 8)>0, then the address of the physical FTL table entry corresponding to the logical FTL table entry to be accessed, calculated by the read address calculation unit according to the index (L), is a byte address. Starting from the N mod 8th bit An address of 1 byte.

2. The FTL accelerator according to claim 1, further comprising: Read address cache unit and read data cache unit; The read address cache unit stores the index (L) of the entry in the logical FTL table to be accessed; The read data cache unit stores entries for the logical FTL table to be accessed; The read address calculation unit is coupled to the read address cache unit, and the index (L) is obtained from the read address cache unit; The read data selection unit stores the portion of the data read from memory that belongs to the entry of the physical FTL table to be accessed in the read data cache; The entries of the physical FTL table to be accessed, stored in the read data cache, are expanded to the size of the entries of the logical FTL table to be accessed, in order to obtain the entries of the logical FTL table to be accessed.

3. The FTL accelerator according to claim 1 or 2, wherein The address calculation unit calculates the address of the physical FTL table entry corresponding to the logical FTL table entry to be accessed based on the index (L). This address is the byte address in the storage space of the physical FTL table. The address of one or more bytes containing N bits of data, starting from the N mod 8th bit.

4. The FTL accelerator according to claim 1 or 2, wherein If N mod 8 is 0, then the portion of the data read from memory by the read address calculation unit that belongs to the entry of the physical FTL table to be accessed includes the byte address. Starting from the Nth mod 8th bit Complete data of an address in bytes; If L*N mod 8 is not 0, the part of the data read from memory by the read address calculation unit that belongs to the entry of the physical FTL table to be accessed includes the L*N mod 8th bit to the last bit of the byte with byte address L*N / 8; If (L+1)*N mod 8 is not 0, then the part of the data read from memory by the read address calculation unit that belongs to the entry of the physical FTL table to be accessed includes the first (L+1)*N mod 8 bits of the byte with byte address (L+1)*N / 8.

5. The FTL accelerator according to claim 1 or 2, further comprising: Write address calculation unit, write command processing unit and write data concatenation unit; The write address calculation unit calculates the address of the physical FTL table entry corresponding to the logical FTL table entry to be updated based on the index (L) of the logical FTL table entry to be updated. The write data splicing unit retrieves the corresponding N-bit physical FTL table entry from the logical FTL table entry to be updated; The write command processing unit is coupled with the write address calculation unit, and writes the N-bit physical FTL table entry obtained by the write data splicing unit into the address of the physical FTL table entry corresponding to the logical FTL table entry to be updated, provided by the write address calculation unit.

6. The FTL accelerator according to claim 5, wherein, The write address calculation unit also calculates one or two addresses to be read from the physical FTL table based on the index (L) of the entry in the logical FTL table to be updated, and provides the one or two addresses to be read from the physical FTL table to the write command processing unit. The write command processing unit reads data from memory based on one or two addresses to be read from the physical FTL table; The write address calculation unit also indicates to the write data selection unit the portion of the data read from memory that does not belong to the entry in the physical FTL table to be updated; The write data selection unit retrieves the portion of the data read from the memory that does not belong to the physical FTL table to be updated according to the instruction of the write address calculation unit, and provides the portion of the data read from the memory that does not belong to the physical FTL table to be updated to the write data splicing unit. The write data splicing unit splices together the corresponding N-bit physical FTL table entry obtained from the logical FTL table entry to be updated with the part of the physical FTL table entry that does not belong to the physical FTL table to be updated, obtained from the data read from the memory provided by the write data selection unit. The write command processing unit writes the N-bit physical FTL table entries provided by the write data splicing unit and the portions of the data read from the memory that do not belong to the physical FTL table to be updated into the address of the physical FTL table entry corresponding to the logical FTL table entry to be updated, provided by the write address calculation unit.

7. The FTL accelerator according to claim 6 further includes a write address sending unit; The write command processing unit includes a read address generation unit and a write address generation unit; The read address generation unit uses one or two addresses to be read from the physical FTL table to read data from the memory through the read address sending unit; The read data receiving unit receives data read from the memory; The write address generation unit sends the address of the physical FTL table entry corresponding to the logical FTL table entry to be updated, provided by the write address calculation unit, through the write address sending unit.

8. The FTL accelerator according to claim 1 or 2, further comprising: The master device interface is used to couple the bus; The read address sending unit sends the read address to the bus through the master device interface; The data receiving unit acquires the read data from the bus through the master device interface; The write address sending unit sends the write address to the bus through the master device interface; The write data sending unit sends the data to be written to the bus through the master device interface.

9. A control component, comprising: First master device, FTL accelerator, memory controller and bus; The FTL accelerator is coupled to the bus via a host device interface; The memory controller is connected to the memory via a device interface and the bus; the memory controller is also coupled to the memory. The aforementioned FTL accelerator is the FTL accelerator according to any one of claims 1-8.

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