Digital dynamic bias circuit

Abstract

Circuits and methods for reducing the cost and / or power consumption of user terminals and / or gateways in telecommunications systems (550) that may include telecommunications satellites. Embodiments generate a dynamic input bias signal based on the information signal envelope (which may be pre-distorted) applied to the signal input of a power amplifier (PA), thereby reducing average power consumption. Other embodiments include dynamic linearization (518) of the information signal, and / or variations in the supply voltage to the power amplifier (PA) based on the information signal envelope. Another aspect is a multi-stage “chain” feedback regulated power supply circuit for providing two or more output voltages, which can be used as alternative supply voltages to the power amplifier (PA).

Description

[0001] Relevant application data

[0002] This patent application claims priority to the commonly assigned U.S. Provisional Patent Application No. 62 / 205,286, filed August 14, 2015, entitled “Long-Loop Dynamic Bias for Power Amplifiers,” pursuant to 35 USC §119(e), which is incorporated herein by reference as fully listed. Technical Field

[0003] This invention relates to electronic circuits, and more particularly to bias and linearization circuits for power amplifiers. Background Technology

[0004] Figure 1 This is a block diagram of a prior art telecommunications system 100. A user terminal 102 is coupled to a user antenna 104; the user terminal 102 may optionally be separated between indoor components (e.g., at least one transceiver and local connection circuitry) and outdoor components (e.g., at least one low-noise amplifier). Similarly, a gateway 106, including at least one transceiver, is coupled to a gateway antenna 108 and may be connected to one or more information nodes 110. The gateway 106 typically includes one or more processing nodes that provide various signal processing functions to establish and maintain communication channels with one or more user terminals 102. Signals can be transmitted across a communication network 110 between the user terminals 102 and the gateway 106 via their respective antennas 104, 108; the communication network 110 may include a telecommunications satellite 112 in some applications.

[0005] Examples of applications for the telecommunications system 100 shown include satellite television, wireless network systems (such as WiFi), and cellular or mobile phone systems. Therefore, the telecommunications system 100 will typically include multiple user terminals 102, and information nodes 110 may include the Internet, and / or private connections to multimedia content providers (such as television programs, movies, computer games, etc.) and / or other users (such as other users in a wireless telephone system).

[0006] For many applications, particularly satellite television and wireless telephone systems, it is useful to reduce the cost and / or power consumption of user terminal 102 (e.g., satellite television terminal or mobile phone) and / or gateway 106. One aspect of the invention is to perform one or both of the foregoing. Summary of the Invention

[0007] One aspect of the present invention is to reduce the cost and / or power consumption of user terminals and / or gateways in telecommunications systems while meeting desired performance specifications. Embodiments generate a dynamic input bias signal based on the information signal envelope (which may be pre-distorted) applied to the signal input of a power amplifier, thereby reducing average power consumption. Other embodiments include dynamic linearization of the information signal and / or variations in the supply voltage to the power amplifier based on the envelope of the information signal. Another aspect is a multi-stage “chain” feedback regulated power supply circuit for providing two or more output voltages, which can be used as alternative supply voltages to the power amplifier.

[0008] More specifically, in one embodiment, the source information in digital form is coupled to a digital modulator that generates intermediate I and Q data streams. The digital modulator also outputs a combined modulated information signal, which is coupled to a digital-to-analog (DAC) circuit that outputs an analog signal. The analog signal from the DAC output is coupled to an adder, the output of which is coupled to the signal input of a power amplifier (PA). The output of the PA is the signal applied to and transmitted by an antenna. The intermediate I and Q data streams from the digital modulator are also coupled to an envelope calculation block that generates the envelope E of the source information signal. The envelope E of the modulated information signal exhibits peaks and troughs as the modulated information signal varies over time, but most of the time the envelope remains near an average level significantly below the peak level.

[0009] The output of the envelope calculation block can be used as an undistorted dynamic input bias signal, which can be converted into an analog signal by a DAC and combined with an analog signal derived from the modulation information signal in an adder. The undistorted dynamic input bias signal and the modulation information signal can be applied to the input of the PA, and the current through the PA is changed (modulated) according to the envelope of the modulation information signal.

[0010] For many power amplifier designs, the amplifier gain changes as the input signal level changes, which is an undesirable effect and often leads to distortion. Therefore, in some embodiments of the invention, it is useful to modify the dynamic input bias signal by passing the envelope signal through a predistortion block before applying a combination of the dynamic input bias signal and the information signal to the signal input of the PA. This predistortion is performed in a way that dynamically cancels out level-dependent gain changes within the PA, and thus reduces or even eliminates the gain change of the PA while optimizing the PA's performance and power consumption. More specifically, as the undistorted dynamic input bias signal changes, the predistorted dynamic input bias signal to the PA changes in a complementary manner to eliminate the gain change of the amplifier. In some embodiments, the envelope E is predistorted by multiplying the data representing the envelope E with the inverse distribution of the PA's gain.

[0011] In some applications, the combined signal applied to the signal input of a power amplifier may exhibit some residual distortion. This residual distortion, if present, can be reduced by additional correction (pre-distortion) in the information signal path, separate from the envelope signal path. Therefore, an optional linearization block can be included in the information signal path. Linearization is essentially a form of pre-distortion that modifies the information signal to counteract the nonlinear characteristics typical of power amplifiers. Embodiments of the present invention including an optional linearization block can utilize existing receivers within the user terminal (typically used for full-duplex data communication) to offload the process of calculating linearization calibration data from the user terminal to one or more processing nodes in a gateway. Although there is a “long” loop through the interconnected communication network, this calibration / linearization process is a closed-loop system.

[0012] Another aspect of the invention includes a pre-distorted dynamic input bias (which biases the power amplifier's supply current based on the envelope E) and a bias to the power amplifier's supply voltage based on the occurrence of peaks in the envelope E. Biasing the supply current and supply voltage can significantly reduce power consumption in the PA. In an embodiment of the invention with dual bias, the supply current bias is fast, tracking the full-information signal envelope rate, while the supply voltage bias is slower, tracking only peaks of the envelope exceeding a certain threshold or meeting certain specific criteria at a lower speed. This behavior can be achieved through digital processing, including calculating the envelope E and determining which peaks to track and which peaks to track partially or not at all, as described in further detail below. Typically, only peaks above a certain threshold need to be added to the supply voltage of the PA at a rate that the supply voltage source can satisfy.

[0013] The present invention, with its dual-biased embodiments, requires at least two regulated voltage levels for the power amplifier. A "chained" feedback regulated power supply circuit is disclosed, which eliminates the need for separate regulation circuitry for each regulated voltage pair. In one embodiment, the voltage supply maintains a substantially constant voltage V1 at a first node for a first load and a substantially constant voltage V2 at a second node for a second load, both voltages being regulated by a single controller.

[0014] Embodiments of the present invention can be used with radio frequency (RF), optical and / or wired (e.g., cable, digital subscriber line, etc.) telecommunications systems.

[0015] Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will be apparent from the specification, drawings, and claims. Attached Figure Description

[0016] Figure 1 It is a block diagram of an existing telecommunications system.

[0017] Figure 2 This is a block diagram of a simplified RF transmitter used to transmit RF signals derived from a digital source.

[0018] Figure 3 It is a graph of an exemplary prior art information signal having a voltage (or current) that varies over time in a transmitter with a power amplifier having a fixed input bias signal.

[0019] Figure 4 It is a graph of the voltage (or current) information signal that varies with time in the transmitter of a power amplifier with a dynamic input bias signal.

[0020] Figure 5 This is a block diagram of an embodiment of an RF transmitter that tracks the envelope of an information signal and generates a dynamic input bias signal to a PA.

[0021] Figure 6 It is a graph of the voltage (or current) information signal that varies with time in the transmitter of a power amplifier with a dynamic input bias signal with predistortion.

[0022] Figure 7 It is a graph of the information signal of voltage (or current) that varies with time in the transmitter of a power amplifier with a dynamic input bias signal, showing the threshold level where the predistortion is less than the threshold level.

[0023] Figure 8 This is a block diagram of one embodiment of a transmitter, which includes digital biasing of the power amplifier's supply current and supply voltage.

[0024] Figure 9 This is a block diagram of a simplified embodiment of a transmitter, which includes digital biasing of the power amplifier's supply current and supply voltage.

[0025] Figure 10A This is a schematic diagram of a "chain-type" feedback regulated power supply circuit.

[0026] Figure 10B This is a schematic diagram of an alternative "chain-type" feedback regulated power supply circuit.

[0027] The same reference numerals and symbols in the various figures indicate the same elements. Detailed Implementation

[0028] One aspect of the invention is to reduce the cost and / or power consumption of user terminals and / or gateways in telecommunications systems while meeting desired performance specifications. Embodiments generate a dynamic input bias signal based on the information signal envelope (which may be pre-distorted) applied to the signal input of a power amplifier, thereby reducing average power consumption. Other embodiments include dynamic linearization of the information signal and / or variations in the supply voltage to the power amplifier based on the information signal envelope. Another aspect is a multi-stage “chain” feedback regulated power supply circuit for providing two or more output voltages, which can be used as alternative supply voltages to the power amplifier. Yet another aspect of the invention is to move processing (e.g., computing software and / or hardware) from the user terminal to one or more “remote nodes,” such as processing nodes of a gateway.

[0029] Embodiments of the present invention can be used in conjunction with various telecommunications systems, including radio frequency (RF), wired (e.g., cable, digital subscriber line, etc.), and optical systems. For simplicity, the following examples will be described in the context of RF telecommunications systems, but it should be understood that the present invention is not limited to such systems.

[0030] Exemplary RF Telecommunication System

[0031] In RF telecommunications systems with RF transmitters, the power amplifier is an important component of the RF transmitter. Figure 2 This is a block diagram of a simplified RF transmitter 200 for transmitting RF signals derived from digital source information. The digital source information is coupled to a digital modulator 202 that provides a modulation information signal. The modulation information signal is coupled to a digital-to-analog (DAC) circuit 204 that outputs an analog signal. The analog signal is coupled directly or after up-conversion to another frequency to the signal input of a power amplifier (PA) 206.

[0032] Internally, PA 206 will typically include one or more amplification stages, each comprising one or more power field-effect transistors (FETs), each having a gate, source, and drain terminal (note that some designs may include shared drain and source, and / or a shared gate spanning two or more FETs, or multiple gates per FET). FETs can be fabricated using any of a variety of technologies, including gallium arsenide (GaAs), gallium nitride (GaN), standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and MESFET technologies. However, the invention is not limited to FET or GaAs or GaN fabrication technologies and may include, for example, junction FETs, other insulated-gate FET (IGFET) types (e.g., MOSFETs), or bipolar junction transistors (BJTs) having base, emitter, and collector terminals.

[0033] PA 206 is configured to receive a signal input applied to the base or gate of one or more power transistors, which amplify the signal input for transmission. The signal input can be directly connected to the power transistor input or indirectly coupled to the power transistor input via coupling circuitry (e.g., series capacitors) and / or buffering or level-shifting circuitry (not shown for simplicity). PA 206 also includes power supply terminals, typically a DC voltage (e.g., VDD for a FET, VCC for a BJT) and DC ground (typically also the RF circuit ground). PA 206 may include additional circuitry, such as drivers and / or preamplifiers, to assist in performing amplification functions for a specific application.

[0034] A fixed input bias signal can be applied to the input signal of PA 206 to bias the input (e.g., gate or base) of at least one power transistor to establish the desired operating conditions for the PA. However, power amplifiers with a fixed input bias signal typically waste power because the fixed signal input bias causes PA 206 to continuously draw power through its power supply terminals. For example, Figure 3 This is a graph 300 of an exemplary prior art information signal 302 with a voltage (or current) varying over time in a transmitter with a power amplifier having a fixed input bias signal (for clarity, only the positive half of the waveform of the information signal 302 is shown). Please note that... Figure 3 The purpose is to display the power of the modulated RF signal over time (expressed as voltage or current in the PA), rather than the modulation technique itself; a variety of techniques (such as amplitude modulation, frequency modulation, phase modulation, or a combination of these methods) and other modulation techniques that are particularly useful for transmitting digital data (such as quadrature amplitude modulation (QAM), phase shift keying (PSK), orthogonal frequency division multiplexing (OFDM), etc.) can be used to modulate the information signal 302.

[0035] Figure 3The dashed line 304 in the diagram represents the level of the fixed input bias signal applied to the PA. The power consumed by the PA is proportional to the area below the dashed bias line 304. However, the power level of the information signal 302 is defined by the envelope curve 306. In this example, the power level of the information signal 302 remains relatively low for most of the time, and the peak power at point P is reached only once. Since the PA bias in this example provides the highest efficiency only at peak power, all signals with power levels below this peak waste excessive power. This wasted power has several consequences, including: shorter battery life or larger battery capacity requirements (with a corresponding adverse impact on the size of the user terminal 102); heat generation, typically requiring thermal management (e.g., larger fans, heat sinks, etc.); more robust electronics handling the highest possible power output, rather than the average power output over short distances at higher power; and a shortened lifespan for the electronics.

[0036] Dynamic bias

[0037] Embodiments of the present invention provide an improved method for controlling the bias of current or voltage applied to a PA. Figure 4 This is a graph 400 showing an information signal 302 with a voltage (or current) varying over time in a transmitter with a power amplifier having a dynamic input bias signal. As described below, some embodiments of the invention track the envelope 306 of the information signal 302 and generate a dynamic input bias signal 402 to the PA that provides sufficient bias to the PA's signal input to amplify the information signal 302 without wasting a significant amount of power. The power consumed by the PA is proportional to the area under the dynamic input bias signal 402 (dashed line). Other embodiments described below generate a dynamic input bias signal 402 to the PA that provides sufficient bias to the PA for most information signal 302 power levels, but not always closely tracks the envelope 306 for higher power signal offsets, resulting in a lower average dynamic input bias signal to the PA.

[0038] Envelope detection and generation of dynamic input bias

[0039] Figure 5 This is a block diagram of one embodiment of an RF transmitter 500 that tracks the envelope of an information signal and generates a dynamic input bias signal to a PA. Such an RF transmitter 500 may be a component of, for example, a user terminal 102. This particular exemplary embodiment is useful in RF transmission systems utilizing some form of "IQ modulation," where "I" is the "in-phase" component of the signal waveform and "Q" is the "quadrature" component of the signal waveform, out of phase by 90° relative to the I component. Examples of IQ modulation-based systems include QAM and PSK transmission systems.

[0040] exist Figure 5In this example, the source information in digital form is coupled to a digital modulator 502 that generates intermediate I and Q data streams in a known manner. The digital modulator 502 also outputs a combined modulated information signal generated from the intermediate I and Q data streams. This modulated information signal is coupled to a digital-to-analog (DAC) circuit 504, which outputs an analog signal. The analog signal output from the DAC 504 is coupled to an adder 506, whose output is then coupled to the signal input of a power amplifier (PA) 508. The output of PA 508 is applied to an antenna (…). Figure 1 The signal is transmitted by the user antenna 104. In some embodiments, the modulation information signal may be up-converted to another frequency before or after the DAC 504 in a known manner.

[0041] As shown in the figure, the intermediate I and Q data streams from the digital modulator 502 are also coupled to the envelope calculation block 510, which generates the envelope E of the source information signal. For a system with intermediate I and Q data streams, a convenient way to calculate the envelope E is to apply the following formula:

[0042]

[0043] Alternatively, particularly for RF transmitters that do not use IQ modulation (e.g., AM, FM, or PM-based transmitters), the envelope E of the source information signal can be determined in many known ways. The envelope E of most modulated information signals exhibits peaks and troughs as the modulated information signal varies over time, but for most of the time the envelope remains near an average level significantly below the peak level.

[0044] The output of envelope calculation block 510 can be used as an undistorted dynamic input bias signal, which can be converted into an analog signal by DAC 512 and combined with an analog signal derived from the modulation information signal in adder 506. The undistorted dynamic input bias signal and the modulation information signal can be applied to the input of PA 508, and the current through PA 508 (e.g., the output drain current I of the FET) is altered (modulated) according to the envelope of the modulation information signal. DD Or the collector current I of the BJT cc More specifically, if the PA signal input is eventually coupled to the gate of the FET, the gate voltage of the FET is dynamically biased, and if the PA signal input is eventually coupled to the base of the BJT, the base current of the BJT is dynamically biased.

[0045] In some embodiments, the analog input bias signal and the analog information signal can be directly combined in adder 506. In other embodiments, the carrier frequency of the information signal can be much higher than the frequency of the envelope (e.g., a 30 GHz carrier and a 3 GHz envelope), and accordingly, the modulated carrier signal and the envelope input bias signal can be combined via appropriate circuitry such as a duplex network.

[0046] In some embodiments, the analog RF information signal is directly synthesized with the DAC (without using an upconverter). In such embodiments, one of the two DACs 504, 512 can be eliminated by digitally combining the modulated information signal and the predistorted envelope signal, and their functions can be combined into a single DAC. The single DAC can then convert the combined digital data stream into analog form, and the composite analog signal can then be applied to the signal input of PA 508 to achieve the same function as the two DACs 504, 512. Therefore, the functions of DACs 504, 512 and adder 506 can generally be considered as a "combination and conversion" circuit that can be implemented in many ways that should be clear to those skilled in the art.

[0047] In the example above, the dynamic input bias signal is essentially the envelope E calculated as in EQ.1. However, the dynamic input bias signal (which can also be referred to as the "envelope-derived" signal) can be proportional to the envelope, the square of the envelope, or some other function of the envelope, including incorporating additional offsets, multiplication coefficients, etc., depending on the type of power amplifier and the nonlinearity being linearized.

[0048] Because the envelope tracks the information signal, the stronger the information signal, the higher the envelope, and therefore the higher the dynamic input bias signal. Conversely, the lower the information signal, the lower the envelope, and therefore the lower the dynamic input bias signal. For example, phase-modulated satellite signals (e.g., 16PSK) can have a peak-to-average power ratio of 6 dB (or 4 times). Theoretically, the power supply current (IA) of the PA can be dynamically biased by applying the dynamic input bias signal. DD Or I CC ), and bias the power supply voltage (V) according to the envelope E. DD or V CC (See the description of power supply voltage bias below), power consumption in the PA 508 can be reduced by the same factor. Modulating only the power supply current or voltage can achieve half the improvement; using QAM or OFDM modulation with higher peak power can achieve a greater improvement.

[0049] Therefore, by applying a dynamic input bias signal, the average current through PA 508 is reduced compared to a fixed input bias that would result in a continuously high current through PA 508, thereby reducing overall power consumption. Lower power consumption leads to less heat, longer battery life or smaller battery capacity (with a corresponding beneficial impact on the size of the user terminal), and a longer lifespan for electronic components. In some embodiments, to save even more power, the same dynamic input bias signal (or a scaled version of the signal) can be applied to other amplifier stages or amplifier elements, such as a preamplifier or PA driver before the final PA stage.

[0050] Predistortion of envelope

[0051] For many power amplifier designs, the amplifier gain changes as the input signal level changes, which can be an undesirable effect in some applications and often leads to distortion. For example, the gain of a particular PA may (1) be bloated at low input signal levels (i.e., increase with increasing signal level), (2) peak at medium input signal levels, and (3) be compressed at high input signal levels (i.e., decrease with increasing input signal level).

[0052] Therefore, in some embodiments of the invention, it is useful to modify the dynamic input bias signal by applying a transform function to the envelope signal through the predistortion block 514 before applying the combination of the dynamic input bias signal and the information signal to the signal input of PA 508. This predistortion is performed in a way that dynamically cancels out input signal level-dependent gain variations within PA 508, and thus reduces or even eliminates gain changes in PA 508, while optimizing the performance and power consumption of PA 508.

[0053] More specifically, as the undistorted dynamic input bias signal changes, the predistorted dynamic input bias signal to the PA 508 changes in a complementary manner to eliminate the gain change of the amplifier. Therefore, for example, if the gain of the PA 508 decreases by 1 dB when the input signal bias decreases, the dynamic input bias signal increases by the same amount of 1 dB to maintain a constant gain in the PA 508, thus not reducing linearity.

[0054] Therefore, in some embodiments, the envelope E is predistorted by multiplying the data representing the envelope E with a transformation function that includes the inverse distribution of the gain of PA 508. The gain distribution can be represented as a polynomial with coefficients, and the envelope E can be transformed into a predistorted envelope E′ by applying the computed inverse polynomial coefficients to the predistortion block 514. For example, the power input to power output data of the gain of PA 508 can be determined, and the resulting data can be mapped to a polynomial of the following form (note that higher-order polynomials can be used if needed or desired):

[0055] y = ax + bx 2 +cx 3 EQ.2

[0056] Once the coefficients of the polynomial in EQ.2 are fitted to the curve of power input versus power output data, a corrected transformation function polynomial with (mostly) negative coefficients can be constructed, as shown below:

[0057] y = ax - bx 2 -cx 3 EQ.3

[0058] The predistortion block 514 applies a correction polynomial (e.g., by multiplication) to transform the envelope E into a predistorted envelope E′. The predistorted envelope E′ increases the gain of PA 508 when the level of envelope E is low (i.e., the gain is extended) and decreases the gain of PA 508 when the level of envelope E is high (i.e., the gain is compressed). For example, Figure 6 This is a graph 600 showing the voltage (or current) information signal that varies with time in the transmitter of a power amplifier with a pre-distorted dynamic input bias signal 602. As shown in this example, the pre-distorted dynamic input bias signal 602 has a higher relative bias level B1 for a lower level envelope 306 and a lower relative bias level B2 for a higher level envelope 306.

[0059] Calibration of predistortion block

[0060] The power amplifier gain distribution and corresponding polynomial coefficients can be obtained through calibration, and the calibration data can be transmitted or otherwise provided to the predistortion block 514, such as... Figure 5 As shown. This calibration data can be determined in several ways, including: determining the coefficients by analyzing the circuit design or by circuit modeling, optionally including statistical characterization, and locally programming / storing the coefficients (e.g., in predistortion block 514) (open-loop method); performing transmitter characteristics during production, and locally programming / storing the system (another open-loop method); measuring transmitter characteristics by locally detecting the output of PA 508, and feeding the corresponding calibration data back to predistortion block 514 (local closed-loop method); or measuring transmitter characteristics by remotely monitoring the output of PA 508 (e.g., at gateway 106), and transmitting the corresponding calibration data back to predistortion block 514 (remote "long" closed loop).

[0061] An embodiment of the present invention using a "long" closed-loop calibration method can utilize an existing receiver (typically used for full-duplex data communication) within user terminal 102 to offload the process of calculating pre-distortion calibration data from user terminal 102 to one or more processing nodes in gateway 106. Therefore, a test signal can be transmitted via PA 508, some performance metrics can be measured in gateway 106, the corresponding calibration data can be calculated in gateway 106, and the calibration data can then be sent back to the receiver within user terminal 102 coupled to pre-distortion block 514 (see also the discussion below regarding residual distortion correction).

[0062] The performance metrics and signals used for calibration may include one or more of the following: a single tone output as a test signal, measuring gain and phase, including gain and phase compression and harmonics; a single-tone level sweep test signal; a two-tone test signal, measuring intermodulation and out-of-channel power (e.g., adjacent channel power or ACP; in some embodiments, the modulation rate may be reduced so that adjacent channel frequencies fall within the test channel rather than outside the channel to prevent intrusion and interference with actual adjacent channel service); a multi-tone test signal, testing intermodulation and ACP; and a modulated signal output for normal communication (e.g., 8PSK), measuring power level, signal-to-noise ratio (SNR), error vector magnitude (EVM), bit error rate (BER), frame error rate (FER), and / or one or more of ACP.

[0063] As an example of measuring a performance metric that might be useful when generating calibration data for the predistortion block 514, in some embodiments, the power consumption of the PA 508 can be monitored based on the level of change in the predistortion dynamic input bias signal. One method for power consumption monitoring of a FET-based PA 508 is to measure the V0 of the power supply terminal applied to the PA 508. DD and I DD Value. For example, this can be achieved by directly sensing V using an analog-to-digital converter. DD and I DD This can be accomplished (instead of using a scaled replica FET as is typically done in analog active bias circuits). Another approach could be to measure the temperature change in the PA 508 as the predistorted dynamic input bias signal changes, as an alternative to the power dissipation change. For example, the temperature can be estimated by measuring the voltage drop across a diode physically placed near the PA power transistor, minimizing measurement delay effects, because the diode has a low thermal time constant, making the measurement fast (near instantaneous).

[0064] As another example, a closed loop including a remote gateway 106 and a power amplifier with a dynamic input bias signal with predistortion can be used to measure one or more performance metrics and generate corresponding calibration data for the predistortion block 514. This method utilizes existing receiver circuitry in the user terminal 102, which is typically used for full-duplex data communication over an RF communication system between the user terminal 102 and the remote gateway 106.

[0065] In one embodiment, the gain of the power amplifier 508 in the RF transmitter 500 of the user terminal 102 undergoing calibration is measured at a receiver in the remote gateway 106 based on the power level of the test signal. In some embodiments, one or more processing nodes of the gateway 106 process the measurement data and calculate the predistortion polynomial coefficients according to the algorithm described above or a similar algorithm. In other embodiments, the raw measurement data is sent back to the user terminal 102 under test, and the calculation of the predistortion polynomial coefficients is performed locally in the user terminal 102. In either case, the raw or processed measurement data is modulated, fed back to the receiver in the user terminal 102 via the RF communication network 110, demodulated within the user terminal 102, and coupled to the envelope predistortion block 514 in the RF transmitter 500 of the user terminal 102. As part of the calibration process, the RF transmitter 500 undergoing calibration may change the transmitted test signal (e.g., gradually increase the power level), receive new feedback from the remote gateway 106, change the transmitted test signal again (e.g., increase the power level again), and repeat this operation until the gain across the entire signal range is measured. Based on the feedback data, the cancellation polynomial coefficients are calculated (typically at the remote gateway 106, but optionally within the user terminal 102 where calibration is being performed) and provided to the pre-distortion correction block 514.

[0066] In an alternative embodiment, gateway 106 may measure one or more other performance metrics, such as compression and / or EVM, of the test signal transmitted from user terminal 102. Similar to gain, which is used as a performance metric, predistortion correction block 514 within user terminal 102 adjusts the predistortion correction terms and then transmits an updated signal; this operation is repeated and continues in a closed-loop manner as described above. Specifically for EVM, a predistortion algorithm may use an adaptive filter that optimizes the EVM while adjusting the envelope predistortion coefficients; the correction terms are adjusted until an optimal EVM with minimum power is obtained, and this process is iteratively repeated in a closed loop until an overall optimal EVM result is obtained.

[0067] Dedicated time slots can be used for calibration purposes, enabling the use of test signals without interfering with normal data signal services. However, while many embodiments may use optimized test signals that facilitate the measurement of desired performance metrics, in some embodiments the transmitted test signals may be normal data signals, and thus performance metrics can be monitored for maintenance purposes during normal data communication.

[0068] In some embodiments, calibration tests can be performed at different channel frequencies within the operating frequency range. After the initial calibration is completed, the calibration cycle can be re-executed periodically to update the feedback calibration data and maintain the target conditions. The rate of this update can be adjusted to the rate at which transmission characteristics change; for example, continuous, faster, or slower updates, depending on the cause of these changes. Thus, updates measuring changes in transmission characteristics caused by temperature and component aging can be at a slower rate, while updates measuring changes caused by power supply voltage fluctuations can be at a faster rate.

[0069] The calibration method described above can be used to save power in systems with phased array antennas and many corresponding transmitters (typically one transmitter per antenna element or group of antenna elements). In such systems, the correction coefficients can be optimized on an average basis, and a shared predistortion dynamic input bias signal can be distributed to each transmitter amplifier.

[0070] Timing adjustment

[0071] In some embodiments, it is desirable to match the timing of signals in the information signal path (from digital modulator 502 to adder 506 in the illustrated example) with the timing of signals in the parallel envelope signal path (from envelope calculation block 510 to adder 506 in the illustrated example). Timing mismatches may occur between signal paths because the amount of time required to process the input source information on one signal path differs from that of the other. Therefore, in some embodiments, an optional delay module 516 may be inserted into one or both signal paths to adjust the timing of signals in the respective signal path to match the timing of signals in the other signal path. In some embodiments, the delay amount may vary depending on the source information signal, and thus the delay module 516, which provides a programmable delay amount, can be utilized.

[0072] In the example shown, delay module 516 is depicted as part of digital modulator 102 and predistortion block 514, and in many embodiments, it would be convenient to place the delay function in one or both of those elements. However, delay module 516 can be placed anywhere in the signal path after digital modulator 502, therefore Figure 5The locations shown are for illustrative purposes only. Applying any delay on the digital side of the DAC 504 or 512 is generally the most convenient and accurate, but delays can also be applied on the analog side of the DAC 504 or 512.

[0073] DC bias and selective predistortion

[0074] It should be understood that the dynamic input bias signal is typically time-varying. In some embodiments, including a DC bias (positive or negative) at the input of the PA 508 may be useful. For example, providing a DC bias allows the use of DACs with smaller dynamic ranges, such as the DAC504 and DAC512. Figure 5 As shown, an optional DC bias source can be coupled to adder 506. Alternatively, the DC bias can be introduced within envelope calculation block 510, predistortion block 514, or DAC 512, or via a separate circuit (not shown) coupled to the envelope signal path.

[0075] The level of the DC bias can be varied relative to the voltage (or current) of the envelope E or the predistortion envelope E′. For example, a larger DC bias can be applied when at least one of the envelopes E and E′ is below a first threshold, and a smaller DC bias can be applied when such an envelope is above a second threshold (which may be equal to or different from the first threshold). This approach can further reduce power consumption by decreasing the bias on PA 508 when the envelope level is at its maximum. In some embodiments, the DC bias can be dynamic, for example, inversely proportional to the envelope (E or E′). In some embodiments, a negative DC bias can be applied when at least one of the envelopes E and E′ is above a threshold, thereby further reducing the power consumption of PA 508.

[0076] In some embodiments, rather than applying a DC bias, or in addition to applying a DC bias, it may be desirable to selectively apply predistortion only at low and medium envelope levels, while higher envelope levels in the compressed region of the PA508 are uncorrected, less corrected, or even negatively corrected. For example, Figure 7 The graph 700 shows a voltage (or current) information signal that varies with time in a transmitter with a power amplifier having a dynamic input bias signal, illustrating that the applied predistortion 704 is less than a threshold level 702 for the applied predistortion threshold level. For the illustrated embodiment, the predistortion of the dynamic input bias signal is actually negative above the threshold level 702 (comparing the predistortion level of B1′ to the predistortion level of -B2′).

[0077] This selective correction can be optimized for the best performance / power consumption tradeoff. In some embodiments, this tradeoff can be optimized by continuously increasing the range of the pre-distorted envelope signal from a lower level to a higher level while monitoring the performance of the PA 508. For example, the EVM of the PA 508 output can be correlated with the amount of signal compression at each value point within the envelope signal level range, and the bias distribution can be optimized to achieve minimum power consumption while ensuring that the desired EVM parameters are met.

[0078] Therefore, the dynamic input bias signal (including the predistortion envelope E′ of the information signal), the information signal itself, and any added DC bias are combined and applied to the input of PA 508. The power (voltage / current) applied to the power supply terminals of PA 508 remains constant, but power consumption is reduced due to the dynamic nature of the input bias signal.

[0079] Correction of residual distortion

[0080] In some applications, the combined signal applied to the signal input of a power amplifier may contain some residual distortion. This residual distortion, if present, can be reduced by additional correction (predistortion) in the information signal path, separate from the envelope signal path. For example, refer to... Figure 5 Optional linearization block 518 can be included in the information signal path. Linearization is essentially a form of predistortion that modifies the information signal to counteract the nonlinear characteristics of a typical power amplifier.

[0081] Embodiments of the present invention, including optional linearization block 518, can utilize existing receivers within user terminal 102 (typically used for full-duplex data communication) to offload the process of calculating linearization calibration data from user terminal 102 to one or more processing nodes in gateway 106. Although there is a “long” loop via interconnected RF communication network 110, this calibration / linearization process is a closed-loop system.

[0082] More specifically, in some embodiments, gateway 106 measures selected performance metrics (e.g., EVM, spectrum regeneration, intermodulation, etc.) transmitted from user terminal 102 to gateway 106 via RF communication network 110. The transmitted signal can be a conventional modulated signal or an optimized test signal that facilitates the measurement of desired parameters. In one embodiment, gateway 106 processes the measured data and calculates linearization coefficients / parameters according to a linearization algorithm (described below), and sends this information back to user terminal 102. The received information is captured by antenna 104' and converted into digital data coupled to linearization block 518 by receiver and demodulator module 520. Antenna 104' can be a separate antenna or can be the same as transmit antenna 104, wherein a duplexer or other circuitry separates the input and output RF signals; if an electronic phase array antenna is used, separate receive and transmit antenna elements can be used without a duplexer. Receiver and demodulator module 520 can include, for example, a low-noise amplifier (LNA), downconverter circuitry, analog-to-digital converter circuitry, and a demodulator that essentially performs the inverse function of digital modulator 502.

[0083] The received digital data from receiver and demodulator module 520 is used by linearization block 518 to adjust the correction (linearization) terms. The updated test signal is then transmitted to gateway 106 by PA 508. This operation is repeated and continues in a closed loop until the entire signal range has been measured. Similar to calibration pre-distortion block 514, after the initial linearization calibration is completed, the calibration loop can be re-executed periodically to update the feedback calibration data and maintain the target linearization conditions. The rate of this update can be adjusted to accommodate changes in emission characteristics (e.g., constant, faster, or slower updates), depending on the cause of the change. Therefore, updates measuring changes in emission characteristics caused by temperature and component aging can be at a slower rate, while updates measuring changes caused by power supply voltage fluctuations can be at a faster rate.

[0084] Similar to calibration predistortion block 514, dedicated time slots can be used for linearization calibration purposes, enabling the use of test signals without interfering with normal data signal services. However, in some embodiments, monitoring of performance metrics can be performed for maintenance purposes during normal data communication.

[0085] A linearization algorithm that can be used to set the operating parameters of linearization block 518 is employed in an adaptive filter that minimizes the EVM while adjusting the nonlinear predistortion coefficients. The magnitude of the nonlinear correction term is adjusted until the optimal EVM is achieved, and then the phase correction term is adjusted to obtain the optimal EVM. The process is iteratively repeated in the closed loop until the overall optimal EVM result is obtained.

[0086] The advantage of offloading the process of calculating linearized calibration data from user terminal 102 to gateway 106 is that gateway 106 usually already has more computing power for other functions, and user terminal 102 does not need to spend computing time or power to perform this calculation.

[0087] Another advantage of the disclosed method is that the remote gateway 106 processes the signal actually transmitted from the user terminal 102, as opposed to the user terminal 102 sampling or tapping a local signal that may not fully represent the actually transmitted signal (e.g., due to imperfections in the directional coupler, mismatch / reflection, signal leakage, etc.). This advantage is particularly useful in embodiments of the invention that use Frequency Division Duplex (FDD), such as LTE mobile phones, satellite systems, etc. In FDD systems, the receiver and transmitter in the user terminal 102 can operate at different frequencies. In this case, the receiver may not be able to tune to the transmission frequency, and an additional dedicated receiver is required to monitor the transmitter. Therefore, the “long loop” linearization processing described above is particularly useful because the actually transmitted signal cannot be easily locally sampled.

[0088] Power supply voltage bias

[0089] Another aspect of the invention includes a predistorted dynamic input bias (which effectively biases the power amplifier's supply current (I) based on the envelope E). DD Or I CC The power amplifier's supply voltage (V) is biased based on the appearance of the peak value in the envelope E. DD or V CC Bias supply current and supply voltage can significantly reduce power consumption in PA 508.

[0090] In an embodiment of the invention with dual bias, the power supply current bias is fast, tracking the envelope rate of the full-information signal, while the power supply voltage bias is slower, tracking only peaks of the envelope that exceed a certain threshold or meet certain specific criteria at a lower speed. This behavior can be achieved through digital processing, including calculating the envelope E and determining which peaks to track and which peaks to track partially or not at all, as described in further detail below. Peaks exceeding a certain threshold can be tracked at a rate that the power supply voltage source can satisfy, by increasing the power supply voltage to the PA 508.

[0091] Figure 8 This is a block diagram of one embodiment of a transmitter 800, which includes digital biasing of the supply current through PA 508 and the supply voltage to PA 508. The dynamic input bias signal is generated as follows... Figure 5As shown. Additionally, a parallel peak envelope signal path applies the envelope signal E to the peak envelope prefetch block 802. The digital output of the peak envelope prefetch block 802 is coupled to a DAC 804, which controls the voltage output of a variable voltage power supply 806. The output of the variable voltage power supply 806 is a slowly varying voltage applied to the power supply terminal of PA 508 (another power supply terminal DC return path is typically at RF ground).

[0092] The variable voltage power supply 806 is characterized by a limited rate of voltage increase; that is, it cannot immediately output a specified voltage. Furthermore, the greater the specific voltage deviation, the longer it takes for the variable voltage power supply 806 to reach the specified voltage, and this time ratio may not be linear. Therefore, for example, moving from a 16-volt output to 24 volts may take more than twice the time to move from a 16-volt output to 20 volts, and the rate of change of these two changes relative to the envelope E of the information signal may take a considerable amount of time.

[0093] The function of the peak envelope prefetch block 802 is to monitor the waveform data representing the envelope E of the information signal and identify only the peak value of the envelope that exceeds a threshold or some other standard. Furthermore, the peak envelope prefetch block 802 must operate sufficiently before generating the dynamic input bias signal, so that the variable voltage power supply 806 can output the desired power supply voltage bias to PA 508 in a timely manner to meet the input envelope peak value and achieve the desired performance level. Due to this predictive characteristic, a delay module 516 can be included to delay the information signal path and the envelope signal path (via the predistortion block 514), thereby providing sufficient prediction time 802 for the prefetch block 802 and adjusting the timing between paths (see the description above regarding the options for placing the delay module 516).

[0094] Peak envelope pre-read block 802 estimates the minimum supply voltage required to meet the desired performance specifications of the input envelope peak and sends a control command to variable voltage supply 806 via DAC 804 to output this minimum voltage. Based on knowledge of the response time of variable voltage supply 806 (which in turn depends on its loop bandwidth and other characteristics, as well as the amount of voltage change required within the available time), the command is sent to variable voltage supply 806 early enough before the (delayed) envelope peak is output as a dynamic input bias level, giving variable voltage supply 806 sufficient time to respond and adjust the output voltage to meet the input envelope peak.

[0095] More specifically, the peak envelope prefetch block 802 may include a buffer memory storing a sequence of running values ​​representing the envelope E; the length of the buffer memory can be optimized to match the response time of the variable voltage supply 806. The stored values ​​are analyzed to track high envelope peaks (e.g., Figure 3The timing and level of the next highest input peak are considered, based on their time occurrence and level values. For example, if two high peaks occur in relatively close proximity, the intervention of the lower peak can be ignored, thus avoiding an attempt to switch the output of the variable voltage power supply 806 from high to low and then from low to high within a short time span.

[0096] As a result, only some medium and low peaks can be tracked from the higher voltage portion, or not at all. This method allows the use of a relatively slow variable voltage supply 806, whose response time is slower than the envelope rate, while ensuring that the output supply voltage provided to the PA508 is always equal to or higher than the minimum voltage to meet the desired performance level. Although the efficiency improvement may not be as high as the supply voltage tracking the envelope E at full speed, the power reduction can still be significant because there is often a period when the supply voltage corresponds to a lower level of envelope peaks at a lower level.

[0097] Typically, the DAC 804 driving the variable voltage power supply 806 does not need to be very fast; it can be only a few times faster than the loop bandwidth of the variable voltage power supply 806 (typically no more than about 10 times). For example, if the variable voltage power supply 806 has a 10 kHz bandwidth, the DAC 804 does not need to be faster than about 100 kHz. In some embodiments, the function of the voltage-controlled DAC 804 can be implemented as a filtered pulse-width modulation (PWM) digital output from the peak envelope pre-read block 802. In other embodiments, the function of the voltage-controlled DAC 804 can be integrated within the variable voltage power supply 806.

[0098] The dynamic input bias signal to PA 508 can be additionally predistorted to correct any distortion that may occur due to changes in the supply voltage to PA 508. However, the voltage level mapped to the envelope peak may then need to be readjusted to correct for this change in the predistortion of the dynamic input bias signal. Therefore, a calibration process similar to one of the types described above can be applied iteratively to adjust both the predistortion block 514 and the peak envelope prereading block 802 to achieve optimal operation for each other.

[0099] In another embodiment, the output level of the variable voltage power supply 806 may be intermittently (essentially statically) settable, rather than dynamically controlled based on the peak envelope E (thus, the peak envelope pre-readout block 802 can be eliminated or bypassed). More specifically, the output level of the variable voltage power supply 806 may be optimized (statically adjusted) for the actual power amplifier device used in the transmitter and subsequently adjusted in response to tracking factors such as temperature and component aging. A closed-loop or open-loop control loop coupled (directly or indirectly) to the variable voltage power supply 806 periodically measures the tracked parameters (e.g., the temperature of PA 508) and adjusts the power supply voltage output level to the optimal value for the measured state.

[0100] In another embodiment, the variable voltage power supply 806 can be coupled to the peak envelope pre-read block 802 (to allow dynamic control of its output voltage based on the envelope peak value) and to a control loop that intermittently provides a set minimum output voltage. For example, the intermittently settable function can be used to adjust the minimum output voltage to cope with the effects of temperature and component aging, while allowing dynamic changes based on the envelope peak value to reduce average power consumption.

[0101] Figure 9 This is a block diagram of a simplified embodiment of transmitter 900, which includes digital biasing of the supply current through power amplifier 508 and the supply voltage to power amplifier 508. The dynamic input bias signal is generated as follows... Figure 5 As shown. Additionally, the parallel envelope signal path applies the envelope signal E to the digital comparator 902, which outputs a switching control signal to the switching module 904 to select the high voltage potential V. HIGH or low voltage potential V LOW The power supply voltage (V) for PA 508 DD or V CC ).

[0102] In the example shown, the switching module 904, controlled by the digital comparator 902, includes a top switch and a bottom switch in a complementary state. In some embodiments, the bottom switch (for V) LOW The diode is replaced with a Schottky diode, which is based on V. HIGH and V LOW The relative voltage behavior is that of a switch.

[0103] exist Figure 8 In this simplified version of the circuit shown, the digital comparator 902 simply compares the value of the envelope E with a threshold and selects V when the envelope exceeds the threshold. HIGH And recovers to V when the envelope drops below the threshold. LOWSome hysteresis can be added within the digital comparator 902 to prevent oscillating behavior. The threshold is typically determined through calibration and optimized for minimum power consumption while meeting the required performance level. Any distortion that may occur due to switching transients can be calibrated and reduced by adding, offset pre-distortion in the dynamic input bias path.

[0104] It should be understood that the switching module 904 can be configured to select and output more than two power supply voltages. For example, the digital comparator 902 can output "low," "medium," and "high" switching control signals based on comparing the envelope E with two spaced thresholds.

[0105] Multi-stage regulated voltage power supply

[0106] Figure 9 The circuit shown requires at least two voltage levels (e.g., V). HIGH and V LOW In practice, such a voltage power supply should provide a stable, essentially constant voltage for a specific range of loads. Typically, if an electronic device requires two or more regulated voltages, each regulated voltage is generated and maintained by a separate voltage regulation circuit, which occupies space on the device and is therefore costly. Therefore, it would be useful if a single circuit could provide two or more regulated voltages.

[0107] Figure 10A This is a schematic diagram of a "chain-feedback" regulated power supply circuit 1000. The illustrated embodiment eliminates the need for a separate regulation circuit for each regulated voltage. The illustrated regulated power supply circuit 1000 is designed such that a first load 1 maintains a substantially constant voltage V1 at a first node N1, and a second load 2 maintains a substantially constant voltage V2 at a second node N2.

[0108] More specifically, the illustrated regulated power supply circuit 1000 is a DC / DC (switching mode) converter that steps down the applied high voltage to V1 (also known as a "buck" converter). In an alternative embodiment, the regulated power supply circuit 1000 can be configured to boost the applied source voltage (also known as a "boost" converter).

[0109] The regulated power supply circuit 1000 includes at least two stages. In the example shown, the first output stage 1002 includes two stacked switches T1 and T2 connected in series, coupled to the source voltage (high voltage V) as shown. HBetween the source voltage (V1) and the low voltage (typically circuit ground). A first LC circuit, including inductor L1 and capacitor C1, is coupled between the junction of T1 and T2 and the load 1. Similarly, the second output stage 1004 includes stacked switches T3 and T4 in series, coupled between the source voltage (V1 in this case) and the low voltage (typically circuit ground), as shown. A second LC circuit, including inductor L2 and capacitor C2, is coupled between the junction of T3 and T4 and the load 2. Other similar output stages can be “linked” in a similar manner; for example, a third stage could use V2 as its source voltage. In some embodiments, all switches (T1 to T4 in this example) can be field-effect transistors (FETs). In some embodiments, the “top” switches (T1 and T3 in this example) can be FETs, while the “bottom” switches (T2 and T4 in this example) can be Schottky diodes.

[0110] The regulated power supply circuit 1000 also includes a controller that provides a series of first control pulses HD (for "high drive") and a series of second control pulses LD (for "low drive"). The HD and LD control pulses are non-overlapping and complementary (and therefore their duty cycles are also complementary). In the example shown, the HD control pulses are connected to the control inputs (e.g., FET gates) of T1 and T3, while the LD control pulses are connected to the control inputs of T2 and T4 (see below for...). Figure 10B (Discussion of alternative configurations). Note that if Schottky diodes are used in the "bottom" switch (T2 and T4 in this example), the diode switch will switch automatically based on the voltage polarity, so no LD control pulse is required.

[0111] The regulated power supply circuit 1000 also includes a feedback loop from N1 to the controller, which operates by comparing the actual voltage V1 at node N1 with a reference voltage Vref. The controller adjusts the duty cycle of the HD and LD control pulses to maintain V1 at the target value of Vref. For example, if V... H To reduce the duty cycle, the feedback loop increases the duty cycle of the HD control pulse, allowing for longer (in the case of duty cycle-controlled DC / DC converters) or more frequent (in the case of frequency-controlled switches) coupling of V through T1 to N1. H To compensate for this change. More generally, the controller adjusts the duty cycle (“d”) of the control pulse to achieve the target output voltage VI, so V1 is essentially equal to d*V. H .

[0112] The adjustment of V2 is linked to V1, and T3 and T4 are switched by HD and LD control pulses at the same rate and duty cycle as T1 and T2, respectively. Figure 10AAs shown. For simplicity, no level shifters or scaling circuits that might be needed to properly drive T3 and T4 are shown. Therefore, the same duty cycle d is applied to the linked switches T3 and T4, resulting in a voltage ratio V2 / V1 equal to the voltage ratio V1 / V2. H Basically the same:

[0113] V1 / V H =d=V2 / V1=>V1=d*V H and V2=d 2 *V H EQ.4

[0114] For example, if d = 1 / 2 or 50%, V1 will be V H V2 will be half of V1 (i.e., V1 = V2). H (one-quarter); in V H In the case of 48V, in this example, V1 is 24V and V2 is 12V (ignoring potential voltage output variations due to parasitic losses, such as those in inductors L1 and L2).

[0115] Figure 10B This is a schematic diagram of the alternative "chain" feedback regulated power supply circuit 1020. In the example shown, the HD control pulse is connected to the control inputs of T1 and T4, while the LD control pulse is connected to the control inputs of T2 and T3 (with offset and scaling to obtain the appropriate drive level if needed). Therefore, with Figure 10A In contrast, the HD and LD control pulse lines intersect each other, as shown by the dashed ellipse X. For this configuration, V2 = d*(1-d)*V H In another variant configuration, T3 is disconnected from N1 and the same terminal of T3 is connected to V. H (i.e., from V) H Instead of feeding T3 from V1, but keeping Figure 10B (As shown in the diagram, the "crossed" LD and HD control pulse connections) then V2 = (1-d)*V H In another configuration change, via V H Feed T3, but as Figure 10A The HD and LD control pulses are coupled as shown, then V2 = d*V H This is essentially the same as V1; this configuration allows for greater current capability at the same voltage without requiring larger switches (T1 to T4 in this example) and larger inductor and capacitor sizes that might be needed in a single (traditional) stage voltage power supply circuit. It should be clear that by inserting switches in appropriate locations to control which control pulses are applied to the control inputs of T3 and T4, and / or to control the voltage input of T3, a circuit can be constructed that can output four different values ​​up to V2: V2 = d * VH V2 = d 2 *V H V2=d*(1-d)*V H ; and / or V2 = (1-d)*V H .

[0116] therefore, Figure 10A Or a 10B "chain" regulated power supply circuit and its variations can provide at least two output voltage levels with only one controller, thus saving space and cost. Therefore, such a circuit may be suitable for... Figure 9 The illustrated embodiment of a circuit requiring at least two voltage levels is very useful; for example, V1 can be used for V. HIGH V2 can be used for V LOW (In this application, load is not a factor because only one load can be connected at a time due to the complementary states of the top and bottom switches in switching module 904.) Furthermore, the "chained" architecture can be extended by adding more levels in a similar manner, with each new level feeding from the previous level. For example, the third level can be linked to the second level 1004 by feeding from V2 and switching via HD. The third level will produce an output equal to d. 3 *V H The voltage V3. Furthermore, by inserting switches in appropriate positions to control which control pulses are applied to the control input of each stage's switch, and / or to the voltage input of each stage, a circuit can be constructed that can output more supply voltage at low cost.

[0117] method

[0118] Another aspect of the present invention is a method for biasing a transmitter circuit in a telecommunications system, comprising: receiving digital source information; generating a modulation information signal from the received digital source information; generating a dynamic input bias signal with an envelope in the form of the source information; combining the modulation information signal and the dynamic input bias signal; and outputting an analog signal of the combined modulation information signal and the dynamic input bias signal, the analog signal being suitable for application to the input of a power amplifier.

[0119] Another aspect of the present invention is a method for biasing a transmitter circuit in a telecommunications system, comprising: receiving digital source information; generating a modulation information signal from the received digital source information; generating a dynamic input bias signal with an envelope in the form of the source information; combining the modulation information signal and the dynamic input bias signal; outputting an analog signal of the combined modulation information signal and the dynamic input bias signal; and coupling the analog signal to the input of a power amplifier for amplification by the power amplifier.

[0120] Another aspect of the present invention is a method for biasing a transmitter circuit in a telecommunications system, comprising: receiving digital source information; generating a modulation information signal from the received digital source information; applying a linearization transform function to the modulation information signal; applying the transform function to an envelope in the form of the source information to generate a predistortion envelope; generating a dynamic input bias signal based on the predistortion envelope; combining the linearized modulation information signal and the dynamic input bias signal; outputting an analog signal of the combined linearized modulation information signal and the dynamic input bias signal; and coupling the analog signal to the input of a power amplifier for amplification by the power amplifier.

[0121] Other aspects of one or more of the above methods include: applying a transform function to the envelope of the source information before generating a dynamic input bias signal, such that the dynamic input bias signal is a pre-distorted dynamic input bias signal; applying a first pre-distortion level to the transform function for envelope levels below a selected threshold, and applying a second pre-distortion level below the first pre-distortion level to envelope levels above the selected threshold; applying the transform function only to envelope levels below the selected threshold; the transform function being the inverse distribution of the gain distribution of the power amplifier; receiving a calibration signal derived from a signal transmitted by a transmitter circuit of a telecommunications system from a remote gateway, and adjusting the transform function according to the received calibration signal; determining the expected occurrence of a peak in the envelope of the information signal, and outputting a power supply voltage for the power amplifier, the power supply voltage having a voltage potential based on the determined occurrence of the expected peak in the envelope of the information signal. The system adjusts the transformation function based on the power supply voltage potential; determines the occurrence of a peak value exceeding at least one selected threshold in the envelope of the information signal, and outputs a first power supply voltage to the power amplifier in response to the determination of the occurrence of a peak value exceeding at least one selected threshold in the envelope of the information signal; otherwise, outputs a second power supply voltage to the power amplifier; adjusts the transformation function based on the output power supply voltage; applies the linearization transformation function to the modulated information signal; receives a calibration signal derived from the signal transmitted by the transmitter circuit of the telecommunications system from the remote gateway, and adjusts the linearization transformation function based on the received calibration signal; and adds a selected amount of DC bias to the input of the power amplifier.

[0122] Another aspect of the invention is a method for providing two or more regulated output voltages, comprising: providing a first output stage including stacked transistors configured to be coupled between a first voltage and a second voltage, each transistor having a corresponding control input, the first output stage being configured to provide a first output voltage at a first output node; providing at least one subsequent output stage, each subsequent output stage including stacked transistors configured to be coupled between (1) an output node of a previous output stage or between the first voltage and (2) a second voltage, each transistor having a corresponding control input, each subsequent output stage being configured to provide a corresponding subsequent output stage output voltage at a corresponding output node; and providing a controller configured to be coupled to a reference voltage and to the first output voltage from the first output stage, the controller outputting a first output pulse signal and a non-overlapping and complementary second output pulse signal, wherein the first output pulse signal is coupled to a control input of one of the two transistors in each output stage, and the second output pulse signal is coupled to a control input of the other of the two transistors in each output stage, wherein the controller adjusts the duty cycle of the first output pulse signal and the second output pulse signal based on a comparison of the reference voltage and the first output voltage.

[0123] Another aspect of the invention is a method for providing two regulated output voltages, comprising: providing a first output stage including stacked field-effect transistors (FETs) configured to be coupled between a first voltage and ground, each FET having a corresponding control input, the first output stage being configured to provide a first output voltage at a first node; providing a second output stage including stacked FETs configured to be coupled between (1) the output node of the first stage or between the first voltage and (2) ground, each FET having a corresponding control input, the second output stage being configured to provide a second output voltage at a second output node; and a controller configured to be coupled to a reference voltage and to the first output voltage from the first output stage, the controller outputting a first output pulse signal and a non-overlapping and complementary second output pulse signal, wherein the first output pulse signal is coupled to a control input of one of two transistors in each of the first and second output stages, and the second output pulse signal is coupled to a control input of the other of two transistors in each of the first and second output stages, wherein the controller adjusts the duty cycle of the first and second output pulse signals based on a comparison of the reference voltage and the first output voltage.

[0124] Other aspects of the above-mentioned methods for providing regulated output voltage include: each transistor being a field-effect transistor; and the output voltage of the subsequent output stage of the first stage in at least one subsequent output stage being approximately d*V. H d 2 *V Hd*(1-d)*V H Or (1-d)*V H One of them, where d is the duty cycle of the first output pulse signal and the second output pulse signal, and V H It is the first voltage.

[0125] Manufacturing technology and selection

[0126] In practical implementations, the input signal bias at the modulation envelope frequency can generate spectral energy at the output envelope frequency of the PA508. Therefore, this energy may need to be filtered out. Conventional output filters or matching networks can be used to accomplish this filtering function; the wider the interval between the RF carrier frequency and the envelope frequency, the easier the filtering. Additionally, anti-aliasing filters and interface circuitry between the inputs of the DACs 504 and 512 and the PA 508 may be required.

[0127] It will be apparent to those skilled in the art that various embodiments of the invention can be implemented to meet a wide range of specifications. Circuitry that may be required for a particular application (e.g., up / down conversion, voltage offset, negative power rail, etc.) is not shown for simplicity.

[0128] Although the above description has focused on the transmitter circuit of user terminal 102 by way of example, the present invention can be applied to the transmitter circuit within gateway 106 and to reduce power consumption.

[0129] Although the embodiments described above and shown in the accompanying drawings contain various elements shown as separate functional blocks, the functionality of these blocks can be integrated into fewer or more blocks. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice, and various embodiments of the invention can be implemented using any suitable IC technology (including, but not limited to, MOSFET and IGFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to GaN, GaAs, standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and MESFET technologies.

[0130] The term "MOSFET" technically refers to a metal-oxide-semiconductor; another synonym for MOSFET is "MISFET," which stands for metal-insulating-semiconductor FET. However, "MOSFET" has become the common label for the vast majority of types of insulated-gate FETs ("IGFETs"). Nevertheless, it is well known that the term "metal" in the names of MOSFET and MISFET is now often inaccurate, as the previously used metal gate material is now typically a layer of polysilicon (polysilicon). Similarly, the "oxide" in the name of MOSFET may be inaccurate, as different dielectric materials are used to achieve a strong channel with a smaller applied voltage. Therefore, the term "MOSFET" as used herein should not be understood to be literally limited to metal-oxide-semiconductor, but rather generally includes IGFETs.

[0131] Depending on specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels can be adjusted or voltage and / or logic signal polarities can be reversed. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering the circuit's original function.

[0132] Several embodiments of the invention have been described. It should be understood that various modifications can be made without departing from the principles and scope of the invention. For example, some of the steps described above may be independent of the order and therefore may be performed in a different order than that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the above methods may be performed in a repetitive, serial, or parallel manner. It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. (Note that, (1) as used in this specification, the drawings, and the following claims, "comprising" is interpreted as meaning "including," "containing," or "comprises," and (2) the bracket markings of the claim elements are for ease of reference to these elements and do not in themselves indicate a particular order or enumeration of the elements; furthermore, these markings may be reused in dependent claims as references to additional elements and are not considered as a contradictory sequence of labels.)

Claims

1. A circuit for providing two or more output voltages in a multi-stage chain feedback regulated power supply, comprising: 1) A first output stage comprising stacked transistors configured to be coupled between a first voltage and a second voltage, each transistor having a corresponding control input, the first output stage being configured to provide a first output voltage at a first output node; 2) At least one subsequent output stage, each subsequent output stage including transistors configured to be coupled to the output node of the previous output stage or stacked between a first voltage and a second voltage, each transistor having a corresponding control input, each subsequent output stage being configured to provide a corresponding subsequent output stage output voltage at the corresponding output node; and 3) A controller configured to be coupled to a reference voltage and to a first output voltage from a first output stage, the controller outputting a first output pulse signal and a non-overlapping and complementary second output pulse signal, wherein the first output pulse signal is coupled to a control input of one of two transistors in each output stage, and the second output pulse signal is coupled to a control input of the other of two transistors in each output stage, wherein the controller adjusts the duty cycle of the first output pulse signal and the second output pulse signal based on a comparison of the reference voltage and the first output voltage.

2. The circuit of claim 1, wherein each transistor is a field-effect transistor.

3. The circuit according to claim 1, wherein the output voltage of the subsequent output stage of the first stage in at least one subsequent output stage is d*V. H d2*V H d*(1-d)*V H Or (1-d)*V H One of them, where d is the duty cycle of the first output pulse signal and the second output pulse signal, and V H It is the first voltage.

4. The circuit according to claim 1, wherein the second voltage is grounded.

5. A method for providing two or more regulated output voltages, comprising: 1) Provide a first output stage comprising stacked transistors configured to be coupled between a first voltage and a second voltage, each transistor having a corresponding control input, the first output stage being configured to provide a first output voltage at a first output node; 2) Provide at least one subsequent output stage, each subsequent output stage including transistors configured to be coupled to the output node of the previous output stage or stacked between a first voltage and a second voltage, each transistor having a corresponding control input, and each subsequent output stage being configured to provide a corresponding subsequent output stage output voltage at the corresponding output node; and 3) Provide a controller configured to be coupled to a reference voltage and to a first output voltage from a first output stage, the controller outputting a first output pulse signal and a non-overlapping and complementary second output pulse signal, wherein the first output pulse signal is coupled to a control input of one of two transistors in each output stage, and the second output pulse signal is coupled to a control input of the other of two transistors in each output stage, wherein the controller adjusts the duty cycle of the first output pulse signal and the second output pulse signal based on a comparison of the reference voltage and the first output voltage.

6. The method of claim 5, wherein each transistor is a field-effect transistor.

7. The method according to claim 5, wherein the output voltage of the subsequent output stage of the first stage in at least one subsequent output stage is d*V. H d 2 *V H d*(1-d)*V H Or (1-d)*V H One of them, where d is the duty cycle of the first output pulse signal and the second output pulse signal, and V H It is the first voltage.

8. The method of claim 5, wherein the second voltage is grounded.

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