LED load control method, integrated chip and lighting device

Abstract

The present application provides a control method, an integrated chip and a lighting device for an LED load. The control method for the LED load includes: detecting an instantaneous reference value of a negative terminal voltage of an LED load, setting a decreasing critical value of the instantaneous reference value as a peak reference value, and selecting a maximum value of the peak reference value and the instantaneous reference value as a voltage peak value within a first time window; receiving the voltage peak value, and outputting a first signal when detecting that a difference between the negative terminal voltage of the load and the voltage peak value exceeds a first threshold value; generating a second signal according to the negative terminal voltage of the load and an input voltage, and controlling the current of the LED load according to the first signal and the second signal, wherein the first signal is used to quickly respond to fluctuations in the negative terminal voltage of the load. The control method for the LED load can quickly respond to significant changes in the driving current, and reduces the cost and complexity of the peripheral design.

Description

Technical Field

[0001] The present application relates to electronic power technology, and more specifically, to a control method for an LED load, an integrated chip, and a lighting device. Background Art

[0002] LED (Light Emitting Diode) is used in a variety of electronic applications, such as architectural lighting, car headlights and taillights, backlights and flashlights of liquid crystal display devices including personal computers and high-definition televisions, etc. Compared with conventional light sources such as incandescent lamps and fluorescent lamps, LEDs have significant advantages, including high efficiency, good directionality, color stability, high reliability, long life, small size, and environmental safety. Since LED is a current-driven device, it is inevitable that a current ripple of 100-120Hz will be generated in the prior art. Although this low-frequency flicker is difficult for the human eye to perceive, long-term exposure of the human eye to this lighting environment will cause visual nerve fatigue and endanger human health. Therefore, in high-end applications, it is necessary to eliminate the current ripple contained in the driving current provided by the LED driver to the LED.

[0003] Although the current ripple or flash removal circuit technology can meet the needs of full-load applications, when dimming is required, there are problems such as low loop bandwidth, slow system loop response speed, and easy current overshoot. For the above situations, existing technical solutions such as Figure 1 As shown in the figure, by setting the resistor voltage divider ratio of the VLMT pin, according to different applications (lamp voltage, current, electrolytic capacitor and other related parameters), different resistor voltage divider ratios can be set. When the DRAIN voltage is higher than the set threshold voltage, there will be a fast pull-up action of the VC capacitor inside the chip, which can well solve the problem of fast response when the LED current increases rapidly during the dimming process. However, although this solution can be well adapted to various dimming applications, the chip needs an extra functional pin, and the peripheral needs to add resistors, which increases the peripheral cost and system volume. In lighting applications that require smaller and smaller volumes, it is increasingly unable to meet the current market demand.

[0004] Therefore, it is desirable to provide an improved control circuit for LED loads to meet the requirements of fast response system loop dimming process and reduce cost and peripheral volume. Summary of the invention

[0005] This Summary is provided to introduce some concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] The purpose of the present application is to provide an improved control circuit for LED loads to meet the requirements of fast response system loop dimming process and reduce cost and peripheral volume. The above and other purposes are achieved by the features of the independent claims. Further implementation forms are obvious from the dependent claims, the description and the drawings.

[0007] According to the first aspect of the present application, a control method for an LED load is provided, characterized in that it includes: detecting an instantaneous reference value of the negative terminal voltage of the LED load, setting a decreasing critical value of the instantaneous reference value as a peak reference value, and selecting a maximum value of the peak reference value and the instantaneous reference value as a voltage peak value within a first time window; receiving the voltage peak value, and outputting a first signal when detecting that a difference between the negative terminal voltage of the load and the voltage peak value exceeds a first threshold value; generating a second signal according to the negative terminal voltage of the load and an input voltage, and controlling the current of the LED load according to the first signal and the second signal, wherein the first signal is used to quickly respond to fluctuations in the negative terminal voltage of the load.

[0008] Optionally, the instantaneous reference value of the negative terminal voltage of the LED load is detected, the falling critical value of the instantaneous reference value is set as the peak reference value, and within a first time window, the maximum value of the peak reference value and the instantaneous reference value is selected as the voltage peak value, including: when no larger instantaneous reference value is detected within the first time window, the peak reference value is saved as the voltage peak value; otherwise, the peak reference value is cleared, the falling critical value of the instantaneous reference value is resampled and set as the peak reference value; the peak reference value is output as the voltage peak value.

[0009] Optionally, the method includes: receiving the load negative terminal voltage and generating the instantaneous reference value of the load negative terminal voltage; offsetting the instantaneous reference value up and down by a set amount to generate an upper instantaneous reference value and a lower instantaneous reference value; comparing the current load negative terminal voltage with the upper instantaneous reference value to generate a third signal, and comparing with the lower instantaneous reference value to generate a fourth signal; outputting the first clock signal according to the third signal and the fourth signal; when the first clock signal is valid, the third signal and the fourth signal are subjected to logical operation, and the instantaneous reference value is counted and updated, and the falling critical point of the instantaneous reference value is saved as the peak reference value; when the first clock signal is invalid, counting is stopped.

[0010] Optionally, the method includes: comparing the peak reference value with the instantaneous reference value, and outputting a pulse signal when the instantaneous reference value does not exceed the peak reference value within the first time window; and outputting the peak reference value as the voltage peak value according to the pulse signal.

[0011] Optionally, when the third signal and the fourth signal are both at a low level, the first clock signal is invalid.

[0012] Optionally, the method also includes: controlling the voltage across the capacitive device according to the second signal to eliminate the ripple of the driving current, and when the second signal outputs a high level, outputting a first charging current to the capacitive device; when the first signal is output, outputting a third charging current to the capacitive device, and the current value of the third charging current is greater than the current value of the first charging current.

[0013] Optionally, eliminating the ripple of the driving current according to the load negative terminal voltage and the input voltage includes: receiving the input voltage and generating a reference voltage according to the input voltage; and outputting the second signal after comparing the reference voltage with the load negative terminal voltage.

[0014] According to a second aspect of the present application, an integrated chip for an LED load is provided, characterized in that it comprises: a control circuit for an LED load, wherein the control circuit for the LED load is integrated inside the chip; the control circuit for the LED load comprises: a peak holding circuit, configured to detect an instantaneous reference value of the voltage at the negative terminal of the load, set a critical value of a decrease of the instantaneous reference value as a peak reference value, and select a maximum value of the peak reference value and the instantaneous reference value as a voltage peak value within a first time window; a voltage detection circuit, configured to receive the voltage peak value, and output a first signal when detecting that a difference between the voltage at the negative terminal of the load and the voltage peak value exceeds a first threshold value; a load control circuit, configured to generate a second signal according to the voltage at the negative terminal of the load and the input voltage, and control the current of the LED load according to the first signal and the second signal, wherein the first signal is used to quickly respond to fluctuations in the voltage at the negative terminal of the load.

[0015] Optionally, the integrated chip further includes: a first pin configured to access an input voltage; a second pin configured to be connected to a negative terminal of a load to receive a negative terminal voltage of the load; and a third pin configured to be connected to a reference ground.

[0016] Optionally, the input end of the peak holding circuit is connected to the second pin to receive the negative terminal voltage of the load, the input end of the voltage detection circuit is electrically connected to the output end of the peak holding circuit, the first input end of the load control circuit is connected to the first pin to receive the input voltage, the second input end is connected to the output end of the voltage detection circuit for receiving the first signal, and the third end is connected to the third pin and is configured to be connected to the reference ground.

[0017] Optionally, the peak holding circuit includes: a first comparator, configured to receive the upward offset of the instantaneous reference value at the first input terminal, receive the negative terminal voltage of the load at the second input terminal, and output a third signal at the output terminal; a second comparator, configured to receive the negative terminal voltage of the load at the first input terminal, receive the downward offset of the instantaneous reference value at the second input terminal, and output a fourth signal at the output terminal; an oscillator, generating an original clock signal; a clock logic circuit, receiving the original clock signal, the third signal and the fourth signal, and generating the first clock signal, wherein when the first clock signal is valid, the third signal and the fourth signal are counted and saved as the instantaneous reference value after logical operation, and the falling critical point of the instantaneous reference value is saved as the peak reference value, and when the first clock signal is invalid, counting is stopped; a third comparator, configured to receive the peak reference value at the first input terminal, receive the instantaneous reference value for comparison at the second input terminal, and output a fifth signal, wherein when the instantaneous reference value exceeds the peak reference value, the fifth signal is output, and when the peak holding circuit does not receive the fifth signal within the first time window, the peak reference value is stored as the voltage peak.

[0018] Optionally, the load control circuit includes: a reference voltage circuit, configured to receive the input voltage and generate a reference voltage based on the input voltage; a fifth comparator, configured to receive the negative voltage of the load at a first input terminal, receive the reference voltage at a second input terminal, and output a second signal at an output terminal; an integration circuit, configured to include a capacitive device, the first terminal of the integration circuit is connected to the output terminal of the fifth comparator, and the second terminal is connected to the voltage detection circuit, when the second signal outputs a high level, a first charging current is output to the capacitive device; when the second signal outputs a low level, a second charging current is output to the capacitive device, and when the first signal outputs a high level, a third charging current is output to the capacitive device; a sixth comparator, configured to have a first input terminal connected to the capacitive device, and a second input terminal grounded through a resistor; a first switch tube, configured to have a first polarity terminal connected to the negative terminal of the load, a second polarity terminal connected to the second input terminal of the sixth comparator, and a control terminal connected to the output terminal of the sixth comparator.

[0019] According to a third aspect of the present application, a lighting device is provided, characterized in that it includes: an LED driving circuit configured to generate a driving current; an LED light string configured to receive the driving current and be lit; and an integrated chip as described above, wherein the integrated chip is electrically connected to the LED light string.

[0020] The control method, integrated chip and lighting device of the LED load provided in the present application sample the peak value information of the negative terminal voltage of the load cycle by cycle, and compare the instantaneous negative terminal voltage information of the load representing the magnitude of the driving current with the stored voltage peak value. When a large change in the driving current is detected, a signal is sent to enable the circuit to respond quickly to adapt to the new driving current. According to this method, the control circuit of the LED load has a short response time and does not require peripheral components, so the cost is low and the applicability is stronger. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0022] Figure 1 A schematic diagram of a control circuit of an LED load in the prior art is shown;

[0023] Figure 2 A structural block diagram of an embodiment of the present application is shown;

[0024] Figure 3 A schematic diagram showing the structure of a peak holding circuit according to an embodiment of the present application is shown;

[0025] Figure 4 A schematic diagram showing the structure of a voltage detection circuit according to an embodiment of the present application is shown;

[0026] Figure 5 A schematic diagram showing the structure of a load control circuit according to an embodiment of the present application is shown;

[0027] Figure 6 The circuit structure diagram of the chip embodiment of the present application is shown;

[0028] Figure 7 A schematic structural diagram of an embodiment of a lighting device of the present application is shown.

[0029] In the following, identical reference numerals denote identical or at least functionally identical features. DETAILED DESCRIPTION

[0030] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] For example, it should be understood that the disclosure in conjunction with the described method is also applicable to the corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include a unit for performing the described method step, even if such a unit is not described or shown in detail in the accompanying drawings. On the other hand, for example, if a specific device is described based on a functional unit, the corresponding method may include a step for performing the described function, even if the step is not explicitly described or illustrated in the accompanying drawings. In addition, it should be understood that the features of the various example aspects described herein may be combined with each other unless otherwise specifically stated.

[0032] It should be understood that the connection / coupling of A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiment of the present application is not limited to this.

[0033] In the prior art, the control circuit of the LED load usually has a relatively narrow bandwidth because it filters the power frequency ripple (100Hz-120Hz), which determines that the system's rapid response capability is very poor. For example, in the field of dimming, when the LED drive current suddenly increases rapidly, it is impossible to respond quickly by relying solely on the conventional loop, which will cause the drain voltage to rise rapidly and the loss to increase sharply. In order to solve this problem, a pin is usually added and a voltage divider resistor is used to solve the problem of poor rapid response capability of the system, but this solution makes the peripheral design of the circuit complicated and more expensive. The present application proposes an improved control circuit of the LED load to solve the above problems.

[0034] The control circuit of the LED load provided in the embodiment of the present application is applied to a circuit in which a driving device transmits a driving current to a load. Figure 2 A structural block diagram of an embodiment of the present application is shown. Figure 2As shown, the control circuit of the LED load includes a peak holding circuit 101, a voltage detection circuit 102 and a load control circuit 103, wherein the peak holding circuit 101 receives the load negative terminal voltage, detects and saves the peak value of the load negative terminal voltage within a first time window, and the saved voltage peak value is updated within each first time window. When a higher voltage value appears, it is re-saved as a new voltage peak value and the first time window is re-timed. The voltage detection circuit 102 receives the voltage peak value saved by the peak holding circuit 101, and monitors the load negative terminal voltage in real time. When the load negative terminal voltage suddenly jumps to exceed the first threshold within the first time window, a first signal is output to the load control circuit 103. The load control circuit 103 receives an input voltage, and the input voltage is generated according to a driving current through a large capacitor. When there is no fast response intervention, the load control circuit 103 generates different charging currents according to the input voltage to remove ripples. After receiving the first signal, in response to the first signal, a charging current with a larger current value is generated to adapt to the sudden increase in the driving current to prevent the drain voltage of the switch tube used to neutralize the ripple from rising rapidly.

[0035] As an example, the load control circuit 103 receives an input voltage, sets a reference voltage according to the input voltage, removes ripples after comparing with the load negative terminal voltage, and when the load control circuit 103 receives a first signal, the load control circuit 103 quickly pulls up the current output to quickly respond to the system loop. As an example, the first time window can be 15ms, and the first threshold can be 0.2V. The first time window and the first threshold can be set according to actual applications, and this application does not limit this.

[0036] Figure 3 FIG. 4 shows a schematic diagram of a peak holding circuit according to an embodiment of the present application. Figure 3 As shown, the peak holding circuit includes a first comparator OP1 and a second comparator OP2, wherein the first input terminal of the first comparator OP1 receives the upper offset of the instantaneous reference value, the second input terminal receives the real-time load negative terminal voltage VDREF, and the output terminal outputs a third signal VH, the first input terminal of the second comparator OP2 receives the load negative terminal voltage VDREF, the second input terminal receives the lower offset of the instantaneous reference value, and the output terminal outputs a fourth signal VL, wherein the upper and lower offsets of the instantaneous reference value may be the same value or different values, which is not limited in this document, wherein the relationship between the third signal VH, the fourth signal VL and the load negative terminal voltage VD is as shown in formula (1):

[0037]

[0038] The third signal VH and the fourth signal VL simultaneously determine the output of the clock signal. The oscillator generates an original clock signal. The third signal VH and the fourth signal VL generate the first clock signal CKI through two NOR gates. When the third signal VH and the fourth signal VL simultaneously output a low level, the first clock signal CKI is shielded. When the voltage at the negative end of the load is greater than the instantaneous reference value, VH=1, VL=0. At this time, the first clock signal CKI is valid. After the third signal VH and the fourth signal VL are operated by the logic circuit, the fourth signal VL branch continues to count and save the instantaneous reference value. When the voltage at the negative end of the load continues to be greater than the upper offset of the instantaneous reference value, the instantaneous reference value is kept updated. When the voltage at the negative end of the load begins to drop, when the voltage at the negative end of the load is less than the lower offset of the current instantaneous reference value, VH=0, VL=1. At this time, the first clock signal CKI is valid. After the third signal VH and the fourth signal VL are operated by the logic circuit, the fourth signal VL branch is no longer output. The pull-up signal stops counting, the third signal VH branch outputs a pulse, and the control register saves the instantaneous reference value at this time as the peak reference value through the register. When the negative terminal voltage of the load is between the upper and lower offsets of the instantaneous reference value, VH=0, VL=0, and the first clock signal CKI is shielded, that is, counting stops. The peak reference value VPKREF is compared with the instantaneous reference value VDREF through the third comparator OP3. If the instantaneous reference value VDREF is not greater than the peak reference value VPKREF within 15ms, a pulse is output, and the control register saves the peak reference value VPKREF at this time as the voltage peak value VDPK.

[0039] Figure 4 FIG. 4 shows a schematic diagram of a voltage detection circuit according to an embodiment of the present application. Figure 4 As shown, the voltage detection circuit 102 includes a fourth comparator, wherein the first input terminal of the fourth comparator receives the negative terminal voltage of the load, and the second input terminal receives the voltage peak value VDPK recorded by the peak holding circuit in each cycle and shifted upward by a first threshold. As an example, the first threshold here is 200mV. Different application scenarios may have different threshold settings, which is not limited in the present application. The output terminal outputs a first signal to indicate that the load control circuit 103 responds quickly to the pull-up current.

[0040] Some examples of the voltage detection circuit of the embodiments of the present application are described above. However, the embodiments of the present application are not limited thereto, and there may be other expansions and deformations.

[0041] For example, it should be understood that the second input terminal of the voltage detection circuit can also be set to the voltage peak value VDPK recorded by the peak holding circuit. When it is detected that the voltage at the negative terminal of the load is higher than the voltage peak value for a certain period of time, it is determined that the dimming stroke of the system has changed from a small current to a large current. Therefore, the first signal output from the output terminal instructs the load control circuit 103 to quickly respond to the pull-up current to adapt to the system.

[0042] Figure 5 FIG. 4 shows a schematic diagram of a load control circuit according to an embodiment of the present application. Figure 5 As shown, the load control circuit 103 includes a reference voltage circuit, a fifth comparator, an integration circuit, a sixth comparator and a first switch tube, wherein the reference voltage circuit is configured to receive an input voltage and generate a reference voltage according to a formula based on the input voltage; the fifth comparator is configured to receive the load negative terminal voltage at the first input terminal, receive the reference voltage generated by the reference voltage circuit at the second input terminal, and output a second signal at the output terminal; the integration circuit is configured to include a capacitive device, the first terminal of the integration circuit is connected to the output terminal of the fifth comparator, and the second terminal is connected to the voltage detection circuit. Optionally, when the load negative terminal voltage is greater than the reference voltage, the second signal outputs a high level, outputs a first charging current to the capacitive device, and the voltage across the capacitive device increases instantaneously; when the load negative terminal voltage is less than the reference voltage, the second signal outputs a low level, outputs a second charging current to the capacitive device, and the instantaneous voltage across the capacitive device decreases; when the voltage detection circuit 102 detects that the load negative terminal voltage is greater than the first threshold of the voltage peak, it determines that the system is in the dimming process, that is, the first signal output High level, outputting a third charging current to the capacitive device. Compared with the first charging current and the second charging current, the third charging current has a larger current value, and can quickly charge the capacitive device. The sixth comparator is configured such that the first input terminal is connected to the capacitive device, and the second input terminal is grounded through a resistor; the first switch tube is configured such that the first polarity terminal is connected to the negative terminal of the load, the second polarity terminal is connected to the second input terminal of the sixth comparator, and the control terminal is connected to the output terminal of the sixth comparator. The voltage of the capacitive device can be considered to be stable, so that the source voltage of the first switch tube remains unchanged. The input voltage on the line is divided by the load and the drain-source voltage in the first switch tube, that is, the voltage on the load is DC, thereby eliminating the influence of ripple on the circuit. When it is determined that the system is in the dimming process, the first signal enables the third charging current to quickly charge the capacitive device, quickly pull up the gate voltage in the first switch tube, so that the current of the first switch tube responds quickly, prevents the drain voltage of the first switch tube from accumulating and damaging the switch tube, and also enables the current of the load to respond quickly, with a better dynamic tracking sense.

[0043] It should be understood that according to the control circuit of the LED load provided above, the peak information of the negative terminal voltage of the load is sampled cycle by cycle, and the instantaneous negative terminal voltage information of the load representing the size of the driving current is compared with the recorded peak information. When a large change in the driving current is detected, a signal is sent to make the circuit respond quickly to eliminate the ripple. According to this method, the control circuit of the LED load has a short response time and does not require peripheral components, so it is low in cost and more applicable.

[0044] Some examples of control circuits for LED loads according to embodiments of the present application are described above; however, embodiments of the present application are not limited thereto and may also be expanded and deformed in other ways.

[0045] For example, it should be understood that the reference ground potential in the aforementioned embodiments may be replaced by other non-zero reference potentials (having a positive voltage amplitude or a negative voltage amplitude) or a reference signal with a controlled variation in alternative embodiments.

[0046] For another example, the resistors and capacitors provided in the embodiments of the present application may be lumped parameter capacitor elements and resistor elements, or may be other equivalent elements with similar functions to capacitors and resistors. The equivalent structures described here may be, for example but not limited to, microstrip lines, varactors, conductor structures with certain patterns, and the like that may provide inductive impedance and / or capacitive impedance.

[0047] At the same time, those skilled in the art can realize that, in combination with the structures and methods of the various examples described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure, but such implementation should not be considered to be beyond the scope of the present application. In addition, it should be understood that the connection relationship between the various components of the amplifier in the aforementioned figure in the embodiments of the present application is a schematic example and does not impose any limitation on the embodiments of the present application.

[0048] Figure 6 The circuit structure diagram of the integrated chip embodiment of the present application is shown in FIG. Figure 6 As shown, the control circuit of the LED load as described above can be integrated into a chip, and the chip includes a first pin Vin, a second pin VD, and a third pin GND, wherein the first pin Vin receives the input voltage of the system, the second pin VD receives the negative terminal voltage of the load of the system, and the third pin GND is connected to the reference ground.

[0049] It can be understood that the integrated chip includes a peak holding circuit, which is configured to detect the instantaneous reference value of the negative terminal voltage of the load, set the falling critical value of the instantaneous reference value as the peak reference value, and select the maximum value of the peak reference value and the instantaneous reference value as the voltage peak within the first time window; the voltage detection circuit is configured to receive the voltage peak value, and output a first signal when detecting that the difference between the negative terminal voltage of the load and the voltage peak value exceeds a first threshold value; the load control circuit is configured to generate a second signal according to the negative terminal voltage of the load and the input voltage, and control the current of the LED load based on the first signal and the second signal, wherein the first signal is used to quickly respond to fluctuations in the negative terminal voltage of the load.

[0050] As an example, the input end of the peak holding circuit is connected to the second pin VD to receive the negative terminal voltage of the load, the input end of the voltage detection circuit is electrically connected to the output end of the peak holding circuit, the first input end of the load control circuit is connected to the first pin Vin to receive the input voltage, the second input end is connected to the output end of the voltage detection circuit for receiving the first signal, and the third end is connected to the third pin GND and is configured to be connected to the reference ground.

[0051] An example of a chip according to an embodiment of the present application is described above; however, the embodiment of the present application is not limited thereto, and other extensions and modifications may also exist.

[0052] For example, the control circuit of the LED load as described above can be partially or completely integrated into the chip. For example, the first switch tube can be integrated into the chip in the form of an embodiment of the present application, or it can be integrated outside the chip. The present application does not limit this.

[0053] It should be understood that the control circuit of the LED load of the present application samples the peak information of the load negative terminal voltage cycle by cycle, and compares the instantaneous load negative terminal voltage information representing the size of the driving current with the recorded peak information. When a large change in the driving current is detected, a signal is sent to make the circuit respond quickly to eliminate the ripple. When the control circuit of the LED load is integrated inside the chip, according to this method, there is no need for external capacitors or resistors for voltage division as in the prior art, and compared with the prior art, it saves more pins, that is, the present application saves peripheral components, has low cost, and is more applicable.

[0054] Figure 7 A schematic diagram of the structure of an embodiment of the lighting device of the present application is shown in FIG. Figure 7 As shown, the lighting device includes an LED driving circuit, which is configured to generate a driving current, and the driving current generates an input voltage through a large capacitor C01; an LED light string, which is configured to receive the driving current and be lit; as the chip described above, the first pin of the chip is connected to the system bus to receive the input voltage, the second pin VD is connected to the negative end of the LED light string to receive the input voltage, and the third pin GND is grounded to the system.

[0055] The LED light string may be one LED light, or may be an LED light string formed by connecting at least two LED lights in series and / or in parallel. It should also be noted that although the above embodiments are described using LED lights as an example, the technical solution of the present application is not limited to LED lights, but may also be any other suitable load, such as a DC motor.

[0056] The present application also provides a control method for an LED load, comprising: detecting an instantaneous reference value of the negative terminal voltage of the LED load, setting a decreasing critical value of the instantaneous reference value as a peak reference value, and selecting a maximum value of the peak reference value and the instantaneous reference value as a voltage peak value within a first time window; receiving the voltage peak value, and outputting a first signal when detecting that a difference between the negative terminal voltage of the load and the voltage peak value exceeds a first threshold value; generating a second signal according to the negative terminal voltage of the load and an input voltage, and controlling the current of the LED load according to the first signal and the second signal, wherein the first signal is used to quickly respond to fluctuations in the negative terminal voltage of the load.

[0057] Optionally, the instantaneous reference value of the negative terminal voltage of the LED load is detected, the falling critical value of the instantaneous reference value is set as the peak reference value, and within a first time window, the maximum value of the peak reference value and the instantaneous reference value is selected as the voltage peak value, including: when no larger instantaneous reference value is detected within the first time window, the peak reference value is saved as the voltage peak value; otherwise, the peak reference value is cleared, the falling critical value of the instantaneous reference value is resampled and set as the peak reference value; the peak reference value is output as the voltage peak value.

[0058] Optionally, the method includes: receiving the load negative terminal voltage and generating the instantaneous reference value of the load negative terminal voltage; shifting the instantaneous reference value up and down by the same amount to generate an upper instantaneous reference value and a lower instantaneous reference value; comparing the current load negative terminal voltage with the upper instantaneous reference value to generate a third signal, and comparing with the lower instantaneous reference value to generate a fourth signal; outputting the first clock signal according to the third signal and the fourth signal; when the first clock signal is valid, the third signal and the fourth signal are subjected to logical operation, and the instantaneous reference value is counted and updated, and the falling critical point of the instantaneous reference value is saved as the peak reference value; when the first clock signal is invalid, counting is stopped.

[0059] Optionally, the method includes: comparing the peak reference value with the instantaneous reference value, and outputting a pulse signal when the instantaneous reference value does not exceed the peak reference value within the first time window; and outputting the peak reference value as the voltage peak value according to the pulse signal.

[0060] Optionally, when the third signal and the fourth signal are both at a low level, the first clock signal is invalid.

[0061] Optionally, the method also includes: controlling the voltage across the capacitive device according to the second signal to eliminate the ripple of the driving current, and when the second signal outputs a high level, outputting a first charging current to the capacitive device; when the first signal is output, outputting a third charging current to the capacitive device, and the current value of the third charging current is greater than the current value of the first charging current.

[0062] Optionally, the eliminating the ripple of the driving current according to the load negative terminal voltage and the input voltage includes: receiving the input voltage and generating a reference voltage according to the input voltage; and outputting the second signal after comparing the reference voltage with the load negative terminal voltage. Any range or device value given herein can be expanded or changed without losing the effect sought. In addition, any embodiment can be combined with another embodiment that is not explicitly prohibited.

[0063] Although the subject matter has been described in language specific to structural features and / or acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Instead, the specific features and acts described above are disclosed as examples of implementing the claims, and other equivalent features and acts are intended to fall within the scope of the claims.

[0064] It should be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to embodiments that solve any or all of the problems described, or embodiments that have any or all of the benefits and advantages described. It should also be understood that reference to "an" item may refer to one or more of those items.

[0065] The steps of the methods described herein may be performed in any suitable order, or simultaneously where appropriate. In addition, individual blocks may be deleted from any method without departing from the spirit and scope of the subject matter described herein. Aspects of any of the above embodiments may be combined with aspects of any other embodiment described to form further embodiments without losing the effects sought.

[0066] The terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0067] It should be understood that the above description is given as an example only, and various modifications may be made by those skilled in the art. The above description, examples and data provide a complete description of the structure and use of the exemplary embodiments. Although various embodiments with a certain degree of particularity have been described above, or with reference to one or more separate embodiments, those skilled in the art may make various changes to the disclosed embodiments without departing from the spirit or scope of this specification.

Claims

1. A method for controlling an LED load, characterized in that: include: Detecting an instantaneous reference value of the negative terminal voltage of the LED load, setting a decreasing critical value of the instantaneous reference value as a peak reference value, and selecting a maximum value of the peak reference value and the instantaneous reference value as a voltage peak value within a first time window; receiving the voltage peak value, and outputting a first signal when detecting that the difference between the load negative terminal voltage and the voltage peak value exceeds a first threshold value, wherein the first signal is used to quickly respond to fluctuations in the load negative terminal voltage; Generating a second signal according to the load negative terminal voltage and the input voltage, wherein the load negative terminal voltage is compared with a reference voltage to output a second signal of a different level; The current of the LED load is controlled according to the first signal and the second signal, wherein the voltage across the capacitive device is controlled according to the second signal to eliminate the ripple of the driving current, and when the second signal outputs a high level, the first charging current is output to the capacitive device, and when the second signal outputs a low level, the second charging current is output to the capacitive device; when the first signal outputs a high level, the third charging current is output to the capacitive device.

2. The method for controlling an LED load according to claim 1, characterized in that: The detecting of the instantaneous reference value of the negative terminal voltage of the LED load, setting the falling critical value of the instantaneous reference value as the peak reference value, and selecting the maximum value of the peak reference value and the instantaneous reference value as the voltage peak value within the first time window includes: When no greater instantaneous reference value is detected within the first time window, saving the peak reference value as the voltage peak value; Otherwise, the peak reference value is cleared, and the falling critical value of the instantaneous reference value is resampled and set as the peak reference value; The peak reference value is output as the voltage peak value.

3. The method for controlling an LED load according to claim 2, characterized in that: The method comprises: Receiving the load negative terminal voltage and generating the instantaneous reference value of the load negative terminal voltage; The instantaneous reference value is shifted up and down by a set amount to generate an upper instantaneous reference value and a lower instantaneous reference value; Compare the current voltage at the negative terminal of the load with the upper instantaneous reference value to generate a third signal, and compare it with the lower instantaneous reference value to generate a fourth signal; Outputting a first clock signal according to the third signal and the fourth signal; When the first clock signal is valid, the third signal and the fourth signal are logically operated to count and update the instantaneous reference value, and the falling critical point of the instantaneous reference value is saved as the peak reference value; when the first clock signal is invalid, counting is stopped.

4. The method for controlling an LED load according to claim 2, characterized in that: include: Comparing the peak reference value with the instantaneous reference value, and outputting a pulse signal when the instantaneous reference value does not exceed the peak reference value within the first time window; According to the pulse signal, the peak reference value is output as the voltage peak value.

5. The method for controlling an LED load according to claim 3, characterized in that: When the third signal and the fourth signal are both at low levels, the first clock signal is invalid.

6. The method for controlling an LED load according to claim 1, characterized in that: A current value of the third charging current is greater than a current value of the first charging current.

7. The method for controlling an LED load according to claim 6, characterized in that: The generating a second signal according to the load negative terminal voltage and the input voltage comprises: receiving the input voltage and generating a reference voltage according to the input voltage; The second signal is output after comparing the reference voltage with the load negative terminal voltage.

8. An integrated chip for controlling LED loads, characterized in that: include: A control circuit of an LED load, wherein the control circuit of the LED load is integrated inside the chip, and the control circuit of the LED load comprises: A peak hold circuit is configured to detect an instantaneous reference value of a voltage at a negative terminal of a load, set a falling critical value of the instantaneous reference value as a peak reference value, and select a maximum value of the peak reference value and the instantaneous reference value as a voltage peak value within a first time window; A voltage detection circuit is configured to receive the voltage peak value, and output a first signal when detecting that the difference between the load negative terminal voltage and the voltage peak value exceeds a first threshold value, wherein the first signal is used to quickly respond to fluctuations in the load negative terminal voltage; A load control circuit is configured to generate a second signal according to the load negative terminal voltage and the input voltage, wherein the load negative terminal voltage is compared with a reference voltage to output a second signal of a different level; the current of the LED load is controlled according to the first signal and the second signal, wherein the voltage across the capacitive device is controlled according to the second signal to eliminate the ripple of the driving current, when the second signal outputs a high level, a first charging current is output to the capacitive device, and when the second signal outputs a low level, a second charging current is output to the capacitive device; when the first signal outputs a high level, a third charging current is output to the capacitive device.

9. The integrated chip according to claim 8, characterized in that: The integrated chip further includes: a first pin configured to be connected to an input voltage; a second pin configured to be connected to a negative end of a load to receive a voltage at the negative end of the load; and a third pin configured to be connected to a reference ground.

10. The integrated chip according to claim 9, characterized in that: The input end of the peak holding circuit is connected to the second pin to receive the negative terminal voltage of the load, the input end of the voltage detection circuit is electrically connected to the output end of the peak holding circuit, the first input end of the load control circuit is connected to the first pin to receive the input voltage, the second input end is connected to the output end of the voltage detection circuit to receive the first signal, and the third end is connected to the third pin and is configured to be connected to the reference ground.

11. The integrated chip according to claim 8, characterized in that: The peak hold circuit comprises: A first comparator is configured to receive the upward offset of the instantaneous reference value at a first input terminal, receive the negative terminal voltage of the load at a second input terminal, and output a third signal at an output terminal; A second comparator is configured to receive the load negative terminal voltage at a first input terminal, receive the instantaneous reference value downward shift at a second input terminal, and output a fourth signal at an output terminal; Oscillator, which generates the raw clock signal; A clock logic circuit receives the original clock signal, the third signal and the fourth signal, and generates a first clock signal. Wherein, when the first clock signal is valid, the third signal and the fourth signal are counted and saved as the instantaneous reference value after logical operation, and the falling critical point of the instantaneous reference value is saved as the peak reference value, and when the first clock signal is invalid, the counting is stopped; A third comparator is configured to receive the peak reference value at a first input terminal and the instantaneous reference value at a second input terminal, and output a fifth signal. When the instantaneous reference value exceeds the peak reference value, the fifth signal is output; when the peak holding circuit does not receive the fifth signal within the first time window, the peak reference value is stored as the voltage peak value.

12. The integrated chip according to claim 8, characterized in that: The load control circuit comprises: a reference voltage circuit configured to receive the input voltage and generate a reference voltage according to the input voltage; A fifth comparator, configured to receive the load negative terminal voltage at a first input terminal, receive the reference voltage at a second input terminal, and output a second signal at an output terminal; An integration circuit is configured to include a capacitive device, wherein a first end of the integration circuit is connected to the output end of the fifth comparator, and a second end of the integration circuit is connected to the voltage detection circuit, and when the second signal outputs a high level, a first charging current is output to the capacitive device; when the second signal outputs a low level, a second charging current is output to the capacitive device; when the first signal outputs a high level, a third charging current is output to the capacitive device; a sixth comparator, configured such that a first input terminal is connected to the capacitive device, and a second input terminal is grounded via a resistor; The first switch tube is configured such that a first polarity end is connected to the negative end of the load, a second polarity end is connected to the second input end of the sixth comparator, and a control end is connected to the output end of the sixth comparator.

13. A lighting device, characterized in that: include: The LED driving circuit is configured to generate a driving current; The LED light string is configured to receive the driving current and be illuminated; The integrated chip as described in claims 8-12, wherein the integrated chip is electrically connected to the LED light string.

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