Semiconductor structure manufacturing method and semiconductor structure

Abstract

The embodiment of the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, the manufacturing method comprising: providing a substrate, wherein the substrate has an electrical contact layer; forming an insulating layer on the substrate, wherein the insulating layer has a through hole penetrating the insulating layer, and the through hole exposes the surface of the electrical contact layer; forming a sidewall layer on the sidewall of the through hole; forming a first isolation layer, wherein the first isolation layer covers the surface of the sidewall layer and the exposed surface of the insulating layer; removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; forming a conductive layer filling the through hole, wherein the conductive layer is electrically connected to the electrical contact layer. The method for manufacturing a semiconductor structure provided by the embodiment of the present invention can effectively reduce the parasitic capacitance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of semiconductor manufacturing technology, the feature size of semiconductor processes has been reduced to the deep submicron level. As the feature size continues to shrink, the distance between interconnects in semiconductor structures is getting closer and closer, and parasitic capacitance is also increasing. Parasitic capacitance will seriously affect the performance of semiconductor structures, especially reducing the operating speed and reliability of semiconductor structures.

[0003] Therefore, how to reduce the parasitic capacitance within the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present invention provide a method for manufacturing a semiconductor structure and a semiconductor structure to reduce parasitic capacitance in the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, wherein the substrate has an electrical contact layer; forming an insulating layer on the substrate, wherein the insulating layer has a through hole penetrating the insulating layer, and the through hole exposes the surface of the electrical contact layer; forming a sidewall layer on the sidewall of the through hole; forming a first isolation layer, wherein the first isolation layer covers the surface of the sidewall layer and the exposed surface of the insulating layer; removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; and forming a conductive layer filling the through hole, wherein the conductive layer is electrically connected to the electrical contact layer.

[0006] In addition, the method for removing the sidewall layer includes: providing a plasma source, wherein the ion beam generated by the plasma source reacts with the sidewall layer after passing through the first isolation layer to form reaction by-products, and at least part of the reaction by-products is discharged through the first isolation layer.

[0007] In addition, the process step of removing the sidewall layer includes: generating the ion beam based on an oxygen plasma source, the oxygen flow rate is 100 sccm-600 sccm, and the radio frequency power is 500W-1000W.

[0008] In addition, the material of the spacer layer includes: amorphous carbon, hydrocarbon or polymer.

[0009] In addition, the top surface of the side wall layer is lower than the top surface of the insulating layer; the step of forming the side wall layer includes: forming an initial side wall layer on the surface of the insulating layer and the bottom of the through hole; removing the initial side wall layer located at the bottom of the through hole and the top surface of the insulating layer, and also removing part of the initial side wall layer located on the side wall of the through hole, and the remaining initial side wall layer serves as the side wall layer.

[0010] In addition, in a direction perpendicular to the surface of the substrate, a ratio of a height of the spacer layer to a height of the insulating layer is greater than or equal to 0.3.

[0011] In addition, after removing the sidewall layer and before forming the conductive layer, the method further includes forming a second isolation layer on the surface of the first isolation layer, wherein the density of the second isolation layer is greater than the density of the first isolation layer.

[0012] In addition, the material of the second isolation layer includes silicon dioxide or silicon nitride.

[0013] In addition, after the conductive layer is formed, the method further includes a step of planarization to remove a portion of the conductive layer, a portion of the insulating layer, a portion of the first isolation layer, and a portion of the second isolation layer that are higher than the gap.

[0014] In addition, the method for forming the first isolation layer includes: a low temperature atomic layer deposition process.

[0015] In addition, the material of the first isolation layer includes silicon dioxide or silicon-oxygen-hydrocarbon.

[0016] In addition, before the step of forming a conductive layer filling the through hole, the step also includes: removing the first isolation layer and the second isolation layer located at the bottom of the through hole and the top surface of the insulating layer; and depositing a barrier layer covering the sidewalls of the through hole.

[0017] An embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, wherein the substrate has an electrical contact layer; an insulating layer located on the substrate, wherein the insulating layer has a conductive layer, and the conductive layer is electrically connected to the electrical contact layer; a first isolation layer located between the insulating layer and the conductive layer, wherein the first isolation layer is also located on a portion of the side wall of the insulating layer, wherein a gap is formed between the insulating layer and the first isolation layer, and the first isolation layer seals the gap.

[0018] In addition, the invention also includes: a second isolation layer located between the first isolation layer and the conductive layer, and the density of the second isolation layer is greater than the density of the first isolation layer.

[0019] In addition, it also includes: a barrier layer located between the first isolation layer and the conductive layer, and the barrier layer also covers the surface of the electrical contact layer.

[0020] In addition, the first isolation layer and the second isolation layer are both located on the substrate outside the electrical contact layer and expose the entire surface of the electrical contact layer.

[0021] In addition, in a direction perpendicular to the surface of the substrate, a ratio of a height of the gap to a height of the insulating layer is greater than or equal to 0.3.

[0022] In addition, in a direction parallel to the surface of the substrate, a thickness ratio of the second isolation layer to the first isolation layer is 1.5:1 to 3:1.

[0023] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0024] In the semiconductor structure manufacturing method provided by the embodiment of the present invention, a first isolation layer covering the surface of the sidewall layer is formed, that is, the first isolation layer also covers the top of the sidewall layer; after the sidewall layer is removed to form a gap, since the first isolation layer completely seals the gap, there is no need to seal the gap; thereby, it is possible to avoid the formation of a deposition layer in the gap during the sealing process, or to avoid the occurrence of loose sealing, etc.; and thus, the parasitic capacitance of the semiconductor structure can be effectively reduced.

[0025] In addition, the method for removing the sidewall layer includes: providing a plasma source, the ion beam generated by the plasma source reacts with the sidewall layer after passing through the first isolation layer to form reaction byproducts, and at least part of the reaction byproducts is discharged through the first isolation layer. Compared with the wet process, this method has less residue and can remove the sidewall layer more thoroughly. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0027] Figure 1-Figure 11 A schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As can be seen from the background technology, the parasitic capacitance in the semiconductor structure needs to be further reduced. The method of reducing the parasitic capacitance may include: forming a sacrificial layer between the adjacent conductive layer and the insulating layer, removing the sacrificial layer to form a gap, and sealing the gap. Since there is air in the gap, and the dielectric constant of air is small, the parasitic capacitance can be reduced. In the process step of sealing the gap, part of the reaction gas will enter the gap and form a deposition layer at the bottom of the gap, thereby reducing the volume of the gap. In addition, if the sealing is not strict, the conductive material will easily enter the gap during the subsequent deposition of the conductive material, thereby causing electrical conduction between the interconnects that should be isolated from each other. Therefore, the above method is less effective in reducing the parasitic capacitance and may also affect the yield of the semiconductor structure.

[0029] In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, the method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having an electrical contact layer; forming an insulating layer on the substrate, the insulating layer having a through hole penetrating the insulating layer, and the through hole exposing the surface of the electrical contact layer; forming a sidewall layer on the sidewall of the through hole; forming a first isolation layer, the first isolation layer covering the surface of the sidewall layer and the exposed surface of the insulating layer; removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; forming a conductive layer filling the through hole, the conductive layer being electrically connected to the electrical contact layer. Since the first isolation layer covers the entire surface of the sidewall layer, the gap formed after removing the sidewall layer is completely surrounded by the first isolation layer, and no sealing is required, thereby ensuring that the parasitic capacitance can be reduced to a large extent and the yield of the semiconductor structure is improved.

[0030] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0031] Figure 1-Figure 11 The schematic diagram of the structure corresponding to each step in the method for manufacturing a semiconductor structure provided by the first embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0032] refer to Figure 1 A substrate 100 is provided, and an electrical contact layer 101 is provided in the substrate 100. The substrate 100 may include structures such as word lines, bit lines, source and drain electrodes, etc. The material of the substrate 100 may include silicon, sapphire, silicon carbide, gallium arsenide, aluminum nitride, or zinc oxide silicon, etc.

[0033] The electrical contact layer 101 is used to realize the electrical connection between the structure inside the substrate 100 and the subsequently formed conductive layer. In one example, the subsequently formed conductive layer can be electrically connected to the bit line inside the substrate 100 through the electrical contact layer. In this embodiment, the material of the electrical contact layer 101 is copper. In other embodiments, the material of the electrical contact layer can also be a conductive material such as polysilicon, tungsten or titanium.

[0034] In this embodiment, the substrate 100 further has an isolation structure 102, and the isolation structure 102 is used to isolate the adjacent electrical contact layer 101. In this embodiment, the material of the isolation structure 102 is silicon oxide. In other embodiments, the material of the isolation structure can also be an insulating material such as silicon carbide or silicon nitride.

[0035] refer to Figure 1-Figure 2 , an insulating layer 103 is formed on a substrate 100 , wherein the insulating layer 103 has a through hole 110 penetrating the insulating layer 103 , and the through hole 110 exposes a surface of the electrical contact layer 101 .

[0036] The insulating layer 103 is used to isolate a conductive layer that is subsequently formed in the through hole 110 .

[0037] The insulating layer 103 is located on the isolation structure 102, and in the direction parallel to the surface of the substrate 100, the width of the insulating layer 103 is smaller than the width of the isolation structure 102. The main reason is that: a gap, a first isolation layer and a second isolation layer will be formed on the side wall of the insulating layer 103 later, and the width of the insulating layer 103 is smaller than the width of the isolation structure 102. When the width difference satisfies a certain range of values, the gap, the first isolation layer and the second isolation layer can face the isolation structure 102, thereby exposing the entire surface of the electrical contact layer 101, so as to increase the contact area between the subsequently formed conductive layer and the electrical contact layer 101, thereby reducing the contact resistance.

[0038] The width of the insulating layer 103 is greater than or equal to one half of the width of the isolation structure 102, and less than or equal to the width of the isolation structure 102. When the width of the insulating layer 103 is within the above range, it has a good supporting effect on the first isolation layer and the second isolation layer formed subsequently, and can improve the stability of the semiconductor structure; and it can also reserve enough space for the gap, the first isolation layer and the second isolation layer formed subsequently, so that the gap, the first isolation layer and the second isolation layer can be located on the isolation structure 102, and the entire surface of the electrical contact layer 101 is exposed, so as to increase the contact area between the conductive layer formed subsequently and the electrical contact layer 101.

[0039] In this embodiment, the material of the insulating layer 103 is the same as the material of the isolation structure 102. The insulating layer 103 and the isolation structure 102 are made of the same material, which can improve the tightness of the two fittings, thereby improving the stability of the semiconductor structure. For example, the material of the insulating layer 103 and the material of the isolation structure 102 are both silicon dioxide. In other embodiments, the material of the insulating layer and the material of the isolation layer may also be different, for example, they may be insulating materials such as silicon carbide or silicon nitride.

[0040] Specifically, the process steps for forming the insulating layer 103 and the through hole 110 include: Figure 1 , forming an initial insulating layer 103a on the substrate 100, and forming a patterned photoresist layer 104 on the initial insulating layer 103a; referring to Figure 2 , with the patterned photoresist layer 104 (reference Figure 1 ) is used as a mask to etch the initial insulating layer 103a (reference Figure 1 ) to form an insulating layer 103.

[0041] In this embodiment, the initial insulating layer 103 a is formed by a chemical vapor deposition process. The deposition rate of the chemical vapor deposition process is relatively fast, and the process time can be shortened.

[0042] In this embodiment, the initial insulating layer 103 a is etched by dry etching until the electrical contact layer 101 is exposed, so as to form the insulating layer 103 and the through hole 110 exposing the electrical contact layer 101 .

[0043] refer to Figure 3-Figure 4 , a spacer layer 105 is formed on the sidewall of the through hole 110 .

[0044] The spacer layer 105 is used to occupy a space position for the gap to be formed subsequently, that is, the position where the spacer layer 105 is located is the position of the gap to be formed subsequently.

[0045] The material of the spacer layer 105 needs to be easy to decompose, so that in the subsequent process of removing the spacer layer 105 to form a gap, under the action of oxygen plasma, the spacer layer 105 can be discharged in the form of gas after decomposition. The material of the spacer layer 105 includes amorphous carbon, hydrocarbons or polymers, such as C x H y .

[0046] In this embodiment, in the direction perpendicular to the surface of the substrate 100, the ratio of the height of the spacer layer 105 to the height of the insulating layer 103 is greater than or equal to 0.3. That is, the top surface of the spacer layer 105 can be flush with the top surface of the insulating layer 103 or lower than the top surface of the insulating layer 103.

[0047] When the ratio of the height of the spacer layer 105 to the height of the insulating layer 103 is greater than or equal to 0.3, the height of the spacer layer 105 is high, and the height of the gap formed subsequently is also high, thereby being able to reduce parasitic capacitance to a greater extent.

[0048] Preferably, the top surface of the spacer layer 105 is lower than the top surface of the insulating layer 103, and the ratio of the height of the spacer layer 105 to the height of the insulating layer 103 is less than or equal to 0.8. In this way, the first isolation layer formed subsequently can be located on the side wall of the insulating layer 103 exposed by the spacer layer 105, that is, the first isolation layer formed subsequently can be well supported by the side wall of the insulating layer 103, so that it is not easy to collapse and has good stability.

[0049] The steps of forming the spacer layer 105 will be described in detail below.

[0050] refer to Figure 3 , an initial spacer layer 105a is formed on the surface of the insulating layer 103 and the bottom of the through hole 110. In this embodiment, the initial spacer layer 105a is formed by an atomic layer deposition process. The initial spacer layer formed by the atomic layer deposition process has a relatively uniform thickness. In other embodiments, the initial spacer layer can also be formed by a chemical vapor deposition process or a physical vapor deposition process.

[0051] refer to Figure 4 , remove the initial spacer layer 105a located at the bottom of the through hole 110 and the top surface of the insulating layer 103 (refer to Figure 3 ), a portion of the initial spacer layer 105 a located on the side wall of the through hole 110 is also removed, and the remaining initial spacer layer 105 a serves as the spacer layer 105.

[0052] That is, the top surface of the spacer layer 105 is lower than the top surface of the insulating layer 103, so that the first isolation layer formed subsequently also covers the sidewall of the insulating layer 103 exposed by the spacer layer 105. In this way, after removing the spacer layer, the first isolation layer has good stability because it is still supported by the sidewall of the insulating layer.

[0053] In other embodiments, the initial spacer layer on the sidewall of the through hole may not be removed, that is, the top surface of the formed spacer layer is flush with the top surface of the insulating layer, and the subsequently formed first isolation layer does not cover the sidewall of the insulating layer.

[0054] In this embodiment, dry etching is used to remove part of the initial insulating layer 105a (refer to Figure 3 ).

[0055] refer to Figure 5 , forming a first isolation layer 106 , the first isolation layer 106 covers the surface of the spacer layer 105 and the exposed surface of the insulating layer 103 .

[0056] Compared with the sidewall layer 105 , the first isolation layer 106 needs to meet the characteristic of being difficult to decompose. Thus, in the subsequent process of removing the sidewall layer 105 , the first isolation layer 106 is not easily damaged and has better stability.

[0057] In addition, the thickness of the first isolation layer 106 is relatively small, for example, less than 3 nm, so that the ion beam can more easily pass through the first isolation layer 106 and remove the spacer layer 105 .

[0058] In addition, the first isolation layer 106 has pores, so that the ion beam passes directly through the pores, thereby removing the sidewall layer 105 more thoroughly.

[0059] In this embodiment, the material of the first isolation layer 106 is silicon dioxide. In other embodiments, the material of the first isolation layer may also be silicon-oxygen hydrocarbons. Silicon dioxide or silicon-oxygen hydrocarbons are not easily decomposed under the action of oxygen plasma and have good stability.

[0060] In this embodiment, a low temperature atomic layer deposition process is used to form the first isolation layer 106. In this way, a first isolation layer 106 with a relatively thin thickness can be formed, making it easier to remove the sidewall layer 105 completely covered by the first isolation layer 106 later. The temperature range of the low temperature atomic layer deposition process is a low temperature range of 50°C-135°C. The low temperature atomic layer deposition process can more accurately control the thickness of the first isolation layer 106 to obtain a homogeneous thin first isolation layer 106, and the first isolation layer 106 will have the characteristics of a flatter surface.

[0061] refer to Figure 6 , remove the sidewall layer 105 (reference Figure 5 ), forming a gap 107 between the first isolation layer 106 and the insulating layer 103.

[0062] Remove the sidewall layer 105 (reference Figure 5 ) includes: providing a plasma source, the ion beam generated by the plasma source reacts with the spacer layer 105 after passing through the first isolation layer 106 to form reaction by-products, and at least part of the reaction by-products are discharged through the first isolation layer 106. Compared with the wet process, when the spacer layer 105 is removed by the above method, less residues are left and the cleanliness is higher.

[0063] In this embodiment, oxygen is used as a plasma source, and the process steps for removing the sidewall layer 105 include: generating an ion beam based on the oxygen plasma source, the ion beam passes through the first isolation layer 106 through the pores on the first isolation layer 106, and contacts the sidewall layer 105 (refer to Figure 5) reacts, the sidewall layer 105 is thermally decomposed, thereby generating reaction by-products such as carbon dioxide, carbon monoxide, water and methane. Gases such as carbon dioxide, carbon monoxide, water and methane can be discharged through the pores on the first isolation layer 106.

[0064] The oxygen flow rate is 100sccm-600sccm. When the oxygen flow rate is within the above range, oxygen can react more fully with the material of the sidewall layer 105, so that the sidewall layer 105 can be removed more thoroughly; and it can avoid causing greater damage to the first isolation layer 106, ensuring that the first isolation layer 106 has higher stability.

[0065] The RF power is 500 W-1000 W. When the RF power is within the above range, the ion beam has sufficient energy to remove the sidewall layer 105 more thoroughly, and can also avoid causing greater damage to the first isolation layer 106, ensuring that the first isolation layer 106 has higher stability.

[0066] refer to Figure 7 A second isolation layer 108 is formed on the surface of the first isolation layer 106 , and the density of the second isolation layer 108 is greater than the density of the first isolation layer 106 .

[0067] It can be understood that in order to allow more ion beams to pass through the first isolation layer 106 and thereby make the removal of the side wall layer 105 more thorough, the density of the first isolation layer 106 is relatively low; after removing the side wall layer 105, a second isolation layer 108 with a higher density is formed on the surface of the first isolation layer 106, which can improve the density of the first isolation layer 106 and thereby improve the firmness and stability of the first isolation layer 106.

[0068] The thickness of the second isolation layer 108 is greater than that of the first isolation layer 106, which can further improve the firmness of the first isolation layer 106. Preferably, the thickness ratio of the second isolation layer 108 to the first isolation layer 106 is 1.5:1 to 3:1. When the thickness ratio of the second isolation layer 108 to the first isolation layer 106 is within the above range, the second isolation layer 108 can play a good reinforcement role on the first isolation layer 106. In addition, the second isolation layer 108 can occupy a more reasonable area on the isolation structure 102, so that the second isolation layer 108 can completely expose the surface of the electrical contact layer 101 to increase the contact area between the electrical contact layer 101 and the conductive layer formed subsequently.

[0069] In this embodiment, the material of the second isolation layer 108 is the same as that of the first isolation layer 106, so that the second isolation layer 108 and the first isolation layer 106 can be more closely attached, thereby further improving the reinforcement effect of the second isolation layer 108. For example, the material of the second isolation layer 108 and the material of the first isolation layer 106 are both silicon dioxide. In other embodiments, the material of the second isolation layer can also be different from that of the first isolation layer, such as silicon nitride.

[0070] The second isolation layer 108 is formed by an atomic layer deposition process or a chemical vapor deposition process with good step coverage.

[0071] refer to Figure 8 , remove the first isolation layer 106 and the second isolation layer 108 located at the bottom of the through hole 110 and the top surface of the insulating layer 103.

[0072] In this embodiment, a dry etching method is used to remove a portion of the first isolation layer 106 and the second isolation layer 108 .

[0073] After partially removing the first isolation layer 106 and the second isolation layer 108 , the remaining first isolation layer 106 and the second isolation layer 108 expose the entire surface of the electrical contact layer 101 , thereby increasing the contact area between the subsequently formed conductive layer and the electrical contact layer 101 and reducing the contact resistance.

[0074] In other embodiments, the remaining first isolation layer and the second isolation layer may only expose a portion of the surface of the electrical contact layer.

[0075] refer to Fig. 9 , a barrier layer 109 is deposited to cover the sidewalls of the through hole 110 .

[0076] The barrier layer 109 is used to prevent the mutual diffusion of atoms in the subsequently formed conductive layer and atoms in the second isolation layer 108, and can also increase the adhesion between the conductive layer and the second isolation layer 108, thereby improving the stability and firmness of the subsequently formed conductive layer.

[0077] In this embodiment, the barrier layer 109 is also located at the bottom of the through hole 110. The barrier layer 109 can also block the mutual diffusion of atoms in the subsequently formed conductive layer and the atoms in the electrical contact layer 101, and can also increase the adhesion between the conductive layer and the electrical contact layer 101.

[0078] The material of the barrier layer 109 includes tantalum, tantalum nitride, ruthenium or rhenium.

[0079] In this embodiment, the barrier layer 109 is formed by an atomic layer deposition process.

[0080] refer to Fig.10 , forming a filled through hole 110 (refer to Fig. 9 ), the conductive layer 111 is electrically connected to the electrical contact layer 101. The conductive layer 111 is also higher than the top of the insulating layer 103.

[0081] The conductive layer 111 serves as an interconnection line in the semiconductor structure, connecting the structures in the substrate 100 according to design requirements to achieve specific functions.

[0082] In this embodiment, the material of the conductive layer 111 is copper, gold, silver, titanium or tungsten.

[0083] In this embodiment, a chemical vapor deposition process is used to form the conductive layer 111. In other embodiments, a physical vapor deposition process may also be used to form the conductive layer.

[0084] refer to Fig.11 , a planarization process is performed to remove a portion of the conductive layer 111 , a portion of the insulating layer 103 , a portion of the first isolation layer 106 , and a portion of the second isolation layer 108 above the gap 107 .

[0085] It is worth noting that during the planarization process, the process should be stopped at a position higher than the gap 107 to ensure that the gap 107 is still in a sealed state.

[0086] In this embodiment, the planarization process is performed by chemical mechanical polishing.

[0087] In other embodiments, if the formed gap is located on the entire side wall of the insulating layer, that is, in the direction perpendicular to the substrate surface, the height of the gap is the same as the height of the insulating layer, then during the planarization process, in order to ensure the sealing of the gap, only the conductive layer higher than the gap can be removed, while the insulating layer, the first isolation layer, the second isolation layer and the blocking layer are retained.

[0088] In summary, in this embodiment, the spacer layer covered by the first isolation layer is removed by plasma process to form a gap, which no longer requires a sealing process step, so that the gap has a larger volume and stability, and can effectively reduce the parasitic capacitance of the semiconductor structure.

[0089] A second embodiment of the present invention provides a semiconductor structure. Fig.11 A schematic diagram of a semiconductor structure provided by a second embodiment of the present invention, referring to Fig.11The semiconductor structure includes: a substrate 100, wherein the substrate 100 has an electrical contact layer 101; an insulating layer 103 located on the substrate 100, wherein the insulating layer 103 has a conductive layer 111, and the conductive layer 111 is electrically connected to the electrical contact layer 101; a first isolation layer 106 located between the insulating layer 103 and the conductive layer 111, wherein the first isolation layer 106 is also located on a portion of the side wall of the insulating layer 103, wherein a gap 107 is provided between the insulating layer 103 and the first isolation layer 106, and the first isolation layer 106 seals the gap 107.

[0090] The following is a detailed description with reference to the accompanying drawings.

[0091] refer to Fig.11 The substrate 100 may include structures such as word lines, bit lines, source and drain electrodes, etc. The material of the substrate 100 may include silicon, sapphire, silicon carbide, gallium arsenide, aluminum nitride, or zinc oxide silicon, etc.

[0092] The electrical contact layer 101 is used to realize electrical connection between the structure inside the substrate 100 and the conductive layer 111. In one example, the conductive layer 111 can be electrically connected to the bit line inside the substrate 100 through the electrical contact layer 101. In this embodiment, the material of the electrical contact layer 101 is copper. In other embodiments, the material of the electrical contact layer can also be a conductive material such as polysilicon, tungsten or titanium.

[0093] The substrate 100 also has an isolation structure 102, which is used to isolate the adjacent electrical contact layer 101. In this embodiment, the isolation structure 102 is made of silicon oxide. In other embodiments, the isolation structure may also be made of insulating materials such as silicon carbide or silicon nitride.

[0094] The insulating layer 103 is used to isolate adjacent conductive layers 111 .

[0095] The insulating layer 103 is located on the isolation structure 102, and in the direction parallel to the surface of the substrate 100, the width of the insulating layer 103 is smaller than the width of the isolation structure 102. The main reason is that: a gap, a first isolation layer and a second isolation layer will be formed on the side wall of the insulating layer 103 later, and the width of the insulating layer 103 is smaller than the width of the isolation structure 102. When the width difference satisfies a certain range of values, the gap, the first isolation layer and the second isolation layer can face the isolation structure 102, thereby exposing the entire surface of the electrical contact layer 101, so as to increase the contact area between the subsequently formed conductive layer and the electrical contact layer 101, thereby reducing the contact resistance.

[0096] The width of the insulating layer 103 is greater than or equal to one half of the width of the isolation structure 102, and less than or equal to the width of the isolation structure 102. When the width of the insulating layer 103 is within the above range, it has a good supporting effect on the first isolation layer 106 and the second isolation layer 108, which can improve the stability of the semiconductor structure; and it can also reserve enough space for the gap 107, the first isolation layer 106 and the second isolation layer 108, so that the gap 107, the first isolation layer 106 and the second isolation layer 108 can be located on the isolation structure 102, and the entire surface of the electrical contact layer 101 is exposed, so as to increase the contact area between the conductive layer 111 and the electrical contact layer 101.

[0097] The material of the insulating layer 103 includes silicon dioxide, silicon nitride or silicon carbide.

[0098] The conductive layer 111 serves as an interconnection line in the semiconductor structure, connecting the structures in the substrate 100 according to design requirements to achieve specific functions.

[0099] The material of the conductive layer 111 includes copper, gold, silver, titanium or tungsten.

[0100] The first isolation layer 106 is used to seal the gap 107 . Since the first isolation layer 106 is also located on the top of the gap 107 , the gap 107 does not need any other isolation layer for sealing.

[0101] The first isolation layer 106 is also located on the isolation structure 102 and exposes the entire surface of the electrical contact layer 101 to increase the contact area between the electrical contact layer 101 and the conductive layer 111 and reduce the contact resistance.

[0102] The second isolation layer 108 covers the surface of the first isolation layer 106 , and the density of the second isolation layer 108 is greater than that of the first isolation layer 106 .

[0103] It can be understood that in the process of forming the gap 107, in order to allow more ion beams to pass through the first isolation layer 106, the density of the first isolation layer 106 is relatively small; after the gap 107 is formed, the larger and denser second isolation layer 108 can increase the density of the first isolation layer 106, thereby improving the firmness and stability of the first isolation layer 106.

[0104] In the direction parallel to the surface of the substrate 100, the thickness of the second isolation layer 108 is greater than the thickness of the first isolation layer 106, so that the stability of the first isolation layer 106 can be improved, and the collapse of the first stability layer 106 can be avoided. Preferably, the thickness ratio of the second isolation layer 108 to the first isolation layer 106 is 1.5:1 to 3:1. When the thickness ratio of the second isolation layer 108 to the first isolation layer 106 is within the above range, the second isolation layer 108 can play a good reinforcement role on the first isolation layer 106. In addition, the second isolation layer 108 can occupy a more reasonable area on the isolation structure 102, so that the second isolation layer 108 can completely expose the surface of the electrical contact layer 101 to increase the contact area between the electrical contact layer 101 and the conductive layer 111.

[0105] The first isolation layer 106 and the second isolation layer 108 are both located on the substrate 100 outside the electrical contact layer 101, and expose the entire surface of the electrical contact layer 101. In this way, the contact area between the conductive layer 111 and the electrical contact layer 101 can be increased, thereby reducing the contact resistance and improving the operating speed of the semiconductor structure.

[0106] In this embodiment, the material of the first isolation layer 106 is silicon dioxide. In other embodiments, the material of the first isolation layer may also be silicon-oxygen hydrocarbons. Silicon dioxide or silicon-oxygen hydrocarbons are not easily decomposed under the action of oxygen plasma and have good stability.

[0107] In this embodiment, the material of the second isolation layer 108 is the same as that of the first isolation layer 106, so that the second isolation layer 108 and the first isolation layer 106 can be more closely attached, thereby further improving the reinforcement effect of the second isolation layer 108. For example, the material of the second isolation layer 108 and the material of the first isolation layer 106 are both silicon dioxide. In other embodiments, the material of the second isolation layer can also be different from that of the first isolation layer, such as silicon nitride.

[0108] In this embodiment, the width of the gap 107 may be 1 nm-5 nm. When the width of the gap 107 is within the above range, the parasitic capacitance can be effectively reduced and the stability of the first isolation layer 106 and the second isolation layer 108 can be ensured.

[0109] In a direction perpendicular to the surface of the substrate 100, the ratio of the height of the gap 107 to the height of the insulating layer 103 is greater than or equal to 0.3. The height of the gap 107 is within the above range, that is, the gap 107 occupies a larger space, which can greatly reduce parasitic capacitance.

[0110] Furthermore, in the direction perpendicular to the surface of the substrate 100, the ratio of the height of the gap 107 to the height of the insulating layer 103 is less than or equal to 0.9. That is, the contact area between the first isolation layer 106 and the insulating layer 103 is greater than or equal to 0.1 of the total area of ​​the sidewalls of the insulating layer 103. When the contact area is within the above range, the first isolation layer 106 can fit the sidewalls of the insulating layer 103 more closely, thereby ensuring that the first isolation layer 106 can completely seal the top of the gap 107, so that the gap 107 has better sealing and stability, which can effectively reduce parasitic capacitance.

[0111] The semiconductor structure further includes a barrier layer 109 located between the first isolation layer 106 and the conductive layer 111. In this embodiment, the barrier layer 109 covers the surface of the second isolation layer 108. The barrier layer 109 is used to block the mutual diffusion between atoms in the conductive layer 111 and atoms in the second isolation layer 108, and to enhance the adhesion between the barrier layer 109 and the second isolation layer 108.

[0112] In this embodiment, the barrier layer 109 also covers the surface of the electrical contact layer 101. The barrier layer 109 is also used to block the mutual diffusion of atoms in the conductive layer 111 and atoms in the electrical contact layer 101, and to enhance the adhesion between the barrier layer 109 and the electrical contact layer 101.

[0113] The material of the barrier layer 109 includes tantalum, tantalum nitride, ruthenium or rhenium.

[0114] In summary, in this embodiment, the first isolation layer 106 completely seals the gap 107 , so that the gap 107 has good sealing and stability, which can effectively reduce parasitic capacitance.

[0115] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has an electrical contact layer and an isolation structure isolating adjacent electrical contact layers; An insulating layer is formed on the substrate, wherein the insulating layer has a through hole penetrating the insulating layer, and the through hole exposes the surface of the electrical contact layer; the width of the insulating layer is greater than or equal to one half of the width of the isolation structure, and less than or equal to the width of the isolation structure; forming a sidewall layer on the sidewall of the through hole; the top surface of the sidewall layer is lower than the top surface of the insulating layer; forming a first isolation layer, wherein the first isolation layer covers a surface of the spacer layer and an exposed surface of the insulating layer; Removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; A conductive layer filling the through hole is formed, wherein the conductive layer is electrically connected to the electrical contact layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method for removing the sidewall layer includes: providing a plasma source, wherein the ion beam generated by the plasma source reacts with the sidewall layer after passing through the first isolation layer to form reaction by-products, and at least part of the reaction by-products is discharged through the first isolation layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The process steps of removing the sidewall layer include: generating the ion beam based on an oxygen plasma source, the oxygen flow rate is 100 sccm-600 sccm, and the radio frequency power is 500W-1000W.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The material of the sidewall layer includes: amorphous carbon, hydrocarbon or polymer.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming the sidewall layer includes: forming an initial sidewall layer on the surface of the insulating layer and the bottom of the through hole; removing the initial sidewall layer located at the bottom of the through hole and the top surface of the insulating layer, and also removing part of the initial sidewall layer located on the side wall of the through hole, and the remaining initial sidewall layer serves as the sidewall layer.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: In a direction perpendicular to the surface of the substrate, a ratio of a height of the spacer layer to a height of the insulating layer is greater than or equal to 0.

3.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After removing the sidewall layer and before forming the conductive layer, the method further includes forming a second isolation layer on the surface of the first isolation layer, wherein the density of the second isolation layer is greater than the density of the first isolation layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The material of the second isolation layer includes silicon dioxide or silicon nitride.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: After the conductive layer is formed, the method further includes the step of: performing a planarization process to remove a portion of the conductive layer, a portion of the insulating layer, a portion of the first isolation layer, and a portion of the second isolation layer that are higher than the gap.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method for forming the first isolation layer includes: a low temperature atomic layer deposition process.

11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The material of the first isolation layer includes silicon dioxide or silicon-oxygen-hydrocarbon.

12. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: Before the step of forming a conductive layer filling the through hole, the method further includes the steps of: removing the first isolation layer and the second isolation layer located at the bottom of the through hole and the top surface of the insulating layer; and depositing a barrier layer covering the sidewalls of the through hole.

13. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has an electrical contact layer and an isolation structure isolating adjacent electrical contact layers; an insulating layer located on the substrate, wherein the insulating layer has a conductive layer therein, and the conductive layer is electrically connected to the electrical contact layer; the width of the insulating layer is greater than or equal to one half of the width of the isolation structure, and less than or equal to the width of the isolation structure; A first isolation layer is located between the insulating layer and the conductive layer, wherein the first isolation layer is also located on a portion of the side wall of the insulating layer, a gap is provided between the insulating layer and the first isolation layer, and the first isolation layer seals the gap.

14. The semiconductor structure according to claim 13, characterized in that: Also includes: A second isolation layer is located between the first isolation layer and the conductive layer, and the density of the second isolation layer is greater than the density of the first isolation layer.

15. The semiconductor structure according to claim 13, characterized in that: Also includes: A barrier layer is located between the first isolation layer and the conductive layer, and the barrier layer also covers a surface of the electrical contact layer.

16. The semiconductor structure according to claim 14, characterized in that The first isolation layer and the second isolation layer are both located on the substrate outside the electrical contact layer and expose the entire surface of the electrical contact layer.

17. The semiconductor structure according to claim 13, characterized in that In a direction perpendicular to the surface of the substrate, a ratio of a height of the gap to a height of the insulating layer is greater than or equal to 0.

3.

18. The semiconductor structure according to claim 14, wherein: In a direction parallel to the surface of the substrate, a thickness ratio of the second isolation layer to the first isolation layer is 1.5:1 to 3:1.

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