Three-dimensional memory and methods of making the same, memory systems

Abstract

The application provides a three-dimensional memory, a preparation method thereof, and a storage system. The preparation method of the three-dimensional memory comprises the following steps: forming a first dielectric layer on a first surface of a substrate, and forming an initial conductive column penetrating through the first dielectric layer and extending to the substrate; removing a part of the substrate corresponding to the initial conductive column to form a groove exposing at least part of the initial conductive column; removing a first part of the initial conductive column to form a conductive column, wherein the first part comprises a part of the initial conductive column located in the groove; and sequentially forming an isolation layer and a through-silicon contact connected with the conductive column in a space formed by a gap formed by removing the first part and the groove.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method and storage system. Background Technology

[0002] With the rapid development of integrated circuit technology, people have increasingly higher requirements for the integration density of 3D NAND flash memory. Existing 3D NAND fabrication processes typically use through-silicon contacts (TSCs) to electrically connect memory devices to semiconductor devices in peripheral circuits. The application of TSCs can significantly reduce the complexity and overall size of semiconductor circuit internal wiring, and can provide vertically aligned interconnects of electronic devices, achieving higher interconnectivity, higher device density, and shorter connection lengths.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory. The method includes: forming a first dielectric layer on a first surface of a substrate; forming an initial conductive pillar penetrating the first dielectric layer and extending to the substrate; removing a portion of the substrate corresponding to the initial conductive pillar to form a groove that exposes at least a portion of the initial conductive pillar; removing a first portion of the initial conductive pillar to form a conductive pillar, wherein the first portion includes a portion of the initial conductive pillar located within the groove; and sequentially forming an isolation layer and a through-silicon contact connected to the conductive pillar within the space formed by the void created by removing the first portion and the groove.

[0005] In one embodiment, the initial conductive pillar further includes a second portion connected to the first portion and penetrating the first dielectric layer, and the step of removing the first portion to form the conductive pillar includes: removing the first portion of the initial conductive pillar by an etching process to form the conductive pillar, wherein the etching rate of the initial conductive pillar is greater than the etching rate of the first dielectric layer, and the second portion forms the conductive pillar after the first portion is removed.

[0006] In one embodiment, the substrate includes a conductive interconnect layer connected to a first portion of each of the plurality of initial conductive pillars.

[0007] In one embodiment, the method further includes removing at least a portion of the conductive interconnect layer adjacent to the first portion during the step of removing the first portion.

[0008] In one embodiment, the first portion further includes a portion connected to the portion of the initial conductive post located within the groove and extending into the first dielectric layer.

[0009] In one embodiment, the substrate includes a first substrate and a second substrate, the first substrate having the first surface, and the conductive interconnect layer being located within the first substrate and / or the second substrate.

[0010] In one embodiment, the step of forming the isolation layer includes: forming an initial isolation layer in the gap formed by removing the first portion, the sidewall of the groove, and the bottom of the groove; and removing the portion of the initial isolation layer connected to the conductive post to form the isolation layer.

[0011] In one embodiment, the step of forming the isolation layer further includes: removing the portion of the first dielectric layer that is in contact with the space to form a conductive cut; and after forming the isolation layer, the method further includes: forming the through silicon contact connecting the conductive post in the conductive cut and the remaining portion of the space.

[0012] In one embodiment, a second dielectric layer is formed on a second surface of the substrate, the groove extends through and into the substrate through the second dielectric layer, and the step of forming the initial isolation layer further includes forming the initial isolation layer on the side of the second dielectric layer away from the substrate.

[0013] In one embodiment, during the formation of the groove, the method further includes: forming an isolation trench that extends through the second dielectric layer and the substrate and surrounds the groove; and during the formation of the initial isolation layer, the method further includes: filling the isolation trench with an insulating material to form an isolation trench structure.

[0014] Another aspect of this application provides a three-dimensional memory, comprising: a substrate having a first surface; a first dielectric layer disposed on the first surface; a through-silicon contact extending through the substrate and into the first dielectric layer; a conductive pillar connected to the through-silicon contact and extending through the first dielectric layer; a conductive interconnect layer located within the substrate; and an isolation layer surrounding the through-silicon contact and located between the substrate and the through-silicon contact, and extending into the substrate and located between the conductive interconnect layer and the through-silicon contact.

[0015] In one embodiment, the isolation layer further extends into the substrate and is located between the through-silicon contact and the conductive interconnect layer.

[0016] In one embodiment, the etching rate of the conductive pillar is greater than the etching rate of the first dielectric layer.

[0017] In one embodiment, the substrate includes a first substrate having the first surface and a second substrate having the second surface, and the conductive interconnect layer is located within the first substrate and / or the second substrate.

[0018] In one embodiment, the three-dimensional memory further includes: a second dielectric layer located on a second surface of the substrate, and the isolation layer is also located on the side of the second dielectric layer away from the substrate.

[0019] In one embodiment, the three-dimensional memory further includes an isolation trench structure extending through the second dielectric layer and the substrate, and surrounding the through-silicon contact.

[0020] In one embodiment, the substrate further includes an insulating layer located between the first substrate and the second substrate.

[0021] In another aspect, this application provides a three-dimensional memory system, comprising: a three-dimensional memory as described in any of the above embodiments, wherein the three-dimensional memory includes a storage string for storing data; and a controller electrically connected to the three-dimensional memory and configured to control the operation of the storage string.

[0022] In one embodiment, the three-dimensional memory includes a 3D NAND memory.

[0023] The method for fabricating the three-dimensional memory provided in this application can have at least one of the following beneficial effects:

[0024] According to some embodiments of this application, the initial conductive pillar and the first dielectric layer have a high etching selectivity ratio. When the first part of the initial conductive pillar is completely removed, the first dielectric layer is hardly removed, and the impact on the device structure is small.

[0025] The process for forming through-silicon contacts according to some embodiments of this application is more controllable than the traditional wet etching process for forming through-silicon contacts; and

[0026] According to some embodiments of this application, the risk of short circuits between conductive posts and the risk of voltage breakdown leakage can be reduced. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0028] Figures 1 to 4 This is a schematic diagram of the fabrication process of semiconductor structures in related technologies;

[0029] Figure 5 This is a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of this application;

[0030] Figures 6a to 10 This is a process schematic diagram of a method for fabricating a semiconductor structure according to an exemplary embodiment of this application;

[0031] Figure 11 This is a schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application;

[0032] Figure 12 yes Figure 11 A schematic diagram of the partial structure within the dashed box of the three-dimensional memory shown; and

[0033] Figure 13 This is a schematic diagram of a three-dimensional memory system according to an exemplary embodiment of this application. Detailed Implementation

[0034] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first dielectric layer discussed herein may also be referred to as the second dielectric layer, and the first surface may also be referred to as the second surface, and vice versa.

[0036] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the first dielectric layer shown in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] The features, principles and other aspects of this application are described in detail below.

[0041] Figures 1 to 4 This is a schematic diagram of the fabrication process of the semiconductor structure 100 in the related technology. Exemplarily, the semiconductor structure 100 can serve as an intermediate structure in the fabrication process of a three-dimensional memory, such as a 3D NAND memory. Figure 1 As shown, it can be on the upper side of substrate 110 (along...) y A second dielectric layer 120 is formed on the other side of the substrate 110 (along the direction) and on the other side of the substrate 110 (along the direction) y (In the opposite direction) A first dielectric layer 130 is formed. Then, conductive pillars 140 are formed that penetrate the first dielectric layer 130 and extend into the substrate 110. The portions of the second dielectric layer 120 and the substrate 110 corresponding to the conductive pillars 140 are removed to form grooves 150 that expose the conductive pillars 140.

[0042] Exemplarily, an isolation layer 160 is deposited on the bottom and sidewalls of the groove 150 (e.g., Figure 2 (As shown). Then, the portion of the insulating layer 160 located at the bottom of the groove 150 and the portion of the conductive layer 140 extending into the groove 150 are removed, exposing the upper surface of the remaining portion of the conductive post 140 (as shown). Figure 3(As shown). Finally, conductive material is deposited in the remaining space of the groove 150 to form a through silicon contact 170 that connects to the exposed upper surface of the remaining portion of the conductive post 140 (as shown). Figure 4 (As shown).

[0043] The inventors of this application have discovered that in some semiconductor structures 100, the conductive pillars 140, after being formed, do not interact with... Figures 1 to 4 The ideal morphology shown is completely consistent, but the portion of the conductive pillar 140 located in the groove 150 will form irregular protrusions or accumulations. These protrusions / accumulations may even extend into the upper part of the first dielectric layer 130. Even if the portion of the conductive pillar 140 located in the groove 150 is removed, it cannot completely prevent the conductive material within the conductive pillar 140 from contacting the substrate 110. In addition, some conductive material may also exist within the substrate 110 due to damage to the substrate 110, such as polysilicon material, caused by insufficient removal of the etchant (e.g., chlorine) during the etching process. This damage will be filled by conductive material in subsequent processes. The irregular accumulation of the conductive pillar 140 extending into the groove 150 and / or the portion extending into the first dielectric layer 130 increases the risk of it connecting with the conductive material at the damaged area of ​​the substrate 110. When two or more conductive pillars 140 are connected to the conductive material at the damaged area of ​​the substrate 110, interconnect short circuits are formed between the different conductive pillars 140, thereby affecting the performance of the semiconductor structure 100.

[0044] This application proposes a three-dimensional memory and its manufacturing method, which can at least partially improve or solve the above-mentioned problems, and the process is highly controllable with minimal adverse effects on the device.

[0045] Figure 5 This is a flowchart of a semiconductor structure fabrication method 1000 according to an embodiment of this application. For example... Figure 5 As shown, this application provides a method 1000 for fabricating a semiconductor structure, comprising:

[0046] Step S1100: A first dielectric layer is formed on the first surface of the substrate, and an initial conductive pillar is formed that penetrates the first dielectric layer and extends to the substrate.

[0047] Step S1200: Remove the portion of the substrate corresponding to the initial conductive pillar to form a groove that exposes at least a portion of the initial conductive pillar;

[0048] Step S1300: Remove the first portion of the initial conductive post to form a conductive post, wherein the first portion includes the portion of the initial conductive post located within the groove; and

[0049] In step S1400, an isolation layer and a through silicon contact connected to a conductive pillar are sequentially formed in the space formed by the gap and groove created in the first part.

[0050] It should be understood that the steps shown in preparation method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps shown may be performed simultaneously or in a manner different from [the steps described in the original text]. Figure 5 The execution is performed in the order shown.

[0051] Figures 6a to 10 This is a schematic diagram of a method 1000 for fabricating a semiconductor structure 200 according to an embodiment of this application. Exemplarily, the semiconductor structure 200 can serve as an intermediate structure in the fabrication process of a three-dimensional memory, such as a 3D NAND memory. The following is in conjunction with... Figures 6a to 10 The above steps S1100 to S1400 are further described.

[0052] Step S1100: Forming a first dielectric layer on the first surface of the substrate, and forming a layer penetrating the first dielectric layer and... Initial conductive pillars extending into the substrate.

[0053] like Figure 6a As shown, a first dielectric layer 220 can be formed on the first surface 210a of the substrate 210, and then an initial conductive pillar 240 is formed through the first dielectric layer 220 and extends to the substrate 210.

[0054] In some embodiments, the material of the substrate 210 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any combination thereof.

[0055] In other embodiments, the substrate 210 may be a composite structure, for example, formed by sequentially stacking a first substrate 211, an insulating layer 212, and a second substrate 213, wherein the first substrate 211 has a second surface 210b, and the second substrate 213 has a first surface 210a. Exemplarily, the materials of the first substrate 211 and the second substrate 213 may be the same or different, and may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. The material of the insulating layer 212 may include, for example, oxides.

[0056] In some embodiments, a second dielectric layer 230 may also be formed on the second surface 210b of the substrate 210. The materials used for the second dielectric layer 230 and the first dielectric layer 220 may be the same or different, for example, both may include oxides, nitrides, high dielectric constant materials or any combination thereof.

[0057] In some embodiments, after the second dielectric layer 230 is formed, the substrate 210 and the second dielectric layer 230 can be flipped together, for example, by 180 degrees, so that the first surface 210a is above the second surface 210b (along...). y (direction) to facilitate the formation of the first dielectric layer 220 on the first surface 210a.

[0058] For example, a second dielectric layer 230 and a first dielectric layer 220 may be formed on a first surface 210a and a second surface 210b of a substrate 210 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0059] In some embodiments, the first dielectric layer 220 can be etched from the side of the first dielectric layer 220 away from the second surface 210b to form an etched hole. Then, a conductive material is filled into the etched hole to form an initial conductive pillar 240. The etched hole can penetrate the first dielectric layer 220 and extend into the substrate 210. The initial conductive pillar 240 formed in this way includes a first portion 241 (…). Figure 6a (as shown in the dashed box) and Part 242.

[0060] In some embodiments, the first portion 241 includes a portion of the initial conductive post 240 located within the groove 250, which is connected to the substrate 210; in other embodiments, the first portion 241 includes the portion of the initial conductive post 240 located within the groove 250, and a portion connected to the portion of the initial conductive post 240 located within the groove 150 and extending into the first dielectric layer 220. The second portion 242 is connected to the first portion 242 and extends through the first dielectric layer 220. It is understood that the first portion 241 and the second portion 242 of the initial conductive post 240 are formed in the same step of the fabrication process and are not formed independently of each other.

[0061] It should be noted that, since the initial conductive pillars are formed in multiple ways, initial conductive pillars 340 can also be formed during the process of forming initial conductive pillar 240. Figure 6b As shown). The first part 341 of the initial conductive post 340 ( Figure 6b (As shown in the dashed box) It does not contact the substrate 210.

[0062] For example, an etched hole can be formed using a combination of photolithography and etching processes, and an initial conductive pillar 240 can be formed in the etched hole by depositing a conductive material, such as a conductive material, using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). The conductive material may include tungsten, copper, aluminum, ruthenium, tungsten alloys, or any combination thereof.

[0063] In some embodiments, the substrate 210 has a conductive interconnect layer 243, which may be located at the bottom of the substrate 210. y (in the opposite direction). In other embodiments, the conductive interconnect layer 243 may be located at the bottom and top of the substrate 210. The same conductive interconnect layer 243 may be simultaneously connected to the first portions 241 of a plurality of initial conductive pillars 240.

[0064] In some embodiments, substrate 210 includes a first substrate 211 and a second substrate 213. A conductive interconnect layer 243 is located within the second substrate 213. First portions 241 of a plurality of initial conductive pillars 240 are in contact with the conductive interconnect layer 243 within the second substrate 213.

[0065] Step S1200: Remove the portion of the substrate corresponding to the initial conductive pillar to form at least a portion of the initial conductive pillar exposed. The groove.

[0066] In some embodiments, a portion of the substrate 210 corresponding to the initial conductive post 240 may be removed to form a groove 250, thereby exposing at least a portion of the initial conductive post 240. The projection of this corresponding portion onto the first dielectric layer 220 overlaps the projection of the initial conductive post 240 onto the first dielectric layer 220. In embodiments having a second dielectric layer 230, the process further includes removing the second dielectric layer 230 and the portion of the substrate 210 corresponding to the initial conductive post 240 to form the groove 250, thereby exposing at least a portion of the initial conductive post 240.

[0067] In some embodiments, a portion of the second dielectric layer 230 and the substrate 210 may be removed to form an isolation trench 260. Exemplarily, the isolation trench 260 extends through the second dielectric layer 230 and the substrate 210, and its projection onto the first dielectric layer 220 is a closed shape, such as an annular shape. The projection of the groove 250 onto the first dielectric layer 220 lies within this closed shape. In other embodiments, the projection shape of the isolation trench 260 onto the first dielectric layer 220 may be an open shape, such as an annular shape with a notch, and the projection of the groove 250 onto the first dielectric layer 220 lies within this annular shape with the notch.

[0068] For example, the groove 250 and the isolation trench 260 may be formed using a combination of photolithography and etching processes. In this process, a patterned mask may be formed on the side of the second dielectric layer 230 away from the first surface 210a, and the second dielectric layer 230 and the substrate 210 may be etched using a combination of photolithography and etching processes.

[0069] Step S1300: Remove the first portion of the initial conductive post to form a conductive post, wherein the first portion includes the initial conductive post. The portion of the electric column located within the groove.

[0070] like Figure 7As shown, after removing the first portion 241 of the initial conductive post 240, a second portion 242 forms the conductive post 240'. The first portion 241 may include the portion of the initial conductive post 240 exposed within the groove 250 and the portion of the initial conductive post 240 penetrating the first dielectric layer 220 and close to the substrate 210. After removing the first portion 241, the conductive post 240' is not in contact with the conductive interconnect layer 243, thereby reducing the risk of short circuits between different conductive posts 240' and the risk of voltage breakdown leakage.

[0071] It should be noted that during the removal of the first portion 241 of the initial conductive post 240, the first portion 341 of the conductive post 340 will also be removed. After this process, Figure 6a and Figure 6b The initial conductive pillars 240 / 340 shown will all form Figure 7 The conductive post 240' is shown.

[0072] For example, a wet etching process can be used to remove the first portion 241 / 341 of the initial conductive pillars 240 / 340. It should be noted that the etching rate of the material used for the initial conductive pillars 240 / 340 in this application is greater than the etching rate of the material used for the first dielectric layer 220. Therefore, when the first portion 241 / 341 of the initial conductive pillars 240 / 340 is completely removed, the first dielectric layer 220 is hardly removed, forming conductive pillars 240' recessed within the first dielectric layer 220.

[0073] In some embodiments, during the removal of the first portion 241 / 341, in order to ensure that the connection between the first portion 241 / 341 and the conductive interconnect layer 243 is completely broken, a portion of the conductive interconnect layer 243 is also removed, and the removed portion is close to the first portion 241 / 341.

[0074] In the context of this invention, the process of forming the conductive pillar 240' may also include, for example, planarization, surface cleaning, and removal of scum. These are not the focus of this invention and will not be described in detail here. Those skilled in the art can add or remove steps from the manufacturing method of this invention as needed.

[0075] Step S1400: Separation is sequentially formed within the space created by removing the gaps and grooves formed in the first part. Layers and through-silicon contacts connected to conductive pillars.

[0076] Figure 8 This is a process diagram illustrating the formation of the initial isolation layer 280 of the semiconductor structure according to an embodiment of this application. Figure 8As shown, removing the first portion 241 / 341 of the initial conductive pillars 240 / 340 creates a gap, which, together with the groove 250, constitutes space 270. Space 270 consists of the sidewall of the groove 250, the sidewall of the conductive interconnect layer 243 near the groove 250, and the upper surface of the conductive pillars 240' (along...). y The orientation), a portion of the substrate 210 on its bottom side, and a portion of the first dielectric layer 220 together define the composition. For example... Figure 8 As shown, an initial isolation layer 280 is filled within space 270. The initial isolation layer 280 may not completely fill space 270, leaving some remaining space, i.e., a second space 270'. Exemplarily, the initial isolation layer 280 is formed on the side of space 270 near the conductive post 240' and on the sidewall of space 270. The initial isolation layer 280 completely separates the conductive post 240' from the conductive interconnect layer 243 of the initial conductive post 240. In some embodiments, the second dielectric layer 230 may be located on its upper surface (along...). y (Direction) to form an initial isolation layer 280.

[0077] In some embodiments, insulating material may be filled within the isolation trench 260 to form an isolation trench structure 290. The isolation trench structure 290 is, for example, a closed ring structure, and the through-silicon contact 310 formed in subsequent processes (…) Figure 10 (As shown) Enclosed within. The isolation trench structure 290 can isolate the through silicon contact 310 from adjacent electronic components such as memory cells to reduce electrical interference.

[0078] For example, the materials of the initial isolation layer 280 and the isolation trench structure 290 can be the same or different, for example, both include oxides, nitrides, high dielectric constant materials or any combination thereof. The initial isolation layer 280 and the isolation trench structure 290 can be formed using one or more thin film deposition processes (e.g., ALD, CVD, PVD or combinations thereof).

[0079] Figure 9a and Figure 9b This is a process diagram illustrating the formation of an isolation layer 280' in a semiconductor structure according to an embodiment of this application. Figure 9a As shown, the portion of the initial insulating layer 280 connected to the conductive post 240' can be removed to form the insulating layer 280'. After removing this connection portion, the upper surface of the conductive post 240' (along...) y (Direction) exposed. In other embodiments, it also includes removing the portion of the first dielectric layer 220 corresponding to the second space 270' to form a conductive cutout 271 (e.g., direction). Figure 9b(As shown). The lower surface of the conductive notch 271 is substantially flush with the upper surface of the conductive post 240'. Exemplarily, a combination of photolithography and etching processes can be used to etch away the portion of the initial isolation layer 280 connected to the conductive post 240', as well as the portion of the first dielectric layer 220 corresponding to the second space 270'.

[0080] Figure 10 This is a process diagram illustrating the formation of the through-silicon contact 310 according to an embodiment of the present application. (See diagram for example.) Figure 10 As shown, conductive material is filled into the conductive notch 271 and the second space 270' to form a through-silicon contact 310, which is connected to the exposed upper surface of the conductive pillar 240'. The insulating layer 280' completely isolates the conductive interconnect layer 243 from the through-silicon contact 310.

[0081] For example, the material through the silicon contact 310 may include tungsten, copper, aluminum, ruthenium, tungsten alloys, or any combination thereof. The through silicon contact 310 may be formed using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof).

[0082] Another aspect of this application provides a three-dimensional memory that can be prepared using any of the preparation methods described in the above embodiments.

[0083] Figure 11 This is a schematic diagram of the structure of a three-dimensional memory 300 according to an embodiment of this application; Figure 12 yes Figure 11 A schematic diagram of a partial structure 300' within the dashed box of the shown three-dimensional memory 300. (Combined with...) Figure 11 and Figure 12 As shown, the three-dimensional memory partial structure 300' may include a substrate 210, a first dielectric layer 220, a through-silicon contact 310, a conductive pillar 240', a conductive interconnect layer 243, and an isolation layer 280'. The substrate 210 has a first surface, the first dielectric layer 220 is located on the first surface 210a, the through-silicon contact 310 penetrates the substrate 210 and extends into the first dielectric layer 220; the conductive pillar 240' is connected to the through-silicon contact 310 and penetrates the first dielectric layer 220; the conductive interconnect layer 243 is located within the substrate 210; the isolation layer 280' surrounds the through-silicon contact 310 and is located between the substrate 210 and the through-silicon contact 310, isolating the through-silicon contact 310 from the conductive interconnect layer 243. In some embodiments, the isolation layer 280' also extends into the substrate 210 and is located between the conductive interconnect layer 243 and the through-silicon contact 310.

[0084] In some embodiments, the substrate 210 has opposing first surfaces 210a and second surfaces 210b, a second dielectric layer 230 is formed on the second surface 210b, and a first dielectric layer 220 is formed on the first surface 210a.

[0085] In some embodiments, the etching rate of the conductive pillar 240' is greater than the etching rate of the first dielectric layer 220. In some embodiments, the substrate 210 includes a second substrate 213 having a first surface 210a and a first substrate 211 having a second surface 210b. A conductive interconnect layer 243 is located within the first substrate 211 and / or the second substrate 213, and an isolation layer 280' is located between the conductive interconnect layer 243 and the through silicon contact 310. In some embodiments, the substrate 210 further includes an insulating layer 212, which is located between the first substrate 211 and the second substrate 213. In some embodiments, the isolation layer 280' is also located on the upper surface of the second dielectric layer 230 (along...). y direction).

[0086] In some embodiments, the 3D memory 300 further includes an isolation trench structure 290. The isolation trench structure 290 extends through the second dielectric layer 230 and the substrate 210, and its projection onto the first dielectric layer 220 may have, for example, a closed annular shape, within which the projection of the through silicon contact 310 onto the first dielectric layer 220 lies. In other embodiments, the projection of the isolation trench structure 290 onto the first dielectric layer 220 includes an open shape, such as a notched ring, within which the projection of the through silicon contact 310 onto the first dielectric layer 220 lies.

[0087] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0088] Another aspect of this application provides a three-dimensional memory system, such as Figure 13 As shown, the three-dimensional storage system includes a three-dimensional memory 301 and a controller 302 as described in any embodiment of this application. The three-dimensional memory 301 includes multiple memory strings with storage functions, each memory string being composed of multiple memory cells. The controller 302 is electrically connected to the three-dimensional memory 301 via peripheral circuitry and is configured to control the operation of the memory strings.

[0089] In some embodiments, memory 301 is electrically connected to and controlled by controller 302. Controller 302 may, for example, control the application of different voltage signals to memory cells (not shown) in memory 301 to achieve the effect of controlling memory 301 to perform at least one of, for example, read operations, programming operations, and erase operations.

[0090] In some implementations, controller 302 may be configured to control operations of memory 301, such as read, program, and erase operations. Controller 302 may also be configured to manage various functions related to data stored in or to be stored in memory 301, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0091] In some embodiments, the 3D memory 301 includes a 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the 3D memory system also includes a connector 303, which can be connected to a device such as a host computer for transmitting data.

[0092] In some embodiments, the three-dimensional memory system includes a solid-state drive (SSD), a memory card, or any combination thereof. In some embodiments, the controller 302 and the memory 301 may be integrated onto the SSD to form the three-dimensional memory system. The storage capacity and / or operating speed of the SSD may be higher than that of the memory card. The three-dimensional memory 301 of any embodiment of this application can be applied to storage devices or memory cards such as memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, and universal flash memory (UFS).

[0093] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, wherein, The method includes: A first dielectric layer is formed on a first surface of a substrate, and an initial conductive pillar is formed through the first dielectric layer and extends to the substrate. Remove the portion of the substrate corresponding to the initial conductive pillar to form a groove that exposes at least a portion of the initial conductive pillar; Removing a first portion of the initial conductive post to form a conductive post, wherein the first portion includes the portion of the initial conductive post located within the groove; and An isolation layer and a through silicon contact connected to the conductive pillar are sequentially formed within the space formed by removing the gap created by the first part and the groove.

2. The method according to claim 1, wherein, The initial conductive pillar further includes a second portion connected to the first portion and penetrating the first dielectric layer, and The step of removing the first portion that forms the conductive pillar includes: The conductive pillar is formed by removing the first portion of the initial conductive pillar through an etching process. The etching rate of the initial conductive pillar is greater than the etching rate of the first dielectric layer, and the second portion forms the conductive pillar after the first portion is removed.

3. The method according to claim 1 or 2, wherein, The substrate includes a conductive interconnect layer, which is connected to the first portion of each of the plurality of initial conductive pillars.

4. The method according to claim 3, wherein, In the step of removing the first portion, the method further includes: Remove at least a portion of the conductive interconnect layer near the first portion.

5. The method according to claim 1 or 2, wherein, The first portion also includes a portion connected to the portion of the initial conductive post located within the groove and extending into the first dielectric layer.

6. The method according to claim 3, wherein, The substrate includes a first substrate and a second substrate, the first substrate having the first surface, and The conductive interconnect layer is located within the first substrate and / or the second substrate.

7. The method according to claim 1, wherein, The steps for forming the isolation layer include: An initial insulating layer is formed within the void created by removing the first portion, on the sidewalls of the groove, and at the bottom of the groove; and The portion of the initial isolation layer connected to the conductive pillar is removed to form the isolation layer.

8. The method according to claim 7, wherein, The step of forming the isolation layer further includes: Remove the portion of the first dielectric layer that is in contact with the space to form a conductive cut; and After forming the isolation layer, the method further includes forming the through silicon contact connecting the conductive post within the conductive cut and the remaining portion of the space.

9. The method according to claim 7, wherein, A second dielectric layer is formed on the second surface of the substrate, and the groove extends through and into the substrate through the second dielectric layer. The step of forming the initial isolation layer further includes: The initial isolation layer is formed on the side of the second dielectric layer away from the substrate.

10. The method according to claim 9, wherein, In the process of forming the groove, the method further includes: An isolation trench is formed that extends through the second dielectric layer and the substrate and surrounds the groove; and In the process of forming the initial isolation layer, the method further includes filling the isolation trench with insulating material to form an isolation trench structure.

11. A three-dimensional memory, comprising: Substrate, having a first surface; A first dielectric layer is disposed on the first surface; The silicon contact extends through the substrate and into the first dielectric layer; A conductive post is connected to the through-silicon contact and penetrates the first dielectric layer; A conductive interconnect layer is located within the substrate; as well as An isolation layer surrounds the through-silicon contact and is located between the through-silicon contact and the substrate; Wherein, the cross-sectional area of ​​the through silicon contact in the direction perpendicular to the first surface is greater than the cross-sectional area of ​​the conductive post in the direction perpendicular to the first surface.

12. The three-dimensional memory according to claim 11, wherein, The isolation layer also extends into the substrate and is located between the through silicon contact and the conductive interconnect layer.

13. The three-dimensional memory according to claim 11 or 12, wherein, The etching rate of the conductive pillar is greater than the etching rate of the first dielectric layer.

14. The three-dimensional memory according to claim 11, wherein, The substrate further includes a second surface opposite to the first surface; The substrate includes a first substrate having the first surface and a second substrate having the second surface, and the conductive interconnect layer is located within the first substrate and / or the second substrate.

15. The three-dimensional memory according to claim 11, wherein, The substrate further includes a second surface opposite to the first surface; the three-dimensional memory further includes: A second dielectric layer is located on the second surface of the substrate, and The isolation layer is also located on the side of the second dielectric layer away from the substrate.

16. The three-dimensional memory according to claim 11, wherein, The substrate further includes a second surface opposite to the first surface; the three-dimensional memory further includes: A second dielectric layer is located on the second surface of the substrate, and An isolation trench structure extends through the second dielectric layer and the substrate, and surrounds the through-silicon contact.

17. The three-dimensional memory according to claim 14, wherein, The substrate further includes an insulating layer located between the first substrate and the second substrate.

18. A three-dimensional memory system, comprising: The three-dimensional memory as described in any one of claims 11-17, wherein the three-dimensional memory includes a storage string for storing data; and A controller, electrically connected to the three-dimensional memory, is configured to control the operation of the memory string.

19. The three-dimensional memory system according to claim 18, wherein, The three-dimensional memory includes 3D NAND memory.

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