Logarithmic adder-accumulator circuitry, processing pipeline including the same, and method of operation

Abstract

An integrated circuit comprising a plurality of serially connected log-add-accumulator circuits to perform, in operation, log-add and accumulate operations, wherein each log-add-accumulator circuit comprises: (i) a log-add circuit to add first input data each having a log data format to filter weight data and generate and output first sum data having a log data format, and (ii) an accumulator coupled to the log-add circuit of the associated log-add-accumulator circuit to add second input data to the first sum data output by the associated log-add circuit to generate first accumulate data. The integrated circuit can further comprise first data format conversion circuitry coupled to an output of each log-add circuit to convert a data format of the first sum data to a floating point data format, wherein the accumulator can be of a floating point type.

Description

[0001] Related applications

[0002] This non-provisional application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 943,336, filed December 4, 2019, entitled "Logarithmic Addition-Accumulator Circuit, Processing Pipeline include Same and Method of Operating Same". Provisional Application '336 is hereby incorporated in its entirety by reference. Background Technology

[0003] This document describes and illustrates numerous inventions. The invention is neither limited to any single aspect or embodiment thereof, nor to any combination and / or arrangement of such aspects and / or embodiments. Importantly, each aspect and / or embodiment of the invention can be used alone or in combination with one or more other aspects and / or embodiments of the invention. All combinations and arrangements thereof are intended to fall within the scope of this invention.

[0004] In one aspect, the invention relates to one or more integrated circuits (and methods of operating such circuit systems) having a logarithmic adder-accumulator circuit system, wherein data (e.g., image data) is processed at least in part based on a logarithmic data format, for example, associated with inference operations. In one embodiment, the invention includes, for example, a plurality of logarithmic adder-accumulator circuits interconnected in series (sometimes referred to herein as "a plurality of LACs" or "a plurality of LAC circuits," and singularly / individually referred to as "LACs" or "LAC circuits") to pipeline logarithmic addition and accumulation operations. In one embodiment, the invention includes a circuit system for converting or transforming input data / values ​​having a first or initial data format (e.g., floating-point or fixed-point data format) to a logarithmic data format (e.g., having a base of 2), and processing data having a logarithmic data format in part via logarithmic addition. In one embodiment, the conversion circuit system alters, transforms, and / or converts the data format of the input data / values ​​by remapping the value of the fractional domain of each input data / value from a floating-point data format to the logarithm of its value.

[0005] For example, in operation, input data / values ​​in logarithmic data format are added to image filter weights or coefficients that are also in logarithmic data format (e.g., with a base of 2). Filter weights or coefficients used in image data processing may be stored in memory in logarithmic data format or in a different format and converted or transformed to logarithmic data format before processing (e.g., immediately before processing). In one embodiment, the conversion circuitry changes, transforms, and / or converts the data format of the filter weights by remapping the values ​​of the fractional domain of each filter weight from floating-point data format to the logarithm of the fractional domain values.

[0006] After logarithmic addition, the sum data can be converted or transformed into another / different data format (e.g., floating-point format or fixed-point format—e.g., back to the input data format—however, the length of the values ​​may be the same or different) for appending / further processing. For example, image data processed in logarithmic data format can be converted or transformed into floating-point data format (i.e., the same data format as the input data). Subsequently, the partially processed data in floating-point data format can be further processed to implement, for example, accumulation operations related to image data processing associated with inference operations. Notably, in one embodiment, the conversion circuitry system changes, transforms, and / or converts the data format of the sum data by remapping the value of the fractional domain of each data / value from logarithmic data format to floating-point data format.

[0007] On the other hand, the present invention relates to one or more integrated circuits (and methods of operating such circuits), comprising multiple execution or processing pipelines having a logarithmic adder-accumulator circuit system (sometimes referred to as a "logarithmic adder-accumulator circuit system") that processes data based on a logarithmic data format to, for example, generate processed image data. For example, each execution or processing pipeline includes multiple logarithmic adder-accumulator circuits for processing data, for example, as described above. In one embodiment, in operation, image data (which may be in a floating-point data format) is provided to multiple execution or processing pipelines, each pipeline including multiple logarithmic adder-accumulator circuits. Here, the data (e.g., image data having a floating-point or fixed-point data format) is initially converted or transformed into a logarithmic data format (via a format conversion circuit system), and then the data is added to associated image filter weights or coefficients (which are in or have been converted / transformed into a logarithmic data format) via a logarithmic adder / adder circuit system of multiple logarithmic adder-accumulator circuit systems. In one embodiment, the output (i.e., sum data) of the logarithmic adder / adder circuitry is applied to or provided to a format conversion circuitry to convert or transform the logarithmic data format from the sum / output of the logarithmic adder / adder circuitry into a different data format—for example, a data format that facilitates subsequent processing by the processing circuitry or is consistent with subsequent processing by the processing circuitry (e.g., floating-point data format). In this regard, the sum / output of the logarithmic adder-accumulator circuitry in floating-point data format can then be further processed via an accumulator circuitry system of multiple logarithmic adder-accumulator circuitry systems to implement the accumulation operation of the processing circuitry system. The accumulator circuitry system accumulates, for example, image data associated with multiple associated partial processing operations related to inference operations. It is noteworthy that multiple execution or processing pipelines can operate concurrently.

[0008] Multiple logarithmic adder-accumulator circuits may include multiple registers (including multiple shadow registers) to implement or facilitate the pipelining of multiplication and accumulation operations performed by the logarithmic adder-accumulator circuits, thereby increasing the throughput of the logarithmic adder-accumulator execution or processing pipeline associated with processing input data (e.g., image data). It is noteworthy that the present invention can employ one or more circuit architectures described and illustrated in U.S. Patent Application No. 16 / 545,345, wherein the logarithmic adder circuit is an alternative to or an addition to the multiplication circuit to implement the logarithmic adder circuit system as described herein. Implementing the logarithmic adder circuit as described and illustrated herein into such a circuit architecture (including multiple registers, e.g., shadow registers) facilitates the cascading of logarithmic adder and accumulation operations consistent with the present invention. In this way, multiple logarithmic adder-accumulator circuits can be configured and / or reconfigured to process data (e.g., image data) in a manner that performs processing and operations more quickly and / or efficiently. '345 application is incorporated herein by reference in its entirety.

[0009] In another aspect, the present invention relates to one or more integrated circuits having circuitry for implementing logarithmic addition and accumulation operations as well as multiplication and accumulation operations. Here, the one or more integrated circuits include a logarithmic adder-accumulator circuitry for performing logarithmic addition and accumulation operations (e.g., as discussed herein) and a multiplier-accumulator circuitry for performing multiplication and accumulation operations (e.g., as discussed in detail below). The one or more integrated circuits may include a mode selection circuitry to control (i.e., enable and / or disable) the operability and / or operation of the logarithmic adder-accumulator circuitry and the multiplier-accumulator circuitry, thereby selecting a circuitry for processing, for example, image data associated with inference operations. In this respect, the mode selection circuitry controls or determines the data processing, and the circuitry employed therein, including the logarithmic adder-accumulator circuitry or the multiplier-accumulator circuitry.

[0010] In one embodiment, the mode selection circuitry may be programmable only once; in another embodiment, it may be programmable more than once (i.e., multiple times). The mode selection circuitry may be programmed, for example, in situ (i.e., during operation of the integrated circuit), at manufacturing time, and / or during or after power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc. For example, the mode selection circuitry may receive a mode selection signal from internal or external circuitry including one or more data storage circuitry (e.g., one or more memory cells, registers, flip-flops, latches, memory blocks / arrays), one or more input pins / conductors, (any type) lookup table (LUT), processor or controller, and / or discrete control logic (i.e., outside one or more integrated circuits—e.g., a host computer / processor). In response, the mode selection circuitry may use one or more such signals to enable or disable the selected processing circuitry (as applicable), thereby implementing one of the processing modes (i.e., logarithmic addition and accumulation or multiplication and accumulation) in situ and / or during or after power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc.

[0011] It is worth noting that when the processing circuit system includes both a logarithmic adder-accumulator circuit system and a multiplier-accumulator circuit system, such circuit systems can share one or more circuits, and thus, the respective circuit systems may not be completely separate and distinct. For example, the data path of the logarithmic adder-accumulator circuit system and the data path of the multiplier-accumulator circuit system can share the circuit system associated with the filter weights or coefficients, as well as the circuit system that performs the aforementioned accumulation operation. Furthermore, when multiple respective circuit systems are implemented in multiple execution or processing pipelines having a logarithmic adder-accumulator circuit system that processes data with logarithmic data format and a multiplier-accumulator circuit system that processes data with floating-point or fixed-point format, the data paths can share most of the integrated circuit's circuit system—except for, for example, the data format conversion circuit system (i.e., the circuit system that converts / converts data to logarithmic data format), the logarithmic adder circuit system of the logarithmic adder-accumulator circuit system, and the multiplication circuit system of the multiplier-accumulator circuit system. In this embodiment, such an execution or processing pipeline can be combined with a logarithmic adder-accumulator circuit system or a multiplier-accumulator circuit system to process, for example, image data related to inference operations.

[0012] The circuit systems of the present invention can be disposed on or within one or more integrated circuits, such as (i) processors, controllers, state machines, gate arrays, system-on-a-chip (“SOC”), programmable gate arrays (“PGA”), and / or field-programmable gate arrays (“FPGA”), and / or (ii) processors, controllers, state machines, and SOCs including embedded FPGAs, and / or (iii) integrated circuits (e.g., processors, controllers, state machines, and SoCs) – including embedded processors, controllers, state machines, and / or PGAs. In practice, the circuit systems of the present invention can be disposed on or within one or more integrated circuits specifically designed for such circuit systems. Attached Figure Description

[0013] This invention can be implemented in conjunction with the embodiments shown in the accompanying drawings. These drawings illustrate different aspects of the invention, and where appropriate, reference numerals, nomenclature, or names illustrating similar circuits, architectures, structures, components, materials, and / or circuits are similarly labeled in different figures. It should be understood that various combinations of structures, components, materials, and / or circuits, in addition to those specifically shown, are considered and are within the scope of this invention.

[0014] Furthermore, numerous inventions are described and illustrated herein. The invention is not limited to any single aspect or embodiment thereof, nor to any combination and / or arrangement of such aspects and / or embodiments. Moreover, each aspect and / or embodiment of the invention may be used alone or in combination with one or more other aspects and / or embodiments of the invention. For the sake of brevity, certain arrangements and combinations are not discussed and / or illustrated separately herein. It is important to note that embodiments or implementations described herein as “exemplary” should not be construed as being preferred or advantageous, for example, relative to other embodiments or implementations; rather, it is intended to reflect or indicate that one or more embodiments are “example” embodiments.

[0015] It is worth noting that the configurations, block / data widths, data path widths, bandwidths, data lengths, values, processes, pseudocodes, operations, and / or algorithms described and / or illustrated herein, as well as the associated text, are exemplary. In fact, the invention is not limited to any particular or exemplary circuit, logic, block, function, and / or physical diagram, the number of multiplier-accumulator circuits employed in the execution pipeline, the number of execution pipelines employed in a particular processing configuration, memory organization / allocation, block / data width, data path width, bandwidth, values, processes, pseudocodes, operations, and / or algorithms illustrated and / or described according to, for example, exemplary circuits, logic, blocks, functions, and / or physical diagrams. In fact, while several exemplary embodiments and features of the invention are illustrated in the context of floating-point data formats (e.g., FP16 or FP24) and logarithmic data formats (e.g., LL8 or LL16), the embodiments and inventions are applicable to other precisions (e.g., FPxx, where: 8 ≤ xx ≤ 39) and LLxx, where: 8 ≤ xx ≤ 24). For the sake of brevity, any precision other than that shown and / or described herein is intended to fall within the scope of the invention, and will be quite clear to those skilled in the art based on, for example, this application.

[0016] Furthermore, while illustrative / exemplary embodiments include multiple memories (e.g., L3 memory, L2 memory, L1 memory, L0 memory) assigned, allocated, and / or used to store certain data and / or within certain organizations, one or more memories may be added, and / or one or more memories may be omitted and / or combined / merged—e.g., L3 memory or L2 memory—and / or the organization may be changed, supplemented, and / or modified. This invention is not limited to the illustrative / exemplary embodiments of memory organization and / or allocation set forth in the application. Similarly, this invention is not limited to the illustrative / exemplary embodiments set forth herein.

[0017] Figure 1AThe illustration shows a schematic block diagram of the logic of an exemplary logarithmic adder-accumulator execution pipeline connected in a linear pipeline configuration according to one or more aspects of the present invention, wherein the logarithmic adder-accumulator processing or execution pipeline (“LAC pipeline”) includes a logarithmic adder-accumulator circuit system illustrated in block diagram form; notably, the logarithmic adder-accumulator circuit system includes one or more logarithmic adder-accumulator circuits (“multiple LACs” (or a singular / single “LAC”) – exemplary logarithmic adder-accumulator circuits (sometimes also referred to as “logarithmic adder-accumulator circuits”) illustrated in schematic block diagram form in Illustration A); in this exemplary embodiment, “m” (e.g., 64 in the illustrative embodiment) logarithmic adder-accumulator circuits are connected in the linear execution pipeline to operate concurrently, whereby the processing circuitry performs m x m (e.g., 64) cycle intervals (here, the cycle may nominally be 1 ns) in each m (e.g., 64) cycle interval (here, the cycle may nominally be 1 ns). x64) logarithmic addition and accumulation operations; notably, the input and output pixels / data at a specific (i,j) position (indexes of the width Dw / Yw and height Dh / Yh dimensions in this exemplary embodiment -- Dw = 512, Dh = 256 and Dd = 128, and Yw = 512, Yh = 256 and Yd = 64) are processed every m (e.g., 64) cycles for each Dw*Dh depth column in this stage; furthermore, in one embodiment, before the logarithmic adder-accumulator circuitry begins processing (see, for example, '345 application, as described above, incorporated herein by reference), the filter weights or weight data of the logarithmic data format are loaded into memory (e.g., L1 / L0 – such as (one or more) SRAM memories); furthermore, in this embodiment, a format conversion circuitry is employed to convert the input data (D D The data format of the filter weights (Fkl) is converted from a first data format (e.g., floating-point data format or fixed-point data format (e.g., integer or block-scaled fractional data format)) to a logarithmic data format to facilitate processing in the LAC of the execution pipeline;

[0018] Figure 1BThe illustration shows a schematic block diagram of an exemplary logic overview of an exemplary logarithmic adder-accumulator circuit system (sometimes also referred to as a "logarithmic adder-accumulator circuit system") according to an embodiment of the present invention. The logarithmic adder-accumulator circuit system includes a logarithmic adder circuit system ("MUL") that performs logarithmic addition operations on both input data and filter weights in logarithmic data format, and an accumulator circuit system ("ADD") that performs accumulation / addition operations in floating-point data format. In this embodiment, a data format conversion circuit system is used to convert the input data / values ​​into logarithmic data formats (FPxx to LLxx (e.g., FP24 to L...). L16); and, moreover, a data format conversion circuit system is used to convert the output of the logarithmic adder circuit system from logarithmic data format to floating-point data format to facilitate additional data processing of the exemplary logarithmic adder-accumulator circuit; here, the output data / value (and data) of the logarithmic adder circuit system in logarithmic data format is converted or transformed into a different data format (e.g., the initial data format, such as floating-point or fixed-point format—although in some embodiments the bit length may be changed) for subsequent processing; it is worth noting that although this illustrative block diagram provides bit precision for data and operations, such bit precision is exemplary and not applicable to the present invention. No Limited to (i) logarithmic data formats (LLxx, where xx is an integer), floating-point formats (FPxx, where xx is an integer), fixed-point formats (e.g., block-scaled fractional data format "BSF"), block / data width, data path width, bandwidth, and / or specific bit precision of values, (ii) exemplary logical or physical overview configurations of specific circuit systems and / or overall pipelines, and / or (iii) exemplary module / circuit system configurations and / or pipeline architectures; in fact, in one embodiment, an exemplary logarithmic adder-accumulator circuit may include two dedicated memory groups (i.e., group 0 and group 1) to store at least two different sets of filter weights—each set of filter weights is associated with and used to process a set of data), wherein each memory group may be alternately read to process a given set of associated data and alternately written to after processing a given set of associated data in preparation for subsequent processing (e.g., the next set of associated data);

[0019] Figure 1CThe illustration depicts a high-level block diagram layout of an integrated circuit or portion thereof (sometimes referred to as an "X1 component") comprising multiple multi-bit LAC execution pipelines according to certain aspects of the present invention. The multi-bit LAC execution pipelines have multiple logarithmic adder-accumulator circuit systems, each implementing logarithmic addition and accumulation operations. The multi-bit LAC execution pipelines and / or the multiple logarithmic adder-accumulator circuits can be configured to implement one or more processing architectures or technologies (single / alone or in combination with one or more X1 components). In one embodiment, the multi-bit LAC execution pipelines are organized into clusters (in this illustrative embodiment, four clusters, each cluster comprising multiple multi-bit LAC execution pipelines (in this illustrative embodiment, each cluster comprises 16 64-LAC execution pipelines (hereinafter also referred to individually as LAC processors)); in one embodiment, multiple logarithmic adder-accumulator circuitry systems are configurable or programmable (once or multiple times, e.g., at startup and / or in situ) to implement one or more pipelined processing architectures or techniques (see, for example, the lower right corner). Figure 1C An extended view of a portion of the high-level block diagram is a single LAC execution pipeline (in the illustrative embodiment, including, for example, a system of 64 logarithmic adder-accumulator circuits (“LAC”) – also referred to as an LAC processor), which is a schematic block diagram of the logic overview of an exemplary logarithmic adder-accumulator circuit system arranged in a linear execution pipeline configuration (-see Figure 1A(Related); The processing components in this illustrative embodiment include: memory (e.g., L2 memory, L1 memory, and L0 memory (e.g., SRAM)), bus interfaces (e.g., PHY and / or GPIO), circuitry for facilitating communication with external circuitry for the components and for use by the circuitry for storing and supplying the components (e.g., SRAM and DRAM), and a plurality of switches / multiplexers electrically interconnected to form a switch interconnect network “Network on Chip” (“NOC”) to facilitate the interconnection of clusters of logarithmic adder-accumulator circuitry for LAC execution pipelines; in one embodiment, the NOC includes a switch interconnect network (e.g., a hybrid mode interconnect network (i.e., a hierarchical switch matrix interconnect)). The network and interconnects such as meshes, tori, etc. (hereinafter collectively referred to as "mesh networks" or "mesh interconnects"), associated data storage circuitry, input pins, and / or lookup tables (LUTs) that determine the operation of switches / multiplexers when programmed; in one embodiment, one or more (or all) clusters include one or more computing circuitry (e.g., multiple logarithmic adder-accumulator circuitry systems - labeled "NMAX rows" - see, for example, '345 application, where the logarithmic adder circuitry system is a substitute for a multiplier circuitry system in addition to the data formatting circuitry system); notably, in one embodiment, each LAC executes a pipeline (in one embodiment, consisting of multiple serially interconnected logarithmic adder-accumulator circuitry) connected to... The associated L0 memory (e.g., SRAM memory) is connected to a dedicated L0 memory for that processing pipeline; the associated L0 memory stores the filter weights used by the logarithmic adder-accumulator circuitry of each logarithmic adder-accumulator circuit of that particular LAC processing pipeline when performing logarithmic addition operations, wherein each LAC processing pipeline of a given cluster is connected to the associated L0 memory (in one embodiment, it is dedicated to the logarithmic adder-accumulator circuitry of that LAC processing pipeline – 64 LACs in this illustrative embodiment); multiple (e.g., 16) LAC execution pipelines of the LAC cluster (and in particular the L0 memory of each LAC execution pipeline in the cluster) are coupled to the associated L0 memory. L1 memory (e.g., SRAM memory); here, the associated L1 memory is connected to and shared by each LAC execution pipeline in the cluster to receive filter weights stored in the L0 memory associated with each LAC execution pipeline in the cluster; in one embodiment, the associated L1 memory is assigned and dedicated to multiple pipelines of the LAC cluster; notably, the move-in and move-out paths of each 64-LAC execution pipeline are coupled to L2 memory (e.g., SRAM memory), wherein the L2 memory is also coupled to L1 memory and L0 memory; the NOC couples the L2 memory to the PHY (physical interface), which may be connected to L3 memory (e.g., external DRAM);The NOC is also coupled to a PCIe or PHY, which in turn can provide interconnection or communication with circuitry outside the X1 processing components (e.g., external processors, such as processors in a host computer); in one embodiment, according to one or more aspects of the invention, the NOC can also connect to multiple X1 components (e.g., via GPIO input / output PHYs), which allow multiple X1 components to process associated data (e.g., image data), as discussed herein;

[0020] Figure 1D An exemplary schematic block diagram illustrates an exemplary logic overview of an exemplary multiplier-accumulator circuit and an exemplary logarithmic adder-accumulator circuit system (sometimes referred to as a "logarithmic adder-accumulator circuit system");

[0021] Figure 1E The illustration shows a schematic block diagram of an exemplary logic overview of an exemplary logarithmic addition-accumulation execution or processing circuit according to an embodiment of the present invention, including a logarithmic addition circuit system (MUL) that performs operations in a 16-bit logarithmic data format (LL16 MUL), a format conversion circuit system that converts or transforms the logarithmic data format (and data) to, for example, a floating-point data format, and an accumulator circuit system (ADD) that performs the accumulation / addition operation, in one embodiment in a 24-bit floating-point format (FP24). (ADD); It is worth noting that the bit width of the processing circuitry and operations is exemplary - that is, in this illustrative embodiment, the data and filter weights are in a 16-bit logarithmic data format (LL16), wherein the conversion circuitry can change or modify (e.g., increase or decrease) the bit width of the input data and filter weights; As indicated above, the logarithmic adder circuitry and the floating-point accumulator perform operations in 16-bit (LL16) and 24-bit floating-point data formats (FP24), respectively; Other floating-point formats or width precisions are also applicable (e.g., 8, 16, and 32 bits); As mentioned above, in one embodiment, the precision / format adopted by the logarithmic adder circuitry and / or the floating-point accumulator may depend on the available / allocated memory bandwidth, the available / allocated wiring bandwidth, and / or, for example, the amount of area within the integrated circuit available / allocated to the floating-point circuitry for storing, transferring / reading, and / or processing data (e.g., partially processed and unprocessed data); It is worth noting that the invention can be implemented via floating-point execution circuitry that can be configured with the same precision width or different precision widths / formats;

[0022] Figure 1F and 1G The illustration depicts an exemplary logarithmic adder-accumulator execution or processing pipeline according to certain embodiments of the present invention (see [link]). Figure 1A and 1CA schematic block diagram outlining an exemplary logic of ), wherein each logarithmic adder-accumulator circuit includes a logarithmic adder circuit system that operates in logarithmic data format and / or an accumulator circuit system that operates in floating-point format; in one embodiment, in Figure 1F In one embodiment, a data format conversion circuit system is used to convert the input data into a logarithmic data format (FPxx to LLxx (e.g., FP24 to LL16); in another embodiment, in Figure 1G In this embodiment, a data format conversion circuitry system converts the input data and filter weights into a logarithmic data format (FPxx to LLxx (e.g., FP24 to LL16 and FP8 to LL16)); in these exemplary embodiments, the logarithmic adder-accumulator circuitry may include multiple memory banks (e.g., SRAM memory banks) dedicated to the logarithmic adder-accumulator circuitry to store the filter weights used by the associated logarithmic adder-accumulator circuitry system; in one illustrative embodiment, the LAC execution or processing pipeline includes 64 logarithmic adder-accumulator circuits (see...). Figure 1A and 1C It is worth noting that, in this logical overview of the linear pipeline configuration of this exemplary logarithmic adder-accumulator execution or processing pipeline, multiple processing (LAC) circuitry systems (“p”) are connected in the execution pipeline and operate concurrently; for example, in an exemplary embodiment where p = 64, the logarithmic adder-accumulator processing circuitry performs 64 x 64 logarithmic adder-accumulator operations in every 64-cycle interval; thereafter, during the same 64-cycle interval, the next 64 input pixels / data are shifted in while the previous output pixels / data are shifted out; it is worth noting that, in one embodiment, each logarithmic adder-accumulator circuitry may include two dedicated memory banks to store at least two different sets of filter weights (each set of filter weights is associated with and used to process a set of data), wherein each memory bank may be alternately read for processing a given set of associated data and alternately written after processing a given set of associated data; the filter weights or weight data are loaded from, for example, external memory or the processor into memory (e.g., L1 / L0) before the start of stage processing. In SRAM memory (e.g., see '345 application); it is worth noting that the logarithmic adder-accumulator circuitry and circuitry system of the present invention can be interconnected or implemented in one or more logarithmic adder-accumulator execution or processing pipelines, including, for example, the execution or processing pipelines associated with the MAC processing pipeline described and / or illustrated in U.S. Provisional Patent Application No. 63 / 012,111; '111 application is incorporated herein by reference in its entirety; as noted above, LAC and LAC pipelines replace MAC and MAC pipelines in the exemplary processing pipelines described and / or illustrated in '111 application;

[0023] Figure 1H The illustration shows a schematic block diagram of an exemplary logic overview of an exemplary logarithmic adder-accumulator circuit according to an embodiment of the present invention, comprising a logarithmic adder circuit system (“MUL”) that performs logarithmic addition operations on input data and filter weights both in logarithmic data format, and an accumulator circuit system (“ADD”) that performs accumulation / addition operations, for example, in this embodiment, in floating-point data format; in this embodiment, a data format conversion circuit system is used to convert the input data and filter weights into logarithmic data formats (FPxx to LLxx (e.g., FP24 to LL16, FP8 to LL16)). Furthermore, a format conversion circuit system is employed to convert the output of the logarithmic adder circuit system from logarithmic data format to floating-point data format to facilitate additional data processing of the exemplary logarithmic adder-accumulator circuit; here, the output data / value (and data) of the logarithmic adder circuit system in logarithmic data format is converted or transformed into a different data format (e.g., the initial data format, such as floating-point or fixed-point format - although the bit length may be changed in some embodiments) for subsequent processing; it is worth noting that although this illustrative block diagram provides bit precision for data and operations, such bit precision is exemplary, and the present invention No Limited to (i) specific bit precision of logarithmic data formats (LLxx, where xx is an integer), floating-point formats (FPxx, where xx is an integer), fixed-point formats (e.g., block-scaled fractional data format "BSF"), block / data width, data path width, bandwidth and / or specific bit precision of values, (ii) exemplary logical or physical overview configurations of specific circuit systems and / or overall pipelines, and / or (iii) exemplary module / circuit system configurations and / or pipeline architectures;

[0024] Figure 2AThe illustration shows a schematic / flowchart of an exemplary data format conversion circuit system with a lookup table according to certain aspects of the present invention. The lookup table stores pre-computed and / or encoded values ​​that make data / values ​​(in this exemplary embodiment, in floating-point data format) equivalent to "equivalent" values ​​in logarithmic data format. Here, for each data / value, an appropriate output value is pre-computed (and encoded) and compiled into the format conversion lookup table (using the y = LOG2(x) calculation technique), and then stored in memory (e.g., non-volatile read-only memory, such as ROM or flash memory). In this illustrative embodiment, the lookup table includes floating-point data format (specifically FP16) and logarithmic data format (specifically...). The correlation between LL16 and FP16 can be used; the contents of the table can be pre-calculated using any circuit system and / or technology now known or developed later; it is worth noting that the exponent field “E” in LL16 and FP16 formats is similar - it is the bias value, representing the integer value of the exponent base of the number (i.e., “2^(E-Ebias)”), where the “E-Ebias” value is the logarithm of the integer of the number to base 2; moreover, the standard floating-point format mixes this integer logarithm in the E field with the binary fraction (also called the mantissa or significant number) in the F field to (approximately) represent the true number, and the logarithmic floating-point format mixes the integer logarithm in the E field with the fractional logarithm in the G field to (approximately) represent the true number;

[0025] Figure 2BThe illustration shows a schematic / flowchart of another exemplary data format conversion circuit system for converting data / values ​​from floating-point data format to logarithmic data format according to certain aspects of the present invention. The conversion circuit system includes a lookup table storing pre-computed and / or encoded values ​​that make the data / value (in this exemplary embodiment, having a floating-point data format) equivalent to an "equivalent" data value having a logarithmic data format (using the y = LOG2(x) calculation technique). In this exemplary embodiment, for each data / value, the "equivalent" value is pre-computed (and encoded) and stored in memory (e.g., a non-volatile read-only memory, such as ROM or flash memory) in the form of a format conversion lookup table. In this illustrative embodiment, the lookup table contains both floating-point data format (specifically FP24) and logarithmic data format (specifically LL). The correlation between 16) can be calculated in advance using any circuit system and / or technology now known or developed later; in this embodiment, the fractional field (F) is rounded via rounding logic (here, from 15-bit values ​​to 7-bit values); it is worth noting that the exponent field “E” in LL16 and FP16 formats is similar - it is a bias value, representing the integer value of the exponent base of the number (i.e., “2^(E-Ebias)”), where the “E-Ebias” value is the logarithm of the integer of the number to base 2; moreover, the standard floating-point format mixes this integer logarithm in the exponent field with the binary fractional part (also called the mantissa or significant number) in the fractional field “F” to represent or approximate the true number, and the logarithmic floating-point format mixes the integer logarithm in the exponent field with the fractional logarithm in the logarithmic value field “G” to represent the true number;

[0026] Figure 3A , 3C The diagrams and 3D illustrations respectively depict schematic / flowcharts and corresponding circuit block diagrams of exemplary data format conversion circuit systems according to certain aspects of the present invention, wherein the logic circuit system uses the y = LOG2(x) calculation technique to convert or transform data / values ​​(input) having a floating-point data format into data / values ​​(output) having a logarithmic floating-point data format; in this embodiment, the fractional field (F) of the data / value is adjusted by logic gates and multiplexers (mux blocks); in the FP16 to LL16 conversion circuit system, the conversion of the fractional field uses approximately 30 logic gates for converting the value of the field into a logarithmic floating-point data format. Figure 3A logic blocks and Figure 3C In the logic 1), an x-bit adder (add or ADD block) and an x-bit multiplexer (e.g., x = 7, see...). Figure 3C It is worth noting that, Figure 3C The embodiment of the data format conversion circuit system shown is Figure 3AThe circuit block diagram implementation of the data format conversion block diagram shown here—implements the y = LOG2(x) calculation method to provide a data conversion with a medium level of precision from floating-point data format to logarithmic floating-point data format; similarly, Figure 3D The embodiment of the data format conversion circuit system shown is Figure 3A The circuit block diagram implementation of the data format conversion block diagram shown - implements the y = LOG2(x) calculation method to provide a high level of precision data conversion from floating-point data format to logarithmic floating-point data format (i.e., relative to...). Figure 3C The embodiments shown have a higher level of accuracy; in one embodiment, Figure 3D The level of precision is 32 or 64 bits from floating-point data format to logarithmic data format; the result is that the converted value can be correctly rounded to the target format.

[0027] Figure 3B The illustration shows a schematic / flowchart of an exemplary data format conversion circuit system according to certain aspects of the present invention, wherein the logic circuit system uses the y = LOG2(x) calculation technique to convert or transform data / values ​​(input) having a floating-point data format into data / values ​​(output) having a logarithmic floating-point data format; in this embodiment, the fractional field (F) of the data / value is rounded via rounding logic (here, from a 15-bit value to a 7-bit value) and adjusted using logic gates and multiplexers (mux blocks); in the FP24 to LL16 conversion circuit system, the conversion of the fractional field uses logic to convert the value of the field into a logarithmic floating-point data format; it is worth noting that, as Figures 3A-3D As an addition to or alternative to computing techniques, the present invention may also employ extrapolation techniques to convert data formats from floating-point data formats to logarithmic floating-point data formats.

[0028] Figure 4A and 4B Schematic / flowcharts and corresponding circuit block diagrams of exemplary data format conversion circuit systems according to certain aspects of the present invention are illustrated, wherein the logic circuit system converts or transforms data / values ​​(inputs) having a logarithmic data format and a first bit length into data / values ​​(outputs) having a logarithmic floating-point data format and a second bit length; in one embodiment, the conversion circuit system shown herein can be used to convert filter weights or coefficients of a logarithmic data format (e.g., LL8 – an 8-bit logarithmic data format having a sign (1 bit), exponent (3 bits), and fraction (4 bits)) into filter weights or coefficients of a logarithmic data format having a larger dynamic range and precision (e.g., LL8 – a 16-bit logarithmic data format having a sign (1 bit), exponent (8 bits), and fraction (7 bits)); this conversion technique is performed via a logic circuit system, a y-bit adder, and one or more multiplexers (see...). Figure 4BThis approximately doubles the number of digits in the exponent and fraction fields of the LL8 input format; it is worth noting that the three result fields may also require special values, operands, or characters to be replaced by the line substitution of the multiplexer; moreover, the multiplexer selects between three (3) substitution conversions specified as “x” logarithmic data format (LL8x), “y” logarithmic data format (LL8y), and “z” logarithmic data format (LL8z);

[0029] Figures 5A-5C Schematic / flowcharts and corresponding circuit block diagrams of exemplary logarithmic adder / adder circuit systems according to certain aspects of the present invention are illustrated, wherein the circuit system receives two operands / values ​​(input - in this illustrative example, image / input data and filter weights / coefficients) each having a logarithmic data format, and adds the operands / values ​​to generate a sum-or result (output); in this embodiment, the sign field of the input is XORed, the values ​​of the exponent fields are added (incremented if rounding causes fraction overflow), and the two fraction fields (in logarithmic form) are added together (via two's complement) - in this embodiment, a 7-bit fixed-point adder is used; it is worth noting that Figure 5B The diagram shows... Figure 5A The detailed exemplary circuit block diagram of the logarithmic adder circuit system shown is as follows: Figure 5C Provided Figure 5B Details of some of the logic blocks shown (see “Logic 1”, “Logic 2”, and “Logic 3”); Figure 5B The logarithmic addition circuit system (GA+GB) shown can be replaced or supplemented by a circuit system that implements other functions (such as reciprocals, square roots, power functions), wherein other operations or functions can be implemented after the operands are in logarithmic data format (for example, division A / B can be performed by executing GA-GB (along with subtraction of exponents EA-EB, instead of addition EA+EB for multiplication)).

[0030] Figure 6A The illustration shows a schematic / flowchart of an exemplary data format conversion circuit system according to certain aspects of the present invention. This circuit system has a lookup table that stores pre-computed and / or encoded values ​​that make data / values ​​in a logarithmic data format equivalent to "equivalent" values ​​in another data format (in this exemplary embodiment, a floating-point data format); here, for each data / value, an appropriate output value is pre-computed (and encoded) and compiled into the format conversion lookup table (using y = 2). xThe data is computed and then stored in memory (e.g., non-volatile, read-only memory, such as ROM or flash memory); in this illustrative embodiment, the lookup table contains a correlation between logarithmic data format (specifically LL16) and floating-point data format (specifically FP16); the contents of the table can be pre-computed using any circuitry and / or technology now known or developed in the future;

[0031] Figure 6B The illustration shows a schematic / flowchart of an exemplary data format conversion circuit system according to certain aspects of the present invention, wherein the logic circuit system uses y=2 x The computing technique converts or transforms data / values ​​(input) with logarithmic data format into data / values ​​(output) with floating-point data format; in this embodiment, the fractional field (G) of the data / value is adjusted using logic gates, adders (add blocks), and multiplexers (mux blocks).

[0032] Figure 6C-6E The diagram shows... Figure 6B A schematic / flowchart circuit block diagram of an exemplary data format conversion circuit system, wherein each circuit block diagram provides a different level of accuracy; in one embodiment ( Figure 6C A medium-precision LL16 to FP16 conversion circuit system can be implemented using, for example, approximately 30 logic gates, an x-bit adder, and an x-bit multiplexer (e.g., x = 7) to achieve fractional domain conversion; in another embodiment ( Figure 6D ), has more Figure 6C In one embodiment, a higher-precision LL16 to FP16 conversion circuit system can be implemented using the y = 2^x calculation technique; in one embodiment ( Figure 6E The accuracy level of the conversion from LL16 to FP16 via the conversion circuit system is greater than that of... Figure 6C and 6D In one embodiment, the logarithmic data format to floating-point format conversion circuitry provides a level of precision for the data conversion from logarithmic data format to floating-point data format (here, y = 2^x is calculated) - for example, 32-bit or 64-bit precision; as described above, the present invention can employ any data format conversion circuitry or method to convert, modify, expand / shrink and / or adapt the data format of image / input data to a logarithmic data format now known or later developed - all of which are intended to fall within the scope of the present invention;

[0033] Figure 7The illustrations depict exemplary floating-point data formats with different widths or lengths (including corresponding ranges), and exemplary logarithmic data formats with different widths or lengths (including corresponding ranges), wherein the logarithmic data formats are “equivalent” to the floating-point data formats; it is worth noting that these three logarithmic data formats use a signed magnitude numeric format for the sign field S and the fraction field G, wherein the highest weight of the fraction field G is 0.5 and there are no hidden (implicit) bits, so it includes non-normalized values; the exponent field is a two's complement numeric format with an added bias of 127; the minimum and maximum exponent values ​​are reserved for special operands or characters (NAN, INF, DNRM, ZERO);

[0034] Figure 8 The diagram illustrates an exemplary numeric space for the logarithmic data format (LL16), where the minimum and maximum exponents E[7:0] are reserved for special operands (NAN, INF, ZRO); NAN values ​​are generated when an undefined operation (0*∞ or ∞-∞) occurs; ±INF values ​​are saturation values ​​for exponent overflow; and ±ZRO values ​​are saturation values ​​for exponent underflow. EXP[7:0] = 8'b00000000) shows the binade corresponding to the DNRM values ​​in the floating-point data format (FP16), where its response is the same as the other binades except that G[1:7] = 7'b0000000 is reserved for ZRO;

[0035] Figure 9A The illustrations illustrate exemplary encoding techniques for a logarithmic data format (LL8y) having a 1-bit sign field (S), a 3-bit exponent field (E), and a 4-bit fraction field (F) according to certain embodiments of the present invention, such as those implemented in conjunction with certain data (e.g., filter weights / coefficients) – for example, related to implementations of conversion circuitry systems employing lookup tables; it is noteworthy that similar or corresponding lookup tables related to other logarithmic data formats (e.g., LL8x and LL8z) can be employed, provided, and / or generated;

[0036] Figure 9B and 9C The illustrations depict portions of the selection of encoding techniques for the logarithmic data format (LL8y) according to embodiments of certain aspects of the present invention, such as... Figure 9A Identified in the middle;

[0037] Figure 10AThe illustration depicts an exemplary encoding technique for a logarithmic data format (LL8y) having a 1-bit sign field (S), a 3-bit exponent field (E), and a 4-bit fraction field (F), implemented as in conjunction with certain data (e.g., filter weights / coefficients) in some embodiments of the invention—for example, related to a data format conversion circuitry system for implementing a lookup table; in this illustration, according to one embodiment of the invention, the exemplary floating-point format (LL8y) includes (e.g., dynamically) configurable range and precision; notably, the “permissible” number space depicted below the horizontal line of the logarithmic data format LL16 is graphically represented in relation to the logarithmic data formats LL8x, LL8y, and LL8z; the range and precision of LL8y include the central four binades ( The LL8y format has the same precision (4 bits) as the FP8 format (-2 to +2). However, unlike FP8, the precision of the LL8y format decays symmetrically; it has zero bits of precision (single value) in the three bindes from -11 to -8 and the two bindes from +8 to +10. The symmetrical decay of LL8y is similar to the decay seen in the distribution of data weight values ​​used in image filtering applications. In contrast, the INT8 format decays in the bindes in the negative direction but has hard edges in the width of the bindes in the positive direction. The LL8x format is depicted, in which it has one more bit of precision (5 bits) than the LL8y format in the two middle bindes (-1 to +1). Like LL8y, the precision of the LL8x format decays symmetrically. Zero precision (single value) exists in binades from -5 to -6 and +5; additionally, the LL8z format is described, where its precision in the eight central binades (-4 to +4) is one bit less than that of the previously discussed LL8y format (3 bits); like the LL8y format, the precision of the LL8x format decreases symmetrically; furthermore, zero precision (single value) exists in binades from -19 to -12 and binades from +12 to +18; it is worth noting that the main advantage of the set of three floating-point formats (LL8x, LL8y, LL8z) is that they provide a variety of alternative implementations / executives that offer variations in range and precision; this can reduce rounding and saturation errors when using data values;

[0038] Figure 10B The diagram illustrates the "permissible" numeric space below the horizontal line depicting the logarithmic data format LL16, as shown below. Figure 10A As shown, and the INT8 format including attenuation of the binade in the negative direction but hard edges in the width of the binade in the positive direction, such as Figure 10A As shown;

[0039] Figure 10C-10E The diagram shows... Figure 10AThe graphical representation of the logarithmic data formats LL8x, LL8y, and LL8z shown is illustrated; it is worth noting that... Figure 10C (relative to) Figure 10A The encoding techniques used for the logarithmic data format LL8x will be isolated to provide greater clarity. Figure 10D (relative to) Figure 10A The encoding techniques used for the logarithmic data format LL8y are isolated to provide greater clarity, and Figure 10E (relative to) Figure 10A The encoding techniques used for the logarithmic data format LL8z will be isolated to provide greater clarity;

[0040] Figure 11 The illustration shows the special operand or character SD / ED / GD fields of a logarithmic addition circuit system according to various aspects of the present invention; it is noteworthy that the details of the SD / ED / GD fields for interactive cases are illustrated in three 4x4 tables, each of which includes four cases {ZRO, NRM, INF, NAN} for each operand, where operand A is along the horizontal axis and operand B is along the vertical axis; here, the three tables include, from left to right, the sign SD, exponent ED[7:0] and fraction GD[0:7] of the result / output of the logarithmic addition circuit system for these different values ​​of A and B operands;

[0041] Figure 12A The illustration shows a schematic block diagram of an exemplary logic overview of an exemplary processing circuit including a logarithmic adder-accumulator circuit system and a multiplier-accumulator circuit system according to an embodiment of the present invention. The exemplary processing circuit system is configurable to implement logarithmic addition and accumulation (LAC) operations and multiplication and accumulation (MAC) operations. Notably, the mode selection circuit system can generate and emit a mode or mode control signal “MODE” to select or enable which processing format option to use in the filtering operation / application. When LAC is enabled / selected, the logarithmic adder-accumulator circuit... The system and data path perform or implement logarithmic addition and accumulation operations, while the multiplier-accumulator circuitry and data path perform or implement multiplication and accumulation operations when MAC is enabled / selected; by controlling, determining, or enabling the processed data path to include the logarithmic adder-accumulator circuitry or the multiplier-accumulator circuitry, the mode selection circuitry can responsively control (i.e., enable and / or disable) the operability of the logarithmic adder-accumulator circuitry and the multiplier-accumulator circuitry to select the circuitry used to process, for example, image data related to inference operations; and

[0042] Figure 12BThe illustration shows a schematic block diagram of another exemplary logic overview of an exemplary processing circuit including a logarithmic adder-accumulator circuit system and a multiplier-accumulator circuit system according to an embodiment of the present invention. The exemplary processing circuit system is configurable to implement logarithmic addition and accumulation (LAC) operations and multiplication and accumulation (MAC) operations, and includes a conversion circuit system that converts the data format of the input data / values ​​and filter weights from floating-point data format to logarithmic data format. Notably, the mode selection circuit system can generate and emit a mode or mode control signal "MODE" to select or enable which processing format option to use in the filtering operation / application. When LAC is enabled / selected, the data format conversion circuit system converts the input data and filter weights into a logarithmic data format (FPxx to LLxx (e.g., FP24 to LL16 and FP8 to LL16)). The logarithmic adder-accumulator circuitry and data path perform or implement logarithmic addition and accumulation operations; and wherein when the MAC is enabled / selected via a mode selection signal, the multiplier-accumulator circuitry and data path perform or implement multiplication and accumulation operations, and no data format conversion circuitry is employed; by controlling, determining, or enabling the processed data path to include the logarithmic adder-accumulator circuitry or the multiplier-accumulator circuitry, the mode selection circuitry can responsively control (i.e., enable and / or disable) the operability of the logarithmic adder-accumulator circuitry and the multiplier-accumulator circuitry to select the circuitry employed to process, for example, input data / values ​​related to inference operations (e.g., image data); it is worth noting that, in addition, unselected or disabled circuitry (e.g., LAC or MAC) can also be electrically disabled to, for example, reduce and / or minimize power consumption and spurious noise.

[0043] Again, this document describes and illustrates numerous inventions. The invention is not limited to illustrative exemplary embodiments, but includes those relating to: (i) a particular floating-point data format (one or more), a particular fixed-point data format (one or more), a particular logarithmic data format, block / data width or length, data path width, bandwidth, value, process, and / or algorithm, or (ii) exemplary logical or physical overview configurations, exemplary circuit system configurations, and / or exemplary Verilog code. In fact, while several exemplary embodiments and features of the invention are illustrated in the context of floating-point data formats (e.g., FP16 or FP24) and logarithmic data formats (e.g., LL8 or LL16), embodiments and inventions are applicable to other precisions (e.g., FPxx, where: 8 ≤ xx ≤ 39, and LLxx, where: 8 ≤ xx ≤ 24). For the avoidance of doubt, the precision of the data formats need not be equal. Moreover, for the sake of brevity, precisions other than those described and / or illustrated herein are intended to fall within the scope of the invention and will be readily apparent to those skilled in the art based on, for example, this application.

[0044] This invention is neither limited to any single aspect or embodiment thereof, nor to any combination and / or substitution of such aspects and / or embodiments. Each aspect and / or embodiment of the invention may be used alone or in combination with one or more other aspects and / or embodiments of the invention. For the sake of brevity, many of those combinations and substitutions are not discussed or described separately herein. Detailed Implementation

[0045] In a first aspect, the present invention relates to the integration (and methods of operating such circuitry) of one or more logarithmic adder-accumulator circuitry systems, wherein input data (e.g., image data) is processed at least in part based on a logarithmic data format, for example, in relation to inference operations. In one embodiment, the invention includes, for example, multiple logarithmic adder-accumulator circuits (sometimes also referred to as “logarithmic adder-accumulator circuits”) interconnected in series to pipeline logarithmic addition and accumulation operations. A data format conversion circuitry system can be used to convert or transform input data having a first or initial data format (e.g., floating-point or fixed-point data format) to a logarithmic data format (e.g., having a base of 2) – in cases where the data is not in a logarithmic data format. In one embodiment, after processing the input data and performing logarithmic addition incorporating filter weights, the data format conversion circuitry system converts or transforms the data to a different data format (e.g., the initial data format, such as floating-point format) for subsequent processing. In one embodiment, the data format conversion circuitry changes, transforms, and / or converts the data format of the input data / values ​​by remapping the value of the fractional field of each input data / value from floating-point data format to the logarithm of the value of the fractional field, and remapping the value of the fractional field of each sum data from logarithmic data format to floating-point data format after a logarithmic addition operation.

[0046] For example, in operation, image data in logarithmic data format is added to image filter weights or coefficients that are also in logarithmic data format (e.g., with a base of 2). The filter weights or coefficients used in image data processing can be stored in memory in logarithmic data format or in a different format and converted or transformed to logarithmic data format before processing (e.g., immediately before processing). After logarithmic addition, the processed image data can be converted or transformed to another / different data format (e.g., floating-point or fixed-point format—e.g., back to the input data format—however, the length of the values ​​can be the same or different) for additional / further processing.

[0047] On the other hand, the present invention relates to one or more integrated circuits comprising multiple execution or processing pipelines (and methods of operating such circuits), the execution or processing pipelines having a logarithmic adder-accumulator circuit system that processes data based on a logarithmic data format, for example, to generate processed image data. For example, each execution or processing pipeline includes multiple logarithmic adder-accumulator circuits to process the data, for example, as discussed above. In one embodiment, in operation, image data (which may be in a floating-point data format) is provided to multiple execution or processing pipelines, each pipeline including multiple logarithmic adder-accumulator circuits. Here, the data (e.g., image data having a floating-point or fixed-point data format) is initially converted or transformed into a logarithmic data format (via a format conversion circuit system), and then the data is added to associated image filter weights or coefficients (which are in or have been converted / transformed into a logarithmic data format) via a logarithmic adder / adder circuit system of multiple logarithmic adder-accumulator circuit systems. In one embodiment, the output (i.e., sum data) of the logarithmic adder / adder circuitry is applied to or provided to a format conversion circuitry to convert or transform the logarithmic data format from the sum / output of the logarithmic adder / adder circuitry into a different data format—for example, a data format that facilitates subsequent processing by the processing circuitry or is consistent with subsequent processing by the processing circuitry (e.g., floating-point data format). In this regard, the sum / output of the logarithmic adder-accumulator circuitry in floating-point data format can then be further processed via an accumulator circuitry system of multiple logarithmic adder-accumulator circuitry systems to implement the accumulation operation of the processing circuitry system. The accumulator circuitry system accumulates multiple associated partially processed image data, for example, data associated with inference operations. It is noteworthy that multiple execution or processing pipelines can operate simultaneously.

[0048] In another aspect, the present invention relates to one or more integrated circuits having circuitry for implementing logarithmic addition and accumulation operations as well as multiplication and accumulation operations. Here, the one or more integrated circuits include a logarithmic adder-accumulator circuitry for performing logarithmic addition and accumulation operations (e.g., as discussed herein) and a multiplier-accumulator circuitry for performing multiplication and accumulation operations (e.g., as discussed in detail below). One or more of the integrated circuits may include a mode selection circuitry to control (i.e., enable and / or disable) the operability and / or operation of the logarithmic adder-accumulator circuitry and the multiplier-accumulator circuitry to select circuitry for processing, for example, image data associated with inference operations. In this respect, the mode selection circuitry controls or determines the data processing and the circuitry employed therein, including the logarithmic adder-accumulator circuitry or the multiplier-accumulator circuitry.

[0049] In one embodiment, the mode selection circuitry may be programmable once; in another embodiment, it may be programmable more than once (i.e., multiple times). The mode selection circuitry may be programmed, for example, in situ (i.e., during operation of the integrated circuit), at manufacturing time, and / or during or after power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc. For example, the mode selection circuitry may receive a mode selection signal from an internal or external circuitry (i.e., outside one or more integrated circuits—e.g., a host computer / processor) including one or more data storage circuitry (e.g., one or more memory cells, registers, flip-flops, latches, blocks / arrays of memory), one or more input pins / conductors, a lookup table (LUT) of any type, a processor or controller, and / or discrete control logic. In response, the mode selection circuitry may employ one or more such signals to enable or disable the selected processing circuitry (as applicable), thereby enabling one of the processing modes (i.e., logarithmic addition and accumulation or multiplication and accumulation) in situ and / or during or after power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc.

[0050] As described above, in one aspect, the present invention relates to one or more integrated circuits (and methods of operating such circuit systems) having logarithmic adder-accumulator circuit systems, in one embodiment including multiple execution or processing pipelines, each having multiple logarithmic adder-accumulator circuit systems. For example, refer to... Figure 1A-1CIn one embodiment of the invention, a logarithmic adder-accumulator circuitry (“LAC”) is implemented in an execution pipeline. In an exemplary embodiment, “m” (e.g., 64 processing circuits in the illustrative embodiment) LAC processing circuits in the execution pipeline perform logarithmic addition and accumulation operations, whereby the processing circuits perform m x m (e.g., 64 x 64) logarithmic adder-accumulator operations every r (e.g., 64) cycle intervals (here, the cycle may nominally be 1 ns). In operation, input pixels / data (Do – e.g., 64) are output from memory (illustrated as L2 SRAM in this embodiment) to a format conversion circuitry that converts or transforms the data format of the input pixels / data (Do) into a logarithmic data format (e.g., having a base of 2), and then outputs the input pixels / data (Do) to the circuitry of the execution pipeline. Furthermore, the filter weights or coefficients are output from memory (illustrated as L2 in this embodiment) to a format conversion circuitry that converts or transforms the filter weights' data format into a logarithmic data format (e.g., with a base of 2), and then outputs the filter weights in logarithmic data format to memory (illustrated as L1 SRAM in this embodiment) for access by the execution pipeline during logarithmic addition and accumulation operations. In one embodiment, in addition to converting the filter weights' data format to logarithmic data format, or instead (e.g., if the filter weights are already in logarithmic data format), the data format conversion circuitry may also adjust the length of the filter weights from 8 bits to 16 bits.

[0051] In this exemplary embodiment, the execution or processing pipeline moves in new input pixels / data (e.g., 64) and removes previous output pixels / data (Y) during the same m (e.g., 64) cycle intervals. D It is worth noting that every m (e.g., 64) cycle intervals, the input and output pixels / data of the Dd / Yd (depth) column at a specific (i,j) position (index of the width Dw / Yw and height Dh / Yh dimensions) are processed. For each Dw*Dh depth column in this stage, the m (e.g., 64) cycle intervals are repeated.

[0052] In this exemplary embodiment, the filter weights or coefficients, after being converted to a logarithmic data format via a format conversion circuitry, are stored or loaded into memory (e.g., L1 / L0 SRAM memory) before the LAC circuitry initiates processing of the input data / values. In this particular example, the input stage has Dw = 512, Dh = 256, and Dd = 128, and the output stage has Yw = 512, Yh = 256, and Yd = 64. Note that in each 64x64 LAC execution step, only 64 of the 128 Dd input planes are processed. It is worth noting that, as described and / or illustrated in U.S. Patent Application No. 16 / 545,345, filed August 20, 2019, the present invention can employ or implement aspects of circuitry, architectures, and integrated circuits that facilitate pipelined multiplication and accumulation operations. While '345 application describes and illustrates a multiplier-accumulator circuit system, this circuit system and its operation may replace, or otherwise substitute for, a multiplication circuit system or implement a logarithmic addition circuit system to facilitate cascading logarithmic addition and accumulation operations consistent with the present invention. '345 application is incorporated herein by reference in its entirety.

[0053] Continue to refer to Figure 1A The data processing flow shown can be adapted to any image / data plane dimension (Dw / Yw and Dh / Yh) by simply adjusting the number of iterations of the basic 64x64 LAC accumulation operation. The loop indices “I” and “j” are adjusted by the control and serialization logic circuitry to implement the image / data plane dimension. Furthermore, the data processing flow or method can be adjusted and / or extended to handle Yd column depths larger than the number of LAC processing circuitry systems executing the pipeline (e.g., 64 in this illustrative example). In one embodiment, this can be achieved by dividing the depth column of the output pixels into 64 blocks and repeating the process for each of these blocks. Figure 1A It is achieved through 64x64 LAC accumulation.

[0054] In fact, Figure 1A The data processing flow or method illustrated can also be extended to handle column depths Dd greater than the number of LAC processing circuits in the execution pipeline (64 in this illustrative example). In one embodiment, this can be achieved by initially performing partial accumulation of the first block of 64 input pixels Dijk into each output pixel Yijl. Then, in a second operational step, these partially accumulated values ​​Yijl are read back into the execution pipeline as initial values ​​for continuing accumulation of the next block of 64 input pixels Dijk into each output pixel Yijl. The memory storing or holding the continuously accumulated values ​​(e.g., L2 memory) can be organized, partitioned, and / or resized to accommodate any additional read / write bandwidth to support the operation.

[0055] These techniques, which summarize the applicability of 64x64 MAC execution pipelines, can also be used or extended to the generality of additional methods described in the later parts of this application.

[0056] It is worth noting that, Figure 1A An exemplary embodiment of logarithmic addition and accumulation operations associated with one or more additional 64-LAC execution pipelines according to certain aspects of the present invention is illustrated. In this embodiment, 64x64 Fkl filter weights are distributed across 64 L0 SRAMs (one L0 SRAM in each of the 64 processing circuits). In each execution cycle, 64 Fkl values ​​(green) are read and passed to the LAC circuits. After being loaded from the Dijk shift chain (orange), the Dijk data values ​​are held in one processing circuit for 64 execution cycles. In this illustrative embodiment, the data format of the filter weights and input / pixel data is converted to logarithmic data format via a format conversion circuitry system before being input to the pipeline.

[0057] After being loaded from the Yijl shift chain, the Yijl LAC value will cycle through all 64 processing circuits over 64 execution cycles and will be unloaded using the same shift chain. Figure 1A The diagram illustrates a loop executed by the control and serialization logic associated with the LAC execution pipeline. This loop shows the product of the Dijk input data / pixel and the Fkl filter value being accumulated in the partial sum and Yijl. In this embodiment, the partial sum and Yijl are then accumulated into the final output pixel value Yijl.

[0058] It is worth noting that, reference Figure 1A In one embodiment, the processing level can utilize an additional 64-LAC execution pipeline in parallel to concurrently operate on other pixels / data (i,j) of the input frame or data layer. In this embodiment, additional L2 memory ports can be employed (e.g., by partitioning, segmenting, or splitting L2 memory across multiple physical SRAM blocks). Here, concurrent LAC execution pipeline operations copy weight data (denoted as Fkl) across memory (e.g., L0 memory) in the parallel execution pipeline. It is worth noting that in Figure 1A In the exemplary embodiment shown, the input stage has Dw = 512, Dh = 256 and Dd = 128, and the output stage has Yw = 512, Yh = 256 and Yd = 64.

[0059] This invention can employ and / or implement an architecture (and methods of operating such circuit systems) for executing or processing pipelines to process data concurrently or in parallel, thereby increasing pipeline throughput—for example, as described and / or illustrated in U.S. Patent Application No. 16 / 816,164 and U.S. Provisional Patent Application No. 62 / 831,413; '164 and '413 are incorporated herein by reference in their entirety. Herein, multiple processing or execution pipelines, each comprising multiple LAC circuits, can process data concurrently to increase data processing and overall pipeline throughput.

[0060] Figure 1B The invention is illustrated in block diagram form. Figure 1A An exemplary embodiment of the circuitry system for the LAC execution pipeline is provided, wherein a "logarithmic" floating-point format is employed, such that the logarithmic addition circuitry system logarithmically adds the input data / values ​​in logarithmic data format (e.g., base-2) to the filter weights or coefficients (of the logarithmic data format (e.g., base-2)) during execution. The conversion circuitry system remaps the binary value in the fractional domain of the input data / values ​​from standard floating-point format to the logarithm of that binary value.

[0061] In short, the input image / pixel data (D) is read from memory (e.g., L2 memory bank – SRAM). In one embodiment, the input image / pixel data is in a floating-point data format (e.g., FP24 – 24 bits for sign, exponent, fraction). Here, the input image / pixel data is either acquired (raw image data) or may have been generated earlier via filtering operations and subsequently stored in memory.

[0062] In one embodiment, input image / pixel data is read from memory into a format conversion circuitry system, thereby converting it "on the fly" into a logarithmic data format (e.g., LL16 format - a 16-bit value, which can have the same number of bits as FP16 format (but with a different interpretation)). The logarithmic data format input image / pixel data is then output by the data format conversion circuitry system and input / shifted to the LAC processing circuitry system using the load register "D_SI". Logarithmic data format input data / values ​​can also be loaded in parallel into the same data register "D" for use in the execution process.

[0063] refer to Figure 1A , 1BIn one embodiment, the filter weights or coefficients are previously converted to a logarithmic data format (e.g., LL8 – an 8-bit logarithmic data format with signs, exponents, and fractions) and stored in memory (L2 in this illustrative embodiment, which may be SRAM). For example, in one embodiment, the filter weights or coefficients can be read from memory (L2) and “on the fly” converted, transformed, and / or modified to an appropriate logarithmic data format (e.g., converting LL8 format to LL16 format) for storage in memory (here, the L1 memory level – e.g., SRAM) via a format conversion circuitry. The filter weights or coefficients can then be accessed via processing circuitry associated with logarithmic addition and accumulation operations.

[0064] In another embodiment, the filter weights or coefficients are stored in memory (L2) in floating-point or fixed-point data format and then converted or transformed into logarithmic data format via a data format conversion circuitry system. For example, refer to Figure 1G In one embodiment, filter weights or coefficients are read from memory (L2) into a format conversion circuitry and converted or transformed from a floating-point data format to a logarithmic data format (e.g., FP8 to LL16 format in the illustrative embodiment). In practice, filter weights or coefficients in integer data format (INT) or block-scaled fractional data format (BSF) can be read from memory (L2) and then converted or transformed into a logarithmic data format (e.g., from INT8 to LL16; or, for example, BSF8 to LL16).

[0065] refer to Figure 1A , 1B In operation, 1E, 1F, 1G, and 1H read filter weights from memory (L1 memory) and store them in memory (L0, e.g., SRAM) local to / dedicated to a specific LAC processing circuitry before the start of processing of the input data / values ​​(in logarithmic data format). Subsequently, the processing pipeline circuitry reads the filter weights or coefficients (in logarithmic data format) from the L0 memory and performs a logarithmic addition operation. In one embodiment, the filter weights or coefficients are read via a logarithmic addition-accumulation circuitry and loaded into the filter weight register "F" for processing. Here, the execution process obtains data from registers "D" and "F" (both LL16 data / values ​​in this illustrative embodiment) and via the logarithmic addition circuitry (see...). Figure 1B and 1H The circuit block "LL16 MUL" in the exemplary circuit system block diagram sums / adds the image data and filter weights. In this embodiment, the logarithmic addition circuit system uses fixed-point addition.

[0066] Subsequently, the data (LL16) is output to a format conversion circuitry to convert the data / value from a logarithmic data format to a format that facilitates or is consistent with further processing (e.g., floating-point or fixed-point data format). (See also...) Figure 1A , 1B 1E, 1F, 1G, and 1H). In one embodiment, partially processed image / input data (in this particular embodiment, and / or output data in LL16 format) is converted to a floating-point data format (e.g., FP16 format) via a data format conversion circuitry system to facilitate additional / follow-up processing via an accumulation circuitry system. Continue to refer to Figure 1A , 1B In one embodiment, 1E, 1F, 1G, and 1H, partially processed data (in FP16 data format) is provided to the accumulator stage via the “D*F” register, and multiple partially processed image data are accumulated via an accumulator circuitry (e.g., with FP24 precision) and output to memory (here, the “Y” register). In one embodiment, after each result “Y” has been accumulated by 64 sums / products, the total accumulation is loaded in parallel into the “MAC-SO” register. This data can be serially output (e.g., shifted out) during the next execution sequence. Here, the temporary and Yijlk LAC values ​​will be cyclically passed through the processing circuitry (64 in this illustrative embodiment) during the execution cycle following loading from the Yijk shift chain, unloaded using the same shift chain, and then accumulated to the final output pixel / data value Yijl. (See, for example...) Figure 1A ).

[0067] It is worth noting that in one embodiment, the input data / values ​​(e.g., image data) are stored in memory (e.g., L2) in a logarithmic data format, making the format conversion circuitry deployed in its data path unnecessary. In another embodiment, in addition to or instead of this, the filter weights or coefficients are stored in memory (e.g., L2) in a logarithmic data format with an appropriate bit length, making the format conversion circuitry deployed in its data path unnecessary.

[0068] Furthermore, in one embodiment, the format conversion circuitry associated with the filter weights or coefficients is deployed in the data path between memory L1 and memory L0. Alternatively, the format conversion circuitry associated with the filter weights or coefficients is deployed in the data path between memory L0 and the logarithmic addition-accumulation circuitry.

[0069] refer to Figure 1CIn this illustrative embodiment, each 64-LAC execution pipeline has its own L0 memory (e.g., SRAM), and each 16x64-LAC cluster includes a shared L1 memory (e.g., SRAM). The shift-in and shift-out data paths of the 64-LAC execution pipeline are coupled to memory (in this embodiment, L2 memory (e.g., SRAM)), which is also coupled to one or more additional / other memories (in this embodiment, L1 / L0 memory). The network on-chip (NOC) couples the L2 memory to a PHY (physical interface) for L3 memory (in this embodiment, external memory (e.g., DRAM)). The NOC is also coupled to a PCIe PHY, which in turn can be coupled to an external host computer / processor. Notably, in one embodiment, the NOC is also coupled to a GPIO input / output PHY, which allows multiple X1 components to be operated—e.g., concurrently in one embodiment.

[0070] Figure 1C Exemplary embodiments of a circuit system for a logic tile according to certain aspects of the present invention are illustrated, comprising multiple execution pipelines and resources, wherein the circuit system of the pipelines implements LAC execution pipelines; notably, in the illustrative embodiment, the logic tile comprises four clusters, each cluster comprising 16 64-LAC execution pipelines, wherein exemplary 64-LAC execution pipelines are shown in block diagram form for reference. In cases where an integrated circuit comprises multiple such logic tiles, the logic tiles may be interconnected. As described above, the present invention can employ or implement aspects of the circuit systems, architectures, and integrated circuits described and / or illustrated in U.S. Patent Application No. 16 / 545,345, filed August 20, 2019. While '345 application describes and illustrates a multiplier-accumulator circuit system, this circuit system and its operation may replace, or otherwise replace / implement, a logarithmic addition circuit system and a conversion circuit system to facilitate the cascading of logarithmic addition and accumulation operations consistent with the present invention. Other features described and illustrated in '345 application, including, for example, architecture, circuitry of interconnect networks, and NLINX interface connectors, may also be used in conjunction with the invention described and illustrated herein. Again, '345 application is incorporated herein by reference in its entirety.

[0071] Logarithmic adder-accumulator circuitry systems can be interconnected into execution or processing pipelines and architectures, as described and / or illustrated in U.S. Provisional Patent Application No. 63 / 012,111 (relating to MAC); application 63 / 012,111 is incorporated herein by reference in its entirety. In one embodiment, the circuitry systems configure and control rows / groups (sometimes referred to as “clusters”) of multiple individual logarithmic adder-accumulator circuits (instead of the MAC circuitry mentioned therein) or interconnected (in series) logarithmic adder-accumulator circuits to pipeline logarithmic addition and accumulation operations. In one embodiment, the interconnection of one or more pipelines is configurable or programmable to provide different forms of pipelined architecture—as set forth in application '111'. Here, the pipelined architecture provided by the interconnection of multiple logarithmic adder-accumulator circuitry systems can be controllable or programmable. In this way, multiple logarithmic adder-accumulator circuits can be configured and / or reconfigured to form or provide one or more desired processing pipelines to process data (e.g., image data), as described in the context of MAC in the '111 application.

[0072] For example, referring to application '111, in one embodiment, a control / configuration circuitry system may configure or determine the logarithmic adder-accumulator circuitry described herein, or rows / groups of interconnected logarithmic adder-accumulator circuitry interconnected (in series) to perform logarithmic addition and accumulation operations, and / or a pipelined architecture or configuration implemented via connections of logarithmic adder-accumulator circuitry (or rows / groups of interconnected logarithmic adder-accumulator circuitry). Thus, in one embodiment, the control / configuration circuitry system described and illustrated in application '111' configures or implements a pipelined architecture by controlling or providing connections between rows (or groups) of logarithmic adder-accumulator circuitry employing any of the logarithmic adder-accumulator circuitry embodiments described herein.

[0073] refer to Figure 1C As described above, an integrated circuit may include multiple multi-bit LAC execution pipelines organized as clusters of components. Here, components may include "resources" such as bus interfaces (e.g., PHY and / or GPIO) to facilitate communication with circuitry external to the component and the memory (e.g., SRAM and DRAM) used by the component's circuitry. For example, in one embodiment, four clusters are included in the component (sometimes labeled "X1"), where each cluster includes multiple multi-bit MAC execution pipelines (in this illustrative embodiment, 16 64-LAC execution pipelines). It is worth noting that... Figure 1A and 1B A single 64-LAC execution pipeline is shown in the upper right corner for reference.

[0074] Continue to refer to Figure 1C The memory hierarchy in this exemplary embodiment includes L0 memory resources associated with each 64 LAC execution pipeline. Larger L1 SRAM memory resources are associated with each cluster of the 16x64 LAC execution pipelines. These two memories can store, retain, and / or hold the filter weight values ​​Fijklm used in logarithmic addition operations (regardless of whether a logarithmic data format (e.g., FP data format) is used).

[0075] It is worth noting that, Figure 1C Implementations may employ larger L2 memory (SRAM) and even larger external L3 memory (DRAM), both shared by all four clusters of the 16x64 LAC execution pipeline. These memories store or hold input image pixels Dijk and output image pixels Yijl, as well as filter weight values ​​Fijklm.

[0076] As mentioned above, in the illustrative embodiments (text and figures) described herein, the logarithmic adder-accumulator circuit system is sometimes referred to as "LAC" or "LAC pipeline".

[0077] As described above, pipelined circuitry can process data concurrently to increase pipeline throughput. For example, in one embodiment, the invention may include multiple separate logarithmic adder-accumulator circuits (sometimes referred to herein (including text / figures of the applications incorporated herein by reference) as “LAC”) and multiple registers (in one embodiment, including multiple shadow registers – see, for example, '345 application) that facilitate the pipelined operation of logarithmic addition and accumulation, wherein the pipelined circuitry processes data concurrently to increase pipeline throughput. Here, the invention can implement concurrent and / or parallel processing techniques (and methods of operating such circuitry) for multiplier-accumulator execution or processing pipelines, which increases pipeline throughput, as described and / or illustrated in U.S. Patent Application No. 16 / 816,164 and U.S. Provisional Patent Application No. 62 / 831,413. In one embodiment, the execution or processing pipelines of the present invention (including logarithmic adder-accumulator circuitry) can be interconnected in a ring configuration or architecture to process data concurrently or in parallel, as described in applications '164 and '413'. Here, multiple LAC execution pipelines of one or more clusters of one or more X1 components (which may be integrated / manufactured on a single die or multiple dies) can be interconnected in a ring configuration or architecture (where bus interconnect components) to process related data concurrently. Again, while applications '164 and '413' describe and illustrate multiplier-accumulator circuitry (MAC circuitry), the circuitry and its operation can replace the multiplication circuitry, or otherwise, replace / implement the logarithmic adder circuitry to facilitate cascading logarithmic addition and accumulation operations consistent with the present invention.

[0078] refer to Figure 1A , 1B 1E, 1F, and 1G, input data / values ​​are input into a logarithmic adder-accumulator circuit system (or pipeline circuit system), and, if the image / input data is in a different data format than logarithmic data, the image / input data is converted to logarithmic data format via a format conversion circuit system. For example, if the input data / values ​​are in floating-point data format, the format conversion circuit system converts the image data from floating-point data format to logarithmic data format before the image data is processed by the logarithmic adder-accumulator circuit system. This invention can employ any data format conversion circuit system or method to convert, modify, expand / shrink, and / or adapt the data format of image / input data to a now-known or later-developed logarithmic data format—all of which are intended to fall within the scope of this invention.

[0079] refer to Figure 1DIn one embodiment, the MAC-based processing circuitry and the LAC-based processing are similar in many respects. For example, both include format conversion circuitry in the data path from memory (e.g., L2 memory) to the processing circuitry executing the pipeline. In an illustrative embodiment, filter weights or coefficients include data format conversions from FP8 to FP16 (MAC-based processing circuitry) and from LL8 to LL16 (LAC-based processing circuitry), and image / input data includes data format conversions from FP24 to FP16 (MAC-based processing circuitry) and from FP24 to LL16 (LAC-based processing circuitry). However, the MAC-based processing circuitry differs from the LAC-based processing in that the MAC-based processing circuitry includes multiplication circuitry to multiply the filter weights or coefficients by the image / input data (see [link to documentation]). Figure 1D The FP16 MUL block in the MAC processing circuit section), while the LAC-based processing circuit system includes an additive circuit system to add filter weights or coefficients to the image / input data (see...). Figure 1D (LL16 MUL block in the LAC processing circuit section). It is worth noting that, in the illustrative embodiment, the LAC-based processing circuit system also includes a data format conversion circuit system (i.e., LL16 to FP16 conversion block) to convert the partially processed image / input data into a data format different from the logarithmic data format to facilitate subsequent data processing.

[0080] In one embodiment, the format conversion circuitry employs a lookup table to transform or convert image / input data into a logarithmic data format, wherein the logarithmic data format "equivalent" for each input data / value is pre-calculated and stored and / or encoded in memory (e.g., non-volatile memory, such as ROM or flash memory). For example, see reference... Figure 2A and 2B The floating-point data format of the fractional field value of the input data / value (e.g., FP16 or FP24 respectively) can be converted into a logarithmic data format (e.g., to LL16) using a lookup table-based circuit system / method. Here, the logarithmic data format (LL16 in this exemplary embodiment) equivalent of the value in the fractional field of the input data / value in the floating-point data format (FP16 in this illustrative embodiment) can be pre-computed and stored and / or encoded in memory. In one embodiment, the FP16 / LL16 format can use a lookup table of approximately 900 bits.

[0081] It is worth noting that the values ​​in the sign field and exponent field can be converted or transformed using circuitry. Here, the value of the exponent field "E" in the logarithmic data format (LL16) is similar to that in the floating-point data format (FP16) in that, in one embodiment, it is a bias value representing the integer value of the exponent base of the number (i.e., 2^(E-Ebias)). The "E-Ebias" value is the value in the exponent field divided by the base-2 logarithm of the integer of the number. The standard floating-point format mixes the integer logarithm in the exponent field with the binary fraction (also called the mantissa or significant bit) in the fraction field to (approximately) represent the true number. In this embodiment, the logarithmic floating-point data format mixes the integer logarithm in the exponent field with the fractional logarithm in the fraction field of the logarithmic data format to (approximately) represent the true number.

[0082] Continue to refer to Figure 2B Input / image data in floating-point format (FP24 in this illustrative embodiment) is converted to logarithmic floating-point format (LL16 in this illustrative embodiment). However, in this embodiment, rounding logic is used to round the value of the fractional field of the floating-point data format from 15 bits to 7 bits before the lookup table (here, the input is FP24 for...). Figure 2A The circuit system / method shown has 8 more fractional bits than the FP16 format. Here, the number of bits in the fractional field of the floating-point data format (F) is rounded to correlate with or correspond to the number of bits in the result fractional field of the logarithmic data format (G). Data stored in memory can also be encoded before being stored in non-volatile memory.

[0083] Furthermore, in one embodiment, the lookup table includes pre-computed values ​​that correlate the larger fractional field of the floating-point data format with the smaller fractional field of the “equivalent” logarithmic data format. In this embodiment, rounding logic is omitted or fewer bits are rounded. For example, a conversion circuitry system that transforms image / input data from a floating-point data format (e.g., FP24) to an “equivalent” logarithmic data format (e.g., LL24) for each input data / value is pre-computed and stored and / or encoded in memory.

[0084] In another embodiment, the data format conversion circuitry includes a logic circuitry that converts the fractional domain of input / image data in floating-point data format into an equivalent logarithmic data format. For example, see reference... Figure 3A and 3B The fractional domain of the input / image values ​​is adjusted using logic gates and multiplexer stages. The conversion circuitry (FP16 to LL16 in this illustrative embodiment) can implement fractional domain conversion using, for example, approximately 30 logic gates, an x-bit adder, and an x-bit multiplexer (e.g., x = 7). (See...) Figure 3C It is worth noting that, Figure 3CThe embodiment of the data format conversion circuit system shown is Figure 3A The detailed implementation of the data format conversion block diagram shown – the same method used to calculate y = LOG2(x) to provide a medium level of data conversion; for high-level data conversion (e.g., 32 or 64-bit precision) from floating-point data format to logarithmic data format, see [link to documentation]. Figure 3D The result is a correctly rounded converted value to the target format.

[0085] refer to Figure 3B The conversion circuit system / method can also employ rounding logic (and...). Figure 2B The input data / values ​​are converted or transformed from floating-point data format to logarithmic data format (FP24 to LL16 in this illustrative embodiment) using a similar method. Here, the number of bits in the fractional field of the floating-point data format (F) is rounded to correlate with or correspond to the number of bits in the resulting fractional field of the logarithmic data format (G). Subsequently, the logic of the conversion circuit system can use, for example, approximately 30 logic gates, an x-bit adder, and an x-bit multiplexer (e.g., x = 7) to convert the value of the fractional field (see...). Figure 3C It also enables the calculation of y = LOG2(x) with moderate accuracy in data transformation. Figure 3D A technique is implemented to perform high-level precision data conversion (e.g., 32 or 64-bit precision) from floating-point data format to logarithmic data format. The result is a converted value, appropriately rounded to a predetermined number of bits (“G” - seven in this illustrative embodiment) in the target format for the fractional field.

[0086] Furthermore, the present invention can also use extrapolation technology to convert the data format of the input data / values ​​into a logarithmic floating-point format.

[0087] As described above, in one embodiment, the filter weights are converted, modified, expanded, or adjusted to a suitable logarithmic data format via a format conversion circuitry system. For example, refer to... Figure 1A , 1B And 1D-1F, where the filter weights or coefficients are previously converted to a logarithmic data format (e.g., LL8 – an 8-bit logarithmic data format with signs, exponents, and fractions) and stored in memory (L2 in this illustrative embodiment, which may be SRAM) – in one embodiment, the filter weights or coefficients can be read from memory (L2) and “on the fly” converted, transformed, and / or modified to an appropriate logarithmic data format (e.g., LL8 to LL16 format) via a format conversion circuitry system, and then stored in a more local additional memory (here, the L1 memory level – e.g., SRAM) of one or more processing pipelines. Thereafter, the filter weights or coefficients can be accessed via processing circuitry systems associated with logarithmic addition and accumulation operations.

[0088] refer to Figure 1B , 1D In one exemplary embodiment, the filter weights or coefficients of 1F, 4A, and 4B are previously converted to a logarithmic data format (e.g., LL8 – an 8-bit logarithmic data format with signs, exponents, and fractions) and stored in memory (L2 in this illustrative embodiment, which may be SRAM). It is worth noting that... Figure 4A The transformation logic shown is similar to a format conversion circuit system used to transform filter weights, as described and / or illustrated in U.S. Provisional Application No. 62 / 961,627, filed January 15, 2020, which is incorporated herein by reference. In one embodiment, the format conversion block approximately doubles the number of bits in the exponent and fractional fields of the LL8 input format. In short, this technique is primarily implemented using logic gates, y-bit adders (e.g., 8), and one or more multiplexers. (See, for example, [link to relevant documentation]). Figure 4B (relative to) Figure 4A The block diagram illustrates the transformation or modification of filter weights / coefficients in more detail. It's worth noting that the three result fields may also require special values, operands, or characters to be replaced using multiplexer rows. Figure 4B The circuit block diagram provides Figure 4A Additional details regarding the filter weight / coefficient transformation or modification of the embodiment; however, Figure 4B The filter weight / coefficient transformation or modification techniques implemented in [the document] are similar to those used in [the document]. Figure 4A The technique is the same as that used in the block diagram.

[0089] It is worth noting that in another embodiment, the filter weights or coefficients are stored in memory (L2) in floating-point or fixed-point data format. Here, the filter weights or coefficients are read from memory (L2) into a format conversion circuitry and converted or transformed from a floating-point data format (e.g., FP8) or a fixed-point data format (e.g., INT8 or BSF8) to a logarithmic data format (e.g., the LL16 data format in the illustrative embodiment). As described herein, the circuitry / techniques shown in Figures 2 and 3 can be employed in a similar manner to convert or transform the filter weights from a floating-point or fixed-point data format to a logarithmic data format (e.g., the LL16 data format).

[0090] refer to Figure 1A , 1B Like the 1E-1G, the logarithmic addition circuit system sums the input data / values ​​and filter weights / coefficients—both in logarithmic data format. An exemplary embodiment of the logarithmic addition circuit system is described in... Figure 5AThe diagram illustrates a circuit system in which the exemplary embodiment of this circuitry employs LL16 (in this exemplary embodiment) on two input operands (i.e., input data / values ​​and filter weights / coefficients) and outputs a sum (“D result”) having a sign field, an exponent field, and a fraction field. In this embodiment, the sign field is XORed, and the exponent fields are added (and incremented if rounding causes a fraction overflow). Here, the two fraction fields (in logarithmic form) are added together using an adder (a 7-bit fixed-point adder in the illustrative embodiment) (via two's complement).

[0091] It is worth noting that, Figure 5B The diagram shows... Figure 5A A more detailed exemplary circuit block diagram of the logarithmic addition circuit system shown is provided. Figure 5B Additional details of some of the exemplary logic blocks shown (see “Logic 1”, “Logic 2”, and “Logic 3”) are in Figure 5C Provided by China.

[0092] Continue to refer to Figure 5B In other embodiments, the operations performed by the logarithmic addition circuitry (fractional domain GA + fractional domain GB; and exponential domain EA + exponential domain EB) can be replaced or accompanied by circuitry implementing other functions (such as reciprocal functions, square root functions, power functions). Here, with the operands in logarithmic data format, other functions can be easily implemented (e.g., division of operand A by B can be achieved by performing subtraction (fractional domain GA - fractional domain GB) and subtraction of exponential domain EA by exponential domain EB (instead of addition EA + EB as in the case of multiplication).

[0093] After logarithmic addition, the processed data / values ​​can be converted or transformed into another / different data format (e.g., from logarithmic data format to floating-point or fixed-point format—e.g., back to the format of the input data—however, the bit length of the values ​​in the fractional field can be different) for appending and / or subsequent processing. For example, processed data in logarithmic data format can be converted or transformed into floating-point data format (i.e., the same data format as the input data). A format conversion circuitry is deployed at the output of the logarithmic addition circuitry system (see, for example...). Figure 1A , 1B (and 1E-1G) can implement the inverse of a circuit system for converting input data / values ​​from floating-point data format to logarithmic data format. Here, partially processed image data in a data format different from logarithmic data format can be provided to the accumulator circuit system to implement, for example, an accumulation operation related to image data processing associated with inference operations (see...). Figure 1A , 1B and 1E-1G).

[0094] An exemplary embodiment of the format conversion circuit system deployed at the output of the logarithmic addition circuit system is described in Figure 6A and 6B The diagram (LL16 to FP16) illustrates how to convert the data format of a sum from logarithmic to floating-point. This exemplary embodiment's conversion circuitry can be implemented using, for example, approximately 30 logic gates, an x-bit adder, and an x-bit multiplexer (e.g., x = 7) to achieve fractional domain conversion. (For information on format conversion circuitry / techniques with moderate precision, see...) Figure 6C ).

[0095] Figure 6C The embodiment of the data format conversion circuit system shown is Figure 6B A detailed implementation of the format conversion block diagram shown is provided. Furthermore, Figure 6D The illustration shows another detailed embodiment of a data conversion format circuit system for calculating y = 2^x with medium precision. Figure 6E The illustration depicts a logarithmic data format to floating-point format conversion circuitry system that provides a high level of precision data conversion (here, calculating y = 2^x) – e.g., 32 or 64-bit precision). As mentioned above, the present invention can employ any data format conversion circuitry system or method now known or developed hereafter to (i) convert, modify, expand / shrink, and / or adjust the data / value format from a first data format to a logarithmic data format and / or (ii) convert, modify, expand / shrink, and / or adjust the data / value format from a logarithmic data format to a first or second data format – all of which are intended to fall within the scope of the present invention. It is noteworthy that the conversion format circuitry system / method of the present invention converts or modifies the data format of data (e.g., input data / values ​​(in some embodiments), filter weights / coefficients (in some embodiments), and the output data of logarithmic addition circuitry systems and / or results).

[0096] refer to Figure 7 (The illustration shows examples of several floating-point formats and "equivalent" logarithmic data formats.) The three logarithmic data formats use a signed magnitude numeric format for the sign field S and the fraction field G. The highest weight of the fraction field G is 0.5, and it has no hidden (implicit) bits, therefore it includes unnormalized values. The exponent field is a two's complement numeric format with an offset of 127 added to it. The minimum and maximum exponent values ​​are reserved for special operands or characters (NAN, INF, DNRM, ZERO).

[0097] In one embodiment, the memory allocation corresponding to a logarithmic data format (e.g., LL16) includes special operands or characters. For example, refer to... Figure 8(This illustration shows an exemplary numeric space for the LL16 data format), where the minimum and maximum exponents E[7:0] are reserved for special operands (NAN, INF, ZRO). NAN values ​​are generated when an undefined operation (0*∞ or ∞-∞) occurs. ±INF values ​​are saturation values ​​for exponent overflow. ±ZRO values ​​are saturation values ​​for exponent underflow. The range (EXP[7:0] = 8'b00000000) shows the binade corresponding to the DNRM values ​​in the floating-point data format (FP16)—except that G[1:7] = 7'b0000000 is reserved for ZRO, its "behavior" is the same as the other binades.

[0098] Figures 9A-9C The illustration depicts an exemplary encoding technique for a logarithmic data format (LL8y) having a 1-bit sign field (S), a 3-bit exponent field (E), and a 4-bit fraction field (F), implemented in relation to certain data (e.g., filter weights / coefficients) in some embodiments of the invention—for example, in relation to lookup tables. It is noteworthy that similar or corresponding lookup tables can be adopted, provided, and / or generated in relation to other logarithmic data formats (e.g., LL8x and LL8z).

[0099] Continue to refer to Figures 9A-9C The binade with the largest field size has the highest precision. Other binades increase the number of bits in the exponent field (E) and decrease the number of bits in the fractional field (G). This will reduce the precision of these other binades. The total number of bits (8 bits) of the GFP8y value will remain constant throughout the range.

[0100] The LL8y binade with the highest accuracy is located in Figure 9A Two central columns ( Figure 9B The leftmost column and Figure 9C In the rightmost column, the 3-bit exponent field (E) equals {010, 011, 100, and 101}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 16), where S is the sign bit, E is the three-bit field, and G is the four-bit fraction field. Note that the hidden / implicit bit always added to the fraction field has a value of 1.

[0101] Within this range, the exponent bias value Ek equals four. The four exponent domain values ​​{010, 011, 100, and 101} will create scaling values ​​of {2^(-2), 2^(-1), 2^(0), 2^(+1)}. This exponent bias value is configurable. Changing it will change the center point of the LL8y range of binade values. The exponent bias values ​​of all binades must be changed together so that no gaps or overlapping areas are introduced between binade ranges.

[0102] Figure 9AThe top-right column diagram illustrates the next two larger binades (with lower precision). The 4-bit exponent field (E) equals {1100, 1101}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 8), where S is the sign bit, E is the four-bit field, and G is the three-bit fraction field. Within this range, the exponent bias value Ek equals 10.

[0103] The next two larger binades (with lower precision) have a 5-bit exponent field (E) equal to {11100, 11101}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 4), where S is the sign bit, E is the five-bit field, and G is the two-bit fraction field. Within this range, the exponent bias value Ek equals 24.

[0104] The next two larger binades (with lower precision) have a 6-bit exponent field (E) equal to {111100, 111101}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 2), where S is the sign bit, E is the six-bit field, and F is the one-bit fraction field. Within this range, the exponent bias value Ek equals 54.

[0105] The next three larger binades (with lower precision) have a seven-bit exponent field (E) equal to {1111100, 1111101, 1111110}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(1), where S is the sign bit, E is the seven-bit field, and G is the zero-bit fraction field. Within this range, the exponent bias value Ek equals 116.

[0106] Figure 9A The bottom left column diagram illustrates the next two smaller binades (with lower precision). The 4-bit exponent field (E) equals {0010, 0011}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 8), where S is the sign bit, E is the four-bit field, and G is the three-bit fraction field. Within this range, the exponent bias value Ek equals 6.

[0107] The next two smaller binades (with lower precision) have a 5-bit exponent field (E) equal to {00010, 00011}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 4), where S is the sign bit, E is the five-bit field, and G is the two-bit fraction field. Within this range, the exponent bias value Ek equals 8.

[0108] The next two smaller binades (with lower precision) have a 6-bit exponent field (E) equal to {000010, 000011}. These LL8y encoded values ​​are (-1)^S*2^(E-Ek)*(G / 2), where S is the sign bit, E is the six-bit field, and G is the one-bit fraction field. Within this range, the exponent bias value Ek equals 10.

[0109] The next three smaller binades (with lower precision) have a seven-bit exponent field (E) equal to {0000001, 0000010, 0000011}. The values ​​of these LL8y codes are (-1)^S*2^(E-Ek)*(1), where S is the sign bit, E is the seven-bit field, and G is the zero-bit fraction field. Within this range, the exponent bias value Ek equals 12. This completes the summary of the 252 codes used for the numeric values.

[0110] Four additional codes (out of a total of 256) are assigned to special values. First, the value 8'b00000000 represents zero (ZRO). This is a saturation value for a positive or negative result with exponential underflow (EUNFL). The value 8'b10000000 represents "Not a Number" (NAN). This is the result of an undefined operation. The value 8'b01111111 represents positive infinity (+INF). This is a saturation value for a positive result with exponential overflow (EOVFL). The value 8'b11111111 represents negative infinity (-INF). This is a saturation value for a negative result with exponential overflow (EOVFL).

[0111] Figure 10A The illustration shows another exemplary encoding technique for a logarithmic data format (LL8y) having a 1-bit sign field (S), a 3-bit exponent field (E), and a 4-bit fraction field (F), implemented in conjunction with certain data (e.g., filter weights / coefficients) in some embodiments of the invention—for example, related to lookup tables. In this respect, Figure 10A An example of an alternative floating-point format (LL8y) according to an embodiment of the present invention is illustrated, wherein the range and precision can be dynamically configured; this embodiment can better fit the set of data values ​​it represents.

[0112] refer to Figure 10A (and for specific formats) Figure 10B-10E The "permissible" number space below the horizontal line depicting the logarithmic data format LL16 is graphically represented for the logarithmic data formats LL8x, LL8y, and LL8z. (See also...) Figure 10B The range and precision of the LL8y format are... Figure 10A and 10DAs shown in the diagram. In the four binades at the center (-2 to +2), it has the same precision (4 bits) as the FP8 format discussed earlier. Unlike FP8, the precision of the LL8y format decreases symmetrically.

[0113] There is zero precision (a single value) in the three binades from -11 to -8 and the two binades from +8 to +10.

[0114] This symmetrical decay of LL8y is similar to the decay seen in the distribution of data weight values ​​in image filtering applications. This means that most data values ​​in the dataset will fall into the binade with the highest bit precision.

[0115] refer to Figure 10A and 10B In contrast, the INT8 format has a decay in the binade in the negative direction, but hard edges in the width of the binade in the positive direction. Therefore, smaller data values ​​(in the negative direction) will see "soft" saturation if they are too close to the edge of the range.

[0116] Scaling the dataset presents challenges when using integer formats (e.g., INT8). For example, if the distribution of data / values ​​lies at a hard edge of the width of the binade in the positive direction or moves too "close" to it to take advantage of more bit precision, then larger values ​​of some data will be affected by "hard" saturation. It's worth noting that the LL8y format provides "soft" saturation at both edges of the range.

[0117] In one embodiment, the conversion circuitry can be dynamically configurable, for example, in situ between formats (e.g., LL8x, LL8y, and LL8z). In this regard, circuitry (hardware logic) for converting data values ​​between LL8y and LL16 formats (or any larger LL format) can be dynamically configured to support a range of LL formats. This allows for adjustment of the range and precision to match the distribution characteristics of the data set. Two other formats (LL8x and LL8z) are also described herein and can be used to describe the dynamic configurability of the conversion circuitry.

[0118] LL8x format in Figure 10A and 10C The diagram shows that the LL8x format has one more bit of precision (5 bits) in the two central binades (-1 to +1) than the previously discussed LL8y format. Like LL8y, the precision of the LL8x format decreases symmetrically. There are zero bits of precision (a single value) in the binades from -5 to -6 and the binade at +5.

[0119] LL8z format in Figure 10A and 10EThe diagram shows that the LL8x format has one less bit of precision (3 bits) in the eight binades at the center (-4 to +4). Like LL8y, the precision of the LL8x format decreases symmetrically. There are zero bits of precision (a single value) in the binades from -19 to -12 and from +12 to +18.

[0120] The key benefit of the set of three logarithmic data formats (LL8x, LL8y, LL8z) is that they provide multiple format alternatives to offer different ranges and / or precisions. This reduces rounding and saturation errors when using data values.

[0121] If the exponent bias (Ek) is adjusted for a specific format, the precision distribution can be shifted left or right to match the distribution of the dataset (although this is not explicitly stated in the original text). Figure 10A As shown, but in one embodiment it can be combined, implemented or employed.

[0122] Furthermore, two of these formats can be combined to make the precision distribution asymmetrical about the center point (although this is not yet possible). Figure 10A As shown, but in one embodiment it can be combined, implemented or employed.

[0123] In one embodiment, the encoding methods used by these three logarithmic data formats are extended to floating-point data formats with more bits, such as (LL16x / LL16Py / LLP16z). It is worth noting that, although this is not in... Figure 10A As shown in the figure, but in one embodiment it can be combined, implemented or adopted.

[0124] In some cases, the output of a logarithmic adder circuit system can be interpreted as addressing special operands or characters. (Reference) Figure 11 Details of the SD / ED / GD domains for the interaction cases are listed in three 4x4 tables, each of which includes four cases {ZRO, NRM, INF, NAN} for each operand, where operand A is along the horizontal axis and operand B is along the vertical axis. The three tables, from left to right, include the sign SD, exponent ED[7:0], and fraction GD[0:7] for the results of these different values ​​of operand A and B.

[0125] The default sign of the result is Sw = Sa XOR Sb. This does not occur if either operand is NaN; in these cases, the sign of the result is the sign of the NaN operands. When both operands are NaN, the sign of the result is 1'b0.

[0126] When operands A and B are NRM values, the default exponent of the result is (Ea[7:0]+Eb[7:0]-8'h7F+INC); this is the sum of the operand exponents, minus the exponent offset, and if the multiplicand is ≥2.0, then add INC=1. This default occurs when 8'h01≤(Ea[7:0]+Eb[7:0]-8'h7F+Mov)≤8'hFE, as shown in the center box marked "N" in the NRM.

[0127] The default fraction / mantissa is Gq[0:7], rounded to the appropriate number of bits in the output format. If 8'h00≥(Ea[7:0]+Eb[7:0]-8'h7F+Mov), then EUNFL occurs and the result is ZERO, where the exponent is 8'h00 and the fraction is 23'h000000. If Ea[7:0]+Eb[7:0]-8'h7F+Mov)≥8'hFF, then EOVFL occurs and the result is INF, where the exponent is 8'hFF and the fraction is 23'h000000.

[0128] If both operands A and B are ZERO, or one is ZERO and the other is NRM, then the result is ZERO, with an exponent of 8'h00 and a fraction of 15'h0000. If both operands A and B are INF, or one is INF and the other is NRM, then the result is INF, with an exponent of 8'hFF and a fraction of 7'h00. If one operand of A and B is ZERO and the other is INF, then the result is NAN, with an exponent of 8'hFF and a fraction of 7'h7F. If one operand of A and B is NAN and the other is {ZERO, NRM, INF}, then the result is NAN, with an exponent of 8'hFF and the same fraction as the NAN operand. If both operands of A and B are NAN, then the result is NAN, with an exponent of 8'hFF and a fraction of 7'h7F.

[0129] This document describes and illustrates numerous inventions. While certain embodiments, features, attributes, and advantages of the invention have been described and illustrated, it should be understood that many other, as well as different and / or similar, embodiments, features, attributes, and advantages of the invention will be apparent from the description and illustration. Therefore, the embodiments, features, attributes, and advantages of the invention described and illustrated herein are not exhaustive, and it should be understood that such other, similar, and different embodiments, features, attributes, and advantages of the invention are within the scope of this invention.

[0130] In fact, the present invention is neither limited to any single aspect or embodiment thereof, nor to any combination and / or substitution of such aspects and / or embodiments. Moreover, each aspect and / or embodiment of the present invention may be used alone or in combination with one or more other aspects and / or embodiments thereof.

[0131] For example, in one embodiment of the invention, one or more integrated circuits include circuitry that implements logarithmic addition and accumulation (LAC) operations and multiplication and accumulation (MAC) operations. For example, see reference... Figure 12A and 12B In one embodiment, circuitry for processing / operating floating-point and logarithmic data formats is included in or implemented within processing circuitry / components. A mode or mode control signal “MODE” is output by the mode control circuitry to select which format option to employ in the processing or filtering operation / application. Here, the logarithmic adder-accumulator circuitry and data path perform logarithmic addition and accumulation operations (e.g., as discussed herein) when enabled, and the multiplier-accumulator circuitry and data path perform multiplication and accumulation operations when enabled. The mode selection circuitry controls (i.e., enables and / or disables) the operability of the logarithmic adder-accumulator circuitry and multiplier-accumulator circuitry to select the circuitry used for processing, for example, image data associated with inference operations. In this respect, the mode selection circuitry controls or determines the data path to be processed to include either the logarithmic adder-accumulator circuitry or the multiplier-accumulator circuitry.

[0132] In one embodiment, the mode selection circuitry may be programmable only once; in another embodiment, it may be programmable more than once (i.e., multiple times). The mode selection circuitry may be programmed, for example, in situ (i.e., during operation of the integrated circuit), at manufacturing time, and / or during power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc., or during power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc. For example, the mode selection circuitry may receive mode selection signals from internal or external circuitry (i.e., outside one or more integrated circuits—e.g., a host computer / processor) including one or more data storage circuitry (e.g., one or more memory cells, registers, flip-flops, latches, memory blocks / arrays), one or more input pins / conductors, (any type) lookup table (LUT), processor or controller, and / or discrete control logic. In response, the mode selection circuitry can use one or more such signals to enable or disable the selected processing circuitry (as the case may be) to enable or disable one of the processing modes (i.e., logarithmic addition and accumulation or multiplication and accumulation) in place and / or during power-on, startup, initialization, re-initialization, configuration, reconfiguration, etc.

[0133] Furthermore, the present invention is not limited to (i) the specific logarithmic, fixed-point, and / or floating-point formats, operations (e.g., addition, subtraction, etc.), block / data width, data path width, bandwidth, values, procedures, and / or algorithms described, and (ii) the exemplary logical or physical overview configurations, exemplary module / circuit system configurations, and / or exemplary Verilog code. In practice, the present invention may employ other mathematical operations (in addition to or instead of logarithmic addition), wherein a logarithmic "multiplication" block is expanded to perform division (subtracting the E / G of the two operands) and / or a logarithmic "multiplication" block is expanded to perform square root (shifting the E / G of the operands one bit to the right).

[0134] It is noteworthy that the details of the circuitry, structure, architecture, function, and operation of the multiplier-accumulator pipeline, in particular, are described and / or illustrated in the following documents: (1) U.S. Non-Provisional Patent Application No. 16 / 545,345, (2) U.S. Non-Provisional Patent Application No. 16 / 816,164, (3) U.S. Provisional Patent Application No. 62 / 831,413, (4) U.S. Non-Provisional Patent Application No. 16 / 900,319, (5) U.S. Provisional Patent Application No. 62 / 865,113, (6) U.S. Non-Provisional Patent Application No. 17 / 019,212, (7) U.S. Provisional Patent Application No. 62 / 900,044, (8) U.S. Non-Provisional Patent Application No. 17 / 031,631, and (9) U.S. Provisional Patent Application No. 62 / 909,293. These nine (9) patent applications are incorporated herein by reference in their entirety. In fact, as mentioned above, the present invention can employ multiple execution or processing pipelines (implementing LAC circuitry instead of MAC circuitry) to process data concurrently to increase data processing throughput—for example, as described and / or illustrated in U.S. Nonprovisional Application No. 16 / 816,164.

[0135] Furthermore, or alternatively, the present invention may employ circuitry, functionality, and operation to enhance the dynamic range of filter weights or coefficients, as described and / or illustrated in U.S. Patent Application No. 17 / 074,670 and U.S. Provisional Patent Application No. 62 / 930,601. That is, the present invention may use circuitry and techniques to enhance the dynamic range of the filter weights or coefficients of the applications in '670 and '601. The applications in '670 and '601 are incorporated herein by reference in their entirety.

[0136] While the invention has been described in certain specific aspects, many additional modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that the invention may be practiced in ways different from those specifically described without departing from the scope and spirit of the invention. Accordingly, embodiments of the invention should be considered illustrative / exemplary rather than restrictive in all respects. For example, while a certain bit width is described in the illustrative exemplary embodiment of the input data / value data / value, filter weights, and output data / value conversion circuitry system, such bit width(s) is exemplary. For the sake of brevity, other precisions will not be described separately, but will be readily apparent to those skilled in the art based on, for example, this application. Therefore, the invention… NoLimited to (i) the specific fixed-point data formats shown (e.g., integer formats (INTxx) and block-scaled fractional formats (e.g., BSFxx), block / data widths (FPxx, LLxx, etc.), data path widths, bandwidths, values, processes, and / or algorithms, and not limited to (ii) the exemplary logical or physical overview configurations of specific circuit systems and / or overall pipelines, and / or exemplary module / circuit system configurations, and / or overall pipelines. In fact, the present invention... No Limited to (i) the specific floating-point format, (i) the specific fixed-point format, operation (e.g., addition, subtraction, etc.), block / data width or length, data path width, bandwidth, value, procedure and / or algorithm shown, and not limited to (ii) the exemplary logical or physical overview configuration, and / or the exemplary module / circuit system configuration.

[0137] Furthermore, while the data format conversion circuitry in some exemplary embodiments determines / identifies the largest exponent of the associated filter weights of the set of filter weights, the data format conversion circuitry can compare the exponents of the associated filter weights to determine the smallest exponent. In this alternative embodiment, the shift of the fractional domain of the filter weights can be modified (e.g., left shift for filter weights with a larger exponent) to accommodate a common exponent domain, which is the smallest exponent of the associated filter weights of this set of filter weights.

[0138] It is worth noting that the various circuits, circuit systems, and techniques disclosed herein can be described using computer-aided design tools and can be expressed (or represented) as data and / or instructions implemented in various computer-readable media, based on their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics. Formats of documents and other objects in which such circuits, circuit systems, layouts, and wiring expressions can be implemented include, but are not limited to, formats supporting behavioral languages ​​(such as C, Verilog, and HLDL), formats supporting register-level description languages ​​(such as RTL), and formats supporting geometric description languages ​​(such as GDSII, GDSIII, GDSIV, CIF, and MEBES), as well as any other formats and / or languages ​​now known or developed hereafter. Computer-readable media in which such formatted data and / or instructions can be implemented include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media) and carrier waves, which can be used to transmit such formatted data and / or instructions via wireless, optical, or wired signaling media or any combination thereof. Examples of transmitting such formatted data and / or instructions via carrier waves include, but are not limited to, transmission (uploading, downloading, emailing, etc.) over the Internet and / or other computer networks via one or more data transmission protocols (e.g., HTTP, FTP, SMTP, etc.).

[0139] In practice, when received within a computer system via one or more computer-readable media, such data and / or instruction-based representations of the aforementioned circuits can be processed by a processing entity within the computer system (e.g., one or more processors) in conjunction with the execution of one or more other computer programs, including but not limited to netlist generators, layout and routing programs, etc., to generate a representation or image of the physical appearance of such circuits. This representation or image can then be used in device manufacturing, for example, by enabling the generation of one or more masks used to form various components of the circuits during device manufacturing.

[0140] Furthermore, the various circuits, circuit systems, and techniques disclosed herein can be represented by simulation using computer-aided design and / or testing tools. Simulations of circuits, circuit systems, layouts and wiring, and / or techniques implemented therefrom can be performed by computer systems, wherein the characteristics and operation of such circuits, circuit systems, layouts, and techniques implemented therefrom are imitated, copied, and / or predicted via computer systems. This invention also relates to such simulations of inventive circuits, circuit systems, and / or techniques implemented therefrom, and these are therefore intended to fall within the scope of this invention. Computer-readable media corresponding to such simulation and / or testing tools are also intended to fall within the scope of this invention.

[0141] It is important to note that references to "one embodiment" or "embodiment" (etc.) herein mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included, adopted, and / or incorporated in one, some, or all embodiments of the invention. The use or appearance of the phrases "in one embodiment" or "in another embodiment" (etc.) in the specification does not refer to the same embodiment, and individual or alternative embodiments are not necessarily mutually exclusive with one or more other embodiments, nor are they limited to a single exclusive embodiment. The same applies to the term "implementation." The invention is neither limited to any single aspect or embodiment thereof, nor to any combination and / or substitution of such aspects and / or embodiments. Moreover, each aspect and / or embodiment of the invention may be used alone or in combination with one or more other aspects and / or embodiments of the invention. For the sake of brevity, certain substitutions and combinations are not discussed and / or described separately herein.

[0142] Furthermore, the embodiments or implementations described herein as “exemplary” should not be construed as being ideal, preferred, or advantageous compared to other embodiments or implementations; rather, they are intended to convey or indicate that one or more embodiments are exemplary embodiments.

[0143] While the invention has been described in certain specific aspects, many additional modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that the invention may be practiced in ways different from those specifically described without departing from the scope and spirit of the invention. Consequently, the embodiments of the invention should be considered in all respects as illustrative / exemplary rather than restrictive.

[0144] The terms “comprising,” “including,” and “having,” or any other variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, circuit, article of manufacture, or apparatus that comprises a list of parts or elements includes not only those parts or elements but also other parts or elements not expressly listed or inherent to such process, method, article of manufacture, or apparatus. Additionally, the terms “connected” or “linked” as used herein should be interpreted broadly to include direct or indirect coupling (e.g., via one or more conductors and / or intermediate devices / elements (active or passive) and / or via inductive or capacitive coupling) unless otherwise specified (e.g., the terms “directly connected” or “directly linked” are used).

[0145] The terms “an” and “a” used in this document do not indicate a limitation on quantity, but rather the presence of at least one of the referenced items. Furthermore, the terms “first,” “second,” etc., used in this document do not indicate order, quantity, or importance, but are used to distinguish one element / circuit / feature from another.

[0146] Furthermore, the term "integrated circuit" specifically refers to any integrated circuit, including, for example, general-purpose or non-specific integrated circuits, processors, controllers, state machines, gate arrays, SoCs, PGAs, and / or FPGAs. The term "integrated circuit" also refers to any integrated circuit (e.g., processors, controllers, state machines, and SoCs) – including embedded processors, controllers, state machines, PGAs, and / or FPGAs.

[0147] Furthermore, the term "circuit system" refers, among other things, specifically to a circuit (whether integrated or otherwise), a group of such circuits, one or more processors, one or more state machines, one or more processors implementing software, one or more gate arrays, programmable gate arrays and / or field-programmable gate arrays, or a combination of one or more circuit systems (whether integrated or otherwise), one or more state machines, one or more processors, one or more processors implementing software, one or more gate arrays, programmable gate arrays and / or field-programmable gate arrays. The term "data" refers, among other things, specifically to one or more current or voltage signals (complex or singular) in analog or digital form, which may be a single bit (etc.) or multiple bits (etc.).

[0148] The limitations of the claims are not expressed in the form of components plus functions or steps plus functions. No limitations should be imposed under 35 USC § 112. Or it may be interpreted as §112(f), unless such claims are limited to the explicit use of the phrase “part for…” or “step for…” followed by a statement of function, and without any particular structure.

Claims

1. An integrated circuit, comprising: Multiple logarithmic adder-accumulator circuits are used to perform logarithmic addition and accumulation operations in operation, wherein each logarithmic adder-accumulator circuit includes: A logarithmic adder circuit is used to add first input data in logarithmic data format and filter weight data in logarithmic data format, and output first sum data in logarithmic data format based on this sum. A first data format conversion circuit system, coupled to an associated logarithmic adder-accumulator circuit, converts the logarithmic data format of the first sum data received from the associated logarithmic adder-accumulator circuit into a floating-point data format, and outputs the first sum data in floating-point format. An accumulator, coupled to a first data format conversion circuit system of an associated logarithmic adder-accumulator circuit, to add second input data to a first sum data output by the first data format conversion circuit system of the associated logarithmic adder-accumulator circuit to generate first accumulated data; and The multiple logarithmic adder-accumulator circuits mentioned above are connected in series. Specifically, the first data format conversion circuit system converts the data format of the first sum data of each logarithmic adder circuit into a floating-point data format with a first precision. The second input data includes a floating-point data format with a second precision. The accumulator of each of the plurality of logarithmic adder-accumulator circuits adds the second input data with the floating-point data format including the second precision to the first sum data with the floating-point data format including the first precision to generate the first accumulated data. The first precision is different from the second precision. The first precision and the second precision depend on at least one of the following: available / allocated memory bandwidth, available / allocated wiring bandwidth, and the amount of area within the integrated circuit available / allocated for storing, transmitting / reading and / or processing data.

2. The integrated circuit as claimed in claim 1, wherein: The multiple logarithmic adder-accumulator circuits are connected in series to form a linear pipeline.

3. The integrated circuit as described in claim 1, further comprising: A second data format conversion circuit system is coupled to the input of each of the plurality of logarithmic adder-accumulator circuits to convert the first input data into a logarithmic data format.

4. The integrated circuit as claimed in claim 3, wherein: The second data format conversion circuit system includes a lookup table to associate initial first input data having a first data format with first input data having a logarithmic data format, thereby converting the initial first input data into first input data having a logarithmic data format.

5. The integrated circuit as claimed in claim 3, wherein: The second data format conversion circuit system includes a logic circuit system for converting initial input data having a first data format into first input data having a logarithmic data format.

6. The integrated circuit of claim 1, further comprising: A third data format conversion circuit system is coupled to the first memory to receive filter weight data from the first memory and convert the filter weight data into a logarithmic data format; as well as A second memory, coupled to a third data format conversion circuit system, receives and stores filter weight data in logarithmic data format, and responsively outputs the filter weight data to one or more associated logarithmic adder-accumulator circuits among the plurality of logarithmic adder-accumulator circuits.

7. The integrated circuit of claim 1, further comprising: A second data format conversion circuit system is coupled between the memory and the input of each of the plurality of logarithmic adder-accumulator circuits to convert the data format of the first input data into a logarithmic data format and output the first input data having the logarithmic data format to the logarithmic adder circuit of the associated logarithmic adder-accumulator circuit.

8. The integrated circuit of claim 1, further comprising: A second data format conversion circuit system is coupled between the first memory and the input of each of the plurality of logarithmic adder-accumulator circuits to convert the data format of the first input data into a logarithmic data format and output the first input data having the logarithmic data format to the logarithmic adder circuit of the associated logarithmic adder-accumulator circuit. as well as A third data format conversion circuit system is coupled between the second memory and the input of each of the plurality of logarithmic adder-accumulator circuits to convert the data format of the filter weight data into a logarithmic data format.

9. An integrated circuit, comprising: A logarithmic addition-accumulation execution pipeline, coupled to a first memory, includes multiple logarithmic addition-accumulation circuits to perform logarithmic addition and accumulation operations in operation, wherein each logarithmic addition-accumulation circuit includes: A logarithmic adder circuit, coupled to a first memory, adds first input data in logarithmic data format and filter weight data in logarithmic data format, and outputs a first sum data in logarithmic data format based on this sum. A first data format conversion circuit system, coupled to the logarithmic adder circuit of an associated logarithmic adder-accumulator circuit, converts the logarithmic data format of the first sum data received from the logarithmic adder circuit of the associated logarithmic adder-accumulator circuit into a floating-point data format including a first precision. An accumulator, coupled to an associated logarithmic adder-accumulator circuitry, is a first data format conversion circuitry system that adds second input data to first sum data having a floating-point data format including a first precision to generate first accumulated data; and The logarithmic adder-accumulator execution pipeline wherein the plurality of logarithmic adder-accumulator circuits perform a plurality of logarithmic addition and accumulation operations in operation, and the logarithmic adder-accumulator execution pipeline can be configured to output processed data. Specifically, the first data format conversion circuit system converts the data format of the first sum data of each logarithmic adder circuit into a floating-point data format with a first precision, and the second input data includes a floating-point data format with a second precision; and the accumulator of each of the plurality of logarithmic adder-accumulator circuits adds the second input data with a floating-point data format including the second precision to the first sum data with a floating-point data format including the first precision to generate the first accumulated data, wherein the first precision and the second precision are different, and The first precision and the second precision depend on at least one of the following: available / allocated memory bandwidth, available / allocated wiring bandwidth, and the amount of area within the integrated circuit available / allocated for storing, transmitting / reading and / or processing data.

10. The integrated circuit of claim 9, wherein: The logarithmic adder-accumulator pipeline consists of multiple logarithmic adder-accumulator circuits connected in series to form a ring architecture, and performs multiple cascaded logarithmic addition and accumulation operations in operation.

11. The integrated circuit of claim 9, further comprising: A second data format conversion circuit system is coupled between the first memory and the input of each of the plurality of logarithmic adder-accumulator circuits to: (i) convert the data format of the first input data into a logarithmic data format and (ii) output the first input data having the logarithmic data format to the logarithmic adder circuit of the associated logarithmic adder-accumulator circuit. as well as A third data format conversion circuit system is coupled between the second memory and the input of each of the plurality of logarithmic adder-accumulator circuits to convert the data format of the filter weight data into a logarithmic data format.

12. A method for performing multiple logarithmic addition and accumulation operations by executing a pipelined logarithmic adder-accumulator circuit, wherein the logarithmic adder-accumulator circuit includes a logarithmic adder circuit and an accumulator, the method comprising: A plurality of first input data having a first data format are converted into a plurality of first input data having a logarithmic data format, wherein the first data format is different from the logarithmic data format; Each first input data having a logarithmic data format is added to the associated filter weights having a logarithmic data format in a logarithmic manner to generate a first sum data having a logarithmic data format; Convert each first sum data with logarithmic data format into a first sum data with floating-point data format; as well as Each first sum data having a floating-point data format is added to the second input data having a floating-point data format to generate a first accumulated data having a floating-point data format. The floating-point data format of the first sum includes a precision different from that of the floating-point data format of the first accumulated data, and The precision of the floating-point data format of the first sum data and the precision of the floating-point data format of the first accumulated data depend on at least one of the following: available / allocated memory bandwidth, available / allocated wiring bandwidth, and the amount of area within the integrated circuit available / allocated for storing, transmitting / reading and / or processing data.

13. The method of claim 12, wherein: The first data format is a floating-point data format with a first precision; and The floating-point data format of the first accumulated data includes a second precision.

14. The method of claim 12, further comprising: Before adding each first input data point to the associated filter weight in a logarithmic manner, each of the multiple filter weights is converted from a logarithmic data format with first precision to a logarithmic data format with second precision.

15. The method of claim 12, further comprising: Before adding each first input data point to the associated filter weight in a logarithmic manner, each of the multiple filter weights is converted to a logarithmic data format.

16. The method of claim 15, wherein: The first data format is floating-point data format.

17. A method for performing multiple logarithmic addition and accumulation operations via a logarithmic adder-accumulator circuit including a logarithmic adder circuit and an accumulator, the method comprising: A plurality of first input data having a first data format are converted into a plurality of first input data having a logarithmic data format, wherein the first data format is different from the logarithmic data format; Each first input data having a logarithmic data format is added to the associated filter weights having a logarithmic data format in a logarithmic manner to generate the first sum data; Transform each first sum of data into a first sum of data with a fixed-point data format; as well as Each first sum data having a fixed-point data format is added to the associated second input data having a fixed-point data format to generate a first accumulated data having a fixed-point data format. The fixed-point data format of the first sum data includes a precision different from that of the fixed-point data format of the first accumulated data, and The precision of the first sum data and the precision of the first accumulated data depend on at least one of the following: available / allocated memory bandwidth, available / allocated wiring bandwidth, and the amount of area within the integrated circuit available / allocated for storing, transmitting / reading and / or processing data.

18. The method of claim 17, further comprising: Before adding each first input data point to the associated filter weight in a logarithmic manner, each of the multiple filter weights is converted from a logarithmic data format with first precision to a logarithmic data format with second precision.

19. The method of claim 17, further comprising: Before adding each first input data point to the associated filter weight in a logarithmic manner, each of the multiple filter weights is converted to a logarithmic data format.

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