Display Panel

Abstract

At least one embodiment of the present disclosure provides a display panel, which includes: a first substrate and a second substrate that are aligned with each other, wherein the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer and a second electrode that are sequentially arranged on the base substrate; the first interlayer insulating layer has a first via hole that penetrates the first interlayer insulating layer, the second electrode is electrically connected to the first electrode through the first via hole, and a first supporting structure is arranged in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a portion of the first supporting structure is located in the first via hole; and an orthographic projection of the first via hole on the base substrate and an orthographic projection of the gate line on the base substrate at least partially overlap. The display panel improves the resolution and aperture ratio of the display panel by making at least a portion of the first supporting structure located in the first via hole and making the orthographic projection of the first via hole on the base substrate and the orthographic projection of the gate line on the base substrate at least partially overlap.

Description

[0001] This application claims priority to Chinese Patent Application No. 202210041921.7 filed on January 14, 2022. The contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as a part of this application. Technical Field

[0002] An embodiment of the present disclosure relates to a display panel. Background Art

[0003] Ultra-high PPI products (such as PPI ranging from several hundred to several thousand) are being developed by various manufacturers for use in virtual reality display, sights and other markets and will gradually come into the user's field of vision.

[0004] Take virtual reality technology as an example. Virtual reality technology is a new technology that "seamlessly" integrates real-world information and virtual-world information. Compared with conventional display products, the most obvious feature of virtual reality display products is their ultra-high resolution. With the development of optoelectronic technology and semiconductor manufacturing technology, in display devices, for example, Thin Film Transistor Liquid Crystal Display (TFT-LCD) has a dominant position in the current display market with its superior characteristics such as high-quality image quality, high space utilization, low power consumption, and no radiation. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a display panel, which improves the resolution and aperture ratio of the display panel by making at least a portion of a first supporting structure located in a first via hole, and making the orthographic projection of the first via hole on a base substrate and the orthographic projection of a gate or a gate line on the base substrate at least partially overlap.

[0006] At least one embodiment of the present disclosure provides a display panel, which includes: a first substrate and a second substrate that are aligned with each other, wherein the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer and a second electrode that are sequentially arranged on the base substrate; the first interlayer insulating layer has a first via hole that penetrates the first interlayer insulating layer, the second electrode is electrically connected to the first electrode through the first via hole, and a first supporting structure is arranged in an area corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a portion of the first supporting structure is located in the first via hole; and the orthographic projection of the first via hole on the base substrate and the orthographic projection of the gate line on the base substrate at least partially overlap.

[0007] For example, in the display panel provided in at least one embodiment of the present disclosure, the first substrate is an array substrate, and the array substrate includes the gate lines and data lines arranged horizontally and vertically crosswise on the base substrate, and a plurality of pixel units; the pixel unit includes: the first electrode, the second electrode and the first interlayer insulating layer; the second electrode is in contact with the surface of the first interlayer insulating layer away from the base substrate, and the second electrode extends from the upper surface of the first interlayer insulating layer to the side wall and the lower opening area of ​​the first via hole and is connected to the first electrode located in the lower opening area.

[0008] For example, in the display panel provided by at least one embodiment of the present disclosure, the first interlayer insulating layer at least includes a planarization layer, and the first via hole penetrates the planarization layer.

[0009] For example, in the display panel provided by at least one embodiment of the present disclosure, the surface of the first supporting structure close to the second substrate is a plane or a concave surface that is recessed toward one side of the base substrate.

[0010] For example, in the display panel provided by at least one embodiment of the present disclosure, the first supporting structure extends downward in the first via hole to a lower opening area of ​​the first via hole.

[0011] For example, in the display panel provided in at least one embodiment of the present disclosure, the first supporting structure extends upward in the first via hole to the upper opening area of ​​the first via hole and the top of the first supporting structure is higher than the upper surface of the first interlayer insulating layer.

[0012] For example, in the display panel provided in at least one embodiment of the present disclosure, the pixel unit also includes a third electrode located above the upper surface of the first interlayer insulating layer, and a second interlayer insulating layer is arranged between the third electrode and the second electrode on the upper surface of the first interlayer insulating layer; the second interlayer insulating layer includes an opening that penetrates the first interlayer insulating layer, and the first supporting structure extends toward the second substrate and has a protruding structure that is higher than the second interlayer insulating layer.

[0013] For example, in the display panel provided in at least one embodiment of the present disclosure, the third electrode includes metal oxide strip portions spaced apart from each other and located on the upper surface of the second interlayer insulating layer, and metal portions distributed between the metal oxide strip portions.

[0014] For example, in the display panel provided in at least one embodiment of the present disclosure, the third electrode includes a metal portion and a metal oxide strip portion covering the side surface and the upper surface of the metal portion, and in a direction parallel to the main surface of the base substrate, the third electrode includes a plurality of portions spaced apart from each other.

[0015] For example, in the display panel provided by at least one embodiment of the present disclosure, the portion of the first supporting structure that exceeds the upper surface of the first interlayer insulating layer and the upper surface of the second interlayer insulating layer has a rectangular or trapezoidal cross-sectional shape in a direction perpendicular to the main surface of the base substrate and perpendicular to the extension direction of the gate line, or a trapezoidal-like shape with an upper surface recessed toward one side of the base substrate.

[0016] For example, in the display panel provided in at least one embodiment of the present disclosure, the first supporting structure extends beyond the upper surface of the second interlayer insulating layer toward the second substrate, and extends along the upper surface of the second interlayer insulating layer away from the first via hole.

[0017] For example, in the display panel provided by at least one embodiment of the present disclosure, the pixel unit also includes a thin film transistor, which includes a semiconductor layer, a source and a drain arranged at intervals, and the source and the drain are connected to the semiconductor layer; the second electrode is the pixel electrode of the pixel unit; the first electrode is the drain or a switching electrode used to connect the drain and the pixel electrode.

[0018] For example, in the display panel provided in at least one embodiment of the present disclosure, the first interlayer insulating layer at least includes an organic planarizing layer, the second interlayer insulating layer at least includes an inorganic insulating layer, and the third electrode is a common electrode of the pixel unit.

[0019] For example, in the display panel provided in at least one embodiment of the present disclosure, the material of the drain electrode includes a transparent metal oxide conductive material.

[0020] For example, in the display panel provided in at least one embodiment of the present disclosure, the opening width d of the first via hole close to the upper surface of the first interlayer insulating layer satisfies: d≤(K1*M / PPI)*(1-AR*1 / (1-D min *PPI / M)), and M is a fixed value of 25400μm; PPI is pixel density, and the pixel density is the number of pixel units per inch, 1 inch = 25400μm; the width of a single pixel unit P = M / PPI = 25400μm / PPI, K1 is the aspect ratio of a single pixel, AR is the aperture ratio, PPI is the pixel density, D min It is the process exposure limit value.

[0021] For example, in the display panel provided by at least one embodiment of the present disclosure, the opening width d of the first via hole close to the upper surface of the first interlayer insulating layer satisfies: d≈(K1*M / PPI)*(1-AR).

[0022] For example, in the display panel provided in at least one embodiment of the present disclosure, it also includes a thin film transistor, which includes a source and a drain arranged at intervals, and in the direction perpendicular to the main surface of the base substrate, the angle formed by the edge of the first via hole close to the source and the plane where the main surface of the base substrate is located is α, and the angle formed by the edge of the first via hole close to the drain and the plane where the main surface of the base substrate is located is β, and α≥β.

[0023] For example, in the display panel provided in at least one embodiment of the present disclosure, α>β, and the difference between α and β ranges from 0.5 to 3°.

[0024] For example, in a display panel provided in at least one embodiment of the present disclosure, D min ≤W gate ≤d, d=2.0μm~10μm, D min =1.5μm~2μm.

[0025] For example, in the display panel provided in at least one embodiment of the present disclosure, the design of the first via hole satisfies that the absolute value range of (d1-d2)-tanβ1*d3 is between 0 and 1.5, d1 is the opening width of the first via hole on the side away from the base substrate, d2 is the opening width of the first via hole on the side close to the base substrate, d3 is the thickness of the first interlayer insulation, and β1 is the angle between the side wall of the first via hole and the horizontal plane of the base substrate.

[0026] For example, in the display panel provided in at least one embodiment of the present disclosure, the first substrate also includes a switching transistor arranged on the base substrate; the switching transistor is arranged in the display area; the switching transistor includes a first insulating layer, a light shielding layer, a second insulating layer, a metal oxide semiconductor layer, a gate insulating layer, a first gate, a third insulating layer, a first source, a fourth insulating layer and a first drain which are sequentially stacked on the base substrate, and the first electrode is electrically connected to the metal oxide semiconductor layer through a third via hole that sequentially penetrates the fourth insulating layer, the third insulating layer and the gate insulating layer to serve as the first drain, and the first source is electrically connected to the metal oxide semiconductor layer through a fourth via hole that sequentially penetrates the third insulating layer and the gate insulating layer.

[0027] For example, in the display panel provided by at least one embodiment of the present disclosure, the first substrate also includes a switching transistor arranged on the base substrate; the switching transistor is arranged in the display area; the switching transistor includes a light shielding layer, a buffer layer, a first polysilicon layer, a gate insulating layer, a first gate, a third insulating layer, a basic electrode layer, a fourth insulating layer, a first drain, a fifth insulating layer and a first source which are sequentially stacked on the base substrate, the basic electrode layer includes a first basic electrode and a second basic electrode which are relatively arranged, and the first electrode is electrically connected to the first basic electrode through a fifth via hole penetrating the fourth insulating layer to serve as the first drain, and the first basic electrode is electrically connected to the first polysilicon layer through a sixth via hole penetrating the third insulating layer and the gate insulating layer; the first source is electrically connected to the second basic electrode through a seventh via hole penetrating the fifth insulating layer and the fourth insulating layer in sequence, and the second basic electrode is electrically connected to the first polysilicon layer through an eighth via hole penetrating the third insulating layer and the gate insulating layer.

[0028] For example, in the display panel provided in at least one embodiment of the present disclosure, in a direction parallel to the main surface of the base substrate, the contact portion of the first electrode and the second electrode is located between the fifth via hole and the seventh via hole, and the orthographic projection of the contact portion of the first electrode and the second electrode on the base substrate at least partially overlaps with the orthographic projection of the first gate on the base substrate.

[0029] For example, in the display panel provided in at least one embodiment of the present disclosure, in a direction parallel to the main surface of the base substrate, the distance between the side of the contact portion of the first electrode and the second electrode close to the fifth via hole and the sixth via hole is equal to the length of the first electrode not covering the first gate.

[0030] For example, in the display panel provided in at least one embodiment of the present disclosure, in a direction parallel to the main surface of the base substrate, the endpoints of both ends of the light-shielding layer are located between the seventh via hole and the fifth via hole, and the contact portion of the first electrode and the second electrode is located between the seventh via hole and the endpoint of the light-shielding layer close to the fifth via hole.

[0031] For example, in the display panel provided in at least one embodiment of the present disclosure, a second supporting structure is arranged on the second substrate, and a surface of the first supporting structure close to the second substrate and a surface of the second supporting structure close to the first substrate are in contact with or maintain a set distance.

[0032] For example, in the display panel provided by at least one embodiment of the present disclosure, the orthographic projection of the second supporting structure on the base substrate and the orthographic projection of the first supporting structure on the base substrate at least partially overlap.

[0033] For example, in the display panel provided in at least one embodiment of the present disclosure, the contact surface area between the second supporting structure and the first supporting structure is smaller than the cross-sectional area of ​​the second supporting structure or the first supporting structure close to the base substrate.

[0034] For example, in the display panel provided in at least one embodiment of the present disclosure, the first interlayer insulating layer has a second via hole penetrating the first interlayer insulating layer, the second via hole is provided with a third supporting structure, and the orthographic projection of the third supporting structure on the base substrate and the orthographic projection of the second supporting structure on the base substrate have no overlapping parts.

[0035] For example, in the display panel provided in at least one embodiment of the present disclosure, the third supporting structure extends away from the base substrate and outside the second via hole, and the third supporting structure fills the second via hole so that the shape inside the second via hole is adapted to the shape of the second via hole.

[0036] For example, in the display panel provided by at least one embodiment of the present disclosure, a longitudinal cross-section of a portion of the third supporting structure extending outside the second via hole is in a trapezoidal shape.

[0037] For example, in the display panel provided in at least one embodiment of the present disclosure, the yield strength of the second supporting structure is greater than the product of the bonding pressure of the first substrate and the second substrate when they are bonded, the area of ​​a single second supporting structure, and the number of the second supporting structures.

[0038] For example, in the display panel provided in at least one embodiment of the present disclosure, the planarization layer and the first supporting structure are both made of light-transmitting materials.

[0039] For example, in the display panel provided in at least one embodiment of the present disclosure, the material of the first supporting structure is a light shielding material, and the extension direction of the first supporting structure is parallel to the extension direction of the gate line. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0041] Figure 1 A schematic diagram of a cross-sectional structure of a display panel provided in at least one embodiment of the present disclosure;

[0042] Figure 2 A schematic diagram of a planar structure of a first substrate provided in at least one embodiment of the present disclosure;

[0043] Figure 3 A schematic cross-sectional structure diagram of yet another display panel provided in at least one embodiment of the present disclosure;

[0044] Figure 4 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure;

[0045] Figure 5 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure;

[0046] Figure 6 for Figure 5 a perspective view of the second electrode and the third electrode in the cross-sectional structure shown;

[0047] Figure 7 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure;

[0048] Figure 8 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure;

[0049] Fig. 9 A perspective view of another second electrode and a third electrode provided for at least one embodiment of the present disclosure;

[0050] Fig.10 for Fig. 9 A schematic diagram of the cross-sectional structure of the structure shown in;

[0051] Fig.11 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure;

[0052] Fig.12 A scanning electron microscope image of a first support structure provided for at least one embodiment of the present disclosure;

[0053] Fig.13 A perspective structural schematic diagram of a first substrate provided in at least one embodiment of the present disclosure;

[0054] Fig.14 A perspective structural schematic diagram of another first substrate provided for at least one embodiment of the present disclosure;

[0055] Fig.15 A process diagram of a method for preparing a display panel provided in at least one embodiment of the present disclosure;

[0056] Fig.16 A process diagram of another method for preparing a display panel provided in at least one embodiment of the present disclosure;

[0057] Fig.17A process diagram of another method for preparing a display panel provided for at least one embodiment of the present disclosure; and

[0058] Fig.18 A process diagram of another method for preparing a display panel provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0061] With the development of display technology, in the VR display, sight and other market segments, improving the resolution, aperture ratio and light efficiency of display panels has become a research focus for technical personnel in this field.

[0062] The inventors of the present disclosure noticed that a display panel usually includes a first substrate having an interlayer insulating layer, a via structure is provided in the interlayer insulating layer, an electrode is provided in the via structure, a support structure is provided in an area of ​​the interlayer insulating layer where the via structure is not provided, and there is no overlapping part between the orthographic projection of the gate line on the base substrate and the orthographic projection of the via structure on the base substrate, so that the resolution and aperture ratio of the display panel are relatively low. Therefore, it is possible to consider changing the design of the display panel structure to improve the resolution and aperture ratio of the display panel.

[0063] The inventors of the present disclosure also noticed that in the usual design, the supporting structure is only provided on the first substrate or the second substrate. In this way, the display area corresponding to the first substrate or the display area corresponding to the second substrate is easily scratched during the process of aligning the first substrate and the second substrate. Therefore, it is possible to consider respectively providing the first supporting structure and the second supporting structure on the first substrate and the second substrate, so that during the process of aligning the first substrate and the second substrate, the surface of the first supporting structure close to the second substrate and the surface of the second supporting structure close to the first substrate are in contact with each other, so as to support the second substrate and form a gap between the first substrate and the second substrate, so as to avoid scratching the display area corresponding to the first substrate or the display area corresponding to the second substrate during the process of aligning the first substrate and the second substrate, thereby reducing the risk of light leakage at the edge.

[0064] At least one embodiment of the present disclosure provides a display panel, which can be applied to a high-resolution liquid crystal display panel, the display panel comprising: a first substrate (such as an array substrate) and a second substrate that are aligned with each other, and a liquid crystal layer between the first substrate and the second substrate, wherein the first substrate comprises a base substrate, and a gate line, a first electrode, a first interlayer insulating layer and a second electrode that are sequentially arranged on the base substrate; the first interlayer insulating layer has a first via hole that penetrates the first interlayer insulating layer, the second electrode is electrically connected to the first electrode through the first via hole, a first supporting structure is arranged in the area corresponding to the first via hole and on the side of the second electrode away from the base substrate; at least part of the first supporting structure is located in the first via hole; and the orthographic projection of the first via hole on the base substrate and the orthographic projection of the gate line on the base substrate at least partially overlap. The embodiment of the present disclosure improves the resolution and aperture ratio of the display panel by making at least part of the first supporting structure located in the first via hole, and making the orthographic projection of the first via hole on the base substrate and the orthographic projection of the gate line on the base substrate at least partially overlap.

[0065] For example, Figure 1 A schematic diagram of a cross-sectional structure of a display panel provided in at least one embodiment of the present disclosure is shown in FIG. Figure 1As shown, the display panel 10 includes: a first substrate 101 and a second substrate 102 that are aligned with each other, wherein the first substrate 101 includes a base substrate 1011, and a gate line 1022, a first electrode 1012, a first interlayer insulating layer 1013, and a second electrode 1014 that are sequentially arranged on the base substrate 1011, the first interlayer insulating layer 1013 has a first via hole 1015 that penetrates the first interlayer insulating layer 1013, the second electrode 1014 is electrically connected to the first electrode 1012 through the first via hole 1015, a first supporting structure 1016 is arranged in a region corresponding to the first via hole 1015 and on a side of the second electrode 1014 away from the base substrate 1011; at least a portion of the first supporting structure 1016 is located in the first via hole 1015; and the orthographic projection of the first via hole 1015 on the base substrate 1011 and the orthographic projection of the gate line 1022 on the base substrate 1011 at least partially overlap. For example, Figure 1 The display panel 10 shown improves the resolution and aperture ratio of the display panel 10 by positioning at least a portion of the first support structure 1016 within the first via hole 1015 and by causing the orthographic projection of the first via hole 1015 on the base substrate 1011 and the orthographic projection of the gate line 1022 on the base substrate 1011 to at least partially overlap.

[0066] For example, the first support structure 1016 has a top portion that is close to and opposite to the bottom of the base substrate 1011 , and a side portion.

[0067] For example, it should be noted that the first support structure 1016 is located in the area corresponding to the first via hole 1015, which may be an area where the first support structure 1016 and the first via hole 1015 have at least a partial overlap. In some embodiments, the projection of the first support structure 1016 is located in the overlapping area between the first support structure 1016 and the first via hole 1015. In other embodiments, a portion of the projection of the first support structure 1016 is located in the overlapping area between the first support structure 1016 and the first via hole 1015, for example, the first support structure 1016 is located in the opening area of ​​the first via hole 1015 and in the area extending from the opening area of ​​the first via hole 1015 to the outside.

[0068] For example, Figure 2 A schematic diagram of a planar structure of a first substrate provided in at least one embodiment of the present disclosure is shown as follows: Figure 2 As shown, the first substrate 101 is an array substrate, which includes the gate lines 1022 and data lines 1024 arranged horizontally and vertically on the base substrate 1011, and a plurality of pixel units 1025. Figure 1 and Figure 2As shown, the pixel unit 1025 includes: a first electrode 1012, a second electrode 1014 and a first interlayer insulating layer 1013 between the first electrode 1012 and the second electrode 1014, the second electrode 1014 is in contact with the surface of the first interlayer insulating layer 1013 away from the base substrate 1011, and the second electrode 1014 extends from the upper surface of the first interlayer insulating layer 1013 to the side wall and the lower opening area of ​​the first via 1015 and is in contact with and connected to the first electrode 1012 located in the lower opening area.

[0069] In some implementations, the first interlayer insulating layer 1013 is a single-layer film layer, for example, a single-layer flat layer, and the material may be an organic transparent film layer.

[0070] In some embodiments, the first interlayer insulating layer 1013 is a laminated insulating layer, which may be a multilayer (including two layers). In terms of material, it may be a laminated layer of organic and inorganic insulating layers, or a laminated layer of multiple inorganic insulating layers. The laminated layer of multiple inorganic insulating layers may be a film layer containing different element types, such as a laminated layer of silicon oxide and silicon nitride, or a laminated layer of film layers of the same type of elements but with different molar ratios, for example, each film layer is SixOy, but the values ​​of x or y are different.

[0071] In some embodiments, Figure 1 As shown, the first interlayer insulating layer 1013 is a flat layer having two main surfaces, namely an upper surface and a lower surface, wherein the upper surface is far away from the base substrate 1011, and the lower surface is closer to the base substrate 1011. The first interlayer insulating layer 1013 has a first via hole 1015, and the first via hole 1015 has a side wall, an opening close to the upper surface of the first interlayer insulating layer 1013 (which may be referred to as an upper opening or an upper hole opening), and an opening close to the lower surface of the first interlayer insulating layer 1013 (which may be referred to as a lower opening or a lower hole opening).

[0072] In some embodiments, no other insulating layer is disposed on the first interlayer insulating layer 1013, and the first supporting structure 1016 is filled in the first via hole 1015 of the first interlayer insulating layer 1013 to support the first substrate 101 and the second substrate 102 to ensure a box thickness within a certain range.

[0073] In some embodiments, one or more insulating layers may be disposed on the first interlayer insulating layer 1013, the multiple insulating layers may not be provided with openings or some film layers may be provided with openings that can expose the first supporting structure 1016, at least some film layers cover the first supporting structure 1016, and the film layers are formed on the first interlayer insulating layer 1013 according to the shape of the first supporting structure 1016, so that even if the first supporting structure 1016 is covered by other film layers, the height can still support the first substrate 101 and the second substrate 102, and the cumulative thickness of other covered film layers needs to be considered when designing the support height.

[0074] In one implementation, the first supporting structure 1016 extends toward the second substrate 102 and has a protruding structure higher than the second interlayer insulating layer 1019 .

[0075] In one embodiment, a second interlayer insulating layer 1019 is formed on the first interlayer insulating layer 1013. When the second interlayer insulating layer 1019 is formed on the first interlayer insulating layer 1013 by a deposition method, one embodiment is that the second interlayer insulating layer 1019 is also located in the first via hole 1015. Another embodiment is that the area of ​​the second interlayer insulating layer 1019 corresponding to the first via hole 1015 is removed and only a portion of the upper surface of the first interlayer insulating layer 1013 is retained.

[0076] Regardless of whether the area of ​​the second interlayer insulating layer 1019 corresponding to the first via hole 1015 is removed, the second interlayer insulating layer 1019 is formed on the first interlayer insulating layer 1013 having the first via hole 1015 by a deposition method, and a similar via hole is formed. The via hole still has a hole wall shape almost similar to the first via hole 1015 and two upper and lower openings at approximately the same position, that is, a similar via hole can be formed according to the shape of the first via hole 1015. Accordingly, the second interlayer insulating layer 1019 also has an upper surface, a lower surface, a via hole, an opening close to the upper surface, and an opening close to the lower surface.

[0077] For example, Figure 2 As shown, the pixel unit 1025 is a pixel area defined by the gate lines 1022 and the data lines 1024 arranged horizontally and vertically and intersectingly, and a pixel structure is arranged in the pixel unit 1025.

[0078] For example, in one example, the first interlayer insulating layer 1013 includes at least a planarization layer, and the first via 1015 is a through hole that penetrates the planarization layer. The planarization layer can play a planarizing role and reduce the parasitic capacitance between electrodes or signal lines, so that the electrical signal in the display panel is more stable.

[0079] In one example, the planarization layer and the first support structure 1016 included in the first interlayer insulating layer 1013 are made of light-transmitting materials, such as organic resin, to improve the light transmittance of the display panel. The first support structure 1016 of the light-transmitting material has greater freedom in design size and is not restricted by the gate lines below.

[0080] In another example, the material of the first supporting structure 1016 is a light-shielding material, which can effectively reduce light leakage in the area. However, in order to increase the aperture ratio, the projection of the first supporting structure is located within the projection of the gate line therebelow.

[0081] In some embodiments, the first support structure 1016 is located above the gate line, at least fills in the first via hole 1015 and extends in the width direction and length direction of the gate line 1022 when extending on the upper surface of the first interlayer insulating layer 1013 or the second interlayer insulating layer 1019. In some embodiments, the first support structure 1016 may exceed the edge of the gate line 1022 in the width direction, or may be located within the contour of the gate line 1022. In some embodiments, the first support structure 1016 may extend in the length direction of the gate line 1022, for example, parallel to the extension direction of the gate line 1022.

[0082] A plurality of first support structures 1016 may be disposed above a gate line 1022, for example, one first support structure 1016 may be disposed corresponding to one pixel unit. Then, adjacent first support structures 1016 may be disposed separately from each other, or may be connected to each other, for example, by an extension portion of the first support structure 1016.

[0083] For example, in one example, the surface of the first support structure 1016 close to the second substrate 102 is a plane or a concave surface that is recessed toward one side of the base substrate 1011. Figure 1 In the structure shown, the surface of the first support structure 1016 close to the second substrate 102 is a concave surface that is recessed toward one side of the base substrate 1011 .

[0084] For example, it should be noted that the surface of the first supporting structure 1016 close to the second substrate 102 may also be a convex surface protruding toward the second substrate 102 .

[0085] For example, Figure 1As shown, between the first substrate 101 and the second substrate 102, there is also provided a second supporting structure 1021 which cooperates with the first supporting structure 1016 to support the first substrate 101 and the second substrate 102. One of the first supporting structure 1016 and the second supporting structure 1021 is located on the first substrate 101, and the other is located on the second substrate 102. When the first substrate 101 and the second substrate 102 are aligned, the first supporting structure 1016 and the second supporting structure 1021 can contact each other or maintain a certain distance, and define a space for accommodating the liquid crystal layer 104 between the first substrate 101 and the second substrate 102. The shapes of the contact positions of the first supporting structure 1016 and the second supporting structure 1021 can adapt to each other. For example, if the surface of the first supporting structure 1016 close to the second substrate 102 is concave or flat, then the surface of the second supporting structure 1021 close to the first substrate 101 may be convex or flat; if the surface of the first supporting structure 1016 close to the second substrate 102 is convex or flat, then the surface of the second supporting structure 1021 close to the first substrate 101 may be concave or flat.

[0086] It should be noted that, in the embodiments of the present disclosure, the contact between the surface of the first supporting structure 1016 close to the second substrate 102 and the surface of the second supporting structure 1021 close to the first substrate 101 means that the top surface of the first supporting structure 1016 and the top surface of the second supporting structure 1021 are in contact with at least a portion of the area, so that there is a maximum gap between the first substrate 101 and the second substrate 102 in the direction perpendicular to the main surface of the base substrate 1011, or, the contact between the surface of the first supporting structure 1016 close to the second substrate 102 and the surface of the second supporting structure 1021 close to the first substrate 101 can also mean that the portion of the first supporting structure 1016 at other positions close to the surface of the second substrate 102 and the portion of the second supporting structure 1021 at other positions close to the surface of the first substrate 101 are in contact, as long as there is a gap between the first substrate 101 and the second substrate 102, when the first substrate 101 and the second substrate 102 are aligned, the display area corresponding to the first substrate 101 or the display area corresponding to the second substrate 102 will not be scratched, and there will be no problem of light leakage in the edge area. Furthermore, by disposing the first supporting structure 1016 in the area corresponding to the first via hole 1015 , the problem of light leakage caused by the first via hole 1015 can be avoided.

[0087] For example, in one example, the first support structure 1016 completely fills the first via hole 1015 of the first interlayer insulating layer 1013 and protrudes outside the first via hole 1015. The surface of the first support structure 1016 close to the second substrate 102 is a concave surface, which increases the surface area of ​​the surface, so that the contact area between the first support structure 1016 and the second support structure 1021 is larger, thereby increasing the effective support area of ​​the first support structure 1016 for the second substrate 102 and reducing the risk of the second support structure 1021 sliding off the first substrate 101. Moreover, most of the structure of the first support structure 1016 is located in the first via hole 1015. For example, in one example, the height of the first support structure 1016 is about 0.6 μm, which can meet the requirements of the display panel for the gap size.

[0088] For example, the area of ​​the contact surface between the second supporting structure 1021 and the first supporting structure 1016 is smaller than the area of ​​the cross section of the second supporting structure 1021 or the first supporting structure 1016 close to the base substrate 1011.

[0089] It should be noted that the second substrate 102 may include a substrate and a film layer structure disposed on the substrate.

[0090] For example, Figure 1 As shown, the surface of the first support structure 1016 close to the second substrate 102 is recessed toward the side of the base substrate 1011, and the surface of the second support structure 1021 close to the first substrate 101 is convex toward the side of the first substrate 101. This structural design allows the second support structure 1021 to contact the recessed part of the first support structure 1016, so that the second support structure 1021 must first move upward when sliding off the first substrate 101. This design can make it more difficult for the second support structure 1021 to slide off the first support structure 1016, so that the size of the gap 103 between the first substrate 101 and the second substrate 102 on the main surface perpendicular to the base substrate 1011 can be kept constant. Figure 1 As shown, the dimension of the gap 103 between the first substrate 101 and the second substrate 102 on the main surface perpendicular to the base substrate 1011 is a+b, which is smaller than the dimension a+c, wherein a is the maximum dimension of the second support structure 1021 on the main surface perpendicular to the base substrate 1011, b is the minimum distance from the surface of the first support structure 1016 away from the base substrate 1011 to the surface of the first via 1015 away from the base substrate 1011, and c is the maximum distance from the surface of the first support structure 1016 away from the base substrate 1011 to the surface of the first via 1015 away from the base substrate 1011.

[0091] For example, in one example, the thickness of the liquid crystal cell is a+b, and c>b, and the thickness of the liquid crystal cell affects the response speed of the liquid crystal. The minimum value a of the height of the second support structure 1021 min Determined by process conditions, and a min =1 micron.

[0092] For example, in one example, the cell thickness is 1.6 microns, a min =1 micron, the maximum value of b is 0.6 micron, as a increases, the value of b can decrease, and the minimum value range of b is 0 to 0.6 micron. Preferably, the value of b ranges from 0.30 micron to 0.45 micron.

[0093] For example, Figure 1 As shown, a surface of the first supporting structure 1016 close to the second substrate 102 contacts a surface of the second supporting structure 1021 close to the first substrate 101 to support the second substrate 102 and form a gap between the first substrate 101 and the second substrate 102 .

[0094] For example, Figure 1 As shown, the orthographic projection of the second support structure 1021 on the base substrate 1011 and the orthographic projection of the first support structure 1016 on the base substrate 1011 at least partially overlap.

[0095] For example, Figure 1 As shown, the cross-sectional shape of the second support structure 1021 on a plane perpendicular to the main surface of the base substrate 1011 is semicircular.

[0096] For example, in one example, the yield strength of the second supporting structure 1021 is greater than the product of the pressure of the first substrate 101 and the second substrate 102 when they are aligned, the area of ​​a single second supporting structure 1021 , and the number of the second supporting structures 1021 .

[0097] It should be noted that the yield strength of the second support structure 1021 refers to the maximum pressure at which the material of the second support structure 1021 undergoes elastic deformation, so as to prevent the second support structure 1021 from undergoing plastic deformation during the alignment of the first substrate 101 and the second substrate 102, thereby affecting the alignment effect of the first substrate 101 and the second substrate 102.

[0098] For example, Figure 3 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure is shown in FIG. Figure 3As shown, the surface of the first support structure 1016 close to the second substrate 102 is a convex surface, and the surface of the second support structure 1021 close to the first substrate 101 is a concave surface. The convex surface of the first support structure 1016 abuts against the concave surface of the second support structure 1021. This structural design can make the recessed part of the second support structure 1021 contact with the raised part of the first support structure 1016, so that the second support structure 1021 must move upward before sliding off the first substrate 101. Such a design can make it more difficult for the second support structure 1021 to slide off the first support structure 1016, so that the size of the gap 103 between the first substrate 101 and the second substrate 102 on the main surface perpendicular to the base substrate 1011 can be kept constant.

[0099] It should be noted that the surface of the first support structure 1016 close to the second substrate 102 may also be substantially parallel to the plane of the base substrate 1011 .

[0100] For example, Figure 1 and Figure 3 As shown, the second support structures 1021 correspond to the first support structures 1016 one by one, that is, each first support structure 1016 contacts with a second support structure 1021, and each second support structure 1021 contacts with a first support structure 1016, so that the number of second support structures 1021 and first support structures 1016 is equal.

[0101] For example, Figure 1 As shown, the orthographic projection of the second support structure 1021 on the substrate 1011 and the orthographic projection of the first support structure 1016 on the substrate 1011 at least partially overlap. For example, in one example, the orthographic projection of the second support structure 1021 on the substrate 1011 is located within the orthographic projection of the first support structure 1016 on the substrate 1011. The cross-sectional shape of the second support structure 1021 on a plane perpendicular to the main surface of the substrate 1011 is axisymmetric along a line A-A' connecting two end points A and A' of the x-axis about an axis parallel to the z-axis, and the cross-sectional shape of the first support structure 1016 on a plane perpendicular to the main surface of the substrate 1011 is axisymmetric along a line B-B' connecting two end points B and B' of the x-axis about an axis parallel to the z-axis, the line A-A' is parallel to the line B-B', and the length of the line A-A' is less than the length of the line B-B'.

[0102] For example, Figure 1As shown, the cross-sectional shape of the second support structure 1021 in a plane perpendicular to the main surface of the base substrate 1011 and in a direction perpendicular to the gate line is semicircular, so that the contact between the second support structure 1021 and the first support structure 1016 can be line contact. The embodiments of the present disclosure are not limited thereto, and the cross-sectional shape of the second support structure 1021 in a plane perpendicular to the main surface of the base substrate 1011 can also be rectangular, triangular, etc., and the contact between the second support structure 1021 and the first support structure 1016 can also be surface contact, etc., which is not limited in the embodiments of the present disclosure.

[0103] For example, in Figure 1 and Figure 3 In the structure shown, the first substrate 101 is an array substrate, and the second substrate 102 is a color filter substrate. Alternatively, the first substrate is an array substrate and the color filter function is located on the array substrate, also known as a COA substrate (color film on array, COA), and the second substrate 102 is an opposing substrate.

[0104] In the following embodiments, the first substrate 101 is an array substrate, the second substrate 102 is a color filter substrate, and a liquid crystal layer 104 is provided in the gap 103 between the first substrate 101 and the second substrate 102 as an example for explanation, but the embodiments of the present disclosure are not limited thereto, as long as the ultimately formed structure can satisfy the display function.

[0105] For example, Figure 1 and Figure 3 As shown, the first interlayer insulating layer 1013 has an upper surface and a lower surface, and a first via hole 1015 , wherein the first via hole 1015 has a sidewall, an opening close to the upper surface of the first interlayer insulating layer 1013 , and an opening close to the lower surface of the first interlayer insulating layer 1013 .

[0106] For example, Figure 1 and Figure 3 As shown, the first support structure 1016 extends downward in the first via hole 1015 to the lower opening area of ​​the first via hole 1015 .

[0107] For example, Figure 1 and Figure 3 As shown, the first supporting structure 1016 extends upward from the bottom of the first via 1015 of the first interlayer insulating layer 1013, that is, it extends in a direction away from the main surface of the substrate 1011 to fill the first via 1015 and continues to extend to the outside of the opening of the first via 1015 close to the upper surface of the first interlayer insulating layer, and the first supporting structure 1016 extends to the outside of the first via 1015 on the upper surface of the first interlayer insulating layer 1013, and the part extending outside the first via 1015 overlaps with the upper surface of the first interlayer insulating layer 1013.

[0108] It should be noted that it is not limited to Figure 1 and Figure 3 In the structure shown in , if no other insulating layer is disposed on the first interlayer insulating layer 1013, the first supporting structure 1016 is in contact with the upper surface of the first interlayer insulating layer 1013. If other insulating layers, such as a second interlayer insulating layer, are disposed on the first interlayer insulating layer 1013, the first supporting structure 1016 is in contact with the upper surface of the second interlayer insulating layer. The first supporting structure 1016 extends upward from the bottom of the first via hole 1015 of the first interlayer insulating layer 1013, that is, it extends in a direction away from the main surface of the base substrate 1011 to fill the first via hole 1015 and continues to extend to the upper opening area of ​​the first via hole 1015 close to the upper surface of the first interlayer insulating layer 1013 and continues to extend upward beyond the upper surface of the second interlayer insulating layer, so that at least part of the first supporting structure 1016 is located outside the first via hole 1015 of the first interlayer insulating layer 1013 and contacts the upper surface of the second interlayer insulating layer, thereby making the volume of each first supporting structure 1016 larger and the area of ​​the surface of the first supporting structure 1016 away from the base substrate 1011 larger, so that the second supporting structure 1021 and the first supporting structure 1016 can be in more stable contact, so that the gap 103 between the first substrate 101 and the second substrate 102 is more constant.

[0109] like Figure 1 and Figure 3 As shown, the recessed portion of the first support structure 1016 is located in the middle area of ​​the cross-sectional shape of the first support structure 1016 on a plane perpendicular to the main surface of the substrate 1011, and the surface of the first support structure 1016 away from the substrate 1011 is axisymmetric about the z-axis. By translating the coordinate axis, the position of the surface of the first support structure 1016 away from the substrate 1011 closest to the substrate 1011 can be the intersection of the x-axis and the z-axis, and the recessed portion of the first support structure 1016 is axisymmetric about the z-axis.

[0110] For example, the first via hole 1015 is disposed in the gate line region corresponding to the plurality of pixel units 1025, and one pixel unit 1025 may correspond to one first via hole 1015 and one first support structure 1016 corresponding to the first via hole 1015. The first via hole 1015 is a connection hole between the drain of the thin film transistor in the pixel unit 1025 and the pixel electrode.

[0111] For example, the first electrode 1012 in the first via hole 1015 is connected to the drain of the thin film transistor in the pixel unit 1025, or the first electrode 1012 directly serves as the drain of the thin film transistor and is connected to the semiconductor layer of the thin film transistor.

[0112] For example, Figure 4 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure is shown in FIG. Figure 4 As shown, a second interlayer insulating layer 1019 is further provided on a side of the first interlayer insulating layer 1013 away from the base substrate 1011 , and the first supporting structure 1016 is in contact with an upper surface of the second interlayer insulating layer 1019 . The first supporting structure 1016 extends upward from the bottom of the first via hole 1015 of the first interlayer insulating layer 1013, that is, it extends in the direction away from the main surface of the base substrate 1011 to fill the first via hole 1015 and continues to extend to the upper opening area of ​​the first via hole 1015 close to the upper surface of the first interlayer insulating layer 1013 and continues to extend upward beyond the second interlayer insulating layer 1019. The pixel unit 1025 also includes a third electrode 1110 located on the upper surface of the second interlayer insulating layer 1019, that is, the second interlayer insulating layer 1019 is arranged between the third electrode 1110 and the second electrode 1014 on the upper surface of the first interlayer insulating layer 1013, and the second interlayer insulating layer 1019 includes an opening that penetrates the first via hole 1015 in the first interlayer insulating layer 1013. The first supporting structure 1016 extends toward the second substrate 102 and has a protruding structure that is higher than the second interlayer insulating layer 1019.

[0113] For example, Figure 4 As shown, the third electrode 1110 includes metal oxide strip portions 1110a that are spaced apart from each other and are located on the upper surface of the second interlayer insulating layer 1019, and metal portions 1110b that are distributed between the metal oxide strip portions 1110a. For example, the material of the metal portion 1110b includes a conductive metal, such as copper metal, molybdenum metal, and other materials that have light shielding and conductive properties, and the material of the metal oxide strip portion 1110a includes a transparent conductive material, such as indium tin oxide, etc. The metal portion 1110b can reduce the crosstalk of light in different pixel areas to improve the light effect.

[0114] For example, in one example, the first electrode 1012 can be a drain of a thin film transistor. In one embodiment, the drain is in direct contact with the metal oxide semiconductor layer, such as overlapping. In another embodiment, the drain is a partially conductive region of the metal oxide conductor layer.

[0115] The second electrode 1014 may be a pixel electrode, and the third electrode 1110 may be a common electrode of the pixel unit.

[0116] For example, Figure 4As shown, the materials of the first electrode 1012 and the second electrode 1014 can be transparent metal oxide conductor materials. The metal oxide strip portion 1110a included in the third electrode 1110 is a conductor rather than a semiconductor. The metal portion 1110b included in the third electrode 1110 can block light, thereby reducing the cross-color of different color lights along the z-axis direction, and the metal portion 1110b can also play the role of a black matrix along the x-axis direction, so that when forming the second substrate 102, it is not necessary to make a black matrix along the x-axis direction, and only a black matrix along the y-axis direction that crosses the x-axis direction in a direction parallel to the main surface of the base substrate 1011 needs to be made. Since in the conventional process of making a black matrix, the black matrices in the x-axis direction and the y-axis direction are made in different processes, the process steps of forming the black matrix in the x-axis direction on the second substrate 102 can be reduced.

[0117] For example, Figure 5 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the third electrode 1110 includes a metal portion 1110b and a metal oxide strip portion 1110a covering the side surface and the upper surface of the metal portion 1110b, and the third electrode 1110 includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the base substrate 1011. That is, the combination of the metal portion 1110b and the metal oxide strip portion 1110a covering the side surface of the metal portion 1110a and the surface away from the base substrate 1011 is spaced apart from each other.

[0118] For example, Figure 6 for Figure 5 A perspective view of the second electrode and the third electrode in the cross-sectional structure shown in FIG. Figure 6 As shown, the metal portion 1110b and the metal oxide strip portion 1110a as the common electrode are stacked and contacted, the orthographic projection of the metal portion 1110b on the base substrate 1011 is located within the orthographic projection of the metal oxide strip portion 1110a on the base substrate 1011, and the orthographic projection of the second electrode 1014 on the base substrate 1011 and the orthographic projection of the metal oxide strip portion 1110a on the base substrate 1011 at least partially overlap. The orthographic projection of the second electrode 1014 on the base substrate 1011 is connected between the orthographic projections of the adjacent metal oxide strip portions 1110a on the base substrate 1011.

[0119] For example, Figure 1, 4 and 5, the cross-sectional shape of the portion of the first support structure 1016 that exceeds the upper surface of the first interlayer insulating layer 1013 and the upper surface of the second interlayer insulating layer 1019 in the direction perpendicular to the main surface of the base substrate 1011 and perpendicular to the extension direction of the gate line 1022 is a trapezoidal structure with the upper surface concave toward the side close to the base substrate 1011. Figure 3 As shown, the cross-sectional shape of the portion of the first support structure 1016 that exceeds the upper surface of the first interlayer insulating layer 1013 and the upper surface of the second interlayer insulating layer 1019 in the direction perpendicular to the main surface of the base substrate 1011 and perpendicular to the extension direction of the gate line 1022 is a trapezoidal structure in which the upper surface is convex toward the side away from the base substrate 1011. In other examples, the cross-sectional shape of the portion of the first support structure 1016 that exceeds the upper surface of the first interlayer insulating layer 1013 and the upper surface of the second interlayer insulating layer 1019 in the direction perpendicular to the main surface of the base substrate 1011 and perpendicular to the extension direction of the gate line 1022 can also be a rectangle, a trapezoid, etc., which is not limited in the embodiments of the present disclosure.

[0120] For example, Figure 1 , Figure 3 , Figure 4 and Figure 5 As shown, the first supporting structure 1016 extends beyond the upper surface of the second interlayer insulating layer 1019 toward the second substrate 102, and extends along the upper surface of the second interlayer insulating layer 1019 away from the first via 1015, that is, the first supporting structure 1016 extends beyond the upper surface of the second interlayer insulating layer 1019 in a direction perpendicular to the main surface of the base substrate 1011 and at the same time in a direction parallel to the main surface of the base substrate 1011, and the portion extending in the direction parallel to the main surface of the base substrate 1011 contacts the upper surface of the second interlayer insulating layer 1019, so that the orthographic projection of the first supporting structure 1016 on the base substrate 1011 covers and exceeds the orthographic projection area of ​​the first via 1015 on the base substrate 1011.

[0121] For example, Figure 4 and Figure 5 As shown, the first interlayer insulating layer 1013 further has a second via hole 1017 penetrating the first interlayer insulating layer 1013 , a third supporting structure 1018 is disposed in the second via hole 1017 , and the second via hole 1017 corresponds to the third supporting structure 1018 .

[0122] For example, the second via hole 1017 is similar to the first via hole 1015 and is disposed in a region of the plurality of pixel units 1025 corresponding to the region where the gate line 1022 is disposed. One pixel unit 1025 may correspond to one of the above-mentioned second via holes 1017 and a corresponding third supporting structure 1018. The second via hole 1017 is a connection hole between the drain of the thin film transistor in the pixel unit 1025 and the pixel electrode.

[0123] For example, the first via hole 1015 and the second via hole 1017 are holes in different regions, corresponding to thin film transistors in different regions. The shapes and sizes of the first via hole 1015 and the second via hole 1017 can be the same or different, but the first support structure 1016 and the third support structure 1018 are different. For example, the first support structure 1016 and the second support structure 1021 cooperate to support the first substrate 101 and the second substrate 102, but the third support structure 1018 is used alone to support the first substrate 101 and the second substrate 102. Alternatively, the shapes of the first support structure 1016 and the third support structure 1018 are different. The first via hole 1015 is a hole corresponding to the first support structure 1016, and the second via hole 1017 is a hole corresponding to the third support structure 1018, but it does not mean that the first via hole 1015 and the second via hole 1017 have structural differences. In some embodiments, the first via hole 1015 and the second via hole 1017 are both located in the region corresponding to the gate line 1022 , and the first via hole 1015 and the second via hole 1017 are similar in size and shape.

[0124] For example, in Figure 4 and Figure 5 In the structure shown, the display panel 10 includes two pixel units, and each pixel unit is correspondingly provided with a first via hole 1016 or a second via hole 1017. For each pixel unit, there is a first electrode 1012, a second electrode 1014 and a thin film transistor.

[0125] For example, Figure 4 and Figure 5As shown, a third support structure 1018 is provided in the area corresponding to the second via hole 1017 and on the side of the second electrode 1014 away from the base substrate 1011. The orthographic projection of the third support structure 1018 on the base substrate 1011 and the orthographic projection of the second support structure 1021 on the base substrate 1011 do not have an overlapping part, because the third support structure 1018 only cooperates with the first support structure 1016 to form a larger support structure to support the first substrate 101 and the second substrate 102 to ensure the thickness of the liquid crystal box. The second support structure 1021 does not cooperate with the third support structure 1018 and will not extend to the area where the third support structure 1018 is located. The third support structure 1018 can at least fill the second via hole 1017 to reduce the risk of light leakage from the second via hole 1017.

[0126] For example, Figure 4 and Figure 5 As shown, the third support structure 1018 extends away from the base substrate 1011 to the outside of the second via hole 1017, and the third support structure 1018 fills the second via hole 1017 so that the shape inside the second via hole 1017 is adapted to the shape of the second via hole 1017. Figure 4 and Figure 5 As shown, the third support structure 1018 extends to the outside of the second via hole 1017 along a direction perpendicular to the main surface of the base substrate 1011, that is, extends to the outside of the second via hole 1017 in a direction parallel to the z-axis, and the maximum size of the third support structure 1018 in a direction parallel to the main surface of the base substrate 1011 is equal to the maximum size of the second via hole 1017 in a direction parallel to the main surface of the base substrate 1011. On a plane perpendicular to the main surface of the base substrate 1011 and in a direction parallel to the x-axis, the line connecting the two farthest end points of the third support structure 1018 is the line connecting the two points of the third support structure 1018 in contact with the second electrode 1014, that is, the line connecting the maximum opening of the surface of the first interlayer insulating layer 1013 away from the base substrate 1011 along the x-axis direction.

[0127] For example, Figure 4 and Figure 5 As shown, the third support structure 1018 extends upward from the second via hole 1017 and extends beyond the second via hole 1017 and continues to extend upward and extends to the upper surface of the film layer (eg, the first interlayer insulating layer 1013) where the second via hole 1017 is located.

[0128] For example, Figure 4 and Figure 5As shown, the first via hole 1015 and the second via hole 1017 are formed in the same process step, and the first via hole 1015 and the second via hole 1017 can be formed by patterning using the same mask plate, and the first via hole 1015 and the second via hole 1017 have the same shape and size.

[0129] For example, Figure 4 and Figure 5 As shown in FIG. 1 , the longitudinal section of the portion of the third support structure 1018 extending outside the second via hole 1017 is in the shape of a trapezoid. Figure 4 and Figure 5 As shown, the third support structure 1018 extends to the portion outside the second via hole 1017 along a direction perpendicular to the main surface of the base substrate 1011, and the cross-sectional shape on the plane perpendicular to the main surface of the base substrate 1011 is a right trapezoid, so that the cross-sectional shape of the third support structure 1018 on the plane perpendicular to the main surface of the base substrate 1011 can increase and then decrease along the z-axis direction and from a position close to the base substrate 1011 to a position far from the base substrate 1011.

[0130] For example, Figure 4 and Figure 5 As shown, the second electrode 1014 contacts the surface of the first via 1015 near the base substrate 1011 and the first electrode 1012 to be electrically connected to each other, and the second electrode 1014 contacts the surface of the second via 1017 near the base substrate 1011 and the first electrode 1012 to be electrically connected to each other, thereby ensuring the stability of the connection between the first electrode 1012 and the second electrode 1014. The second electrode 1014 can also completely cover the surfaces of the first via 1015 and the second via 1017 near the base substrate 1011.

[0131] For example, Figure 4 and Figure 5 As shown, the second interlayer insulating layer 1019 is also disposed between the third supporting structure 1018 and the second electrode 1014, a via hole communicating with the second via hole 1017 is disposed in the second interlayer insulating layer 1019, and a third electrode 1110 is disposed on the side of the second interlayer insulating layer 1019 away from the base substrate 1011 around the third supporting structure 1018. The second interlayer insulating layer 1019 can be formed on the side of the first supporting structure 1016 and the third supporting structure 1018 close to the base substrate 101, or on the side of the first supporting structure 1016 and the third supporting structure 1018 away from the base substrate 101, which is not limited in the embodiments of the present disclosure.

[0132] For example, Figure 4 and Figure 5As shown, the third supporting structure 1018 extends to the outside of the second via 1017 along a direction perpendicular to the main surface of the substrate substrate 1011, and the maximum dimension of the third supporting structure 1018 in a direction parallel to the main surface of the substrate substrate 1011 is equal to the maximum dimension of the second via 1017 in a direction parallel to the main surface of the substrate substrate 1011.

[0133] For example, Figure 4 and Figure 5 As shown, the third support structure 1018 extends to a portion outside the second via hole 1017 along a direction perpendicular to the main surface of the base substrate 1011 , and a cross-sectional shape on a plane perpendicular to the main surface of the base substrate 1011 is a regular trapezoid.

[0134] For example, Figure 4 and Figure 5 As shown, the first interlayer insulating layer 1013 includes at least an organic planar layer, the second interlayer insulating layer 1019 includes at least an inorganic insulating layer, the third electrode 1110 is a common electrode of each pixel unit 1025, and an electric field is formed between the pixel electrode and the common electrode to drive the deflection of liquid crystal molecules in the liquid crystal layer 160 between the first substrate 101 and the second substrate 102.

[0135] For example, Figure 7 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the display area of ​​the display panel 100 is a metal oxide thin film transistor. The TFT in the GOA area can be a LTPS or a metal oxide thin film transistor.

[0136] For example, in some embodiments, the semiconductor layer of the thin film transistor on the first substrate 101 includes low temperature polysilicon and metal oxide semiconductor. The first substrate 101 also includes a driving transistor 120 and a switching transistor 130 disposed on the base substrate 1011, the switching transistor 130 is disposed in the display area AA, and the driving transistor 120 is disposed in the peripheral area NA surrounding the display area AA.

[0137] For example, Figure 7As shown, the switching transistor 130 in the pixel unit area includes a first insulating layer 1301, a light shielding layer 1302, a second insulating layer 1303, a metal oxide semiconductor layer 1304, a gate insulating layer 1305, a first gate (gate line) 1306, a third insulating layer 1307, a first source 1308, a fourth insulating layer 1309 and a first drain 1310 which are sequentially stacked on a base substrate 1011, and the first electrode 1012 is electrically connected to the metal oxide semiconductor layer 1304 through a fifth via hole 1311 which sequentially penetrates the fourth insulating layer 1309, the third insulating layer 1307 and the gate insulating layer 1305 to serve as the first drain 1310, and the first source 1308 is electrically connected to the metal oxide semiconductor layer 1304 through a seventh via hole 1312 which sequentially penetrates the third insulating layer 1307 and the gate insulating layer 1305. The switch transistor 130 is configured to provide a turn-on voltage for the photoelectric medium drive of the display panel (for example, the deflection of liquid crystal molecules), and the metal oxide semiconductor layer 1304 in the switch transistor 130 is transparent and can bring a high-transmittance display effect, so that the display effect of virtual reality technology is further improved.

[0138] For example, Figure 7 As shown, the driving transistor 120 includes a second polysilicon layer 1201, a first insulating layer 1301, a second gate (gate line) 1202, a second insulating layer 1303, a gate insulating layer 1305 and a source-drain electrode layer 1203 which are sequentially stacked on a substrate 1011. The source-drain electrode layer 1203 includes a second source 1203a and a second drain 1203b, and the second source 1203a and the second drain 1203b are respectively electrically connected to the second polysilicon layer 1204. The driving transistor 120 is configured to provide a driving voltage when the array substrate is used for display. The driving transistor 120 uses the second polysilicon layer 1204 as a semiconductor layer to improve mobility and bring about a technical effect of a narrow frame. The second gate 1202 is arranged in the same layer as the light shielding layer 1302, that is, the second gate 1202 and the light shielding layer 1302 can be made of the same material, formed in the same process step, and formed in the same layer. For example, the material of the second gate 1202 and the light shielding layer 1302 can be copper metal, molybdenum metal, or other materials with light shielding and conductive properties, which is not limited in the embodiments of the present disclosure. The source-drain electrode layer 1203 is arranged in the same layer as the first gate 1306. For example, the source-drain electrode layer 1203 and the first gate 1306 can be made of the same material, formed in the same process step, and formed in the same layer. The second source 1203a and the second drain 1203b included in the source-drain electrode layer 1203 are electrically connected to the second polysilicon layer 1204 through connection holes, respectively, and the connection holes pass through the gate insulating layer 1305, the second insulating layer 1303, and the first insulating layer 1301 at the same time.

[0139] For example, Figure 7 As shown, the display panel 100 combines the technical effects of high mobility and narrow frame of the driving transistor 120 with polysilicon material as the semiconductor layer, and the display effect of high transmittance of the switching transistor 130 with metal oxide semiconductor material as the semiconductor layer, which can further enhance the display effect of virtual reality of the display panel.

[0140] For example, in Figure 7 In the embodiment, the third electrode 1110 includes metal oxide strip portions 1110a spaced apart from each other in a direction parallel to the main surface of the substrate 1011, and metal portions 1110b between the metal oxide strip portions 1110a. The materials of the metal oxide strip portions 1110a and the metal portions 1110b can be referred to in the above description of Figure 4 Related description.

[0141] For example, Figure 7 As shown, the region where the metal oxide semiconductor layer 1304 and the first gate 1306 are stacked is the channel region, i.e., the M region marked by the elliptical dotted line, and the rest of the region is the conductive region, i.e., the N region marked by the elliptical dotted line. Along the x-axis, the ratio of the length of the channel region (M region) to the length of the conductive region (N region) is 1 / 5 to 1 / 4. For example, the length of the channel region (M region) is 1 / 5 or 1 / 4 of the length of the conductive region (N region), etc. The embodiments of the present disclosure are not limited to this. In one example, the material of the channel region (M region) is indium gallium zinc oxide, which has semiconductor properties. The material of the conductive region (N region) is reduced indium gallium zinc oxide, which has conductor properties.

[0142] For example, Figure 7 As shown, the orthographic projection of the first gate 1306 on the substrate 1011 and the orthographic projection of the light shielding layer 1302 on the substrate 1011 at least partially overlap. In one example, the orthographic projection of the first gate 1306 on the substrate 1011 is located within the orthographic projection of the light shielding layer 1302 on the substrate 1011. In the direction perpendicular to the main surface of the substrate 1011, the distance from the first gate 1306 to the light shielding layer 1302 is 0 micrometers to 5 micrometers. For example, the orthographic projection of the channel region (M region) on the substrate 1011 overlaps with the orthographic projection of the middle region of the light shielding layer 1302 on the substrate 1011, and the orthographic projection of the channel region (M region) on the substrate 1011 is located within the orthographic projection of the light shielding layer 1302 on the substrate 1011.

[0143] For example, in one example, the channel region (M region) is a double-layer structure or a triple-layer structure, and the density of the layer structure of the channel region (M region) away from the base substrate 1011 is greater than the density of the layer structure of the channel region (M region) close to the base substrate 1011.

[0144] For example, the materials of the conductive region (N region) and the channel region (M region) are different. The material of the channel region (M region) includes oxygen, indium, gallium and zinc, and the material of the conductive region N includes oxygen, indium, gallium, zinc, boron or phosphorus.

[0145] For instance, in one example, the material of the metal oxide semiconductor layer 1304 is indium gallium zinc oxide (IGZO), and the portion of the metal oxide semiconductor layer 1304 connected to the first source 1308 and the first drain 1310 is conductorized, so that the portion of the metal oxide semiconductor layer 1304 other than the channel region (M region) can be better connected to the first source 1308 and the first drain 1310.

[0146] For example, Figure 8 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure is shown. Figure 8 and Figure 7 The difference is that in Figure 8 In the embodiment, the metal portion 1110b included in the third electrode 1110 extends into the first via hole 1015, so that the third electrode 1110 and the second electrode 1014 have more overlapping areas. Figure 8 In the embodiment, the second source 1203a includes a source base part and a source transition part, and the second drain 1203b includes a drain base part and a drain transition part. Both the source base part and the source base part penetrate the gate insulating layer 1305, the second insulating layer 1303 and the first insulating layer 1301, and are arranged in the same layer as the first gate 1306. Both the source transition part and the drain transition part penetrate the third insulating layer 1307 and are arranged in the same layer as the first source 1308. The second source 1063a and the second drain 1063b are formed in two steps, which does not increase the process steps and reduces the difficulty of forming the connection hole, thereby ensuring the stability of the electrical connection between the second source 1063a and the second drain 1063b and the polysilicon layer 1061.

[0147] Figure 8 For other structures of the display panel 100, please refer to the above Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 7 The relevant description will not be repeated here.

[0148] For example, Fig. 9 A perspective view of another second electrode and a third electrode provided for at least one embodiment of the present disclosure, Fig.10 for Fig. 9 The cross-sectional structure diagram of the structure shown in FIG. Fig. 9 and Fig.10 The third electrode 1110 includes a metal oxide strip portion 1110a and a metal portion 1110b disposed on a side of the metal oxide strip portion 1110a away from the base substrate 1011, that is, the metal oxide portion 1110a and the metal strip portion 1110b form a stacked structure, and the orthographic projection of the metal portion 1110b on the base substrate 1011 is located within the orthographic projection of the metal oxide strip portion 1110a on the base substrate 1011. The second electrode 1014 is connected between adjacent metal oxide strip portions 1110a, and the orthographic projection of the second electrode 1014 on the base substrate 1011 has an overlapping portion with the orthographic projection of the metal oxide strip portion 1110a on the base substrate 1011.

[0149] It should be noted that the third electrode 1110 can be formed of a metal oxide or a metal or an alloy alone. The third electrode can be used as a common electrode, and the second electrode 1014 can be used as a pixel electrode. The common electrode and the pixel electrode form an electric field to drive the liquid crystal molecules. In addition, the third electrode 1110 can be located in the same layer as the second electrode 1014, or in a different layer from the second electrode 1014. For example, the metal portion of the third electrode 1110 is separated from the second electrode 1014 by a first insulating film, the metal oxide strip portion of the third electrode 1110 is separated from the second electrode 1014 by a second insulating film, and the metal portion of the third electrode 1110 and the metal oxide strip portion are electrically connected through a via that penetrates the first insulating film and the second insulating film. Of course, the structure of the third electrode 1110 is not limited, for example: the display area of ​​the third electrode 1110 is a mesh structure, or a slit-shaped or plate-shaped structure, etc.

[0150] For example, Fig.11 A schematic cross-sectional structure diagram of another display panel provided in at least one embodiment of the present disclosure is shown in FIG. Fig.11As shown, the display panel 100 includes a first substrate 101 on which a channel layer is low temperature polysilicon (LTPS), the first substrate 101 also includes a driving transistor 120 and a switching transistor 130 arranged on a base substrate 1011, the switching transistor 130 is arranged in a display area AA, the driving transistor 120 is arranged in a peripheral area NA surrounding the display area AA, and the switching transistor 130 includes a light shielding layer 1302, a buffer layer 1313, a first polysilicon layer 1314, a gate insulating layer 1305, a first gate electrode 1306, The third insulating layer 1307, the base electrode layer 1315, the fourth insulating layer 1309, the first drain 1310, the fifth insulating layer 1316 and the first source 1308, the base electrode layer 1315 includes a first base electrode 1315a and a second base electrode 1315b arranged opposite to each other, and the first electrode 1012 is electrically connected to the first base electrode 1315a through a fifth via hole 1311 penetrating the fourth insulating layer 1309 to serve as the first drain 1310, and the first base electrode 1315a is electrically connected to the first base electrode 1315a through a sixth via hole 1311 penetrating the third insulating layer 1307 and the gate insulating layer 1305. The first source electrode 1308 is electrically connected to the first polysilicon layer 1314 through a seventh via hole 1312 that sequentially penetrates the fifth insulating layer 1316 and the fourth insulating layer 1309, and the second basic electrode 1315b is electrically connected to the first polysilicon layer 1314 through an eighth via hole 1318 that penetrates the third insulating layer 1307 and the gate insulating layer 1305. The driving transistor 120 includes a buffer layer 1313, a second polysilicon layer 1204, a gate insulating layer 1305, a second gate electrode 1202, and a third via hole 1318 that sequentially penetrates the third insulating layer 1307 and the gate insulating layer 1305. Three insulating layers 1307 and a source-drain electrode layer 1203, the source-drain electrode layer 1203 includes a second source 1203a and a second drain 1203b, and the second source 1203a and the second drain 1203b are both electrically connected to the second polysilicon layer 1204; the first gate 1306 and the second gate 1202 are arranged on the same layer; the source-drain electrode layer 1203 and the base electrode layer 1315 are arranged on the same layer, and the low-temperature polysilicon (LTPS) display panel uses the first polysilicon layer 1314 and the second polysilicon layer 1204 as semiconductor layers to improve mobility and bring about the technical effect of a narrow frame.

[0151] For example, Fig.11 As shown, in a direction parallel to the main surface of the base substrate 1011, the contact portion of the first electrode 1012 and the second electrode 1014 is located between the fifth via 1311 and the seventh via 1312, and the orthographic projection of the contact portion of the first electrode 1012 and the second electrode 1014 on the base substrate 1011 at least partially overlaps with the orthographic projection of the first gate 1306 on the base substrate 1011.

[0152] For example, Fig.11 As shown, in a direction parallel to the main surface of the substrate 1011, the distance between the side of the contact portion of the first electrode 1012 and the second electrode 1014 close to the fifth via 1311 and the sixth via 1317 is equal to the length of the first electrode 1012 not covered by the first gate 1306.

[0153] For example, Fig.11 As shown, in a direction parallel to the main surface of the base substrate 1011, the endpoints of both ends of the light shading layer 1302 are located between the seventh via 1312 and the fifth via 1311, and the contact portion of the first electrode 1012 and the second electrode 1014 is located between the seventh via 1312 and the endpoint of the light shading layer 1302 close to the fifth via 1311.

[0154] For example, in Fig.11 In the embodiment, the first gate 1306 includes two mutually spaced portions in a direction parallel to the main surface of the substrate 1011, that is, a double-gate structure is formed.

[0155] For example, Fig.11 The other structures of the display panel 100 shown may refer to the related structures of a conventional low temperature polycrystalline silicon (LTPS) display panel, and the embodiments of the present disclosure are not limited thereto.

[0156] For example, Figure 7 , Figure 8 and Fig.11 As shown, the pixel unit 1025 also includes a thin film transistor, which includes a switching transistor 130, and the thin film transistor 130 includes a semiconductor layer 1314, a first source 1308 and a first drain 1310 arranged at intervals; the first source 1308 and the first drain 1310 are connected to the semiconductor layer 1314, and the second electrode 1014 is a pixel electrode of the pixel unit 1025; the first electrode 1012 is the first drain 1310 or a switching electrode used to connect the first drain 1310 and the pixel electrode.

[0157] For example, Fig.11 As shown, the material of the first drain electrode 1310 is a transparent conductive oxide. For example, the material of the first drain electrode 1310 includes a transparent metal oxide conductive material, such as indium tin oxide. The second electrode 1014 extends to a side of the first via hole 1015 close to the base substrate 1011. The first drain electrode 1310 is in surface contact with the second electrode 1014, so that the connection between the first drain electrode 1310 and the second electrode 1014 is more stable, and the aperture ratio of the display panel 100 is not affected.

[0158] For example, in one example, the opening width d of the first via hole 1015 close to the upper surface of the first interlayer insulating layer 1013 satisfies: d≤(K1*M / PPI)*(1-AR*1 / (1-D min *PPI / M)), and M is a fixed value of 25400μm; PPI is the pixel density, which is the number of pixel units per inch, 1 inch = 25400μm; the width of a single pixel unit P = M / PPI = 25400μm / PPI, K1 is the aspect ratio of a single pixel, AR is the aperture ratio, PPI is the pixel density, D min It is the process exposure limit value.

[0159] For example, in one example, the opening width d of the first via hole 1015 close to the upper surface of the first interlayer insulating layer 1013 satisfies: d≈(K1*M / PPI)*(1-AR), where PPI is the pixel density, K1 is the aspect ratio of a single pixel, and AR is the aperture ratio. In the following derivation process, W data is the width of the data line, W gate is the width of the gate line, the width of a single pixel P = M / PPI, D min is the process exposure limit value, which is approximately equal to the width of the metal line, for example, equal to the width of the gate line.

[0160] In one example, the above formula d≈(K1*M / PPI)*(1-AR) is derived from the following process: M=25400, AR (aperture ratio)=(PW data )*(K1*Pd) / (P*K1*P), or AR (aperture ratio) = (PW gate )*(K1*Pd) / (P*K1*P);

[0161] With AR and W gate For example,

[0162] AR (aperture ratio) = (PW gate )*(K1*Pd) / (P*K1*P) formula is transformed into the following scheme:

[0163] AR=((1-W gate ) / P)*(1-d / K1*P)=(1-(W gate *PPI) / M)*(1-(d*PPI) / K1*M)

[0164] D min ≤W gate , D min ≤W data ;

[0165] In practical applications, D minIt can be the minimum value among the actual measured values ​​of the gate line or data line.

[0166] Derived: d≤(K1*M / PPI)*(1-AR*1 / (1-D min *PPI / M)),

[0167] 0.4≤AR≤0.8, M=25400, PPI=1100-2500, K1=1.0-3, D min =1.3-2.5μm,

[0168] D min ≤W gate ≤d≤(K1*M / PPI)*(1-P / (1-D min *PPI / M)),

[0169] That is: d≈(K1*M / PPI)*(1-P), the opening width d of the first via hole 1015 on the side away from the base substrate 1011 is proportional to K1, inversely proportional to the pixel density PPI, and inversely proportional to the transmittance.

[0170] The range of the process exposure limit value Dmin is 1.3μm-2.5μm, and the range obtained according to the formula d≈(K1*M / PPI)*(1-AR) is d=2.0μm-10μm.

[0171] For example, in another example, 0.4≤AR≤0.7, M=25400, PPI=1130-1500, K1=1.0~2.5, D min =1.3~1.8, d=3.0μm~6.1μm.

[0172] For example, 0.5≤AR≤0.65, M=25400, PPI=1500~2000, K1=1.0~2.5, D min =1.3~1.5, d=4.5μm~5.2μm.

[0173] Furthermore, the design of the first via 1015 satisfies that the absolute value range of (d1-d2)-tanβ1*d3 is between 0 and 1.5, and one implementation is: d1-d2=tanβ1*d3, wherein d1 is the opening width of the first via 1015 on the side away from the base substrate 1011, and the opening width is the diameter measured at one position or the average value of the opening widths at different positions; d2 is the opening width of the first via 1015 on the side close to the base substrate 1011, and the opening width is the opening width at one position or the average value of the opening widths at different positions; d3 is the thickness of the first interlayer insulating layer 1013 or the average thickness at multiple positions; and β1 is the angle between the side surface of the first via 1015 and the horizontal plane of the base substrate 1011.

[0174] The opening width of the first via hole 1015 at a side away from the base substrate 1011 or at a side close to the base substrate 1011 may be the opening width of the first supporting structure 1016 or the width of the opening on the first interlayer insulating layer 1013 .

[0175] The opening width on the side close to the base substrate 1011 may be the width of the opening on the first interlayer insulating layer 1013 , or the width of the contact position between the first support structure 1016 and the first interlayer insulating layer 1013 or the contact position between the first support structure 1016 and the second interlayer insulating layer 1019 .

[0176] The width may be a width measured at one position or an average width measured at multiple positions.

[0177] For example, in one example, d1 − d2 is approximately 2.0 μm, and d1 − d2 is less than or equal to the thickness of the portion of the first support structure 1016 protruding outside the first via hole 1015 .

[0178] For example, Fig.12 A scanning electron microscope image of a first support structure provided in at least one embodiment of the present disclosure, such as Fig.12 As shown, in a direction perpendicular to the main surface of the substrate 1011, the angle formed between the surface of the first via 1015 close to the first source 1308 and the horizontal plane is α, and the angle formed between the surface of the first via 1015 close to the first drain 1310 and the horizontal plane is β. In one example, α≥β, and in another example, α<β.

[0179] For example, in one example, α>β, and the difference of α-β ranges from 0.5-3°.

[0180] For example, in one example, D min ≤W gate ≤d, d=2.0μm~10μm, D min=1.5μm~2μm.

[0181] For example, in one example, the design of the first via 1015 satisfies d1-d2=tanβ1*d3, d1-d2=2.0μm, wherein d1-d2 is less than or equal to the thickness of the portion of the first supporting structure 1016 protruding outside the first via 1015, d1 is the opening width of the first via 1015 on the side away from the base substrate 1011, d2 is the opening width of the first via 1015 on the side close to the base substrate 1011, d3 is the thickness of the first interlayer insulation 1013, and β1 is the angle between the side wall of the first via 1015 and the horizontal plane.

[0182] For example, in one example, α>β, and the difference between α and β ranges from 0.5 to 3°. In order to make the connection between the first electrode 1012 and the second electrode 1014 more stable, the first electrode 1012 extends to directly above the first gate 1306, that is, the orthographic projection of the first electrode 1012 on the base substrate 1011 and the orthographic projection of the first gate 1306 on the base substrate 1011 at least partially overlap.

[0183] For example, Fig.12 As shown, the width of the right side of the first support structure 1016 extending outside the first gate 1306 is w1, the thickness of the first interlayer insulating layer 1013 is H1, and tanβ=H1 / w1.

[0184] After testing, the following conclusions were obtained: the minimum width w1 of the right side of the first support structure 1016 extending to the outside of the first gate 1306 min The size of w1 is 0.15 microns, the size of H1 is 2.41 microns, and the size of β is 84°. max is the maximum width of the right side of the first support structure 1016 extending outside the first gate 1306. max is 2.0 microns, the size of H1 is 2.41 microns, and the size of β is 50°.

[0185] For example, Fig.13 A perspective structural diagram of a first substrate provided in at least one embodiment of the present disclosure is shown in FIG. Fig.13 As shown, the metal oxide semiconductor layer 1304 is electrically connected to the first electrode 1012 through the fifth via hole 1311, the metal oxide semiconductor layer 1304 is electrically connected to the first source 1308 through the seventh via hole 1312, the extension direction of the light shielding layer 1302 is parallel to the direction perpendicular to the extension direction of the portion of the metal oxide semiconductor layer 1304 electrically connected to the first electrode 1012, and the orthographic projection of the light shielding layer 1302 on the base substrate 1011 overlaps with the orthographic projection of the first gate 1306 on the base substrate 1011. Fig.13The portion indicated by the dotted circle is the first support structure 1016. Fig.11 and Fig.13 As shown, the orthographic projection of the contact portion of the first electrode 1012 and the second electrode 1014 on the substrate 1011 is located within the orthographic projection of the first gate 1306 on the substrate 1011 .

[0186] For example, Fig.11 As shown, in a direction parallel to the main surface of the substrate 1011 , the distance between the side of the contact portion of the first electrode 1012 and the second electrode 1014 close to the fifth via 1311 and the fifth via 1311 is equal to the length of the first electrode 1012 not covering the first gate 1306 .

[0187] For example, Fig.11 As shown, in a direction parallel to the main surface of the base substrate 1011, the first contact portion E of the first electrode 1012 and the second electrode 1014 is located between the fifth via hole 1311 and the seventh via hole 1312, and the orthographic projection of the first contact portion E on the base substrate 1011 at least partially overlaps with the orthographic projection of the first gate 1306 on the base substrate 1011. In a direction parallel to the main surface of the base substrate 1011, the endpoints of both ends of the light shielding layer 1302 are located between the fifth via hole 1311 and the seventh via hole 1312, and the first contact portion E is located between the fifth via hole 1311 and the endpoint of the light shielding layer 1302 close to the fourth via hole 1312.

[0188] For example, Fig.11 As shown, the distance from the orthographic projection of the contact portion on the first gate 1306 to the leftmost end of the first gate 1306 is 1 / 5 to 1 / 3 of the total length of the first gate 1306. The distance from the orthographic projection of the contact portion on the first gate 1306 to the seventh via 1312 is equal to the length of the first electrode 1012 not covering the first gate 1306.

[0189] For example, Fig.11 As shown, the endpoint of the left end of the light-shielding layer 1302 is located to the left of the left end point corresponding to the first gate 1306, and the endpoint of the right end of the light-shielding layer 1302 is located to the right of the right end point corresponding to the first gate 1306, that is, the orthographic projection of the first gate 1306 on the base substrate 1011 is located within the orthographic projection of the light-shielding layer 1302 on the base substrate 1011.

[0190] For example, the orthographic projection of the first contact portion on the base substrate 1011 is located between the orthographic projection of the endpoint of the left end of the light shielding layer 1302 on the base substrate 1011 and the orthographic projection of the fifth via hole 1311 on the base substrate 1011 .

[0191] For example, the distance from the orthographic projection of the endpoint of the left side of the light shielding layer 1302 on the base substrate 1011 to the leftmost end of the first gate 1306 is 1 / 5 to 1 / 3 of the total length of the light shielding layer 1302 .

[0192] For example, Fig.11 As shown, the distance between the fifth via hole 1311 and the seventh via hole 1312 is equal to the distance between the endpoint of the right side end of the light shielding layer 1302 and the endpoint of the right side end of the first gate 1306 .

[0193] For example, in one example, the distance between the fifth via hole 1311 and the seventh via hole 1312 / the width of a pixel = 1.8 / 6.2 = 0.29.

[0194] For example, in another example, the distance between the fifth via hole 1311 and the seventh via hole 1312 / the width of the pixel = 3.3 / 13.7 = 0.24.

[0195] For example, in one example, the overlapping area of ​​the first electrode 1012 and the metal oxide semiconductor layer 1304 satisfies: S≥(S1*R1) / R max , where S1 and R1 are the area of ​​the fifth via hole 1311 and the contact resistance of the fifth via hole 1311, respectively, and R max is the maximum contact resistance that meets the characteristic requirements, R max =2000 ohms, R1 =100-200 ohms, then it is deduced that the ratio of the overlapping area S of the first electrode 1012 and the metal oxide semiconductor layer 1304 to the area of ​​the fifth via hole 1311 satisfies: S / S1≥1 / 20-1 / 10.

[0196] It should be noted that, from the perspective of resistance, it is desirable that the first electrode 1012 and the metal oxide semiconductor layer 1304 overlap over the entire surface, and the contact resistance is small, which is beneficial to the conduction characteristics of the switch transistor 130. Half-hole overlap is caused by process deviation, and the overlap value of the fifth via 1311 and the metal oxide semiconductor layer 1304 in this direction should not be exceeded. The example of half-hole overlap can also be applied if it meets the resistance requirements.

[0197] For example, in one example, the first electrode 1012 overlaps the side of the metal oxide semiconductor layer 1304, and the length of the first electrode 1012 that does not cover the metal oxide semiconductor layer 1304 accounts for 1 / 4-1 / 30 of the length of the metal oxide semiconductor layer 1304. For example, the length of the first electrode 1012 that does not cover the metal oxide semiconductor layer 1304 is 0.1 micrometers to 0.3 micrometers, which accounts for 1 / 20-1 / 9 of the length of the metal oxide semiconductor layer 1304.

[0198] For example, Fig.11As shown, in a direction parallel to the main surface of the base substrate 1011, the contact portion of the first electrode 1012 and the second electrode 1014 is located between the fifth via 1311 and the seventh via 1312, and the orthographic projection of the contact portion on the base substrate 1011 at least partially overlaps with the orthographic projection of the first gate 1306 on the base substrate 1101.

[0199] For example, Fig.11 As shown, in one example, the first interlayer insulating layer 1013 and the first supporting structure 1016 are made of the same material, which is a light-transmitting material. Since a portion of the first supporting structure 1016 needs to occupy the opening area, the first supporting structure 1016 is usually formed of a transparent material, so that the portion of the first supporting structure 1016 occupying the opening area does not affect the aperture ratio.

[0200] For example, Fig.14 A perspective structural diagram of another first substrate provided in at least one embodiment of the present disclosure is shown in FIG. Fig.14 As shown, the material of the first support structure 1016 is a light shielding material, and the extension direction of the first support structure 1016 is parallel to the extension direction of the gate line. The gate line and the gate 1306 have the same extension direction, that is, the extension direction of the first support structure 1016 is parallel to the extension direction of the gate 1306. The first support structure 1016 can block light to reduce cross-color between adjacent pixels, and can also play the role of a horizontal black matrix, so that there is no need to make a horizontal black matrix on the second substrate 102, and only a vertical black matrix is ​​made, because the horizontal and vertical black matrices are originally made separately, thereby reducing the process steps on the second substrate 102.

[0201] In the above embodiments of the present application, Fig.13 As shown, the gate line is a straight line with a constant line width and extends in the horizontal direction. The gate line is located between two adjacent rows of pixel units, and there are two adjacent pixel areas in the same column of pixel units. Assume that the pixel unit in the previous row is the first pixel unit, and the pixel unit in the next row is the second pixel unit. The metal oxide semiconductor layer 1304 is a routing line, which extends from the area where the first pixel unit is located across the gate line to the second pixel unit. The overlapping area of ​​the gate line and the metal oxide semiconductor layer is the gate of the thin film transistor. The routing line extends from the data line area of ​​the first pixel unit to the gate line and extends to the area corresponding to the fifth via hole in the second pixel unit.

[0202] The data line is in direct contact with the metal oxide semiconductor layer through the via hole thereunder, and a portion of the data line is the source electrode of the TFT. A portion of the gate line is the gate electrode of the TFT. This embodiment can maximize the pixel aperture ratio.

[0203] At least one embodiment of the present disclosure further provides a method for preparing a display panel, for example, Fig.15 A process diagram of a method for preparing a display panel provided in at least one embodiment of the present disclosure, such as Fig.15 As shown, the preparation method comprises the following steps:

[0204] Step S11: providing a substrate.

[0205] For example, the base substrate may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited in the embodiments of the present disclosure.

[0206] Step S12: forming a first electrode on the base substrate.

[0207] For example, the first electrode may be a source-drain electrode of a thin film transistor, and the material of the first electrode may be a transparent metal oxide, such as indium tin oxide.

[0208] Step S13: forming a first interlayer insulating layer on the first electrode.

[0209] For example, the material of the first interlayer insulating layer may be a light-transmitting inorganic material.

[0210] Step S14: performing a patterning process on the first interlayer insulating layer to form a first via hole.

[0211] For example, a conventional patterning process may be used: coating photoresist, shielding the photoresist with a mask plate and irradiating the photoresist with ultraviolet light to form a photoresist pattern, and etching the first interlayer insulating layer using the photoresist pattern as a mask to form a first via hole.

[0212] Step S15: forming a second electrode on the first via hole, and the second electrode is electrically connected to the first electrode.

[0213] For example, the second electrode may be a pixel electrode.

[0214] Step S16: forming a first supporting structure in a region corresponding to the first via hole and on a side of the second electrode away from the substrate.

[0215] For example, the first supporting structure completely fills the first via hole and protrudes outside the first via hole to avoid the problem of light leakage caused by the first via hole.

[0216] Step S17: providing a second substrate, forming a second supporting structure on the second substrate, wherein a surface of the first supporting structure close to the second substrate contacts a surface of the second supporting structure close to the first substrate, so as to support the second substrate and form a gap between the first substrate and the second substrate.

[0217] For example, the surface of the first supporting structure close to the second substrate contacts the surface of the second supporting structure close to the first substrate to support the second substrate and form a gap between the first substrate and the second substrate, thereby avoiding scratches on the display area corresponding to the first substrate or the second substrate during the alignment of the first substrate and the second substrate, thereby reducing the risk of light leakage at the edge.

[0218] For example, the structures of the first supporting structure and the second supporting structure can refer to the relevant descriptions above, which will not be repeated here.

[0219] For example, Fig.16 A process diagram of another method for preparing a display panel provided in at least one embodiment of the present disclosure, such as Fig.16 As shown, the preparation method comprises:

[0220] Step S21: providing a substrate.

[0221] Step S22: forming a first electrode on the base substrate.

[0222] Step S23: forming a first interlayer insulating layer on the first electrode.

[0223] Step S24: performing a patterning process on the first interlayer insulating layer to form a first via hole, and forming a second via hole penetrating the first interlayer insulating layer in the first interlayer insulating layer.

[0224] Step S25: forming a second electrode on the first via hole, and the second electrode is electrically connected to the first electrode.

[0225] Step S26: forming a first insulating layer on a side of the second electrode away from the substrate.

[0226] Step S27: forming a third electrode on a side of the first insulating layer away from the base substrate.

[0227] For example, the third electrode includes metal oxide strip portions spaced apart from each other in a direction parallel to the main surface of the substrate, and metal portions between the metal oxide strip portions, or the third electrode includes a metal layer and a metal oxide coating the side surface of the metal layer and a surface away from the substrate, and the third electrode includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the substrate.

[0228] Step S28: forming a first support structure in a region corresponding to the first via hole and on a side of the second electrode away from the substrate, and forming a third support structure in a region corresponding to the second via hole and on a side of the second electrode away from the substrate.

[0229] For example, the orthographic projection of the third supporting structure on the substrate and the orthographic projection of the second supporting structure on the substrate have no overlapping portion.

[0230] Step S29: providing a second substrate, forming a second supporting structure on the second substrate, wherein a surface of the first supporting structure close to the second substrate contacts a surface of the second supporting structure close to the first substrate, so as to support the second substrate and form a gap between the first substrate and the second substrate.

[0231] For example, the surface of the first supporting structure close to the second substrate contacts the surface of the second supporting structure close to the first substrate to support the second substrate and form a gap between the first substrate and the second substrate, thereby avoiding scratches on the display area corresponding to the first substrate or the second substrate during the alignment of the first substrate and the second substrate, thereby reducing the risk of light leakage at the edge.

[0232] For example, the structures of the first supporting structure and the second supporting structure can refer to the relevant descriptions above, which will not be repeated here.

[0233] For example, Fig.17 A process diagram of another method for preparing a display panel provided in at least one embodiment of the present disclosure, such as Fig.17 As shown, the preparation method comprises:

[0234] Step S31: providing a substrate.

[0235] Step S32: forming a first electrode on the base substrate.

[0236] Step S33: forming a first interlayer insulating layer on the first electrode.

[0237] Step S34: performing a patterning process on the first interlayer insulating layer to form a first via hole, and forming a second via hole penetrating the first interlayer insulating layer in the first interlayer insulating layer.

[0238] Step S35: forming a second electrode on the first via hole, and the second electrode is electrically connected to the first electrode.

[0239] Step S36: forming a first support structure in a region corresponding to the first via hole and on a side of the second electrode away from the substrate, and forming a third support structure in a region corresponding to the second via hole and on a side of the second electrode away from the substrate.

[0240] For example, the orthographic projection of the third supporting structure on the substrate and the orthographic projection of the second supporting structure on the substrate do not have an overlapping portion, that is, the number of the second supporting structures is less than the sum of the numbers of the first supporting structures and the third supporting structures.

[0241] For example, the third support structure extends outside the second via hole in a direction perpendicular to the main surface of the substrate, that is, extends outside the second via hole in a direction parallel to the z-axis, and the maximum size of the third support structure in a direction parallel to the main surface of the substrate is equal to the maximum size of the second via hole in a direction parallel to the main surface of the substrate. The third support structure can at least fill the second via hole to reduce the risk of light leakage from the second via hole.

[0242] Step S37: forming a first insulating layer on a side of the first supporting structure and the third supporting structure away from the substrate.

[0243] Step S38: forming a third electrode on a side of the first insulating layer away from the base substrate.

[0244] For example, the third electrode includes metal oxide strip portions spaced apart from each other in a direction parallel to the main surface of the substrate, and metal portions between the metal oxide strip portions, or the third electrode includes a metal layer and a side surface of the coated metal layer and a metal oxide strip portion on a surface away from the substrate, and the third electrode includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the substrate.

[0245] Step S39: providing a second substrate, forming a second supporting structure on the second substrate, wherein a surface of the first supporting structure close to the second substrate contacts a surface of the second supporting structure close to the first substrate, so as to support the second substrate and form a gap between the first substrate and the second substrate.

[0246] Right now Fig.17 and Fig.16 The difference is: Fig.17 In the step of forming the first support structure and the third support structure, forming the first insulating layer, and then forming the third electrode; Fig.16 In the method, a first insulating layer is formed first, a third electrode is formed, and then a first supporting structure and a third supporting structure are formed.

[0247] For example, the structures such as the third electrode can refer to the relevant description above, which will not be repeated here.

[0248] For example, Fig.18 A process diagram of another method for preparing a display panel provided in at least one embodiment of the present disclosure, such as Fig.18 As shown, the preparation method comprises:

[0249] Step S41: providing a substrate.

[0250] Step S42: forming a first electrode on the base substrate.

[0251] Step S43: forming a first interlayer insulating layer on the first electrode.

[0252] Step S44: performing a patterning process on the first interlayer insulating layer to form a first via hole, and forming a second via hole penetrating the first interlayer insulating layer in the first interlayer insulating layer.

[0253] Step S45: forming a second electrode on the first via hole, and the second electrode is electrically connected to the first electrode.

[0254] Step S46: forming a first supporting structure in the area corresponding to the first via hole and on the side of the second electrode away from the substrate, forming a third supporting structure in the area corresponding to the second via hole and on the side of the second electrode away from the substrate, and forming a first insulating layer in the process of forming the first supporting structure and the third supporting structure.

[0255] For example, the orthographic projection of the third supporting structure on the substrate and the orthographic projection of the second supporting structure on the substrate have no overlapping portion.

[0256] For example, the first supporting structure, the third supporting structure and the first insulating layer are disposed in the same layer and are formed of the same material.

[0257] Step S47: forming a third electrode on a side of the first insulating layer away from the base substrate.

[0258] For example, the third electrode includes metal oxide strip portions spaced apart from each other in a direction parallel to the main surface of the substrate, and metal portions between the metal oxide strip portions, or the third electrode includes a metal layer and a metal oxide coating the side surface of the metal layer and a surface away from the substrate, and the third electrode includes a plurality of portions spaced apart from each other in a direction parallel to the main surface of the substrate.

[0259] For example, the first insulating layer is sandwiched between the second electrode and the third electrode so that the second electrode and the third electrode can correspond to each other at the surface of the first via or the second via close to the substrate substrate, so that the orthographic projection of the second electrode on the substrate substrate and the orthographic projection of the third electrode on the substrate substrate overlap.

[0260] Step S48: providing a second substrate, forming a second supporting structure on the second substrate, wherein a surface of the first supporting structure close to the second substrate contacts a surface of the second supporting structure close to the first substrate, so as to support the second substrate and form a gap between the first substrate and the second substrate.

[0261] The display panel provided by at least one embodiment of the present disclosure has at least one of the following beneficial technical effects:

[0262] (1) The display panel provided by at least one embodiment of the present disclosure improves the resolution and aperture ratio of the display panel by making at least a portion of the first supporting structure located in the first via hole and making the orthographic projection of the first via hole on the base substrate and the orthographic projection of the gate line on the base substrate at least partially overlap.

[0263] (2) The display panel provided by at least one embodiment of the present disclosure comprises a first supporting structure disposed in an area corresponding to the first via hole included in the flat layer on the first substrate, and a second supporting structure disposed on the second substrate, wherein a surface of the first supporting structure close to the second substrate contacts a surface of the second supporting structure close to the first substrate, so as to support the second substrate and form a gap between the first substrate and the second substrate, thereby reducing scratches on the display area corresponding to the first substrate or the second substrate during the alignment of the first substrate and the second substrate, thereby reducing the risk of light leakage at the edge.

[0264] (3) In the display panel provided by at least one embodiment of the present disclosure, since the first supporting structure is disposed in the area corresponding to the first via hole included in the planar layer, the problem of light leakage caused by the first via hole is avoided.

[0265] (4) The display panel provided by at least one embodiment of the present disclosure combines the technical effects of high mobility and narrow frame of the driving transistor of the semiconductor layer made of polysilicon material, and the display effect of high transmittance of the switching transistor of the semiconductor layer made of metal oxide semiconductor material, thereby further improving the display effect of virtual reality of the display panel.

[0266] (5) In the display panel provided by at least one embodiment of the present disclosure, the first polysilicon layer and the second polysilicon layer are used as semiconductor layers to improve mobility and bring about the technical effect of a narrow frame.

[0267] There are a few points to note:

[0268] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0269] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0270] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0271] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display panel, comprising: A first substrate and a second substrate aligned with each other, wherein the first substrate comprises a base substrate, and a gate line, a first electrode, a first interlayer insulating layer and a second electrode sequentially arranged on the base substrate; The first interlayer insulating layer has a first via hole penetrating the first interlayer insulating layer, the second electrode is electrically connected to the first electrode through the first via hole, and a first supporting structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; At least a portion of the first supporting structure is located in the first via hole; and an orthographic projection of the first via hole on the base substrate and an orthographic projection of the gate line on the base substrate at least partially overlap; The first substrate is an array substrate, and the array substrate includes the gate lines and data lines arranged horizontally and vertically crosswise on the base substrate, and a plurality of pixel units; The pixel unit includes: the first electrode, the second electrode and the first interlayer insulating layer; The second electrode contacts the surface of the first interlayer insulating layer away from the base substrate, and the second electrode extends from the upper surface of the first interlayer insulating layer to the sidewall and the lower opening area of ​​the first via hole and is connected to the first electrode located in the lower opening area; The opening width d of the first via hole close to the upper surface of the first interlayer insulating layer satisfies: d≤(K1*M / PPI)*(1-AR*1 / (1-D min *PPI / M)), and M is a fixed value of 25400μm; PPI is pixel density, and the pixel density is the number of pixel units per inch, 1 inch = 25400μm; the width of a single pixel unit P = M / PPI = 25400μm / PPI, K1 is the aspect ratio of a single pixel, AR is the aperture ratio, PPI is the pixel density, D min It is the process exposure limit value.

2. The display panel according to claim 1, wherein: The first interlayer insulating layer at least includes a planarization layer, and the first via hole penetrates the planarization layer.

3. The display panel according to claim 1 or 2, wherein: The surface of the first supporting structure close to the second substrate is a plane or a concave surface recessed toward one side of the base substrate.

4. The display panel according to claim 3, wherein: The first supporting structure extends downward in the first via hole to a lower opening area of ​​the first via hole.

5. The display panel according to claim 1, wherein: The first supporting structure extends upward in the first via hole to an upper opening region of the first via hole, and a top of the first supporting structure is higher than an upper surface of the first interlayer insulating layer.

6. The display panel according to claim 5, wherein: The pixel unit further includes a third electrode located above the upper surface of the first interlayer insulating layer, and a second interlayer insulating layer is disposed between the third electrode and the second electrode on the upper surface of the first interlayer insulating layer; The second interlayer insulating layer includes an opening penetrating the first interlayer insulating layer, and the first supporting structure extends toward the second substrate and has a protruding structure higher than the second interlayer insulating layer.

7. The display panel according to claim 6, wherein: The third electrode includes metal oxide strip portions which are spaced apart from each other and are located on the upper surface of the second interlayer insulating layer, and metal portions which are distributed between the metal oxide strip portions.

8. The display panel according to claim 6, wherein: The third electrode includes a metal portion and a metal oxide strip portion covering a side surface and an upper surface of the metal portion, and in a direction parallel to the main surface of the base substrate, the third electrode includes a plurality of portions spaced apart from each other.

9. The display panel according to claim 6, wherein: The portion of the first supporting structure that exceeds the upper surface of the first interlayer insulating layer and the upper surface of the second interlayer insulating layer has a rectangular or trapezoidal cross-sectional shape in a direction perpendicular to the main surface of the base substrate and perpendicular to the extension direction of the gate line, or a trapezoidal shape with an upper surface recessed toward one side of the base substrate.

10. The display panel according to claim 9, wherein: The first supporting structure extends beyond an upper surface of the second interlayer insulating layer toward the second substrate, and extends along an upper surface of the second interlayer insulating layer away from the first via hole.

11. The display panel according to any one of claims 6 to 10, wherein: The pixel unit further includes a thin film transistor, which includes a semiconductor layer, a source electrode and a drain electrode arranged at intervals, and the source electrode and the drain electrode are connected to the semiconductor layer; The second electrode is a pixel electrode of the pixel unit; The first electrode is the drain electrode or a switching electrode used to connect the drain electrode and the pixel electrode.

12. The display panel according to claim 11, wherein: The first interlayer insulating layer at least includes an organic planar layer, the second interlayer insulating layer at least includes an inorganic insulating layer, and the third electrode is a common electrode of the pixel unit.

13. The display panel according to claim 11, wherein: The material of the drain electrode includes a transparent metal oxide conductive material.

14. The display panel according to claim 1, wherein: An opening width d of the first via hole close to the upper surface of the first interlayer insulating layer satisfies: d≈(K1*M / PPI)*(1-AR).

15. The display panel according to claim 1, wherein: It also includes a thin film transistor, which includes a source and a drain arranged at intervals. In the direction perpendicular to the main surface of the base substrate, the angle formed by the edge of the first via hole close to the source and the plane where the main surface of the base substrate is located is α, and the angle formed by the edge of the first via hole close to the drain and the plane where the main surface of the base substrate is located is β, and α≥β.

16. The display panel according to claim 15, wherein: α>β, and the difference between α and β ranges from 0.5 to 3°.

17. The display panel according to claim 1, wherein: D min ≤W gate ≤d,d=2.0μm~10μm,D min =1.5μm~2μm。 18. The display panel according to claim 15, wherein: The design of the first via hole satisfies that the absolute value range of (d1-d2)-tanβ1*d3 is between 0 and 1.5, d1 is the opening width of the first via hole on the side away from the substrate, d2 is the opening width of the first via hole on the side close to the substrate, d3 is the thickness of the first interlayer insulation, and β1 is the angle between the side wall of the first via hole and the horizontal plane of the substrate.

19. The display panel according to claim 1 or 2, wherein: The first substrate further includes a switching transistor disposed on the base substrate; The switch transistor is arranged in the display area; The switching transistor includes a first insulating layer, a light-shielding layer, a second insulating layer, a metal oxide semiconductor layer, a gate insulating layer, a first gate electrode, a third insulating layer, a first source electrode, a fourth insulating layer and a first drain electrode which are sequentially stacked on the base substrate, and the first electrode is electrically connected to the metal oxide semiconductor layer through a third via hole which sequentially penetrates the fourth insulating layer, the third insulating layer and the gate insulating layer to serve as the first drain electrode, and the first source electrode is electrically connected to the metal oxide semiconductor layer through a fourth via hole which sequentially penetrates the third insulating layer and the gate insulating layer.

20. The display panel according to claim 1 or 2, wherein: The first substrate further includes a switching transistor disposed on the base substrate; The switch transistor is arranged in the display area; The switch transistor includes a light shielding layer, a buffer layer, a first polysilicon layer, a gate insulating layer, a first gate, a third insulating layer, a base electrode layer, a fourth insulating layer, a first drain, a fifth insulating layer and a first source electrode stacked in sequence on the base substrate, the base electrode layer includes a first base electrode and a second base electrode arranged opposite to each other, and the first electrode is electrically connected to the first base electrode through a fifth via hole penetrating the fourth insulating layer to serve as the first drain, and the first base electrode is electrically connected to the first polysilicon layer through a sixth via hole penetrating the third insulating layer and the gate insulating layer; The first source electrode is electrically connected to the second base electrode through a seventh via hole that sequentially penetrates the fifth insulating layer and the fourth insulating layer, and the second base electrode is electrically connected to the first polysilicon layer through an eighth via hole that penetrates the third insulating layer and the gate insulating layer.

21. The display panel according to claim 20, wherein: In a direction parallel to the main surface of the base substrate, the contact portion of the first electrode and the second electrode is located between the fifth via hole and the seventh via hole, and the orthographic projection of the contact portion of the first electrode and the second electrode on the base substrate at least partially overlaps with the orthographic projection of the first gate on the base substrate.

22. The display panel according to claim 21, wherein: In a direction parallel to the main surface of the base substrate, a distance between a side of a contact portion of the first electrode and the second electrode close to the fifth via hole and the sixth via hole is equal to a length of the first electrode not covering the first gate.

23. The display panel according to claim 21, wherein: In a direction parallel to the main surface of the base substrate, the endpoints of both ends of the light-shielding layer are located between the seventh via hole and the fifth via hole, and the contact portion of the first electrode and the second electrode is located between the seventh via hole and the endpoint of the light-shielding layer close to the fifth via hole.

24. The display panel according to claim 1 or 2, wherein: A second supporting structure is disposed on the second substrate, and a surface of the first supporting structure close to the second substrate and a surface of the second supporting structure close to the first substrate are in contact with or maintain a set distance.

25. The display panel according to claim 24, wherein: An orthographic projection of the second support structure on the base substrate at least partially overlaps with an orthographic projection of the first support structure on the base substrate.

26. The display panel according to claim 24, wherein: An area of ​​a contact surface between the second supporting structure and the first supporting structure is smaller than an area of ​​a cross section of a region of the second supporting structure or the first supporting structure close to the substrate.

27. The display panel according to claim 25 or 26, wherein: The first interlayer insulating layer has a second via hole penetrating the first interlayer insulating layer, the second via hole is provided with a third supporting structure, and the orthographic projection of the third supporting structure on the base substrate and the orthographic projection of the second supporting structure on the base substrate have no overlapping parts.

28. The display panel according to claim 27, wherein: The third supporting structure extends away from the base substrate to outside the second via hole, and the third supporting structure fills the second via hole so that a shape in the second via hole is adapted to a shape of the second via hole.

29. The display panel according to claim 28, wherein: A longitudinal cross-section of a portion of the third supporting structure extending outside the second via hole is in a trapezoidal shape.

30. The display panel according to claim 24, wherein: The yield strength of the second supporting structure is greater than the product of the pressure of the first substrate and the second substrate when they are aligned, the area of ​​a single second supporting structure, and the number of the second supporting structures.

31. The display panel according to claim 2, wherein: The planarization layer and the first supporting structure are both made of light-transmitting materials.

32. The display panel according to claim 1 or 2, wherein: The material of the first supporting structure is a light shielding material, and the extending direction of the first supporting structure is parallel to the extending direction of the gate line.

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