Apparatus and method for gray field imaging

By adopting a gray field imaging mode combining optical systems and structured mask patterns in semiconductor manufacturing, the challenge of detecting structural defects of 3D wafers is solved, and detection capabilities and signal apparentity are improved.

CN114746739BActive Publication Date: 2025-04-04KLA CORP
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Patent Information

Application Number
CN202080083596.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-11-27
Filing Date
2020-12-01
Publication Date
2025-04-04
Estimated Expiration
2040-12-01

AI Technical Summary

Technical Problem

During semiconductor manufacturing, there are challenges in detecting defects in 3D wafer structures and other advanced semiconductor designs, especially the problem of strong reflections caused by bright field patterns and the ineffectiveness of dark field patterns on random patterns.

Method used

An optical system is employed, which includes a light source, an objective lens, a chuck, a relay lens, a tunable illumination aperture, a barrel lens, a movable focus lens and a 2D imaging camera. Reduce specular reflections, enhance defect signals, and use high-resolution wafer field illumination optics with high numerical apertures.

Benefits of technology

It improves the detection ability of defects in 3D wafer structure, reduces specular reflection, enhances defect signals, and can independently adjust the lighting and light-gathering focus, optimizing the image clarity and signal apparentness of defect detection.

✦ Generated by Eureka AI based on patent content.

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Abstract

A beam is directed from a light source to a wafer on a chuck. The beam is reflected from the wafer toward a 2D imaging camera. A movable focus lens in the path of the beam can independently change the illumination conjugate and the collection conjugate. A structured mask in the illumination path can be used and the beam can be directed through an aperture in the structured mask. A grayfield image of the wafer in a zone without direct illumination is generated using the 2D imaging camera and the location of a defect on the wafer can be determined using the grayfield image.
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Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to provisional patent application No. 62 / 943,170 filed and assigned on December 3, 2019, the disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] The present disclosure relates to optical systems for semiconductor wafers. Background Art

[0004] The evolution of the semiconductor manufacturing industry places higher demands on yield management and especially on metrology and inspection systems. Critical dimensions continue to shrink, and the industry needs to reduce the time to achieve high-yield, high-value production. Minimizing the total time from detecting a yield problem to resolving the problem determines the return on investment for semiconductor manufacturers.

[0005] The manufacture of semiconductor devices such as logic and memory devices typically includes processing a semiconductor wafer using a number of manufacturing processes to form the various features and multiple levels of the semiconductor devices. For example, photolithography is a semiconductor manufacturing process that involves transferring a pattern from a mask to a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. An arrangement of multiple semiconductor devices fabricated on a single semiconductor wafer may be separated into individual semiconductor devices.

[0006] Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yields and therefore higher profits in the manufacturing process. Inspection has always been an important part of manufacturing semiconductor devices, such as integrated circuits (ICs). However, as the size of semiconductor devices decreases, inspection becomes more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause device failures. For example, as the size of semiconductor devices decreases, detection of defects with reduced sizes has become necessary because even relatively small defects can cause undesirable yield losses in semiconductor devices.

[0007] However, detecting defects in 3D wafer structures and other advanced semiconductor designs presents challenges. For optical inspection, bright field (BF) mode results in strong reflections from the top surface of the wafer. Defect signals can be drowned out or limited by bright wafer patterns. Dark field (DF) mode typically suppresses all wafer patterns in regular array areas, but not for random patterns, because wafer pattern information is lost due to disturber filtering. Without contrast information, it can be difficult to distinguish defects from disturbers.

[0008] Therefore, improvements in inspection systems are needed. Summary of the invention

[0009] In a first embodiment, a system is provided. The system includes: a light source that generates a light beam; an objective lens; a chuck configured to hold a wafer in the path of the light beam traveling through the objective lens; a relay lens disposed between the light source and the objective lens in the path of the light beam; a tunable illumination aperture disposed between the light source and the relay lens in the path of the light beam; a first tube lens disposed between the relay lens and the objective lens in the path of the light beam; a first movable focus lens disposed between the first tube lens and the relay lens in the path of the light beam; a second movable focus lens disposed between the objective lens and a 2D imaging camera in the path of the light beam; a second tube lens disposed between the second movable focus lens and the objective lens in the path of the light beam; and the 2D imaging camera configured to receive light reflected from a wafer through the objective lens. The first movable focus lens and the second movable focus lens are configured to be movable along the path of the light beam to adjust the illumination conjugate between the light source and the wafer and the light collection conjugate between the wafer and the 2D imaging camera. The first movable focus lens and the second movable focus lens are configured to position the illumination focus at, above or below the surface of the wafer. The 2D imaging camera is configured to generate a gray field image of the wafer.

[0010] A structured mask may be disposed between the light source and the objective lens in the path of the light beam. The structured mask defines a plurality of apertures through which the light beam travels. A portion of the light beam is blocked by the structured mask. For example, the structured mask may be disposed between the light source and the first movable focus lens or between the relay lens and the first movable focus lens.

[0011] The structured mask can be configured to be tilted relative to the path of the light beam.

[0012] The illumination numerical aperture may be from 0 to 0.9. The collection path numerical aperture may be at least 0.9.

[0013] The system may further include a processor in electronic communication with the 2D imaging camera.The processor is configured to identify defects in the gray field image from the 2D imaging camera.

[0014] In a second embodiment, a method is provided. The method includes directing a light beam from a light source to a wafer on a chuck. The wafer may include a 3D structure. The light beam is reflected from the wafer to a 2D imaging camera. A first movable focus lens and a second movable focus lens are adjustable. The first movable focus lens is disposed between the light source and the wafer in the path of the light beam. The second movable focus lens is disposed between the wafer and the 2D imaging camera. The adjustment includes independent changes to the illumination conjugate between the light source and the wafer and the collection conjugate between the wafer and the 2D imaging camera. An image of the wafer is generated using the 2D imaging camera. The image is a gray field image. The location of a defect on the wafer is determined using the image.

[0015] The focus of the beam may be below, at, or above the surface of the wafer. As the beam scans across the surface of the wafer, the focus of the beam may change in depth.

[0016] The method may further include directing the light beam through a structured mask disposed in the path of the light beam between the light source and the first movable relay lens. The structured mask defines a plurality of apertures. The plurality of apertures form bright bands on the surface of the wafer and areas of the structured mask between the apertures form dark bands on the surface of the wafer.

[0017] The illumination numerical aperture may be from 0 to 0.9. The collection path numerical aperture may be at least 0.9.

[0018] The adjustment may include changing a position of the first movable focusing lens so that the structure mask is focused and light in the bright band leaks into the dark band. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a more complete understanding of the nature and objects of the present disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 is a diagram of a system according to the present disclosure;

[0021] Figure 2 is an image of an exemplary structured mask pattern (SMP);

[0022] Figure 3 is used Figure 2 An example of a gray field image of a structured mask pattern;

[0023] Figure 4 Demonstrate the relationship between the focus of illumination and the focus of light collection; and

[0024] Figure 5is an embodiment of a flow chart of a method according to the present disclosure. DETAILED DESCRIPTION

[0025] Although the claimed subject matter will be described in terms of specific embodiments, other embodiments (including embodiments that do not provide all of the benefits and features set forth herein) are also within the scope of the present disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure is defined solely by reference to the appended claims.

[0026] Advanced semiconductor devices tend to include 3D structures (DRAM, 3D NAND, wrap-around gate). Defects below the device surface of 3D structures are often difficult to detect because strong reflections from the top surface can saturate the sensor and because insufficient light reaches the defect location, which can be hundreds of nanometers to several microns below the surface. Dark field imaging mode can alleviate the sensor saturation problem by filtering out specular reflections, but dark field imaging also loses context for disturbing point filtering. Additionally, dark field imaging is ineffective for random patterns.

[0027] Embodiments of the apparatus and methods disclosed herein use a grayfield imaging mode that is between brightfield and darkfield. This imaging mode reduces specular reflections without eliminating them so that more light is allowed onto the device without sensor saturation. Thus, the defect absolute signal is enhanced. The wafer pattern is preserved and context-based or other advanced disturber point filtering algorithms can be used.

[0028] In embodiments disclosed herein, illumination optics with high numerical aperture (NA) may be used. Grayfield imaging with high resolution for wafer field illumination may be used or achieved using structured mask patterns. The illumination focus may be independently adjusted at, above, or below the wafer surface. The collection focus may be optimized for improved defect detection. Grayfield imaging may use structured mask patterns with high resolution for wafer plane illumination, independently adjustable illumination and collection focus, or a combination thereof.

[0029] Figure 1 1 is a diagram of system 100. A structured mask pattern can be imaged at scale onto the surface of a wafer 114. Using high resolution and near diffraction limited illumination optics, the structured mask pattern can be projected onto the wafer plane with well defined sharp edges. In general, system 100 is configured to generate an optical-based output of wafer 114 by directing light to wafer 114 (or scanning light over wafer 114) and detecting light from wafer 114. Although wafer 114 is disclosed, a mask or other workpiece may also be imaged.

[0030] exist Figure 1Central illumination is illustrated in FIG, but annular illumination is possible. The aperture shape can vary. The illumination numerical aperture can vary, for example from 0 to 0.9. The collection path numerical aperture can vary and can be at least 0.9.

[0031] Light source 101 generates light beam 104. Light source 101 is configured to direct light to wafer 114 at one or more incident angles that may include one or more tilt angles and / or one or more normal angles. Conceptually, gray field can be used for any wavelength range. The optical wavelength generally depends on the wafer stack material. For example, if the wafer 3D stack includes a large amount of silicon or polycrystalline silicon, near infrared wavelengths can be used. In another example, if the wafer material is transparent, visible wavelengths or deep ultraviolet (DUV) wavelengths can be used for better optical resolution.

[0032] In an example, light source 101 may include a broadband plasma (BBP) source. In this way, the light generated by light source 101 and directed to wafer 114 may include broadband light. However, light source 101 may include any other suitable light source, such as a laser or a light emitting diode (LED). The laser or LED may include any suitable form known in the art and light source 101 may be configured to generate light of any suitable wavelength(s) known in the art. Additionally, light source 101 may be configured to generate monochromatic or near-monochromatic light. In this way, light source 101 may be a narrow-band laser. Light source 101 may also include a polychromatic light source that generates light of multiple discrete wavelengths or bands.

[0033] Objective lens 113 is positioned proximate to chuck 115 that is configured to hold wafer 114 in the path of light beam 104. Light beam 104 travels through objective lens 113. For ease of illustration, arrows indicate the path of light beam 104.

[0034] The system 100 may also include a scanning subsystem configured to cause the light beam 104 to scan across the wafer 114. The scanning subsystem may include any suitable mechanical and / or robotic assembly (including the chuck 115) that may be configured to move the wafer 114 so that the light may scan across the wafer 114. Additionally or alternatively, the system 110 may be configured so that one or more optical elements of the system 100 perform some scanning of the light across the wafer 114. The light may be scanned across the wafer 114 in any suitable manner, such as in a serpentine path or in a spiral path.

[0035] Optional lens 105, tunable illumination aperture 120, relay lens 106, optional structured mask 107, first reflector 108, first movable focus lens 109, first tube lens 110 (three lenses are illustrated, but other numbers are possible), and second reflector 111 are disposed between light source 101 and objective lens 113 in the path of light beam 104. The illumination path may be from light source 101 to wafer 114. Illumination aperture 120 is disposed between light source 101 and relay lens 106 or between optional lens 105 and relay lens 106 in the path of light beam 104. First tube lens 110 is disposed between relay lens 106 and objective lens 113. Structured mask 107 is disposed between light source 101 and first movable focus lens 109. First movable focus lens 109 is disposed between first tube lens 110 and relay lens 106.

[0036] The first movable focus lens 109 can be translated (e.g., using an actuator) along the path of the light beam 104 (which is illustrated using arrows). The first movable focus lens 109 can be adjusted to focus the structured mask 107 pattern relative to the surface of the wafer 114. The motion relationship between the first movable focus lens 109 and the wafer 114 (e.g., the top surface of the wafer 114) can depend on the implemented optical design, such as the illumination numerical aperture, wavelength, and magnification. For example, for an embodiment, the ratio can be 1000:1. In another embodiment, the ratio can be 500:1. The range of motion of the wafer 114 in the z direction is typically less than 15 μm. The light collection path from the wafer 114 to the camera plane of the 2D imaging camera 102 can form an image of both the wafer 114 and the pattern of the structured mask 107 (when present).

[0037] The third reflector 112, the second tube lens 116, the zoom lens 117, and the second movable focus lens 118 are disposed between the objective lens 113 and the 2D imaging camera 102 in the path of the light beam 104 reflected from the wafer 114. The second movable focus lens 118 can be translated (e.g., using an actuator) along the path of the light beam 104 (which is illustrated using arrows). The second tube lens 116 is disposed between the second movable focus lens 118 and the objective lens 113 in the path of the light beam 104. The kinematic relationship between the second movable focus lens 116 and the wafer 114 (e.g., the top surface of the wafer 114) can depend on the implemented optical design form, magnification, numerical aperture, or other variables.

[0038] The system 110 may include a number of other refractive and / or reflective optical elements that in combination focus light from the optical element onto the wafer 114. Thus, the system 110 may include any other suitable optical element (not shown). Examples of such optical elements include, but are not limited to, polarizing components, spectral filter(s), spatial filter(s), reflective optical element(s), apodizer(s), beam splitter(s), aperture(s), and the like, which may include any such suitable optical element known in the art. Additionally, the system 110 may be configured to alter one or more elements of the illumination subsystem based on the type of illumination used to generate the optical-based output. For example, the illumination aperture (pupil plane) may take the form of an annular, circular, arcuate, half-moon, or slit cross-section for suitable illumination incidence angle targets at any location throughout the illumination pupil.

[0039] The 2D imaging camera 102 is configured to receive light reflected from the wafer 114 through the objective lens 113. The 2D imaging camera 102 is configured to generate a gray field image of the wafer.

[0040] The 2D imaging camera 102 may be any suitable detector known in the art. For example, the 2D imaging camera 102 may be a charge coupled device (CCD), a time delayed integration (TDI) camera, or any other suitable detector known in the art. 2D imaging may also be achieved by scanning the wafer 114 or by scanning a 1D or point detector, which may include a photodiode array, a photomultiplier tube (PMT), or an avalanche photodiode (APD). The 2D imaging camera 102 may also include a non-imaging detector or an imaging detector.

[0041] Optionally, the structured mask 107 is disposed between the light source 101 and the objective lens 113 in the path of the light beam 104. In an example, the structured mask 107 is disposed between the relay lens 106 and the first movable focusing lens 109 or between the relay lens 106 and the first reflector 108 in the path of the light beam 104. A conjugate image of the structured mask pattern is formed on the wafer plane using the first movable focusing lens 109 to adjust the optimal focal plane distance from the top surface of the wafer 114.

[0042] The structured mask 107 defines apertures 119. These Figure 1 119. The structured mask 107 is shown in a top view of the structured mask 107 in the insert of FIG. The light from the beam 104 travels through the apertures 119. The structured mask 107 blocks the beam 104 in the area between the apertures 119. A portion of the beam 104 may be blocked by the structured mask 107. The structured mask pattern may take an action duty cycle or geometry different from that described for different application cases. For example, the structured mask 107 may have a checkerboard pattern.

[0043] The structured mask 107 can be formed by various methods. For example, the structured mask 107 can be made of chrome on glass, where the areas with the chrome pattern block light. The structured mask 107 can also be cut out of metal sheets, graphite or other materials. The structured mask 107 can also be implemented by optical interference or diffraction phenomena to achieve dark / bright lighting patterns.

[0044] The thickness of the features used to define the edge of the structured mask 107 can affect the results. For chrome on glass, the chrome pattern thickness can be less than 0.5 μm. For metal, the pattern thickness can be 250 μm.

[0045] The distance between illuminated areas formed using structured mask 107 may also affect imaging. The width of aperture 119 may be minimized to affect the gray image, but different mask configurations may be used for different applications.

[0046] like Figure 1 , the structured mask 107 pattern is placed at a plane conjugate to the wafer plane. The pattern geometry can be a 2D grating where half the pitch transmits light and the other half blocks light, but other pitch values ​​are possible. Any action duty cycle can be used.

[0047] exist Figure 2 An example of a structured mask pattern is shown in . This pattern is illuminated by a light source and the illumination aperture limits the angle of incidence on the structured mask. The optical system between the structured mask 107 and the wafer plane images the structured mask pattern onto the wafer plane with magnification. When a numerical aperture (e.g., 0.9) with near-diffraction-limited optical performance is used, the structured mask pattern forms a clear image at the wafer plane with one or more well-defined edges. The well-defined edges can form a clear boundary between the directly illuminated area and the grayfield imaging area. For wafer inspection, the grayfield imaging area can define the inspection attention area. The clear boundary can invalidate the direct light that creeps into the intended grayfield imaging area and ensure uniform sensitivity in the attention area. The wafer pattern can be modulated by measuring the structured mask pattern across the field of view. By adjusting the first movable focusing lens 109, the structured mask 107 can be focused at, above, or below the surface of the wafer 114 (e.g., at Figure 1 The wafer image is collected by the light collecting optics onto the 2D imaging camera 102. By adjusting the second movable focus lens 118, the 2D imaging camera 102 can capture the wafer pattern image at, above, or below the surface of the wafer 114. Whether the focus is at, above, or below the surface of the wafer may depend on the type of imaging application or the wafer.

[0048] Using actuators (not shown), the structured mask 107 can be translated into and / or out of the beam 104 and / or relative to the beam 104. Figure 1The light beam 104 shown in FIG. 1 is tilted.

[0049] Reference again Figure 1 The processor 103 is in electronic communication with the 2D imaging camera 102. The processor 103 is configured to identify defects in the gray field image from the 2D imaging camera 102.

[0050] Figure 3 Used when the wafer is a reflective mirror surface Figure 2 Example of a grayfield image of a structured mask. Figure 2 The structured mask pattern of is a 2D binary grating. Light is blocked in the dark bands and transmitted in the bright bands. Figure 3 The structured mask pattern in modulates the brightness of the wafer pattern (which is a thin vertical bright line). The wafer pattern has a 3D structure. Figure 2 The dark bands become gray bands and the black spots (defects) are obvious. It is more difficult to distinguish the black spots in the light bands. Figure 3 There is no observable defect signal in the wafer, which can be drowned out by the strong specular reflection from the wafer surface.

[0051] exist Figure 3 In the embodiment of the present invention, light in the bright bands can leak into the dark bands of the 3D wafer structure by diffraction, secondary reflections from the bottom surface, or other optical interactions inside the stack. The amount of light that leaks may depend on the wafer, the illumination wavelength, the shape and size of the apertures in the structured mask, or other parameters. The dark bands appear gray and appear as if they are backlit. Therefore, the structured mask area between the apertures becomes gray. As light leaks from the bright bands into the dark bands, specular light may not be present and defect signals become apparent. A gray field imaging mechanism can be achieved by directly illuminating an area immediately adjacent to the area of ​​interest for defect detection. The 3D structure of the wafer can cause the area of ​​interest to appear gray. Defects buried inside the stack or close to the surface of the stack may become more apparent than the directly illuminated area.

[0052] The wafer 114 may be scanned relative to the beam 104 so that some or all of the surface of the wafer 114 is imaged. This allows defects to be captured across the surface of the wafer 114.

[0053] The illumination focus and collection focus can be adjusted to provide gray field imaging with or without the use of a structured mask. Figure 4 The relationship between the illumination focus and the collection focus of the image shown on the bottom is shown.

[0054] From right to left on the bottom wafer image, the illumination focus is gradually moved into the wafer z stack (e.g., by tilting Figure 1 The structured mask 107 in FIG. Figure 1In the light collection path of FIG. 1 , both the wafer plane and the camera plane are normal to the optical axis. The boundary of the structured mask pattern becomes increasingly blurred from right to left. It should also be noted that the wafer pattern clarity (vertical lines) and defect visibility at the bright bands increase from right to left as the illumination focus gradually moves below the wafer surface. If it were a conventional brightfield flood illumination wafer inspection illumination scheme, the wafer pattern clarity would be uniform from left to right.

[0055] The range of angles used when tilting the structured mask 107 may depend on the application. In one example, the structured mask may be tilted so that the out-of-focus range is approximately 10 to 20 depths of focus, which may be equivalent to 0.3 to 0.5 degrees at the wafer plane.

[0056] Although Figure 4 The embodiment of the invention tilts the structured mask, but it is also possible to remove the structured mask 107 from the path of the light beam 104 .

[0057] This arrangement allows independent focus adjustment of the illumination conjugate (structured mask to wafer) and the collection conjugate (wafer to 2D imaging camera). When using high numerical aperture and diffraction limited illumination optics, the illumination pattern on the wafer has a narrow depth of focus, and therefore the illumination light intensity z-distribution inside the wafer can be narrower than with conventional non-diffraction limited illumination optics. This will help limit the illumination light intensity z-distribution of the illuminated wafer stack. By offsetting the illumination focus below the wafer surface, the intensity of the surface reflection can be reduced. The image path focus can be adjusted independently to achieve either improved pattern sharpness or improved defect signal. Figure 4 The illumination focus is shown gradually moving from right to left below the wafer surface (by tilting the structured mask pattern).

[0058] The wafer plane and the camera plane may not be normal to the optical axis. Using conventional illumination where the optical performance is not diffraction limited, the entire image plane should have the same wafer pattern clarity. However, in this image, only one x position forms a sharp focus at the camera. In other words, the z position of the illumination focus can modulate the image clarity. By adjusting the illumination focus below the wafer surface and imaging the path focus at the wafer surface, specular reflections from the surface pattern can be reduced and defects near the surface can become more visible.

[0059] In an example, by adjusting the numerical aperture, size, shape and / or polarization of the illumination optics, the backlight z-depth of the gray zone can be optimized. The field distribution inside the wafer stack can be changed. Thus, defects at different depths can be selectively enhanced.

[0060] The wavelength, illumination angle, or other parameters of the light may vary depending on the material of wafer 114. For example, the wavelength may change for polysilicon structures compared to crystalline silicon or silicon oxide. In some examples, the illumination angle may affect certain materials more than the wavelength.

[0061] Reference again Figure 1 , system 100 is provided herein to generally illustrate configurations that may be included in or that may produce optical-based outputs used by system embodiments described herein. The system 100 configuration described herein may be altered to optimize the performance of the system 100 as is typically performed when designing a commercial output capture system. Additionally, the systems described herein may be implemented using existing systems (e.g., by adding the functionality described herein to the existing systems). For some such systems, the methods described herein may be provided as optional functionality of the system (e.g., in addition to other functionality of the system). Alternatively, the systems described herein may be designed as entirely new systems.

[0062] Processor 103 may be coupled to components of system 100 in any suitable manner (e.g., via one or more transmission media, which may include wired and / or wireless transmission media) such that processor 103 may receive output. Processor 103 may be configured to perform a number of functions using the output. System 100 may receive instructions or other information from processor 103. Processor 103 and / or electronic data storage unit may optionally electronically communicate with a wafer inspection tool, wafer metrology tool, or wafer review tool (not illustrated) to receive additional information or send instructions. For example, processor 103 and / or electronic data storage unit may electronically communicate with a scanning electron microscope (SEM).

[0063] The processor 103, other system(s), or other subsystem(s) described herein may be part of a variety of systems, including a personal computer system, an image computer, a mainframe computer system, a workstation, a network appliance, an Internet appliance, or other devices. The subsystem(s) or system(s) may also include any suitable processor known in the art (e.g., a parallel processor). In addition, the subsystem or the system may include a platform with high-speed processing and software (as a stand-alone tool or a network tool).

[0064] In fact, the processor 103 may be implemented by any combination of hardware, software, and firmware. Also, its functions as described herein may be performed by one unit or divided among different components, each of which may in turn be implemented by any combination of hardware, software, and firmware. Program code or instructions for the processor 103 to implement various methods and functions may be stored in a readable storage medium, such as a memory in an electronic data storage unit or other memory.

[0065] If the system 100 includes more than one processor 103, the different subsystems may be coupled to each other so that images, data, information, instructions, etc. may be sent between the subsystems. For example, one subsystem may be coupled to the additional subsystem(s) via any suitable transmission media, which may include any suitable wired and / or wireless transmission media known in the art. Two or more such subsystems may also be effectively coupled via a shared computer-readable storage medium (not shown).

[0066] Processor 103 may be configured to perform a number of functions using the output of system 100 or other outputs. For example, processor 103 may be configured to send the output to an electronic data storage unit or another storage medium. Processor 103 may be further configured as described herein.

[0067] The processor 103 may be configured according to any of the embodiments described herein. The processor 103 may also be configured to perform other functions or additional steps using the output of the system 100 or using images or data from other sources.

[0068] The various steps, functions and / or operations of the system 100 and the methods disclosed herein are implemented by one or more of the following: electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controls / switches, microcontrollers, or computing systems. Program instructions implementing methods such as the methods described herein may be transmitted via or stored on a carrier medium. The carrier medium may include storage media such as read-only memory, random access memory, magnetic or optical disks, non-volatile memory, solid-state memory, magnetic tape, and the like. The carrier medium may include transmission media such as wires, cables, or wireless transmission links. For example, the various steps described throughout the present disclosure may be implemented by a single processor 103 or alternatively multiple processors 103. In addition, different subsystems of the system 100 may include one or more computing or logic systems. Therefore, the above description should not be interpreted as limiting the present disclosure but is merely illustrative.

[0069] Figure 5 2 is an embodiment of a flow chart of method 200. At 201, a light beam is directed from a light source to a wafer on a chuck. At 202, the light beam is reflected from the wafer toward a 2D imaging camera. The focus of the light beam may be below the surface of the wafer, but may also be above or at the surface of the wafer. As the light beam scans across the surface of the wafer, the focus may change in depth.

[0070] At 203, a first movable focus lens and a second movable focus lens may be adjusted. The first movable focus lens is disposed between the light source and the wafer in the path of the light beam. The second movable focus lens is disposed between the wafer and the 2D imaging camera. The adjustment includes independent changes to the illumination conjugate and the collection conjugate.

[0071] Adjusting may include changing the position of the first movable focus lens so that the structure mask is focused and light in the bright bands leaks into the dark bands.

[0072] At 204, an image of the wafer is generated using a 2D imaging camera. The image is a gray field image. At 205, the image is used to determine the location of the defect on the wafer. This determination may be performed using a processor, such as Figure 1 The processor 103 may be used to determine the location of a defect in the image using, for example, differences in individual pixels. The processor may compare a pixel to adjacent pixels to determine if a defect exists.

[0073] The light beam can be directed through a structured mask disposed in the path of the light beam between the light source and the first movable relay lens. The structured mask defines a plurality of apertures. The apertures form bright bands on the surface of the wafer, and the areas of the structured mask between the apertures form dark bands on the surface of the wafer, which become dark bands in the light collection path after interacting with the 3D structure on the wafer.

[0074] Reference again Figure 1 , the processor 103 is in communication with the system 100. The processor 103 may be configured to execute or send instructions for some or all of the steps of the method 200.

[0075] Additional embodiments relate to a non-transitory computer-readable medium storing program instructions executable on a controller to perform a computer-implemented method, as disclosed herein. An electronic data storage unit or other storage medium may contain a non-transitory computer-readable medium including program instructions executable on processor 103. The computer-implemented method may include any step(s) of any method(s) described herein, including method 200.

[0076] The program instructions may be implemented in any of a variety of ways, including procedural-based techniques, component-based techniques, and / or object-oriented techniques, etc. For example, the program instructions may optionally be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extensions (SSE), or other techniques or methodologies.

[0077] Although the present disclosure has been described with respect to one or more specific embodiments, it should be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure. Therefore, the present disclosure is deemed to be limited only by the appended claims and reasonable interpretations thereof.

Claims

1. An optical system for a semiconductor wafer, comprising: a light source that generates a light beam; Objective lens; a chuck configured to hold a wafer in a path of the light beam traveling through the objective lens; a relay lens disposed between the light source and the objective lens in the path of the light beam; a tunable illumination aperture disposed in the path of the light beam between the light source and the relay lens; a first tube lens disposed in the path of the light beam between the relay lens and the objective lens; a first movable focusing lens disposed in the path of the light beam between the first tube lens and the relay lens; a 2D imaging camera configured to receive light reflected from the wafer through the objective lens; a second movable focusing lens disposed in the path of the light beam between the objective lens and the 2D imaging camera; and a second tube lens disposed in the path of the light beam between the second movable focus lens and the objective lens; wherein the first movable focus lens and the second movable focus lens are configured to be movable along the path of the light beam to adjust the illumination conjugate between the light source and the wafer and the collection conjugate between the wafer and the 2D imaging camera, and wherein the first movable focus lens and the second movable focus lens are configured to position the illumination focus at, above, or below the surface of the wafer; and The 2D imaging camera is configured to generate a gray field image of the wafer.

2. The optical system of claim 1 , further comprising a structured mask disposed in the path of the light beam between the light source and the objective lens, wherein the structured mask defines a plurality of apertures through which the light beam travels, and wherein a portion of the light beam is blocked by the structured mask.

3. The optical system of claim 2, wherein the structured mask is disposed between the light source and the first movable focus lens.

4. The optical system of claim 3, wherein the structured mask is disposed between the relay lens and the first movable focus lens.

5. The optical system of claim 2, wherein the structured mask is configured to be tilted relative to the path of the light beam.

6. The optical system of claim 1, wherein the illumination numerical aperture of the system is from 0 to 0.

9.

7. The optical system of claim 1, wherein the system has a collection path numerical aperture of at least 0.

9.

8. The optical system of claim 1, further comprising a processor in electronic communication with the 2D imaging camera, wherein the processor is configured to identify defects in the gray field image from the 2D imaging camera.

9. A method for a semiconductor wafer, comprising: directing a light beam from a light source to a wafer on a chuck; reflecting the light beam from the wafer toward a 2D imaging camera; adjusting a first movable focus lens disposed between the light source and the wafer and a second movable focus lens disposed between the wafer and the 2D imaging camera in a path of the light beam, wherein the adjustment comprises independent changes to an illumination conjugate between the light source and the wafer and a collection conjugate between the wafer and the 2D imaging camera; generating an image of the wafer using the 2D imaging camera, wherein the image is a gray field image; and The image is used to determine the location of defects on the wafer.

10. The method of claim 9, wherein a focal point of the light beam is below a surface of the wafer. The method of claim 9 , wherein a focal point of the light beam is at a surface of the wafer.

12. The method of claim 9, wherein a focal point of the light beam is above a surface of the wafer.

13. The method of claim 9, wherein a focus of the beam varies in depth as the beam scans across the surface of the wafer.

14. The method of claim 9, further comprising directing the light beam through a structured mask disposed in the path of the light beam between the light source and the first movable relay lens, wherein the structured mask defines a plurality of apertures, and wherein the plurality of apertures form bright bands on the surface of the wafer and areas of the structured mask between the apertures form dark bands on the surface of the wafer.

15. The method of claim 14, wherein the adjusting comprises changing a position of the first movable focus lens so that the structured mask is focused and light in the bright bands leaks into the dark bands.

16. The method of claim 9, wherein the illumination numerical aperture is from 0 to 0.

9.

17. The method of claim 9, wherein the collection path numerical aperture is at least 0.

9.

18. The method of claim 9, wherein the wafer comprises a 3D structure.

19. An optical system for a semiconductor wafer, comprising: a light source that generates a light beam; Objective lens; a chuck configured to hold a wafer in a path of the light beam traveling through the objective lens; a tunable illumination aperture disposed between the light source and the objective lens in the path of the light beam; a first movable focusing lens disposed between the light source and the objective lens in the path of the light beam; a 2D imaging camera configured to capture an image of the wafer in an illumination area through the objective lens; a second movable focusing lens disposed in the path of the light beam between the objective lens and the 2D imaging camera; and wherein the first movable focus lens and the second movable focus lens are configured to adjust the illumination conjugate between the light source and the wafer and the light collection conjugate between the wafer and the 2D imaging camera, and wherein the first movable focus lens and the second movable focus lens are configured to position the illumination focus at, above, or below the surface of the wafer; and The 2D imaging camera is configured to generate a gray field image of the wafer.

20. The optical system of claim 19, further comprising a structured mask disposed in the path of the light beam between the light source and the objective lens, wherein the structured mask defines a plurality of apertures through which the light beam travels, and wherein a portion of the light beam is blocked by the structured mask.

21. The optical system of claim 20, wherein the structured mask is disposed between the light source and the first movable focus lens.

22. The optical system of claim 20, wherein the structured mask is configured to be tilted relative to the path of the light beam.

23. The optical system of claim 19, wherein the illumination numerical aperture of the system is from 0 to 0.

9.

24. The optical system of claim 19, wherein the system has a collection path numerical aperture of at least 0.

9.

25. The optical system of claim 19, further comprising a processor in electronic communication with the 2D imaging camera, wherein the processor is configured to identify defects in the gray field image from the 2D imaging camera.

26. A method for a semiconductor wafer, comprising: directing a light beam from a light source to a wafer on a chuck; reflecting the light beam from the wafer toward a 2D imaging camera; adjusting illumination conjugation between the light source and the wafer; adjusting the light collection conjugation between the chip and the 2D imaging camera; generating an image of the wafer using the 2D imaging camera, wherein the image is a gray field image; and The image is used to determine the location of defects on the wafer.

27. The method of claim 26, wherein the focus of the light beam is below the surface of the wafer.

28. The method of claim 26, wherein a focal point of the light beam is at a surface of the wafer.

29. The method of claim 26, wherein a focal point of the light beam is above a surface of the wafer.

30. The method of claim 26, wherein a focus of the beam changes in depth as the beam scans across the surface of the wafer.

31. The method of claim 26, further comprising directing the light beam through a structured mask disposed in a path of the light beam between the light source and the wafer, wherein the structured mask defines a plurality of apertures, and wherein the plurality of apertures form bright bands on a surface of the wafer and areas of the structured mask between the apertures form dark bands on the surface of the wafer.

32. The method of claim 31, wherein adjusting the illumination conjugate and adjusting the collection conjugate comprises changing a position of a first movable focusing lens in a path of the light beam so that the structured mask is focused and light in the bright bands leaks into the dark bands.

33. The method of claim 26, wherein the illumination numerical aperture is from 0 to 0.

9.

34. The method of claim 26, wherein the collection path numerical aperture is at least 0.

9.

35. The method of claim 26, wherein the wafer comprises a 3D structure.

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