Semiconductor device and semiconductor system

Abstract

A semiconductor device having at least a crystalline oxide semiconductor layer, characterized in that the crystalline oxide semiconductor layer has a band gap of 4.5 eV or more and a field-effect mobility of 10 cm 2 / V·s or more.

Description

Technical Field

[0001] The present invention relates to a semiconductor device useful as a power device, and a semiconductor system having the semiconductor device. Background Technology

[0002] As a next-generation switching element capable of achieving high voltage withstand, low loss, and high heat resistance, gallium oxide (Ga2O3) semiconductor devices with a large bandgap have attracted attention, with prospects for application in power semiconductor devices such as inverters. Furthermore, due to its wide bandgap, it is also expected to be used in light receiving and emitting devices such as LEDs or sensors. Regarding gallium oxide, according to Non-Patent Document 1, by mixing it with indium and aluminum, either separately or in combination, the bandgap can be controlled, making it a highly attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductor refers to In... X Al Y Ga Z O3 (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5~2.5) can be regarded as the same material system including gallium oxide.

[0003] Furthermore, p-type semiconductors based on gallium oxide have been studied in recent years. For example, Patent Document 1 describes how a substrate exhibiting p-type conductivity can be obtained by forming β-Ga₂O₃ crystals using MgO (a p-type dopant source) via a floating zone method (FZ). Additionally, Patent Document 2 describes how α-(Al₂O₃) semiconductors formed using molecular beam epitaxy (MBE) can achieve p-type conductivity. x Ga 1-x P-type semiconductors are formed by ion implantation of p-type dopants into 2O3 single crystal films. However, it is difficult to fabricate p-type semiconductors using these methods (Non-Patent Document 2), and there are actually no reports of successful fabrication of p-type semiconductors using these methods. Therefore, it is hoped that p-type oxide semiconductors and their fabrication methods can be realized.

[0004] Furthermore, as described in Non-Patent Documents 3 and 4, research has been conducted on using Rh₂O₃ or ZnRh₂O₄ for p-type semiconductors. However, the concentration of Rh₂O₃ becomes extremely low during film formation, which affects film formation. Even with organic solvents, it is difficult to produce Rh₂O₃ single crystals. Additionally, even when Hall effect measurements are performed, the semiconductor is not identified as p-type, making the measurement itself impossible. Furthermore, regarding measured values, for example, the Hall coefficient is only within the measurement limit (0.2 cm⁻¹). 3 The following conditions (C) also pose practical problems. Furthermore, ZnRh2O4 has low mobility and a narrow bandgap, making it unsuitable for use in LEDs or power devices, which is not always satisfactory.

[0005] As wide-bandgap semiconductors, p-type oxide semiconductors, besides Rh₂O₃ or ZnRh₂O₄, have also been studied in various ways. Patent Document 3 describes the use of copper ferrite or oxysulfides as p-type semiconductors. However, these semiconductors have mobility of around 1 cm² / V·s or lower, poor electrical properties, and also suffer from the problem of not being able to form good pn junctions with next-generation n-type oxide semiconductors such as α-Ga₂O₃.

[0006] Furthermore, Ir₂O₃ has been known for some time. For example, Patent Document 4 describes the use of Ir₂O₃ as an iridium catalyst. Patent Document 5 describes the use of Ir₂O₃ as a dielectric. Patent Document 6 describes the use of Ir₂O₃ as an electrode. However, the use of Ir₂O₃ in p-type semiconductors is not yet known. Recently, the applicant has been conducting research and development on using Ir₂O₃ as a p-type semiconductor.

[0007] In power devices such as transistors, low on-resistance and high breakdown voltage are required, but challenges remain regarding electrical characteristics such as leakage current. Gallium oxide (Ga₂O₃), in particular, exhibits excellent semiconductor properties, such as an insulation breakdown electric field strength of around 10, low on-resistance, and superior semiconductor characteristics. However, due to challenges in its electrical characteristics, these semiconductor properties cannot be fully utilized. Specifically, junction leakage current, which is easily generated during ion implantation, negatively impacts the electrical characteristics of oxide semiconductors. Therefore, there is a need for a solution to these electrical characteristic problems that allows for the effective use of excellent semiconductor materials such as gallium oxide (Ga₂O₃) to achieve semiconductor devices with high breakdown voltage, low loss, and high heat resistance.

[0008] Patent Document 1: Japanese Patent Publication No. 2005-340308

[0009] Patent Document 2: Japanese Patent Publication No. 2013-58637

[0010] Patent Document 3: Japanese Patent Publication No. 2016-25256

[0011] Patent Document 4: Japanese Patent Publication No. Hei 9-25255

[0012] Patent Document 5: Japanese Patent Publication No. Hei 8-227793

[0013] Patent Document 6: Japanese Patent Publication No. Hei 11-21687

[0014] Non-Patent Document 1: Kentaro Kaneko, "Growth and Physical Properties of Corundum-Structure Gallium Oxide-Based Mixed Crystal Thin Films", Doctoral Thesis of Kyoto University, March 2013 (Kentaro Kaneko, "Growth and Physical Properties of Corundum-Structure Gallium Oxide-Based Mixed Crystal Thin Films", Doctoral Thesis of Kyoto University, March 2013)

[0015] Non-Patent Document 2: Tatsuya Takemoto, EE Times Japan "Power Semiconductor Gallium Oxide", Thermal Conductivity, P-Type... Overcoming Problems and Moving towards Practical Application, [online], February 27, 2014, ITmedia Co., Ltd., [searched on June 21, 2016], Internet <URL: http: / / eetimes.jp / ee / articles / 1402 / 27 / news028_2.html> (Tatsuya Takemoto, EE Times Japan "Power Semiconductor Gallium Oxide", Thermal Conductivity, P-Type... Overcoming Problems and Moving towards Practical Application, [online], February 27, 2014, ITmedia Co., Ltd., [searched on June 21, 2016], URL <URL: http: / / eetimes.jp / ee / articles / 1402 / 27 / news028_2.html>)

[0016] Non-Patent Document 3: F.P. KOFFYBERG et al., "optical bandgaps and electron affinities of semiconducting Rh2O3(I) and Rh2O3(III)", J. Phys. Chem. Solids Vol.53, No.10, pp.1285 - 1288, 1992

[0017] Non-Patent Document 4: Hideyuki Hosono, "Function Development of Oxide Semiconductors", Physical Property Research·Electronic Edition Vol.3, No.1, 031211 (Combined Issue of November 2013·February 2014) (Hideyuki Hosono, "Function Development of Oxide Semiconductors", Physical Property Research·Electronic Edition, Vol.3, No.1, 031211 (Combined Issue of November 2013·February 2014)) Summary of the Invention

[0018] An object of the present invention is to provide a semiconductor device that is useful as a power device or the like and has excellent semiconductor characteristics.

[0019] The inventor of the present invention conducted in-depth research to achieve the above object, and as a result, by arranging 1.0×10 along the direction of current flow 6Surprisingly, when high-resistivity oxide films with resistances above Ω·cm were used, the electrical properties of the fabricated semiconductor devices were found to be significantly improved. Further repeated studies led to the successful creation of high-mobility gallium oxide semiconductor transistors, and it was discovered that the resulting transistors could solve the aforementioned previous problems.

[0020] Furthermore, after obtaining the above insights, the inventors conducted further and repeated research, and thus completed this invention.

[0021] That is, the present invention relates to the following technical solutions.

[0022] [1] A semiconductor device having at least a crystalline oxide semiconductor layer, characterized in that the crystalline oxide semiconductor layer has a band gap of 4.5 eV or more and a field-effect mobility of 10 cm⁻¹. 2 / V·s and above.

[0023] [2] According to the semiconductor device described above [1], wherein the field-effect mobility is 30 cm⁻¹ 2 / V·s and above.

[0024] [3] The semiconductor device according to [1] or [2] above, wherein the crystalline oxide semiconductor layer comprises a p-type dopant.

[0025] [4] The semiconductor device according to any one of [1] to [3] above, wherein a high-resistivity oxide film is further disposed on the crystalline oxide semiconductor layer, the high-resistivity oxide film having a resistance of 1.0 × 10⁻⁶. 6 Ω·cm or higher.

[0026] [5] In the semiconductor device described above [4], the resistance of the high-resistivity oxide film is 1.0 × 10⁻⁶. 10 Ω·cm or higher.

[0027] [6] The semiconductor device according to [4] or [5] above, wherein the semiconductor device further includes a channel forming region under which the high-resistivity oxide film is disposed.

[0028] [7] The semiconductor device according to any one of [4] to [6] above, wherein the high-resistivity oxide film is a current blocking layer.

[0029] [8] The semiconductor device according to any one of [1] to [7] above, wherein the crystalline oxide semiconductor layer has a corundum structure.

[0030] [9] The semiconductor device according to any one of [1] to [8] above, wherein the crystalline oxide semiconductor layer comprises Ga2O3.

[0031]

[10] The semiconductor device according to any one of [1] to [9] above, wherein the semiconductor device is a vertical device.

[0032]

[11] The semiconductor device according to any one of [1] to

[10] above, wherein the semiconductor device is a power device.

[0033]

[12] The semiconductor device according to any one of [1] to

[11] above, wherein the semiconductor device is a MOSFET.

[0034]

[13] The semiconductor device according to any one of [1] to

[12] above, wherein the switching ratio of the semiconductor device is 1000 or more.

[0035]

[14] The semiconductor device according to any one of [1] to

[13] above, wherein the semiconductor device is normally closed.

[0036]

[15] A semiconductor system comprising a semiconductor device, wherein the semiconductor device is any one of the semiconductor devices described in [1] to

[14] above.

[0037] The semiconductor device of the present invention is useful as a power device and the like, and has excellent semiconductor characteristics. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the preferred film-forming apparatus (atomized CVD apparatus) used in this invention.

[0039] Figure 2 The diagram schematically shows the MOSFET of Embodiment 1, (a) schematically showing the upper surface of the MOSFET, and (b) schematically showing the cross section between A-A' of (a).

[0040] Figure 3 The figures schematically illustrate a preferred embodiment of the MOSFET of the present invention as an example, (a) schematically showing the upper surface of the MOSFET, and (b) schematically showing a cross-section of (a).

[0041] Figure 4 The figure is a schematic illustration of a preferred embodiment of the MOSFET of the present invention.

[0042] Figure 5 The figures schematically illustrate a preferred embodiment of the MOSFET of the present invention as an example, (a) schematically showing the upper surface of the MOSFET, and (b) schematically showing the cross section between B-B' of (a).

[0043] Figure 6The figure is a schematic illustration of a preferred embodiment of the MOSFET of the present invention.

[0044] Figure 7 This is a graph showing the IV measurement results in the embodiment.

[0045] Figure 8 This is a diagram schematically showing a preferred example of a power supply system.

[0046] Figure 9 This is a diagram illustrating a preferred embodiment of a display system device.

[0047] Figure 10 This is a diagram of a preferred example of a power supply circuit diagram schematically showing a power supply device. Detailed Implementation

[0048] The semiconductor device in the embodiments of the present invention is characterized by comprising a crystalline oxide semiconductor layer, wherein the crystalline oxide semiconductor layer has a band gap of 4.5 eV or more and a field-effect mobility of 10 cm⁻¹. 2 / V·s or higher. In embodiments of the present invention, the band gap of the crystalline oxide semiconductor layer is preferably 5 eV or higher. Furthermore, the crystalline oxide semiconductor layer preferably has a corundum structure, and is also preferably composed of an oxide semiconductor film. The oxide semiconductor film is preferably an oxide semiconductor film containing gallium oxide (Ga₂O₃) or a mixture thereof as the main component. Additionally, in embodiments of the present invention, the field-effect mobility is preferably 30 cm⁻¹. 2 / V·s or more, preferably 60cm 2 / V·s or higher. This preferred semiconductor device can be readily obtained by using a semiconductor device with a resistance of 1.0 × 10⁻⁶ V·s on the crystalline oxide semiconductor layer. 6 The semiconductor device is fabricated by depositing a high-resistivity oxide film (Ω·cm or higher) along the direction of current flow. Furthermore, the field-effect mobility typically represents the maximum field-effect mobility. Additionally, the semiconductor device can be readily obtained by using a 1.0 × 10⁻⁶ Ω·cm high-resistivity oxide film, provided it includes at least a gate, source, and drain. 6 The semiconductor device is fabricated by depositing a high-resistivity oxide film of Ω·cm or higher between the source and the drain. Furthermore, the semiconductor device can be readily obtained by: in the case of a semiconductor device in which at least the gate, source, drain, and high-resistivity oxide film are formed directly on or in between other layers on a substrate, using a 1.0 × 10⁻⁶ Ω·cm or higher oxide film. 6 The semiconductor device is fabricated by depositing a high-resistivity oxide film of Ω·cm or higher between the source and / or the drain and the substrate.

[0049] The high-resistivity oxide film only needs to have a resistance of 1.0 × 10⁻⁶. 6 There are no particular limitations on the resistance of the oxide film, which is greater than Ω·cm. In embodiments of the present invention, the resistance of the high-resistivity oxide film is preferably 1.0 × 10⁻⁶. 10 The resistance of the high-resistivity oxide film is preferably 1.0 × 10⁻⁶ Ω·cm or higher. 12 Above Ω·cm. It should be noted that the resistance of the high-resistivity oxide film here refers to its resistivity [Ω·cm]. This resistance can be measured by forming a measuring electrode on the high-resistivity oxide film and flowing a current through it. There is no particular upper limit to the resistance, but it is preferably 1.0 × 10⁻⁶. 15 Ω·cm, more preferably 1.0×10 14 Ω·cm. Furthermore, in embodiments of the present invention, the high-resistivity oxide film is preferably a current-blocking layer. By using the high-resistivity oxide film as a current-blocking layer, superior electrical properties can be achieved.

[0050] The constituent material of the high-resistivity oxide film is not particularly limited, but in embodiments of the present invention, a crystalline film is preferred. The crystalline film can be a polycrystalline film or a monocrystalline film. The crystal structure of the crystalline film is not particularly limited, but in embodiments of the present invention, a corundum structure is preferred. Furthermore, the constituent material of the high-resistivity oxide film preferably includes gallium, more preferably Ga2O3. Additionally, in embodiments of the present invention, the high-resistivity oxide film preferably includes a p-type dopant. Furthermore, according to the present invention, the semiconductor device preferably further includes a channel formation region, under which the high-resistivity oxide film is disposed. Based on these preferred ranges, a 10cm [structure / component] can be easily achieved. 2 / V·s or more (more preferably 30cm) 2 A high field-effect mobility (V / s or higher). Furthermore, the field-effect mobility typically refers to the maximum field-effect mobility, which is the field-effect mobility of a semiconductor device such as a transistor calculated using output current data corresponding to the semiconductor device. Additionally, based on the above-mentioned preferred range, an on / off ratio of 1000 or higher (more preferably 100000 or higher) can be easily achieved. It should be noted that "on / off ratio" refers to the ratio of the on-state current to the off-state current of the semiconductor device. For example, when the semiconductor device has at least a source and a drain, the off-state current refers to the current flowing between the sources when the semiconductor device is off, and the on-state current refers to the current flowing between the sources and the drain when the semiconductor device is on. Furthermore, based on the above-mentioned preferred range, an on / off ratio of 1000 or higher (more preferably 100000 or higher) can be easily achieved.

[0051] The high-resistivity oxide film is preferably an oxide semiconductor film containing gallium oxide (Ga₂O₃) or a mixture thereof as the main component. The oxide semiconductor film in the crystalline oxide semiconductor layer or the high-resistivity oxide film can be a p-type semiconductor film or an n-type semiconductor film. Examples of gallium oxide include α-Ga₂O₃, β-Ga₂O₃, and ε-Ga₂O₃, with α-Ga₂O₃ being preferred. Furthermore, examples of gallium oxide mixtures include mixtures of gallium oxide with one or more metal oxides. Preferred examples of metal oxides include aluminum oxide, indium oxide, iridium oxide, rhodium oxide, and iron oxide. Moreover, the term "main component," for example, when the oxide semiconductor film contains α-Ga₂O₃ as the main component, simply means that α-Ga₂O₃ is present at a ratio where the atomic ratio of gallium in the metal elements of the oxide semiconductor film is 0.5 or more. In embodiments of the present invention, the atomic ratio of gallium in the metal elements of the oxide semiconductor film is preferably 0.7 or more, and more preferably 0.8 or more. Furthermore, for example, when the oxide semiconductor film contains a mixed crystal of α-Ga2O3 and α-Al2O3 as the main component, it is sufficient to include the mixed crystal at a ratio of gallium to aluminum in the metal elements of the oxide semiconductor film of 0.5 or more. However, in an embodiment of the present invention, the atomic ratio of gallium in the metal elements of the oxide semiconductor film is preferably 0.5 or more, and more preferably 0.7 or more.

[0052] Furthermore, the thickness of the high-resistivity oxide film is not particularly limited, and can be less than 1 μm or more than 1 μm. In the embodiments of the present invention, it is preferably more than 1 μm, more preferably 1 μm to 40 μm, and most preferably 1 μm to 25 μm. The surface area of ​​the high-resistivity oxide film is not particularly limited, and can be 1 mm. 2 The above can also be 1mm. 2 Furthermore, the high-resistivity oxide film can be a single-layer film or a multilayer film.

[0053] The high-resistivity oxide film is preferably an oxide semiconductor film containing a dopant. The dopant is not particularly limited as long as it does not hinder the purpose of the present invention, and can be any known dopant. Examples of dopant include p-type dopants such as Mg, Zn, or Ca. Regarding the dopant content, in the composition of the oxide semiconductor film, it is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.0001 atomic% to 20 atomic%.

[0054] Furthermore, regarding the p-type dopant, there are no particular limitations as long as it can impart conductivity to the oxide semiconductor film as a p-type semiconductor film, and any known p-type dopant can be used. Examples of p-type dopants include Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, Pb, N, P, and two or more elements selected from these. In embodiments of the present invention, the p-type dopant is preferably Mg, Zn, or Ca.

[0055] The high-resistivity oxide film, unlike conventional high-resistivity oxide layers formed by ion implantation, is typically obtained using epitaxial crystal growth methods, but the formation method is not particularly limited. The epitaxial crystal growth method is not particularly limited as long as it does not hinder the purpose of this invention and can be any known method. Examples of such epitaxial crystal growth methods include CVD (chemical vapor deposition), MOCVD (metal-organic vapor phase epitaxy), MOVPE (metal-organic vapor phase epitaxy), atomized CVD, atomized epitaxy, MBE (molecular beam epitaxy), HVPE (hydride vapor phase epitaxy), or pulsed growth. In embodiments of this invention, the epitaxial crystal growth method is preferably atomized CVD or atomized epitaxy.

[0056] In an embodiment of the present invention, the film formation is preferably performed by the following steps: atomizing a raw material solution containing metal (atomization step), transporting the resulting atomized droplets to the vicinity of the substrate using a carrier gas (transportation step), and then subjecting the atomized droplets to a thermal reaction (film formation step).

[0057] (Raw material solution)

[0058] Regarding the raw material solution, there are no particular limitations as long as it contains a metal as a film-forming material and can be atomized. It can contain inorganic materials or organic materials. The metal can be an elemental metal or a metal compound, and there are no particular limitations as long as it does not hinder the purpose of the present invention. Examples include: one or more metals selected from gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), gallium (Ga), magnesium (Mg), calcium (Ca), and zirconium (Zr). In the embodiments of the present invention, the metal preferably contains at least one or more metals from the 4th to the 6th period of the periodic table, more preferably at least gallium, indium, aluminum, rhodium, or iridium, and most preferably at least gallium. By using such a preferred metal, an epitaxial film that is more suitable for use in semiconductor devices and the like can be formed.

[0059] In embodiments of the present invention, the raw material solution is preferably a solution obtained by dissolving or dispersing the metal in an organic solvent or water in the form of a complex or salt. Examples of complex forms include acetylacetone complexes, carbonyl complexes, ammonia complexes, and hydride complexes. Examples of salt forms include organometallic salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), sulfide metal salts, nitrate metal salts, phosphate metal salts, and halide metal salts (e.g., metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0060] Regarding the solvent of the raw material solution, there are no particular limitations as long as it does not hinder the purpose of the present invention. It can be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixture of inorganic and organic solvents. In embodiments of the present invention, the solvent preferably includes water.

[0061] In addition, additives such as hydrohalic acids or oxidants may be mixed into the raw material solution. Examples of hydrohalic acids include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of oxidants include hydrogen peroxide (H₂O₂), sodium peroxide (Na₂O₂), barium peroxide (BaO₂), benzoyl peroxide ((C₆H₅CO)₂O₂), hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, or organic peroxides such as nitrobenzene. The proportion of these additives is not particularly limited, but is preferably 0.001 vol% to 50 vol% relative to the raw material solution, more preferably 0.01 vol% to 30 vol%.

[0062] The raw material solution may also contain dopants. There are no particular limitations on the dopants, as long as they do not hinder the purpose of the invention. Examples of dopants include, for instance, the aforementioned n-type or p-type dopants. The concentration of the dopant is typically about 1 × 10⁻⁶. 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the concentration of the dopant can be, for example, about 1 × 10⁻⁶. 17 / cm 3 The following low concentrations. Furthermore, according to the present invention, it is also possible to use approximately 1 × 10⁻⁶. 20 / cm 3 The above high concentrations contain dopants.

[0063] (Atomization process)

[0064] Regarding the atomization process, a raw material solution containing a metal is prepared, and the raw material solution is atomized to produce atomized droplets. The proportion of the metal is not particularly limited, but is preferably 0.0001 mol / L to 20 mol / L relative to the total raw material solution. Regarding the atomization method, there are no particular limitations as long as the raw material solution can be atomized; any known atomization method can be used. In embodiments of the present invention, an atomization method using ultrasonic vibration is preferred. The atomized droplets (e.g., fog) used in the present invention are more preferably atomized droplets floating in the air, which are not blown out like a spray, but are atomized droplets that can be transported by floating in the air with an initial velocity of zero. The droplet size is not particularly limited and can be droplets of about a few millimeters, but is preferably 50 μm or less, more preferably 1 μm to 10 μm.

[0065] (Transportation process)

[0066] In the transport process, the atomized droplets are transported to the substrate using the carrier gas. The type of carrier gas is not particularly limited as long as it does not hinder the purpose of the invention. Preferred examples include oxygen, ozone, inactive gases (such as nitrogen or argon), or reducing gases (such as hydrogen or synthesis gases). Furthermore, one or more types of carrier gas can be used, and a dilution gas that changes the carrier gas concentration (e.g., a 10-fold dilution gas) can be used as a second carrier gas. Additionally, the carrier gas can be supplied from one location or from two or more locations. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 LPM to 20 LPM, more preferably 0.1 LPM to 10 LPM.

[0067] (Film forming process)

[0068] In the film-forming process, the atomized droplets are reacted to form a film on the substrate. Regarding the reaction, there are no particular limitations as long as the atomized droplets form a film; however, in embodiments of the present invention, a thermal reaction is preferred. Regarding the thermal reaction, any reaction that allows the atomized droplets to react with heat is acceptable, and the reaction conditions are not particularly limited as long as they do not hinder the purpose of the present invention. In this process, the thermal reaction is typically carried out at a temperature above the evaporation temperature of the solvent in the raw material solution, but preferably at a temperature not too high, more preferably below 850°C, and most preferably below 650°C. Furthermore, as long as it does not hinder the purpose of the present invention, the thermal reaction can be carried out under any atmosphere, including a vacuum, a non-oxygen atmosphere, a reducing gas atmosphere, and an oxygen atmosphere. It can also be carried out under atmospheric pressure, under pressure, and under reduced pressure. In embodiments of the present invention, carrying out the reaction under atmospheric pressure allows for simpler calculation of the evaporation temperature and simplifies the equipment, making it preferred from these perspectives. Additionally, the film thickness can be set by adjusting the film-forming time.

[0069] (Matrix)

[0070] Regarding the substrate, there are no particular limitations as long as it can support the membrane. The material of the substrate is also not particularly limited as long as it does not hinder the purpose of the invention; it can be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate can be any shape, and all shapes are effective. For example, examples include plate-shaped (such as flat plates or discs), fibrous, rod-shaped, cylindrical, prismatic, tubular, spiral, spherical, and annular shapes. In embodiments of the invention, a substrate is preferred. Regarding the thickness of the substrate, there are no particular limitations in embodiments of the invention.

[0071] The substrate is not particularly limited as long as it is plate-shaped and serves as a support for the high-resistivity oxide film. The substrate can be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but it is preferably an insulating substrate, and also preferably a substrate with a metal film on its surface. Examples of substrates include those comprising a substrate material having a corundum structure as the main component, a substrate material having a β-gallia structure as the main component, or a substrate material having a hexagonal crystal structure as the main component. Here, "main component" refers to, relative to all components of the substrate material, preferably comprising 50% or more of the substrate material having the aforementioned specific crystal structure, more preferably 70% or more, further preferably 90% or more, and may also be 100%.

[0072] Regarding the substrate material, there are no particular limitations as long as it does not hinder the purpose of this invention, and any known material may be used. As examples of the aforementioned substrate material with a corundum structure, α-Al₂O₃ (sapphire substrate) or α-Ga₂O₃ are preferably cited. More preferred examples include a-plane sapphire substrates, m-plane sapphire substrates, r-plane sapphire substrates, c-plane sapphire substrates, and α-type gallium oxide substrates (a-plane, m-plane, or r-plane). As for substrates with a substrate material having a β-gallia structure as the main component, examples include β-Ga₂O₃ substrates, or mixed crystal substrates containing Ga₂O₃ and Al₂O₃, where Al₂O₃ is more than 0 wt% and less than 60 wt%. Furthermore, substrates with a substrate material having a hexagonal crystal structure as the main component include, for example, SiC substrates, ZnO substrates, and GaN substrates.

[0073] In embodiments of the present invention, annealing may be performed after the film-forming process. The annealing temperature is not particularly limited as long as it does not hinder the purpose of the present invention; it is typically 300°C to 650°C, preferably 350°C to 550°C. Furthermore, the annealing time is typically 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. Moreover, annealing can be performed in any atmosphere as long as it does not hinder the purpose of the present invention; a non-oxygen atmosphere is preferred, and a nitrogen atmosphere is more preferred.

[0074] Furthermore, in embodiments of the present invention, the high-resistivity oxide film can be formed directly on the substrate, or it can be formed with other layers such as a buffer layer or a stress relaxation layer in between. The method for forming each layer is not particularly limited and can be any known method; however, in embodiments of the present invention, atomization CVD or atomization epitaxy is preferred.

[0075] Hereinafter, the film-forming apparatus 19, which is preferably used in the atomization CVD method or atomization epitaxy method, will be described with reference to the accompanying drawings. Figure 1 The film-forming apparatus 19 includes: a carrier gas source 22a for supplying carrier gas; a flow regulating valve 23a for regulating the flow rate of the carrier gas supplied from the carrier gas source 22a; a carrier gas (dilution) source 22b for supplying carrier gas (dilution); a flow regulating valve 23b for regulating the flow rate of the carrier gas (dilution) supplied from the carrier gas (dilution) source 22b; a mist generating source 24 for collecting the raw material solution 24a; a container 25 containing water 25a; an ultrasonic transducer 26 mounted on the bottom surface of the container 25; a film-forming chamber 30; a quartz supply pipe 27 connected from the mist generating source 24 to the film-forming chamber 30; and a heating plate (heater) 28 disposed within the film-forming chamber 30. A substrate 20 is disposed on the heating plate 28.

[0076] Then, as Figure 1As shown, the raw material solution 24a is contained within the mist generation source 24. Next, a substrate 20 is placed on a heating plate 28, and the heating plate 28 is operated to raise the temperature within the film-forming chamber 30. Then, flow control valves 23 (23a, 23b) are opened to supply carrier gas from carrier gas sources 22 (22a, 22b) into the film-forming chamber 30. After the atmosphere of the film-forming chamber 30 is fully replaced with carrier gas, the flow rates of the carrier gas and the carrier gas (diluted) are adjusted respectively. Next, the ultrasonic transducer 26 is vibrated, and this vibration is propagated to the raw material solution 24a through water 25a, thereby atomizing the raw material solution 24a to generate atomized droplets 24b. The atomized droplets 24b are introduced into the film-forming chamber 30 using carrier gas and transported to the substrate 20. Then, under atmospheric pressure, the atomized droplets 24b undergo a thermal reaction within the film-forming chamber 30, forming a film on the substrate 20.

[0077] In embodiments of the present invention, the film obtained by the film-forming process can be used directly in a semiconductor device, or it can be used in a semiconductor device after using a known method such as a method for peeling off from the substrate.

[0078] The semiconductor device includes a semiconductor layer and a substrate, and preferably, the high-resistivity oxide film is disposed between the semiconductor layer and the substrate. According to this preferred semiconductor device, a lateral semiconductor device with superior electrical characteristics can be obtained, making it more suitable for use as a power device.

[0079] Furthermore, regarding the semiconductor device, it is also preferable that the high-resistivity oxide film has an opening and that the semiconductor device is a vertical device. According to this preferred semiconductor device, a lateral semiconductor device with better electrical characteristics that can achieve high voltage withstand and high current can be obtained, and it is more suitable for use as a power device.

[0080] The semiconductor device is particularly useful as a power device. Examples of such semiconductor devices include transistors, with MOSFETs being preferred. Furthermore, the semiconductor device is preferably normally closed.

[0081] Examples of transistors include, for instance, semiconductor devices comprising at least a high-resistivity oxide film, a gate insulating film, a gate, a source, and a drain. In embodiments of the present invention, the high-resistivity oxide film may also be used as a semiconductor layer. Furthermore, the semiconductor device preferably includes a channel formation region, and more preferably includes an inversion channel formation region.

[0082] The inversion channel forming region is typically disposed between semiconductor regions exhibiting different types of conductivity. For example, when the inversion channel forming region is disposed within a p-type semiconductor layer, it is typically disposed within a p-type semiconductor layer between semiconductor regions composed of n-type semiconductors. Similarly, when the inversion channel forming region is disposed within an n-type semiconductor layer, it is typically disposed within an n-type semiconductor layer between semiconductor regions composed of p-type semiconductors. Furthermore, the method for forming each semiconductor region can be the same as the method for forming the high-resistivity oxide film.

[0083] Furthermore, in embodiments of the present invention, it is preferable to deposit an oxide film comprising at least one element from Group 15 of the periodic table on the inversion channel forming region. Examples of such elements include nitrogen (N) and phosphorus (P), but in embodiments of the present invention, nitrogen (N) or phosphorus (P) is preferred, and phosphorus (P) is more preferred. For example, by depositing an oxide film comprising at least phosphorus on the inversion channel forming region between the gate insulating film and the inversion channel forming region, hydrogen diffusion to the oxide semiconductor film can be prevented, and the interface states can be further reduced, thus imparting superior semiconductor characteristics to the semiconductor device, especially to a wide-bandgap semiconductor. Furthermore, in embodiments of the present invention, it is more preferable that the oxide film comprises at least one element from Group 15 of the periodic table and one or more metals from Group 13 of the periodic table. Examples of such metals include aluminum (Al), gallium (Ga), and indium (In), wherein Ga and / or Al are preferred, and Ga is more preferred. Additionally, the oxide film is preferably a thin film, more preferably a thin film with a thickness of 100 nm or less, and most preferably a thin film with a thickness of 50 nm or less. By stacking such an oxide film, gate leakage can be suppressed more effectively, thereby enabling the semiconductor to exhibit superior characteristics. Methods for forming the oxide film include, for example, known methods, and more specifically, dry or wet methods, but surface treatment of the inversion channel region using phosphoric acid or the like is preferred.

[0084] Furthermore, in embodiments of the present invention, it is preferable to provide a gate on the reverse channel forming region with a gate insulating film in between, and it is also preferable to provide a gate on the reverse channel forming region and the oxide film with a gate insulating film in between. With this configuration, it is easy to prevent hydrogen diffusion and the like, thereby achieving better semiconductor characteristics.

[0085] Regarding the gate insulating film, there are no particular limitations as long as it does not hinder the purpose of the present invention, and any known insulating film may be used. As a preferred example of the gate insulating film, oxide films comprising at least SiO2, Si3N4, Al2O3, GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, MgO, GdO, or phosphorus may be listed. The method for forming the gate insulating film may be a known method, such as a dry method or a wet method. As a dry method, known methods such as sputtering, vacuum evaporation, CVD, and pulsed laser deposition (PLD) may be listed. As a wet method, coating methods such as screen printing or die coating may be listed.

[0086] The gate electrode can be any known type, and the electrode material can be a conductive inorganic material or a conductive organic material. In embodiments of the present invention, the electrode material is preferably a metal. There are no particular limitations on the metal, but preferably, for example, at least one metal selected from Groups 4 to 11 of the periodic table. Examples of Group 4 metals include titanium (Ti), zirconium (Zr), and hafnium (Hf), with Ti being preferred. Examples of Group 5 metals include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of Group 6 metals include one or more metals selected from chromium (Cr), molybdenum (Mo), and tungsten (W). In embodiments of the present invention, Cr is preferred to improve semiconductor properties such as switching characteristics. Examples of Group 7 metals include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals belonging to Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals belonging to Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals belonging to Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt), with Pt being preferred. Examples of metals belonging to Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). Methods for forming the gate include known methods, and more specifically, dry or wet methods. Dry methods include known methods such as sputtering, vacuum evaporation, and CVD. Wet methods include screen printing or die coating.

[0087] Furthermore, in embodiments of the present invention, in addition to a gate, a source and a drain are typically also provided. However, the source and drain can be known electrodes in the same way as the gate, and the methods for forming the electrodes can also be known methods.

[0088] The preferred embodiments of the present invention will be described in more detail below with the help of the accompanying drawings, but the present invention is not limited thereto.

[0089] (MOSFET)

[0090] As a specific example of the semiconductor device of the present invention, examples can be cited. Figure 2 The MOSFETs shown are examples of this. Figure 2 The MOSFET in this design is a lateral MOSFET, comprising: an n+ type semiconductor layer (n+ type source layer) 1b, an n+ type semiconductor layer (n+ type drain layer) 1c, a high-resistivity oxide film 2 serving as a p-type semiconductor layer, a gate insulating film 4a, a gate 5a, a source 5b, a drain 5c, and a substrate 9. Furthermore, Figure 2 (a) is a top view of the MOSFET from the zenith, schematically showing the upper surface of the MOSFET. Additionally, Figure 2 (b) schematically shows Figure 2 (a) Cross section of the MOSFET between A-A'.

[0091] for Figure 2 Regarding the on-state of the MOSFET, if a voltage is applied between the source 5b and the drain 5c, and a positive voltage is applied between the gate 5a and the source 5b, a channel layer is formed between the n+ type semiconductor layer (n+ type source layer) 1b and the n+ type semiconductor layer (n+ type drain layer) 1c, thus turning on the MOSFET. The off-state is achieved by setting the gate voltage to 0V, preventing the formation of the channel layer and thus turning off the MOSFET.

[0092] As an example of the semiconductor device of the present invention Figure 3 This is one way to display MOSFETs. Furthermore... Figure 3 (a) is a top view of the MOSFET from the zenith, schematically showing the upper surface of the MOSFET. Additionally, Figure 3 (b) schematically shows Figure 3 (a) A cross-section of the MOSFET. Figure 3 The MOSFET in the image is a lateral MOSFET, comprising: an n+ type semiconductor layer 1, an n- type semiconductor layer 3, an n+ type semiconductor layer (n+ type source layer) 1b, an n+ type semiconductor layer (n+ type drain layer) 1c, a high-resistivity oxide film 2, a gate insulating film 4a, a gate 5a, a source 5b, a drain 5c, and a substrate 9. Figure 3Regarding the on-state of the MOSFET, if a voltage is applied between the source 5b and the drain 5c, and a positive voltage is applied to the source 5b through the gate 5a, a channel layer is formed between the n+ type semiconductor layer (n+ type source layer) 1b and the n+ type semiconductor layer (n+ type drain layer) 1c, thus turning on the MOSFET. Furthermore, leakage current is suppressed by inducing current through the high-resistivity oxide film 3. Conversely, the off-state is achieved by setting the voltage at the gate to 0V, preventing the formation of the channel layer and thus turning off the MOSFET.

[0093] As an example of the semiconductor device of the present invention Figure 4 This is one way to display MOSFETs. Figure 4 The MOSFET is a lateral MOSFET, comprising: an n+ type semiconductor layer 1, an n- type semiconductor layer 3, an n+ type semiconductor layer (n+ type source layer) 1b, an n+ type semiconductor layer (n+ type drain layer) 1c, a high-resistivity oxide film 2, a gate insulating film 4a, a gate 5a, a source 5b, a drain 5c, and a substrate 9. Figure 4 The MOSFET in the middle, compared to Figure 3 In the MOSFET, the n+ type semiconductor layer (n+ type drain layer) 1c is mesa-shaped and has a stepped structure. In the n+ type semiconductor layer (n+ type drain layer) 1c, the gate side is lower and the drain side is higher. With this configuration, a semiconductor device with higher withstand voltage can be realized.

[0094] As an example of the semiconductor device of the present invention Figure 5 One way to display MOSFETs. Furthermore, Figure 5 (a) is a top view of the MOSFET from the zenith, schematically showing the upper surface of the MOSFET. Additionally, Figure 5 (b) schematically shows Figure 5 (a) Cross section of the MOSFET between B-B'. Figure 5 The MOSFETs in this design are vertically oriented and are semiconductor devices capable of achieving higher voltage and higher current withstand capabilities. Furthermore, Figure 5The MOSFET includes an n+ type semiconductor layer (n+ type source layer) 1b, an n+ type semiconductor layer (n+ type drain layer) 1c, a high-resistivity oxide film 2, an n- type semiconductor layer 3, a gate insulating film 4a, a gate 5a, a source 5b, a drain 5c, and a substrate 9. The high-resistivity oxide film 2 has an opening below the gate. Regarding the opening, if its width is wider than the gate, the on-resistance can be further reduced; conversely, if its width is narrower than the gate, the breakdown voltage can be further improved. The opening can be formed using known methods such as etching. In embodiments of the present invention, for example, the opening can be formed by etching after the high-resistivity oxide film is formed, or the high-resistivity oxide film can be formed by using a mask at the opening location after the n- type semiconductor layer is formed, and then removing the mask. An example of a high-resistivity oxide film having an opening formed by the latter method is shown in [the following text is missing from the original]. Figure 6 .and Figure 5 The MOSFETs in them are different. Figure 6 This example illustrates a MOSFET display where the opening is located within the n-type semiconductor layer on the gate side. In embodiments of the present invention, Figure 5 MOSFETs and Figure 6 Any of the MOSFETs can be preferably used.

[0095] In addition to the above, the semiconductor device of the present invention further utilizes known methods, making it suitable for use as a power module, inverter, or converter, and, for example, for use in semiconductor systems that utilize power supply devices. The power supply device can be manufactured from the semiconductor device or made into the semiconductor device by using known methods to connect it to wiring patterns, etc. Figure 8 Show examples of power systems. Figure 8 This illustrates a power system 170 comprising multiple power supply devices 171, 172 and control circuitry 173. Regarding the power system 170, as... Figure 9 As shown, electronic circuit 181 can be connected to power supply system 182 (i.e., Figure 8 The power supply system 170) is combined with the system device 180. Furthermore, Figure 10 An example of a power circuit diagram showing a power supply device. Figure 10The power supply circuit of the power supply device, consisting of a power circuit and a control circuit, converts DC voltage to AC voltage via high-frequency switching by an inverter 192 (composed of MOSFETs A to D). A transformer 193 provides insulation and voltage transformation. After rectification by rectifier MOSFETs (A to B'), the voltage is smoothed by DCL195 (smoothing coils L1 and L2) and capacitors, resulting in an output DC voltage. A voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and rectifier MOSFETs 194 to generate the desired output voltage.

[0096] Example

[0097] (Example 1) Figure 2 The fabrication of MOSFETs shown in the image

[0098] 1. Formation of p-type semiconductor layer (high-resistance oxide film)

[0099] 1-1. Film forming apparatus

[0100] use Figure 1 Film-forming device 19.

[0101] 1-2. Preparation of raw material solution

[0102] Prepare a 0.1M gallium bromide aqueous solution containing 20% ​​hydrobromic acid by volume, and then add Mg at a ratio of 10% by volume to form the raw material solution.

[0103] 1-3. Film Formation Preparation

[0104] The raw material solution 24a obtained in steps 1-2 above is placed inside the mist generation source 24. Next, a sapphire substrate 20 is placed on a base 21 (not shown), and the heater 28 is operated to raise the temperature inside the film-forming chamber 30 to 520°C. Then, flow control valves 23a and 23b are opened to supply carrier gas from carrier gas supply sources 22a and 22b, which serve as carrier gas sources, into the film-forming chamber 30. After the atmosphere in the film-forming chamber 30 is fully replaced with carrier gas, the flow rate of the carrier gas is adjusted to 1 LPM, and the flow rate of the carrier gas (diluted) is also adjusted to 1 LPM. Nitrogen is used as the carrier gas.

[0105] 1-4. Semiconductor film formation

[0106] Next, the ultrasonic transducer 26 is vibrated at 2.4 MHz, and the vibration is propagated to the raw material solution 24a through water 25a, thereby atomizing the raw material solution 24a to generate mist. The mist is introduced into the film-forming chamber 30 using a carrier gas, and reacted in the film-forming chamber 30 at atmospheric pressure and 520°C, thereby forming a p-type semiconductor layer (high-resistivity oxide film) on the substrate 20. Furthermore, the film thickness is 0.6 μm, and the film-forming time is 15 minutes.

[0107] 1-5. Evaluation

[0108] The phase of the film obtained from steps 1-4 above was identified using an XRD diffraction apparatus, and the resulting film was α-Ga2O3.

[0109] 2. Formation of n+ type semiconductor regions

[0110] A 0.1M gallium bromide aqueous solution containing 10% hydrobromic acid and 8% tin bromide by volume was used as the raw material solution. The film-forming temperature was set to 580°C and the film-forming time was set to 5 minutes. Otherwise, an n+ type semiconductor film was formed on the p-type semiconductor layer obtained in step 1. in the same manner as described above. The phase of the resulting film was identified using an XRD diffraction apparatus. The result showed that the obtained crystalline oxide semiconductor film was α-Ga₂O₃ with a band gap of 5 eV or more.

[0111] 3. Formation of the gate insulating film and each electrode

[0112] The n+ type semiconductor layer in the region corresponding to the gate portion (between 1b and 1c) was etched with phosphoric acid and further treated with phosphoric acid to form an oxide film containing at least phosphorus on the p-type semiconductor layer. Then, a SiO2 film was formed using tetraethyl orthosilicate (TEOS) as the gate insulating film. Furthermore, the resistance of the high-resistivity oxide film was measured by forming a measuring electrode on the high-resistivity oxide film and flowing current through it; the result was 1.0 × 10⁻⁶. 12 Above Ω·cm. Furthermore, it undergoes photolithography, etching, and electron beam evaporation processes to create materials such as… Figure 2 The MOSFET is as shown. Furthermore, Ti is used in all electrodes.

[0113] (evaluate)

[0114] IV measurements were performed on the obtained MOSFET. The IV measurement results are shown in... Figure 7 .Depend on Figure 7 It has been clearly learned and confirmed that a MOSFET with high mobility gallium oxide semiconductor, formed with a reverse channel region, has been successfully created and is functioning well as a transistor. Furthermore, by... Figure 7 It can be seen that, based on the evaluation of the Id-Vg characteristics (Vd = 10V), the field-effect mobility (when Vg is 20V) is 62.52 cm⁻¹. 2 / V·s、116.9cm 2 / V·s and 54.55cm 2 / V·s, and the field-effect mobility (when Vg is 14V) is 102.5cm. 2 / V·s、131.6cm 2 / V·s and 36.85cm 2 / V·s. Furthermore, the gate voltage threshold voltage derived from the obtained IV characteristics is 7V or higher. Additionally, the on / off ratio is 10,000,000.

[0115] Industrial availability

[0116] The semiconductor device of the present invention can be used in all fields such as semiconductors (e.g., compound semiconductor electronic devices), electronic components and electrical equipment components, optical and electronic photographic devices, and industrial components, and is particularly useful as a power device.

[0117] Symbol Explanation

[0118] 1 n+ type semiconductor layer

[0119] 1b n+ type semiconductor layer (n+ type source layer)

[0120] 1c n+ type semiconductor layer (n+ type drain layer)

[0121] 2 High-resistivity oxide films

[0122] 3 n-type semiconductor layers

[0123] 4a Gate insulating film

[0124] 5a gate

[0125] 5b source

[0126] 5c drain

[0127] 9 substrate

[0128] 19. Atomized CVD Unit

[0129] 20 substrate

[0130] 22a Carrier gas supply source

[0131] 22b Carrier gas (dilution) supply source

[0132] 23a Flow regulating valve

[0133] 23b Flow regulating valve

[0134] 24. Sources of Fog

[0135] 24a Raw material solution

[0136] 24b Atomized droplets

[0137] 25 containers

[0138] 25a Water

[0139] 26. Ultrasonic transducer

[0140] 27 Supply Management

[0141] 28. Heating plate (heater)

[0142] 170 Power System

[0143] 171 Power Supply Unit

[0144] 172 Power Supply Unit

[0145] 173 Control Circuit

[0146] 180 System Device

[0147] 181 Electronic Circuits

[0148] 182 Power System

[0149] 192 Inverter

[0150] 193 Transformer

[0151] 194 Rectifier MOSFET

[0152] 195 DCL

[0153] 196 PWM control circuit

[0154] 197 Voltage comparator

Claims

1. A semiconductor device, comprising a MOSFET having at least a crystalline oxide semiconductor layer, characterized in that, The crystalline oxide semiconductor layer comprises gallium oxide or a mixed crystal of gallium oxide as the main component, the band gap of the crystalline oxide semiconductor layer is 4.5 eV or higher, and the field-effect mobility of the semiconductor device is 10 cm⁻¹. 2 / V･s and above.

2. The semiconductor device according to claim 1, wherein, The field-effect mobility is 30 cm⁻¹ 2 / V･s and above.

3. The semiconductor device according to claim 1, wherein, The crystalline oxide semiconductor layer contains a p-type dopant.

4. The semiconductor device according to claim 2, wherein, The crystalline oxide semiconductor layer contains a p-type dopant.

5. The semiconductor device according to claim 1, wherein, A high-resistivity oxide film is further disposed on the crystalline oxide semiconductor layer, the high-resistivity oxide film having a resistance of 1.0 × 10⁻⁶. 6 Ω･cm and above.

6. The semiconductor device according to claim 2, wherein, A high-resistivity oxide film is further disposed on the crystalline oxide semiconductor layer, the high-resistivity oxide film having a resistance of 1.0 × 10⁻⁶. 6 Ω･cm and above.

7. The semiconductor device according to claim 5, wherein, The resistance of the high-resistivity oxide film is 1.0 × 10⁻⁶. 10 Ω･cm and above.

8. The semiconductor device according to claim 6, wherein, The resistance of the high-resistivity oxide film is 1.0 × 10⁻⁶. 10 Ω･cm and above.

9. The semiconductor device according to claim 5, wherein, The semiconductor device further includes a channel forming region, under which the high-resistivity oxide film is disposed.

10. The semiconductor device according to claim 6, wherein, The semiconductor device further includes a channel forming region, under which the high-resistivity oxide film is disposed.

11. The semiconductor device according to claim 5, wherein, The high-resistivity oxide film is a current-blocking layer.

12. The semiconductor device according to claim 6, wherein, The high-resistivity oxide film is a current-blocking layer.

13. The semiconductor device according to any one of claims 1 to 12, wherein, The crystalline oxide semiconductor layer has a corundum structure.

14. The semiconductor device according to any one of claims 1 to 12, wherein, The semiconductor device is a vertical type device.

15. The semiconductor device according to any one of claims 1 to 12, wherein, The switching ratio of the semiconductor device is 1000 or higher.

16. The semiconductor device according to any one of claims 1 to 12, wherein, The semiconductor device is normally closed.

17. A semiconductor system comprising a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 16.

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