Display device

Abstract

A display device is provided. The display device includes a substrate including a plurality of pixel regions equipped with a first pixel, a second pixel, and a third pixel; a vertical voltage line extending in a first direction on the substrate; a horizontal voltage line extending in a second direction intersecting the first direction on the vertical voltage line and connected to the vertical voltage line; a first electrode of each of the first to third pixels arranged on the horizontal voltage line to receive a driving current; a second electrode of each of the first to third pixels and a third electrode of each of the first to third pixels arranged in parallel with the first electrode to be connected to the horizontal voltage line; a first contact electrode of each of the first to third pixels arranged on the first electrode to be connected to the first electrode; and a second contact electrode of each of the first to third pixels arranged in the same layer as the first contact electrode to be insulated from the first to third electrodes.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device. BACKGROUND

[0002] With the development of information society, the requirements for a display device for displaying an image are increasing in various forms. For example, the display device is applied to various electronic devices such as a smart phone, a digital camera, a notebook computer, a navigator, and a smart TV. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, an organic light emitting display device, etc. In these flat panel display devices, each of the pixels of the display panel of the light emitting display device includes a light emitting element capable of self-emitting light, so that an image can be displayed without a backlight unit for providing light to the display panel. The light emitting element can be an organic light emitting diode using an organic substance as a fluorescent substance and an inorganic light emitting diode using an inorganic substance as a fluorescent substance. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a display device capable of reducing a coupling capacitance between a gate line of a gate layer and a contact electrode of an anode layer to remove a black floating problem or noise at a black level.

[0004] The technical problem of the present application is not limited to the above-mentioned technical problem, and other technical problems not mentioned can be clearly understood by those skilled in the art through the following contents.

[0005] A display device of one embodiment for solving the above-described technical problem includes a substrate including a plurality of pixel regions provided with a first pixel, a second pixel, and a third pixel; a vertical voltage line extending in a first direction on the substrate; a horizontal voltage line extending in a second direction intersecting the first direction on the vertical voltage line and connected to the vertical voltage line; a first electrode of each of the first pixel to the third pixel arranged on the horizontal voltage line to receive a driving current; a second electrode of each of the first pixel to the third pixel and a third electrode of each of the first pixel to the third pixel arranged in parallel with the first electrode to be connected to the horizontal voltage line; a first contact electrode of each of the first pixel to the third pixel arranged on the first electrode to be connected to the first electrode; and a second contact electrode of each of the first pixel to the third pixel arranged in the same layer as the first contact electrode to be insulated from the first electrode to the third electrode.

[0006] The display device can further include an active layer disposed on the vertical voltage line, and an auxiliary gate line disposed between the active layer and the horizontal voltage line to extend in the first direction.

[0007] The second electrode of the second pixel can receive a low potential voltage from the horizontal voltage line to reduce a capacitance between the auxiliary gate line and the second contact electrode of the second pixel.

[0008] The display device can further include a vertical gate line disposed on the same layer as the vertical voltage line, and a horizontal gate line disposed on the same layer as the horizontal voltage line to be connected between the vertical gate line and the auxiliary gate line.

[0009] The display device can further include a first auxiliary electrode disposed on the same layer as the auxiliary gate line to overlap the vertical gate line.

[0010] The second electrode of the first pixel can receive a low potential voltage from the horizontal voltage line to reduce a capacitance between the first auxiliary electrode and the second contact electrode of the first pixel.

[0011] The display device can further include a second auxiliary electrode disposed on the same layer as the horizontal gate line to overlap the vertical gate line.

[0012] The second electrode of the first pixel can receive a low potential voltage from the horizontal voltage line to reduce a capacitance between the second auxiliary electrode and the second contact electrode of the first pixel.

[0013] In a plan view, one end of the first electrode of each of the first to third pixels adjacent to the horizontal gate line and the other end adjacent to the horizontal voltage line can be cut off, and one end of the second electrode of each of the first to third pixels adjacent to the horizontal gate line can be cut off.

[0014] The display device can further include a connection portion connecting the second electrode of the first pixel and the third electrode of the second pixel to extend in the second direction.

[0015] The display device can further include a connection portion connecting the second electrode of the second pixel and the third electrode of the third pixel to extend in the second direction.

[0016] The first electrode can extend in the first direction, the second electrode can be disposed on one side of the first electrode, and the third electrode can be disposed on the other side of the first electrode.

[0017] The second contact electrode of each of the first to third pixels can include a first portion extending in the first direction on the second electrode, a second portion extending in the second direction from the first portion, and a third portion disposed on the first electrode from the second portion.

[0018] Each of the first to third pixels can include a first transistor disposed between a driving voltage line and a plurality of light emitting elements to supply a driving current to the plurality of light emitting elements, a second transistor connecting a data line with a first node which is a gate electrode of the first transistor based on a gate signal, a third transistor connecting a sensing line with a second node which is a source electrode of the first transistor based on the gate signal, and a storage capacitor connected between the first node and the second node.

[0019] The display device can further include a plurality of first light emitting elements connected between the first contact electrode and the second contact electrode, and a plurality of second light emitting elements connected between the second contact electrode and the third electrode.

[0020] The second contact electrode can be a third node between the plurality of first light emitting elements and the plurality of second light emitting elements.

[0021] The plurality of first light emitting elements can be arranged between the first electrode and the second electrode, and the plurality of second light emitting elements can be arranged between the first electrode and the third electrode.

[0022] The display device can further include a first connection electrode disposed in the same layer as the horizontal voltage line to be connected between the first electrode and a source electrode of the first transistor, wherein a gate electrode of the first transistor is a first capacitor electrode of the storage capacitor, and the first connection electrode is a second capacitor electrode of the storage capacitor.

[0023] The display device can further include a second connection electrode bent from the horizontal voltage line to overlap the vertical voltage line in a thickness direction and directly connected to the vertical voltage line through a plurality of contact holes.

[0024] A display device according to an embodiment for solving the above-mentioned technical problems includes: a substrate including a plurality of pixel regions equipped with a first pixel to a third pixel; a vertical voltage line extending on the substrate along a first direction; an active layer disposed on the vertical voltage line; an auxiliary gate line extending on the active layer along the first direction; a horizontal voltage line extending on the auxiliary gate line along a second direction intersecting the first direction and connected to the vertical voltage line; a first electrode disposed on the horizontal voltage line and connected to the active layer; a second electrode and a third electrode disposed parallel to the first electrode and connected to the horizontal voltage line; a first contact electrode disposed on the first electrode and connected to the first electrode; and a second contact electrode disposed on the first electrode and the second electrode and insulated from the first electrode to the third electrode.

[0025] Specific details of other embodiments are provided in the detailed description and accompanying drawings.

[0026] According to an embodiment of the display device, a plurality of light-emitting elements can be arranged between a first electrode and a second electrode. The first electrode receives a drive current from a transistor, and the second electrode receives a low-potential voltage. A contact electrode on the second electrode is insulated from both the first and second electrodes. The second electrode can shield the coupling capacitance between the gate line and the contact electrode. Accordingly, the second electrode can reduce the coupling capacitance between the gate line and the contact electrode, and the display device can eliminate black float problems or noise at black levels in the light-emitting elements.

[0027] The effects of the embodiments are not limited to those illustrated above, and more diverse effects are included in this specification. Attached Figure Description

[0028] Figure 1 This is a plan view showing a display device according to an embodiment.

[0029] Figure 2 This is a diagram illustrating a plurality of pixels and lines in a pixel region of a display device according to an embodiment.

[0030] Figure 3 This is a circuit diagram showing the pixels of a display device according to one embodiment.

[0031] Figure 4 This is a plan view showing a pixel region in a display device according to an embodiment.

[0032] Figure 5 It is shown Figure 4 A plan view of the metal layer and active layer in the display device.

[0033] Figure 6 It is shown Figure 4FIG. 1 is a plan view showing a display device of the present embodiment.

[0034] Figure 7 FIG. 2 is a plan view showing a display device of the present embodiment. Figure 4

[0035] Figure 8 FIG. 3 is a plan view showing a display device of the present embodiment. Figure 4

[0036] Figure 9 FIG. 4 is a plan view showing a display device of the present embodiment. Figure 4

[0037] Figure 10 FIG. 5 is a sectional view taken along line I-I' of FIG. 1. Figures 4 to 9

[0038] Figure 11 FIG. 6 is a sectional view taken along line II-II' of FIG. 1. Figures 4 to 9

[0039] Explanation of Reference Numerals

[0040] 100: display panel 200: display drive section

[0041] 210: flexible film 220: display drive circuit

[0042] 230: circuit board 240: timing control section

[0043] 250: power supply section SP1: first pixel

[0044] SP2: second pixel SP3: third pixel

[0045] DL1: first data line DL2: second data line

[0046] DL3: third data line VGL: vertical gate line

[0047] HGL: horizontal gate line BGL: auxiliary gate line

[0048] VDL: first voltage line VVSL: second vertical voltage line

[0049] HVSL: second horizontal voltage line SL: sense line

[0050] Cst: storage capacitor ST1: first transistor

[0051] ST2: second transistor ST3: third transistor

[0052] ​​​​​EL1: first light emitting element EL2: second light emitting element

[0053] RME1: first electrode RME2: second electrode

[0054] RME3: third electrode CTE1: first contact electrode

[0055] CTE2: second contact electrode DETAILED DESCRIPTION

[0056] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings. Figure 1 Advantages and features of the present application and methods of accomplishing the same can be understood more readily by reference to the following detailed description of embodiments and certain examples. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art, and no part of the specification should be construed as limiting the scope of the claims.

[0057] Reference to elements or layers "on" other elements or layers includes being located on the immediate surface of the other element or layer or intervening layers or elements. Throughout the specification, like reference numerals refer to like elements throughout the specification. The shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings for the purpose of describing embodiments are exemplary, and thus the present application is not limited to the matters illustrated in the drawings.

[0058] Although the terms first, second, etc. are used to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Thus, a first element discussed below could be termed a second element without departing from the spirit and scope of the present application.

[0059] The various features of the embodiments of the present application can be partially or wholly combined or integrated with each other, and can be technically linked or driven in various combinations, and each embodiment can be implemented independently of or in conjunction with the other embodiments.

[0060] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0061] Figure 1 is a plan view showing a display device according to an embodiment.

[0062] In the present specification, "upper", "top", "upper surface" refer to an upper direction with the display device as a reference, that is, the Z-axis direction, and "lower", "bottom", "lower surface" refer to a lower direction with the display device as a reference, that is, the opposite direction of the Z-axis direction. In addition, "left", "right", "up", "down" refer to directions when the display device is viewed from a planar surface. For example, "left" refers to the opposite direction of the X-axis direction, "right" refers to the X-axis direction, "up" refers to the Y-axis direction, and "down" refers to the opposite direction of the Y-axis direction.

[0063] Referring to Figure 1 The display device is a device for displaying a video or a still image, and can be used not only as a mobile phone, a smart phone, a tablet PC, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigator, and an ultra mobile PC (UMPC), but also as a display screen of a television, a notebook computer, a monitor, an advertisement board, and an Internet of Things (IOT) device.

[0064] The display device can include a display panel 100 and a display driving part 200.

[0065] The display panel 100 can be configured in a rectangular shape on a planar surface. For example, the display panel 100 can include a planar shape of a rectangle having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction). An edge corner where the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) meet can be formed as a right angle or smoothly formed in a manner having a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangle, and can be formed as other polygons, a circle, or an ellipse. For example, the display panel 100 can be formed flat, but is not necessarily limited thereto. As another example, the display panel 100 can be formed to be curved in a predetermined curvature.

[0066] The display panel 100 can include a display area DA and a non-display area NDA.

[0067] The display area DA is an area in which an image is displayed, and can be defined as a central area of the display panel 100. The display area DA can include a plurality of pixels SP formed in each pixel area where a plurality of data lines DL and a plurality of gate lines GL cross. The plurality of gate lines GL can include a plurality of vertical gate lines VGL and a plurality of horizontal gate lines HGL. For example, the plurality of vertical gate lines VGL can be connected to the display driving circuit 220 and extend in the second direction (Y-axis direction), and the plurality of horizontal gate lines HGL can be connected to any one of the plurality of vertical gate lines VGL and extend in the first direction (X-axis direction). Each of the plurality of pixels SP can include a first pixel SP1, a second pixel SP2, and a third pixel SP3. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be connected to at least one horizontal gate line HGL and at least one data line DL. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be defined as a minimum unit area in which light is output.

[0068] The plurality of data lines DL can extend in the second direction (Y-axis direction) and can be spaced apart from each other in the first direction (X-axis direction). The plurality of data lines DL can include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 can supply a data voltage to the first pixel SP1, the second pixel SP2, and the third pixel SP3, respectively.

[0069] The plurality of vertical gate lines VGL can extend in the second direction (Y-axis direction) and can be spaced apart from each other in the first direction (X-axis direction). The plurality of vertical gate lines VGL can be arranged in parallel with the plurality of data lines DL. The plurality of horizontal gate lines HGL can extend in the first direction (X-axis direction) and can be spaced apart from each other in the second direction (Y-axis direction). Each of the plurality of horizontal gate lines HGL can intersect the plurality of vertical gate lines VGL.

[0070] The connection relationship between the plurality of data lines DL, the plurality of vertical gate lines VGL, the plurality of horizontal gate lines HGL, and the plurality of pixels SP is not limited to the connection relationship shown in the drawing. The connection relationship between the plurality of data lines DL, the plurality of vertical gate lines VGL, the plurality of horizontal gate lines HGL, and the plurality of pixels SP can be designed to vary according to the number and arrangement of the plurality of pixels SP. Figure 2

[0071] The non-display area NDA can be defined as an area of the display panel 100 other than the display area DA. For example, the non-display area NDA can include a fan-out line connecting the data line DL or the vertical gate line VGL to the display driving circuit 220 and a pad (not shown) connected to the flexible film 210. ​

[0072] The display driving part 200 can be connected to the pad part provided at the non-display area NDA of the display panel 100, thereby displaying an image at the plurality of pixels SP based on image data supplied from a display driving system. The display driving part 200 can include a flexible film 210, a display driving circuit 220, a circuit board 230, a timing control part 240, and a power supply part 250.

[0073] The input terminal provided at one side of the flexible film 210 can be attached to the circuit board 230 through a film-attaching process, and the output terminal provided at the other side of the flexible film 210 can be attached to the pad part through the film-attaching process. For example, the flexible film 210 can be a flexible film (Flexible Film) such as a Tape Carrier Package (TCP), a Chip on Film (COF), or the like. The flexible film 210 can be bent toward the lower portion of the display panel 100 in order to reduce the bezel area of the display device.

[0074] The display driving circuit 220 can be mounted on the flexible film 210. For example, the display driving circuit 220 can be implemented using an integrated circuit (IC). The display driving circuit 220 can receive digital video data and a data control signal from the timing control part 240, and convert the digital video data into an analog data voltage according to the data control signal, and supply the same to the data line DL through a fan-out line. The display driving circuit 220 can generate a gate signal according to a gate control signal supplied from the timing control part 240, and supply the same to the plurality of vertical gate lines VGL in sequence according to a set order.

[0075] The circuit board 230 can support the timing control part 240 and the power supply part 250, and transfer signals and power between the components of the display driving part 200. For example, the circuit board 230 can supply a signal supplied from the timing control part 240 and a driving power supplied from the power supply part 250 to the display driving circuit 220 in order to display an image at each pixel. To this end, a signal transmission line and a plurality of power lines can be provided on the circuit board 230.

[0076] The timing control part 240 can be mounted on the circuit board 230 and receive image data and a timing synchronization signal supplied from a display driving system through a user connector provided on the circuit board 230. The timing control part 240 can sort the image data in a manner suitable for a pixel arrangement structure based on the timing synchronization signal, thereby generating digital video data, and can supply the generated digital video data to the display driving circuit 220. The timing control part 240 can generate a data control signal and a gate control signal based on the timing synchronization signal. The timing control part 240 can control a supply timing of a data voltage of the display driving circuit 220 based on the data control signal, and can control a supply timing of a gate signal of the display driving circuit 220 based on the gate control signal.

[0077] The power supply part 250 can be arranged on the circuit board 230 to supply a driving voltage to the display driving circuit 220 and the display panel 100. For example, the power supply part 250 can generate a first driving voltage and supply the first driving voltage to a driving voltage line, and can generate a second driving voltage and supply the second driving voltage to a low potential voltage line. The first driving voltage can correspond to a high potential voltage to drive a plurality of pixels SP, and the second driving voltage can correspond to a low potential voltage commonly supplied to the plurality of pixels SP.

[0078] Figure 2 FIG. 1 is a diagram illustrating a plurality of pixels and lines of a pixel region in a display apparatus according to an embodiment.

[0079] Referring to Figure 3 The plurality of pixels SP can include a first pixel SP1, a second pixel SP2, and a third pixel SP3. The pixel circuit of the first pixel SP1, the pixel circuit of the third pixel SP3, and the pixel circuit of the second pixel SP2 can be arranged in opposite directions along a second direction (Y-axis direction), but the order of the pixel circuits is not limited thereto.

[0080] The first voltage line VDL can extend along the second direction (Y-axis direction). The first voltage line VDL can be arranged on one side or the left side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The first voltage line VDL can be a driving voltage line to supply a driving voltage or a high potential voltage to the plurality of pixels SP. The first voltage line VDL can supply the driving voltage to the transistors of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0081] The gate line GL can include a vertical gate line VGL, a horizontal gate line HGL, and a auxiliary gate line BGL.

[0082] The nth vertical gate line VGL(n) (hereinafter, n is a positive integer) can extend in the second direction (Y-axis direction). The nth vertical gate line VGL(n) can be disposed on one side or left side of the first voltage line VDL. The nth vertical gate line VGL(n) can be connected between the display driving circuit 220 and the nth horizontal gate line HGL(n). Each of the plurality of vertical gate lines VGL can cross the plurality of horizontal gate lines HGL. The nth vertical gate line VGL(n) can be insulated from each other with respect to the horizontal gate lines other than the nth horizontal gate line HGL(n). The nth vertical gate line VGL(n) can supply the nth gate signal received from the display driving circuit 220 to the nth horizontal gate line HGL(n).

[0083] The nth horizontal gate line HGL(n) can extend in the first direction (X-axis direction). The nth horizontal gate line HGL(n) can be disposed on the upper side of the pixel circuit of the first pixel SP1. The nth horizontal gate line HGL(n) can be connected between the nth vertical gate line VGL(n) and the auxiliary gate line BGL. The nth horizontal gate line HGL(n) can supply the nth gate signal received from the nth vertical gate line VGL(n) to the auxiliary gate line BGL.

[0084] The nth+1 vertical gate line VGL(n+1) can extend in the second direction (Y-axis direction). The nth+1 vertical gate line VGL(n+1) can be disposed on one side or left side of the nth vertical gate line VGL(n). The nth+1 vertical gate line VGL(n+1) can be insulated from each other with respect to the nth horizontal gate line HGL(n). The nth+1 vertical gate line VGL(n+1) can supply the nth+1 gate signal to the plurality of pixels SP after the nth vertical gate line VGL(n) supplies the nth gate signal.

[0085] The second voltage line VSL can include a second vertical voltage line VVSL and a second horizontal voltage line HVSL. The second voltage line VSL can be a low potential voltage line that supplies a low potential voltage to the plurality of pixels SP.

[0086] The second vertical voltage line VVSL can extend in the second direction (Y-axis direction). The second vertical voltage line VVSL can be disposed on one side or left side of the nth+1 vertical gate line VGL(n+1). The second vertical voltage line VVSL can be connected between the power supply part 250 and the second horizontal voltage line HVSL. The second vertical voltage line VVSL can supply a low potential voltage supplied from the power supply part 250 to the second horizontal voltage line HVSL.

[0087] The second horizontal voltage line HVSL can extend in the first direction (X-axis direction). The second horizontal voltage line HVSL can be disposed at the lower side of the pixel circuit of the second pixel SP2. The second horizontal voltage line HVSL can supply a low potential voltage received from the second vertical voltage line VVSL to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0088] The auxiliary gate line BGL can extend in the opposite direction of the second direction (Y-axis direction) from the nth horizontal gate line HGL(n). The auxiliary gate line BGL can be disposed at the other side or right side of the pixel circuit of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The auxiliary gate line BGL can supply the nth gate signal received from the nth horizontal gate line HGL(n) to the pixel circuit of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0089] The plurality of data lines DL can extend in the second direction (Y-axis direction). The plurality of data lines DL can supply a data voltage to the plurality of pixels SP. The plurality of data lines DL can include a first data line DL1, a second data line DL2, and a third data line DL3.

[0090] The first data line DL1 can extend in the second direction (Y-axis direction). The first data line DL1 can be disposed at the other side or right side of the auxiliary gate line BGL. The first data line DL1 can supply a data voltage received from the display driving circuit 220 to the pixel circuit of the first pixel SP1.

[0091] The second data line DL2 can extend in the second direction (Y-axis direction). The second data line DL2 can be disposed at the other side or right side of the first data line DL1. The second data line DL2 can supply a data voltage received from the display driving circuit 220 to the pixel circuit of the second pixel SP2.

[0092] The third data line DL3 can extend in the second direction (Y-axis direction). The third data line DL3 can be disposed at the other side or right side of the second data line DL2. The third data line DL3 can supply a data voltage received from the display driving circuit 220 to the pixel circuit of the third pixel SP3.

[0093] The sensing line SL can extend in the second direction (Y-axis direction). The sensing line SL can be disposed at the other side or right side of the third data line DL3. The sensing line SL can supply an initialization voltage received from the display driving circuit 220 to the pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The sensing line SL can receive a sensing signal from the pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 and supply the sensing signal to the display driving circuit 220.

[0094] Figure 3 is a circuit diagram showing a pixel of a display device according to an embodiment.

[0095] Referring to Figure 4 Each of the plurality of pixels SP can be connected to the gate line GL, the data line DL, the first voltage line VDL, the second voltage line VSL, and the sensing line SL.

[0096] Each of the plurality of pixels SP can include a plurality of switching elements, a storage capacitor Cst, and a plurality of light emitting elements EL. The switching elements can include a first transistor ST1, a second transistor ST2, and a third transistor ST3.

[0097] The first transistor ST1 can include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 can be connected to the first node N1, the drain electrode can be connected to the first voltage line VDL, and the source electrode can be connected to the second node N2. The first transistor ST1 can control a current (or, driving current) between the source and the drain according to a data voltage applied to the gate electrode.

[0098] The plurality of light emitting elements EL can include a first light emitting element EL1 and a second light emitting element EL2. The first light emitting element EL1 and the second light emitting element EL2 can be connected in series. The first light emitting element EL1 and the second light emitting element EL2 can emit light by receiving a driving current. An amount of light emission or brightness of the light emitting element EL can be proportional to a size of the driving current. The light emitting element EL can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode.

[0099] The first electrode of the first light emitting element EL1 can be connected to the second node N2, and the second electrode of the first light emitting element EL1 can be connected to the third node N3. The first electrode of the first light emitting element EL1 can be connected to the source electrode of the first transistor ST1, the source electrode of the third transistor ST3, and the second capacitor electrode of the storage capacitor Cst through the second node N2. The second electrode of the first light emitting element EL1 can be connected to the first electrode of the second light emitting element EL2 through the third node N3.

[0100] The first electrode of the second light emitting element EL2 can be connected to the third node N3, and the second electrode of the second light emitting element EL2 can be connected to the second voltage line VSL. The first electrode of the second light emitting element EL2 can be connected to the second electrode of the first light emitting element EL1 through the third node N3.

[0101] The second transistor ST2 can be turned on by a gate signal of the gate line GL, thereby connecting the data line DL with the first node N1 which is a gate electrode of the first transistor ST1. The second transistor ST2 can be turned on based on the gate signal, thereby supplying the data voltage to the first node N1. The gate electrode of the second transistor ST2 can be connected to the gate line GL, the drain electrode can be connected to the data line DL, and the source electrode can be connected to the first node N1. The source electrode of the second transistor ST2 can be connected to the gate electrode of the first transistor ST1 and the first capacitor electrode of the storage capacitor Cst through the first node N1.

[0102] The third transistor ST3 can be turned on by a gate signal of the gate line GL, thereby connecting the sensing line SL with the second node N2 which is a source electrode of the first transistor ST1. The third transistor ST3 can be turned on based on the gate signal, thereby supplying the initialization voltage to the second node N2. The gate electrode of the third transistor ST3 can be connected to the gate line GL, the drain electrode can be connected to the sensing line SL, and the source electrode can be connected to the second node N2. The source electrode of the third transistor ST3 can be connected to the source electrode of the first transistor ST1, the second capacitor electrode of the storage capacitor Cst, and the first electrode of the first light emitting element EL1 through the second node N2.

[0103] Figure 5 is a plan view showing a pixel region in the display device according to an embodiment. Figure 4 is a plan view showing Figure 6 a plan view showing the metal layer and the active layer in the display device of Figure 4 is a plan view showing Figure 7 a plan view showing the metal layer, the active layer, and the gate layer in the display device of Figure 4 is a plan view showing Figure 8 a plan view showing the metal layer, the active layer, and the source-drain layer in the display device of Figure 4 is a plan view showing Figure 9 a plan view showing the source-drain layer, the electrode layer, and the anode layer in the display device of Figure 4 is a plan view showing Figure 10 a plan view showing the electrode layer and the anode layer in the display device of Figures 4 to 9 is a cross-sectional view taken along the I-I' line of Figure 11 is a cross-sectional view taken along the II-II' line of Figures 4 to 9 is a cross-sectional view taken along the II-II' line of Figure 10 In the display device of Figure 11 and Figures 4 to 11 , the metal layer BML, the buffer layer BF, the active layer ACTL, the gate insulating film GI, the gate layer GTL, the first insulating film IL1, the source-drain layer SDL, the second insulating film IL2, the bank BNK, the electrode layer RMTL, the first protective layer PAS1, and the anode layer ANDL can be sequentially stacked on the substrate SUB.

[0104] Referring to Figures 4 to 11 The display panel 100 can include a plurality of pixel areas SPA. Each of the plurality of pixel areas SPA can include a first pixel SP1, a second pixel SP2, and a third pixel SP3. The pixel circuit of the first pixel SP1, the pixel circuit of the third pixel SP3, and the pixel circuit of the second pixel SP2 can be arranged in opposite directions of a second direction (Y-axis direction).

[0105] The first voltage line VDL can be disposed in the metal layer BML. The first voltage line VDL can be disposed on one side or left side of the pixel circuit of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The first voltage line VDL can overlap the fifth auxiliary electrode AUE5 of the source-drain layer SDL in a thickness direction (Z-axis direction) and be connected to the fifth auxiliary electrode AUE5 through the twenty-ninth contact hole CNT29. Accordingly, the first voltage line VDL can be connected to the fifth auxiliary electrode AUE5, thereby reducing line resistance.

[0106] The first voltage line VDL can be connected to the drain electrode DE1 of the first transistor ST1 of the first pixel SP1 through the first contact hole CNT1, connected to the drain electrode DE1 of the first transistor ST1 of the second pixel SP2 through the seventh contact hole CNT7, and connected to the drain electrode DE1 of the first transistor ST1 of the third pixel SP3 through the thirteenth contact hole CNT13. Accordingly, the first voltage line VDL can supply a driving voltage or a high potential voltage to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0107] The nth vertical gate line VGL(n) can be disposed in the metal layer BML. The nth vertical gate line VGL(n) can be disposed on one side or left side of the first voltage line VDL. The nth vertical gate line VGL(n) can overlap the first auxiliary electrode AUE1 of the gate layer GTL in a thickness direction (Z-axis direction) and can be connected to the first auxiliary electrode AUE1. The nth vertical gate line VGL(n) can overlap the third auxiliary electrode AUE3 of the source-drain layer SDL in the thickness direction (Z-axis direction) and be connected to the third auxiliary electrode AUE3 through the twenty-seventh contact hole CNT27. Accordingly, the nth vertical gate line VGL(n) can be connected to the first auxiliary electrode AUE1 and the third auxiliary electrode AUE3, thereby reducing line resistance.

[0108] The nth horizontal gate line HGL(n) can be disposed in the source-drain layer SDL. The nth horizontal gate line HGL(n) can be disposed on the upper side of the pixel circuit of the first pixel SP1. The nth horizontal gate line HGL(n) can be connected between the nth vertical gate line VGL(n) and the auxiliary gate line BGL. The nth horizontal gate line HGL(n) can supply the nth gate signal received from the nth vertical gate line VGL(n) to the auxiliary gate line BGL.

[0109] The auxiliary gate line BGL can be disposed in the gate layer GTL. The auxiliary gate line BGL can be disposed on the other side or right side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The auxiliary gate line BGL can supply the nth gate signal received from the nth horizontal gate line HGL(n) to the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0110] The nth+1 vertical gate line VGL(n+1) can be disposed in the metal layer BML. The nth+1 vertical gate line VGL(n+1) can be disposed on one side or left side of the nth vertical gate line VGL(n). The nth+1 vertical gate line VGL(n+1) can overlap the second auxiliary electrode AUE2 of the gate layer GTL in the thickness direction (Z-axis direction) and can be connected to the second auxiliary electrode AUE2. The nth+1 vertical gate line VGL(n+1) can overlap the fourth auxiliary electrode AUE4 of the source-drain layer SDL in the thickness direction (Z-axis direction) and can be connected to the fourth auxiliary electrode AUE4 through the twenty-eighth contact hole CNT28. Accordingly, the nth+1 vertical gate line VGL(n+1) can be connected to the second auxiliary electrode AUE2 and the fourth auxiliary electrode AUE4, thereby reducing line resistance.

[0111] The second voltage line VSL can include a second vertical voltage line VVSL and a second horizontal voltage line HVSL. The second voltage line VSL can be a low potential voltage line that supplies a low potential voltage to the plurality of pixels SP.

[0112] The second vertical voltage line VVSL can be disposed in the metal layer BML. The second vertical voltage line VVSL can be disposed on one side or left side of the nth+1 vertical gate line VGL(n+1). The second vertical voltage line VVSL can overlap the tenth connection electrode BE10 of the source-drain layer SDL in the thickness direction (Z-axis direction) and can be connected to the tenth connection electrode BE10 through the nineteenth contact hole CNT19. Accordingly, the second vertical voltage line VVSL can be connected to the tenth connection electrode BE10, thereby reducing line resistance.

[0113] A second horizontal voltage line HVSL can be disposed in the source-drain layer SDL. The second horizontal voltage line HVSL can extend in the first direction (X-axis direction) from the lower side of the tenth connection electrode BE10. The second horizontal voltage line HVSL can be integrally formed with the tenth connection electrode BE10, but is not limited thereto. The second horizontal voltage line HVSL can supply a low potential voltage received from the second vertical voltage line VVSL to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0114] The second horizontal voltage line HVSL can be connected to the third electrode RME3 of the first pixel SP1 disposed in the electrode layer RMTL through the thirtieth contact hole CNT30. Accordingly, the second horizontal voltage line HVSL can supply a low potential voltage to the third electrode RME3 of the first pixel SP1.

[0115] The second horizontal voltage line HVSL can be connected to the third electrode RME3 of the second pixel SP2 disposed in the electrode layer RMTL through the thirtieth contact hole CNT30. The third electrode RME3 of the second pixel SP2 can be connected to the second electrode RME2 of the first pixel SP1 through the connection part CRM. The second electrode RME2 of the first pixel SP1, the connection part CRM, and the third electrode RME3 of the second pixel SP2 can be integrally formed, but are not limited thereto. Accordingly, the second horizontal voltage line HVSL can supply a low potential voltage to the second electrode RME2 of the first pixel SP1 and the third electrode RME3 of the second pixel SP2.

[0116] The second horizontal voltage line HVSL can be connected to the third electrode RME3 of the third pixel SP3 disposed in the electrode layer RMTL through the thirtieth contact hole CNT30. The third electrode RME3 of the third pixel SP3 can be connected to the second electrode RME2 of the second pixel SP2 through the connection part CRM. The second electrode RME2 of the second pixel SP2, the connection part CRM, and the third electrode RME3 of the third pixel SP3 can be integrally formed, but are not limited thereto. Accordingly, the second horizontal voltage line HVSL can supply a low potential voltage to the second electrode RME2 of the second pixel SP2 and the third electrode RME3 of the third pixel SP3.

[0117] The first data line DL1 can be disposed in the metal layer BML. The first data line DL1 can be disposed on the other side or right side of the auxiliary gate line BGL. The first data line DL1 can be connected to the second connection electrode BE2 of the source-drain layer SDL through the twenty-second contact hole CNT22, and the second connection electrode BE2 can be connected to the drain electrode DE2 of the second transistor ST2 of the first pixel SP1 through the third contact hole CNT3. Accordingly, the first data line DL1 can supply a data voltage to the second transistor ST2 of the first pixel SP1.

[0118] The second data line DL2 can be disposed in the metal layer BML. The second data line DL2 can be disposed on the other side or right side of the first data line DL1. The second data line DL2 can be connected to the fifth connection electrode BE5 of the source-drain layer SDL through the twenty-fourth contact hole CNT24, and the fifth connection electrode BE5 can be connected to the drain electrode DE2 of the second transistor ST2 of the second pixel SP2 through the ninth contact hole CNT9. Accordingly, the second data line DL2 can supply a data voltage to the second transistor ST2 of the second pixel SP2.

[0119] The third data line DL3 can be disposed in the metal layer BML. The third data line DL3 can be disposed on the other side or right side of the second data line DL2. The third data line DL3 can be connected to the eighth connection electrode BE8 of the source-drain layer SDL through the twenty-sixth contact hole CNT26, and the eighth connection electrode BE8 can be connected to the drain electrode DE2 of the second transistor ST2 of the third pixel SP3 through the fifteenth contact hole CNT15. Accordingly, the third data line DL3 can supply a data voltage to the second transistor ST2 of the third pixel SP3.

[0120] The sensing line SL can be disposed in the metal layer BML. The sensing line SL can be disposed on the other side or right side of the third data line DL3. The sensing line SL can be connected to the eleventh connection electrode BE11 of the source-drain layer SDL through a plurality of twentieth contact holes CNT20. The eleventh connection electrode BE11 can be connected to the drain electrode DE3 of the third transistor ST3 of the first pixel SP1 through the fifth contact hole CNT5, to the drain electrode DE3 of the third transistor ST3 of the second pixel SP2 through the eleventh contact hole CNT11, and to the drain electrode DE3 of the third transistor ST3 of the third pixel SP3 through the seventeenth contact hole CNT17. Accordingly, the sensing line SL can supply an initialization voltage to the third transistor ST3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3, and can receive a sensing signal from the third transistor ST3.

[0121] The pixel circuit of the first pixel SP1 can include the first transistor ST1, the second transistor ST2, and the third transistor ST3. The first transistor ST1 of the first pixel SP1 can include an active region ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active region ACT1 of the first transistor ST1 can be disposed in the active layer ACTL, and can overlap the gate electrode GE1 of the first transistor ST1 in the thickness direction (Z-axis direction).

[0122] The gate electrode GE1 of the first transistor ST1 can be arranged at the gate layer GTL. The gate electrode GE1 of the first transistor ST1 can be part of a first capacitor electrode CPE1 of the storage capacitor Cst. The first capacitor electrode CPE1 can be connected to a third connection electrode BE3 of the source-drain layer SDL, and the third connection electrode BE3 can be connected to the source electrode SE2 of the second transistor ST2 through a fourth contact hole CNT4.

[0123] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 can be conductorized by heat-treating the active layer ACTL. The drain electrode DE1 of the first transistor ST1 can be connected to a first voltage line VDL of the metal layer BML through a first contact hole CNT1. The drain electrode DE1 of the first transistor ST1 can receive a driving voltage from the first voltage line VDL.

[0124] The source electrode SE1 of the first transistor ST1 can be connected to a first connection electrode BE1 of the source-drain layer SDL through a second contact hole CNT2. The first connection electrode BE1 can be connected to a second capacitor electrode CPE2 of the metal layer BML through a twenty-first contact hole CNT21. Accordingly, the storage capacitor Cst can be formed doubly between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection electrode BE1.

[0125] The first connection electrode BE1 can be connected to the source electrode SE3 of the third transistor ST3 through a sixth contact hole CNT6. The first connection electrode BE1 can be connected to a first electrode RME1 of the electrode layer RMTL through a thirty-first contact hole CNT31.

[0126] The second transistor ST2 of the first pixel SP1 can include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 can be arranged at the active layer ACTL and can overlap the gate electrode GE2 of the second transistor ST2 in a thickness direction (Z-axis direction).

[0127] The gate electrode GE2 of the second transistor ST2 can be arranged at the gate layer GTL. The gate electrode GE2 of the second transistor ST2 can be part of an auxiliary gate line BGL.

[0128] The drain electrode DE2 of the second transistor ST2 can be connected to the first data line DL1 through a third contact hole CNT3. The drain electrode DE2 of the second transistor ST2 can receive a data voltage of the first pixel SP1 from the first data line DL1.

[0129] The source electrode SE2 of the second transistor ST2 can be connected to the third connection electrode BE3 of the source-drain layer SDL through the fourth contact hole CNT4. The third connection electrode BE3 can be connected to the first capacitor electrode CPE1, and thus to the gate electrode GE1 of the first transistor ST1.

[0130] The third transistor ST3 of the first pixel SP1 can include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 can be disposed in the active layer ACTL, and can overlap the gate electrode GE3 of the third transistor ST3 in the thickness direction (Z-axis direction).

[0131] The gate electrode GE3 of the third transistor ST3 can be disposed in the gate layer GTL. The gate electrode GE3 of the third transistor ST3 can be part of the auxiliary gate line BGL.

[0132] The drain electrode DE3 of the third transistor ST3 can be connected to the eleventh connection electrode BE11 of the source-drain layer SDL through the fifth contact hole CNT5. The eleventh connection electrode BE11 can be connected to the sensing line SL of the metal layer BML through a plurality of twentieth contact holes CNT20. The drain electrode DE3 of the third transistor ST3 can receive an initialization voltage from the sensing line SL. The drain electrode DE3 of the third transistor ST3 can supply a sensing signal to the sensing line SL.

[0133] The source electrode SE3 of the third transistor ST3 can be connected to the first connection electrode BE1 of the source-drain layer SDL through the sixth contact hole CNT6. The first connection electrode BE1 can be connected to the source electrode SE1 of the first transistor ST1 through the second contact hole CNT2, to the second capacitor electrode CPE2 of the metal layer BML through the twenty-first contact hole CNT21, and to the first electrode RME1 of the electrode layer RMTL through the thirty-first contact hole CNT31.

[0134] The pixel circuit of the second pixel SP2 can include the first transistor ST1, the second transistor ST2, and the third transistor ST3. The first transistor ST1 of the second pixel SP2 can include an active region ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active region ACT1 of the first transistor ST1 can be disposed in the active layer ACTL, and can overlap the gate electrode GE1 of the first transistor ST1 in the thickness direction (Z-axis direction).

[0135] The gate electrode GE1 of the first transistor ST1 can be arranged in the gate layer GTL. The gate electrode GE1 of the first transistor ST1 can be part of a first capacitor electrode CPE1 of the storage capacitor Cst. The first capacitor electrode CPE1 can be connected to a sixth connection electrode BE6 of the source-drain layer SDL, and the sixth connection electrode BE6 can be connected to the source electrode SE2 of the second transistor ST2 through a tenth contact hole CNT10.

[0136] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 can be conductorized by heat-treating the active layer ACTL. The drain electrode DE1 of the first transistor ST1 can be connected to a first voltage line VDL of the metal layer BML through a seventh contact hole CNT7. The drain electrode DE1 of the first transistor ST1 can receive a drive voltage from the first voltage line VDL.

[0137] The source electrode SE1 of the first transistor ST1 can be connected to a fourth connection electrode BE4 of the source-drain layer SDL through an eighth contact hole CNT8. The fourth connection electrode BE4 can be connected to a second capacitor electrode CPE2 of the metal layer BML through a twenty-third contact hole CNT23. According to this, the storage capacitor Cst can be formed doubly between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the fourth connection electrode BE4.

[0138] The fourth connection electrode BE4 can be connected to the source electrode SE3 of the third transistor ST3 through a twelfth contact hole CNT12. The fourth connection electrode BE4 can be connected to a first electrode RME1 of the electrode layer RMTL through a thirty-second contact hole CNT32.

[0139] The second transistor ST2 of the second pixel SP2 can include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 can be arranged in the active layer ACTL and can overlap the gate electrode GE2 of the second transistor ST2 in the thickness direction (Z-axis direction).

[0140] The gate electrode GE2 of the second transistor ST2 can be arranged in the gate layer GTL. The gate electrode GE2 of the second transistor ST2 can be part of an auxiliary gate line BGL.

[0141] The drain electrode DE2 of the second transistor ST2 can be connected to the second data line DL2 through a ninth contact hole CNT9. The drain electrode DE2 of the second transistor ST2 can receive a data voltage of the second pixel SP2 from the second data line DL2.

[0142] The source electrode SE2 of the second transistor ST2 can be connected to the sixth connection electrode BE6 of the source-drain layer SDL through the tenth contact hole CNT10. The sixth connection electrode BE6 can be connected to the first capacitor electrode CPE1, and thus to the gate electrode GE1 of the first transistor ST1.

[0143] The third transistor ST3 of the second pixel SP2 can include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 can be disposed in the active layer ACTL, and can overlap the gate electrode GE3 of the third transistor ST3 in the thickness direction (Z-axis direction).

[0144] The gate electrode GE3 of the third transistor ST3 can be disposed in the gate layer GTL. The gate electrode GE3 of the third transistor ST3 can be part of the auxiliary gate line BGL.

[0145] The drain electrode DE3 of the third transistor ST3 can be connected to the eleventh connection electrode BE11 of the source-drain layer SDL through the eleventh contact hole CNT11. The eleventh connection electrode BE11 can be connected to the sensing line SL of the metal layer BML through a plurality of twentieth contact holes CNT20. The drain electrode DE3 of the third transistor ST3 can receive an initialization voltage from the sensing line SL. The drain electrode DE3 of the third transistor ST3 can supply a sensing signal to the sensing line SL.

[0146] The source electrode SE3 of the third transistor ST3 can be connected to the fourth connection electrode BE4 of the source-drain layer SDL through the twelfth contact hole CNT12. The fourth connection electrode BE4 can be connected to the source electrode SE1 of the first transistor ST1 through the eighth contact hole CNT8, to the second capacitor electrode CPE2 of the metal layer BML through the twenty-third contact hole CNT23, and to the first electrode RME1 of the electrode layer RMTL through the thirty-second contact hole CNT32.

[0147] The pixel circuit of the third pixel SP3 can include the first transistor ST1, the second transistor ST2, and the third transistor ST3. The first transistor ST1 of the third pixel SP3 can include an active region ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active region ACT1 of the first transistor ST1 can be disposed in the active layer ACTL, and can overlap the gate electrode GE1 of the first transistor ST1 in the thickness direction (Z-axis direction).

[0148] The gate electrode GE1 of the first transistor ST1 can be arranged at the gate layer GTL. The gate electrode GE1 of the first transistor ST1 can be part of a first capacitor electrode CPE1 of the storage capacitor Cst. The first capacitor electrode CPE1 can be connected to a ninth connection electrode BE9 of the source-drain layer SDL, and the ninth connection electrode BE9 can be connected to the source electrode SE2 of the second transistor ST2 through a sixteenth contact hole CNT16.

[0149] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 can be conductorized by heat-treating the active layer ACTL. The drain electrode DE1 of the first transistor ST1 can be connected to a first voltage line VDL of the metal layer BML through a thirteenth contact hole CNT13. The drain electrode DE1 of the first transistor ST1 can receive a drive voltage from the first voltage line VDL.

[0150] The source electrode SE1 of the first transistor ST1 can be connected to a seventh connection electrode BE7 of the source-drain layer SDL through a fourteenth contact hole CNT14. The seventh connection electrode BE7 can be connected to a second capacitor electrode CPE2 of the metal layer BML through a twenty-fifth contact hole CNT25. According to this, the storage capacitor Cst can be formed doubly between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the seventh connection electrode BE7.

[0151] The seventh connection electrode BE7 can be connected to the source electrode SE3 of the third transistor ST3 through an eighteenth contact hole CNT18. The seventh connection electrode BE7 can be connected to a first electrode RME1 of the electrode layer RMTL through a thirty-third contact hole CNT33.

[0152] The second transistor ST2 of the third pixel SP3 can include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 can be arranged at the active layer ACTL and can overlap the gate electrode GE2 of the second transistor ST2 in the thickness direction (Z-axis direction).

[0153] The gate electrode GE2 of the second transistor ST2 can be arranged at the gate layer GTL. The gate electrode GE2 of the second transistor ST2 can be part of the auxiliary gate line BGL.

[0154] The drain electrode DE2 of the second transistor ST2 can be connected to the third data line DL3 through a fifteenth contact hole CNT15. The drain electrode DE2 of the second transistor ST2 can receive a data voltage of the third pixel SP3 from the third data line DL3.

[0155] The source electrode SE2 of the second transistor ST2 can be connected to the ninth connection electrode BE9 of the source-drain layer SDL through the sixteenth contact hole CNT16. The ninth connection electrode BE9 can be connected to the first capacitor electrode CPE1, and thus to the gate electrode GE1 of the first transistor ST1.

[0156] The third transistor ST3 of the third pixel SP3 can include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 can be disposed in the active layer ACTL, and can overlap the gate electrode GE3 of the third transistor ST3 in the thickness direction (Z-axis direction).

[0157] The gate electrode GE3 of the third transistor ST3 can be disposed in the gate layer GTL. The gate electrode GE3 of the third transistor ST3 can be part of the auxiliary gate line BGL.

[0158] The drain electrode DE3 of the third transistor ST3 can be connected to the eleventh connection electrode BE11 of the source-drain layer SDL through the seventeenth contact hole CNT17. The eleventh connection electrode BE11 can be connected to the sensing line SL of the metal layer BML through a plurality of twentieth contact holes CNT20. The drain electrode DE3 of the third transistor ST3 can receive an initialization voltage from the sensing line SL. The drain electrode DE3 of the third transistor ST3 can supply a sensing signal to the sensing line SL.

[0159] The source electrode SE3 of the third transistor ST3 can be connected to the seventh connection electrode BE7 of the source-drain layer SDL through the eighteenth contact hole CNT18. The seventh connection electrode BE7 can be connected to the source electrode SE1 of the first transistor ST1 through the fourteenth contact hole CNT14, to the second capacitor electrode CPE2 of the metal layer BML through the twenty-fifth contact hole CNT25, and to the first electrode RME1 of the electrode layer RMTL through the thirty-third contact hole CNT33.

[0160] The first electrode RME1, the second electrode RME2, and the third electrode RME3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be arranged in the electrode layer RMTL. The first electrode RME1, the second electrode RME2, and the third electrode RME3 of the first pixel SP1 can be arranged at the left side of the pixel area SPA, the first electrode RME1, the second electrode RME2, and the third electrode RME3 of the second pixel SP2 can be arranged at the center of the pixel area SPA, and the first electrode RME1, the second electrode RME2, and the third electrode RME3 of the third pixel SP3 can be arranged at the right side of the pixel area SPA, but are not limited thereto. The first electrode RME1, the second electrode RME2, and the third electrode RME3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can extend in the second direction (Y-axis direction) and can be spaced apart from each other in the first direction (X-axis direction). The second electrode RME2 can be arranged at the right side of the first electrode RME1, and the third electrode RME3 can be arranged at the left side of the first electrode RME1, but are not limited thereto.

[0161] One end of the first electrode RME1 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be adjacent to the nth horizontal gate line HGL(n) on the plane and can be cut off by the cut portion CBA. The other end of the first electrode RME1 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be adjacent to the second horizontal voltage line HVSL on the plane and can be cut off by the cut portion CBA.

[0162] One end of the second electrode RME2 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be adjacent to the nth horizontal gate line HGL(n) on the plane and can be cut off by the cut portion CBA.

[0163] A plurality of first light emitting elements EL1 can be arranged between the first electrode RME1 and the second electrode RME2. Each of the first electrode RME1 and the second electrode RME2 can receive an arrangement signal before one end and the other end of the first electrode RME1 and one end of the second electrode RME2 are cut off by the cut portion CBA, and an electric field can be formed between the first electrode RME1 and the second electrode RME2. For example, the plurality of first light emitting elements EL1 can be jetted onto the first electrode RME1 and the second electrode RME2 by an inkjet printing process, and the plurality of first light emitting elements EL1 dispersed in the ink can be arranged by receiving a dielectrophoresis force through the electric field formed between the first electrode RME1 and the second electrode RME2.

[0164] A plurality of second light emitting elements EL2( Figure 10A plurality of second light emitting elements EL2 (not shown) can be arranged between the first electrode RME1 and the third electrode RME3. Each of the first electrode RME1 and the third electrode RME3 can receive an alignment signal before the one end and the other end of the first electrode RME1 are cut off by the cut portion CBA, and an electric field can be formed between the first electrode RME1 and the third electrode RME3. For example, a plurality of second light emitting elements EL2 can be jetted onto the first electrode RME1 and the third electrode RME3 by an inkjet printing process, and the plurality of second light emitting elements EL2 dispersed in the ink can be aligned by receiving a dielectrophoresis force through the electric field formed between the first electrode RME1 and the third electrode RME3.

[0165] The first electrode RME1 of the first pixel SP1 can be connected to the first connection electrode BE1 of the source-drain layer SDL through the thirty-first contact hole CNT31. The first electrode RME1 can receive a driving current through the first transistor ST1 from the first connection electrode BE1. The first electrode RME1 can supply the driving current to the plurality of first light emitting elements EL1 of the first pixel SP1.

[0166] The second electrode RME2 of the first pixel SP1 can be connected to the third electrode RME3 of the second pixel SP2 through the connection portion CRM. The second electrode RME2 of the first pixel SP1 can be connected to the second horizontal voltage line HVSL of the source-drain layer SDL through the thirtieth contact hole CNT30. Accordingly, the second electrode RME2 of the first pixel SP1 can receive a low potential voltage from the second horizontal voltage line HVSL.

[0167] The third electrode RME3 of the first pixel SP1 can be connected to the second horizontal voltage line HVSL of the source-drain layer SDL through the thirtieth contact hole CNT30. Accordingly, the third electrode RME3 of the first pixel SP1 can receive a low potential voltage from the second horizontal voltage line HVSL.

[0168] In Figure 11In the second pixel SP2, the first electrode RME1 of the second pixel SP2 can be connected to the fourth connection electrode BE4 of the source-drain layer SDL through the thirty-second contact hole CNT32. The first electrode RME1 can receive the driving current from the fourth connection electrode BE4 through the first transistor ST1. The first electrode RME1 can supply the driving current to the plurality of first light emitting elements EL1 of the second pixel SP2.

[0169] The first electrode RME1 of the second pixel SP2 can be connected to the fourth connection electrode BE4 of the source-drain layer SDL through the thirty-second contact hole CNT32. The first electrode RME1 can receive the driving current from the fourth connection electrode BE4 through the first transistor ST1. The first electrode RME1 can supply the driving current to the plurality of first light emitting elements EL1 of the second pixel SP2.

[0170] The second electrode RME2 of the second pixel SP2 can be connected to the third electrode RME3 of the third pixel SP3 through the connection part CRM. The second electrode RME2 of the second pixel SP2 can be connected to the second horizontal voltage line HVSL of the source-drain layer SDL through the thirtieth contact hole CNT30. Accordingly, the second electrode RME2 of the second pixel SP2 can receive the low potential voltage from the second horizontal voltage line HVSL.

[0171] The third electrode RME3 of the second pixel SP2 can be connected to the second horizontal voltage line HVSL of the source-drain layer SDL through the thirtieth contact hole CNT30. Accordingly, the third electrode RME3 of the second pixel SP2 can receive the low potential voltage from the second horizontal voltage line HVSL.

[0172] In Figure 3The second electrode RME2 and the third electrode RME3 of the second pixel SP2 can be connected to the second horizontal voltage line HVSL to receive a low potential voltage. The second contact electrode CTE2 of the second pixel SP2 can be insulated from the first electrode RME1, the second electrode RME2, and the third electrode RME3, and the second electrode RME2 and the third electrode RME3 can shield a coupling capacitance between the gate layer GTL and the anode layer ANDL. Accordingly, the second electrode RME2 and the third electrode RME3 can reduce a second capacitance CAP2 between the auxiliary gate line BGL of the gate layer GTL and the second contact electrode CTE2. Accordingly, the display device can reduce a coupling capacitance between the auxiliary gate line BGL supplying the nth gate signal and the second contact electrode CTE2, thereby removing a black floating problem of the light emitting element EL or noise at a black level.

[0173] The first electrode RME1 of the third pixel SP3 can be connected to the seventh connection electrode BE7 of the source-drain layer SDL through the thirty-third contact hole CNT33. The first electrode RME1 can receive a driving current through the first transistor ST1 from the seventh connection electrode BE7. The first electrode RME1 can supply the driving current to the plurality of first light emitting elements EL1 of the third pixel SP3.

[0174] The second electrode RME2 of the third pixel SP3 can be connected to the second horizontal voltage line HVSL of the source-drain layer SDL. Accordingly, the second electrode RME2 of the third pixel SP3 can receive a low potential voltage from the second horizontal voltage line HVSL.

[0175] The third electrode RME3 of the third pixel SP3 can be connected to the second horizontal voltage line HVSL of the source-drain layer SDL through the thirtieth contact hole CNT30. Accordingly, the third electrode RME3 of the third pixel SP3 can receive a low potential voltage from the second horizontal voltage line HVSL.

[0176] The first contact electrode CTE1 and the second contact electrode CTE2 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can be disposed in the anode layer ANDL. The first contact electrode CTE1 can be disposed on the first electrode RME1 to be connected to the first electrode RME1. The first contact electrode CTE1 can be connected between the first electrode RME1 and the plurality of first light emitting elements EL1. The first contact electrode CTE1 can correspond to an anode electrode of the plurality of first light emitting elements EL1, but is not limited thereto.

[0177] The second contact electrode CTE2 can be disposed on the first and second electrodes RME1 and RME2 and insulated from the first, second, and third electrodes RME1, RME2, and RME3. The second contact electrode CTE2 can include a first portion CTE2a, a second portion CTE2b, and a third portion CTE2c. The first portion CTE2a of the second contact electrode CTE2 can be disposed on the second electrode RME2 and extend in the second direction (Y-axis direction). The second portion CTE2b of the second contact electrode CTE2 can be bent from the lower side of the first portion CTE2a and extend in the opposite direction of the first direction (X-axis direction). The third portion CTE2c of the second contact electrode CTE2 can be bent from the left side of the second portion CTE2b and extend in the second direction (Y-axis direction), and can be disposed on the first electrode RME1.

[0178] The second contact electrode CTE2 can be connected between the plurality of first light emitting elements EL1 and the plurality of second light emitting elements EL2. The second contact electrode CTE2 can correspond to a third node N3 of ​ The second contact electrode CTE2 can correspond to a cathode electrode of the plurality of first light emitting elements EL1, but is not limited thereto. The second contact electrode CTE2 can correspond to an anode electrode of the plurality of second light emitting elements EL2, and the third electrode RME3 can correspond to a cathode electrode of the plurality of second light emitting elements EL2, but is not limited thereto.

[0179] The above-described embodiments of the present application have been explained with reference to the accompanying drawings, it will be appreciated by those skilled in the art that the application can be implemented in other concrete forms without changing the technical idea or essential characteristics of the application. Therefore, the above-described embodiments should be understood as illustrative in all aspects rather than restrictive. Accordingly, the scope of the application should be interpreted by the appended claims rather than the embodiments described above, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are included.

Claims

1. A display device comprising: a substrate including a plurality of pixel regions provided with a first pixel, a second pixel, and a third pixel; a vertical voltage line extending in a first direction on the substrate; a horizontal voltage line extending in a second direction intersecting the first direction on the vertical voltage line and connected to the vertical voltage line; a first electrode of each of the first to third pixels arranged on the horizontal voltage line to receive a drive current; a second electrode of each of the first to third pixels and a third electrode of each of the first to third pixels arranged in parallel with the first electrode to be connected to the horizontal voltage line; a first contact electrode of each of the first to third pixels arranged on the first electrode to be connected to the first electrode; and a second contact electrode of each of the first to third pixels arranged in the same layer as the first contact electrode to be insulated from the first to third electrodes. further comprising:

2. The display device according to claim 1, wherein an active layer arranged on the vertical voltage line; and an auxiliary gate line arranged in a layer between the active layer and the horizontal voltage line to extend in the first direction.

3. The display device according to claim 2, wherein the second electrode of the second pixel receives a low potential voltage from the horizontal voltage line to reduce a capacitance between the auxiliary gate line and the second contact electrode of the second pixel. further comprising:

4. The display device according to claim 2, wherein a vertical gate line arranged in the same layer as the vertical voltage line; and a horizontal gate line arranged in the same layer as the horizontal voltage line to be connected between the vertical gate line and the auxiliary gate line. further comprising:

5. The display device of claim 4, wherein, a first auxiliary electrode arranged in the same layer as the auxiliary gate line to overlap the vertical gate line.

6. The display device according to claim 5, wherein the second electrode of the first pixel receives a low potential voltage from the horizontal voltage line to reduce a capacitance between the first auxiliary electrode and the second contact electrode of the first pixel. further comprising:

7. The display device according to claim 4, wherein a second auxiliary electrode arranged in the same layer as the horizontal gate line to overlap the vertical gate line.

8. The display device according to claim 7, wherein the second electrode of the first pixel receives a low potential voltage from the horizontal voltage line to reduce a capacitance between the second auxiliary electrode and the second contact electrode of the first pixel.

9. The display device according to claim 4, wherein in a planar view, one end of the first electrode of each of the first to third pixels adjacent to the horizontal gate line and the other end adjacent to the horizontal voltage line are cut off, and one end of the second electrode of each of the first to third pixels adjacent to the horizontal gate line is cut off. further comprising:

10. The display device according to claim 1, wherein a connection portion extending in the second direction to connect the second electrode of the first pixel and the third electrode of the second pixel. further comprising:

11. The display device according to claim 1, wherein a connection portion extending in the second direction to connect the second electrode of the second pixel and the third electrode of the third pixel. ​ 12. The display device according to claim 1, wherein the first electrode extends in the first direction, the second electrode is arranged on one side of the first electrode, and the third electrode is arranged on the other side of the first electrode.

13. The display device according to claim 12, wherein the second contact electrode of each of the first to third pixels includes: a first portion extending in the first direction over the second electrode; a second portion extending in the second direction bent from the first portion; and a third portion arranged over the first electrode bent from the second portion.

14. The display device according to claim 1, wherein each of the first to third pixels includes: a first transistor arranged between a drive voltage line and a plurality of light emitting elements to supply a drive current to the plurality of light emitting elements; a second transistor connecting a data line and a first node which is a gate electrode of the first transistor based on a gate signal; a third transistor connecting a sensing line and a second node which is a source electrode of the first transistor based on the gate signal; and a storage capacitor connected between the first node and the second node.

15. The display device of claim 14, wherein, Further comprising: a plurality of first light emitting elements connected between the first contact electrode and the second contact electrode; and a plurality of second light emitting elements connected between the second contact electrode and the third electrode.

16. The display device according to claim 15, wherein the second contact electrode is a third node between the plurality of first light emitting elements and the plurality of second light emitting elements.

17. The display device according to claim 15, wherein the plurality of first light emitting elements are arranged between the first electrode and the second electrode, and the plurality of second light emitting elements are arranged between the first electrode and the third electrode. Further comprising:

18. The display device of claim 14, wherein, a first connection electrode arranged in the same layer as the horizontal voltage line to be connected between the first electrode and a source electrode of the first transistor, wherein a gate electrode of the first transistor is a first capacitor electrode of the storage capacitor, and the first connection electrode is a second capacitor electrode of the storage capacitor. Further comprising:

19. The display device of claim 1, wherein, a second connection electrode bent from the horizontal voltage line to overlap the vertical voltage line in a thickness direction and directly connected to the vertical voltage line through a plurality of contact holes.

20. A display device comprising: a substrate including a plurality of pixel regions provided with first to third pixels; a vertical voltage line extending in a first direction on the substrate; an active layer arranged on the vertical voltage line; an auxiliary gate line extending in the first direction on the active layer; a horizontal voltage line extending in a second direction intersecting the first direction on the auxiliary gate line and connected to the vertical voltage line; a first electrode arranged on the horizontal voltage line to be connected to the active layer; a second electrode and a third electrode arranged in parallel with the first electrode to be connected to the horizontal voltage line; a first contact electrode arranged on the first electrode to be connected to the first electrode; and a second contact electrode arranged on the second electrode to be connected to the second electrode. ​ A second contact electrode is disposed on the first and second electrodes while being insulated from the first through third electrodes. A second contact electrode is disposed on the first and second electrodes while being insulated from the first through third electrodes.

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