Electroluminescent display device

Abstract

Disclosed is an electroluminescent display device. The display device includes: a substrate having a sub-pixel and a circuit line region adjacent to the sub-pixel; a drive transistor in the sub-pixel; a first bottom shield metal portion located below the drive transistor in the sub-pixel and a second bottom shield metal portion in the circuit line region; a first capacitor electrode portion in the sub-pixel and a second capacitor electrode portion in the circuit line region; and a light emitting diode in the sub-pixel, wherein the second bottom shield metal portion is electrically connected to the second capacitor electrode portion in the circuit line region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0186090, filed on December 29, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to an electroluminescent display device, and more specifically, to an electroluminescent display device capable of improving aperture ratio. Background Technology

[0004] As the application scope of display devices as a connection medium between users and information expands, various display devices, such as electroluminescent display devices, have been adopted for electronic devices such as mobile phones and laptops.

[0005] Because electroluminescent displays display images based on light generated from light-emitting elements (light-emitting diodes) located in sub-pixels, no additional light source is required. As a result, electroluminescent displays offer advantages such as a thin profile. The light-emitting elements can be formed from organic or inorganic materials.

[0006] When a gate signal and a data signal are provided to a sub-pixel of an electroluminescent display device, the light-emitting element of the sub-pixel emits light to display an image. The electroluminescent display device includes a driving circuit for driving the sub-pixels and a power supply circuit for supplying power to the sub-pixels. The driving circuit includes a gate driving circuit that provides a gate signal (gate voltage) and a data driving circuit that provides a data signal (data voltage).

[0007] In addition to its driving function, the driving circuit can also have a degradation compensation function. As a result, the driving circuit becomes more complex and has side effects. For example, since a sub-pixel includes multiple lines and multiple thin-film transistors, the area occupied by the multiple lines and multiple thin-film transistors increases, and the area occupied by the light-emitting area of ​​the electroluminescent display device decreases. Summary of the Invention

[0008] Therefore, the present invention aims to provide an electroluminescent display device that largely overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0009] One object of the present invention is to provide an electroluminescent display device in which the light-emitting area of ​​the sub-pixel is expanded by connecting a bottom shielding metal to a capacitor electrode located in a circuit line region other than the sub-pixel.

[0010] Additional features and advantages of the invention will be set forth in the following description, some of which will be apparent from the description or may be learned by practice of the invention. These and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the specification, claims and drawings.

[0011] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and broadly described herein, a display device includes: a substrate having sub-pixels and a circuit line region adjacent to the sub-pixels; a driving transistor in the sub-pixels; a first bottom shielding metal portion located below the driving transistor in the sub-pixels and a second bottom shielding metal portion located in the circuit line region; a first capacitor electrode portion in the sub-pixels and a second capacitor electrode portion located in the circuit line region; and a light-emitting diode in the sub-pixels, wherein the second bottom shielding metal portion is electrically connected to the second capacitor electrode portion located in the circuit line region.

[0012] In another aspect, a display device includes: a sub-pixel and a circuit line region adjacent to the sub-pixel; a driving transistor in the sub-pixel; a bottom shielding metal in the sub-pixel and the circuit line region; and a capacitor electrode in the sub-pixel and the circuit line region, wherein the bottom shielding metal is electrically connected to the capacitor electrode in the circuit line region.

[0013] It should be understood that the foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0015] Figure 1 This is a view showing an electroluminescent display device according to an embodiment of the present invention;

[0016] Figure 2 This is a view showing the sub-pixels of an electroluminescent display device according to an embodiment of the present invention;

[0017] Figure 3A This is a view showing the circuitry of a sub-pixel of an electroluminescent display device according to an embodiment of the present invention;

[0018] Figure 3B This is a plan view showing a sub-pixel of an electroluminescent display device according to an embodiment of the present invention;

[0019] Figure 4This is a timing diagram showing multiple signals of an electroluminescent display device according to an embodiment of the present invention;

[0020] Figure 5 It is along Figure 3B A sectional view taken by line V-V';

[0021] Figure 6 This is a plan view showing the sub-pixels of an electroluminescent display device according to a comparative example;

[0022] Figure 7 It is along Figure 6 A sectional view taken from line VII-VII';

[0023] Figure 8A This is a graph showing the relationship between the data voltage applied to the bottom shielding metal and the brightness of the electroluminescent display device according to the comparative example;

[0024] Figure 8B This is a graph showing the relationship between the data voltage applied to the bottom shielding metal and the brightness of the electroluminescent display device according to an embodiment of the present invention. Detailed Implementation

[0025] The advantages and features of the present invention, and the methods for achieving these advantages and features, will become clear from the exemplary embodiments described below with reference to the accompanying drawings. However, the present invention can be implemented in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make the disclosure of the present invention sufficient and complete, so as to help those skilled in the art to fully understand the scope of the present invention. Furthermore, the present invention is defined only by the scope of the appended claims.

[0026] The shapes, dimensions, proportions, angles, and quantities disclosed in the drawings for the purpose of describing embodiments of the invention are merely examples. Therefore, the invention is not limited to the details illustrated. Similar reference numerals denote similar elements throughout the application. In the following description of the invention, detailed descriptions of relevant known functions or constructions may be omitted where it would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used as described in this specification, additional components may be added unless more restrictive terms such as "only" are used.

[0027] When interpreting a feature, the feature is interpreted as including a range of errors or tolerances, even if there is no explicit description of such a range of errors or tolerances.

[0028] When describing positional relationships, one or more additional parts may be placed between two parts when the positional relationship between two parts is described as such as "on", "above", "below", or "after", unless more restrictive terms such as "immediately following" or "directly" are used.

[0029] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from other elements. For example, without departing from the scope of the invention, a first element may be named a second element, and similarly, a second element may be named a first element.

[0030] The features of the various embodiments of the present invention may be combined or integrated with each other, either partially or entirely, and may interoperate and drive each other in various technical ways, as will be fully understood by those skilled in the art. The embodiments of the present invention may be implemented independently of each other or together in an interdependent relationship.

[0031] In the following description, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings, using an electroluminescent display device as an example. Throughout the description, the same reference numerals refer to the same elements. When a detailed description of a well-known function or structure related to the present invention is determined to unnecessarily obscure key points of the technical concept, such detailed description will be omitted or will be provided briefly.

[0032] Figure 1 This is a view showing an electroluminescent display device according to an embodiment of the present invention. Figure 2 This is a view showing the sub-pixels of an electroluminescent display device according to an embodiment of the present invention.

[0033] exist Figure 1 In this electroluminescent display device, there are an image processing unit 110, a timing control unit 120, a gate driving unit 130, a data driving unit 140, a power supply unit 180, and a display panel 150.

[0034] The image processing unit 110 outputs an image signal provided from an external source, as well as multiple timing signals for each component. For example, the multiple timing signals may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0035] The timing control unit 120 receives an image signal and multiple timing signals from the image processing unit 110. The timing control unit 120 uses the image signal and the multiple timing signals to generate image data DATA, a gate control signal GDC, and a data control signal DDC. The timing control unit 120 transmits the gate control signal GDC to the gate driving unit 130 and transmits the image data and the data control signal DDC to the data driving unit 140.

[0036] The gate driving unit 130 uses the gate control signal GDC transmitted from the timing control unit 120 to generate a gate signal (gate voltage) and applies the gate signal to multiple gate lines GL1 to GLm of the display panel 150. Although the gate driving unit 130 may be formed as an integrated circuit (IC), it is not limited thereto.

[0037] The gate driving section 130 may be of the gate in-panel (GIP) type, wherein the gate driving section 130 is disposed on the substrate of the display panel 150.

[0038] The data driving unit 140 uses the data control signal DDC transmitted from the timing control unit 120 and the image data DATA to generate a data signal (data voltage), and applies the data signal to multiple data lines DL1 to DLn of the display panel 150. The data driving unit 140 samples and latches the digital image data DATA to output an analog data signal based on a gamma reference voltage. The data driving unit 140 may be formed as an integrated circuit (IC), but is not limited thereto.

[0039] The power supply unit 180 outputs a high-level voltage Vdd and a low-level voltage Vss. The power supply unit 180 provides the high-level voltage Vdd to the display panel 150 via the first power line EVDD, and provides the low-level voltage Vss to the display panel 150 via the second power line EVSS. Furthermore, the high-level voltage Vdd and low-level voltage Vss of the power supply unit 180 can be provided to the gate drive unit 130 or the data drive unit 140 for driving.

[0040] The display panel 150 uses the gate signal of the gate driving unit 130, the data signal of the data driving unit 140, and the high-level voltage Vdd and low-level voltage Vss of the power supply unit 180 to display images.

[0041] The display panel 150 includes multiple subpixels SP, multiple gate lines GL1 to GLm, and multiple data lines DL1 to DLn. The multiple subpixels SP may include red, green, and blue subpixels SP, or white, red, green, and blue subpixels SP. The white, red, green, and blue subpixels SP may have the same area as each other, or they may have different areas.

[0042] exist Figure 2In this circuit, a single sub-pixel SP can be connected to gate line GL1, data line DL1, first power line EVDD, and second power line EVSS. The number of transistors and capacitors in the sub-pixel SP, as well as the driving method, can be determined based on the structure of the sub-pixel circuit.

[0043] Figure 3A This is a view showing the circuitry of a sub-pixel of an electroluminescent display device according to an embodiment of the present invention; Figure 3B This is a plan view showing a sub-pixel of an electroluminescent display device according to an embodiment of the present invention; Figure 4 This is a timing diagram showing multiple signals of an electroluminescent display device according to an embodiment of the present invention.

[0044] exist Figure 3A and 3B In this structure, the sub-pixel SP may include multiple switching transistors T1 to T7, a driving transistor DT, a storage capacitor Cst, and a light-emitting diode Del. Although the sub-pixel SP... Figure 3A and 3B The device includes eight transistors, but the invention is not limited thereto. Furthermore, the sub-pixel SP may include a reference voltage compensation section STRC having a first compensation transistor TC1 and a second compensation transistor TC2.

[0045] The first node N1 is the connection node between the driving transistor DT and the bottom shiedling metal. The second node N2 is the connection node between the gate DRG of the driving transistor DT, the second electrode of the first transistor T1, and the first capacitor electrode of the storage capacitor Cst. The third node N3 is the connection electrode between the first electrode of the driving transistor DT, the first electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0046] The (n-1)th gate signal Scan(n-1) is applied to the gate of the first transistor T1, and the initialization voltage Vini is applied to the first electrode of the first transistor T1. The second electrode of the first transistor T1 is connected to the first capacitor electrode of the storage capacitor Cst, the second electrode of the third transistor T3, and the gate DRG of the driving transistor DT.

[0047] The first transistor T1 is turned on by the (n-1)th gate signal Scan(n-1) which is provided with a low logic level via the (n-1)th gate line. When the first transistor T1 is turned on, the second node N2 of the gate DRG of the driving transistor DT is initialized using the initialization signal Vini.

[0048] The nth gate signal Scan(n) is applied to the gate of the second transistor T2, and the initialization signal Vini is applied to the second electrode of the second transistor. The first electrode of the second transistor T2 is connected to the anode of the light-emitting diode Del. The second transistor T2 is turned on according to the nth gate signal Scan(n) which is provided with a low logic level via the nth gate line. When the second transistor T2 is turned on, the anode of the light-emitting diode Del is initialized using the initialization signal Vini.

[0049] The nth gate signal Scan(n) is applied to the gate of the third transistor T3. The first electrode of the third transistor T3 is connected to the first electrode of the driving transistor DT, and the second electrode of the third transistor T3 is connected to the gate DRG of the driving transistor DT. The third transistor T3 is turned on according to the nth gate signal Scan(n) which is provided with a low logic level via the nth gate line. When the third transistor T3 is turned on, the driving transistor DT is in a diode-connected state.

[0050] The nth gate signal Scan(n) is applied to the gate of the fourth transistor T4, and the data signal Vdata is applied to the second electrode of the fourth transistor T4. The first electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5 and the second electrode of the drive transistor DT. The fourth transistor T4 is turned on according to the nth gate signal Scan(n) which is provided with a low logic level via the nth gate line. When the fourth transistor T4 is turned on, the data signal Vdata of the data line DL is charged into the first electrode of the fourth transistor T4 (or charged between the fourth transistor T4 and the fifth transistor T5).

[0051] The nth emission signal Em(n) is applied to the gate of the fifth transistor T5, and a high-level voltage Vdd is applied to the first electrode of the fifth transistor T5. The first electrode of the fifth transistor T5 is connected to the first electrode of the seventh transistor T7, and the second electrode of the fifth transistor T5 is connected to the first electrode of the fourth transistor T4. The fifth transistor is turned on according to the nth emission signal Em(n) with a low logic level provided via the nth emission line. When the fifth transistor T5 is turned on, the data signal Vdata charged into the first electrode of the fourth transistor T4 is transmitted to the second capacitor electrode of the storage capacitor Cst via the seventh transistor T7.

[0052] The nth emission signal Em(n) is applied to the gate of the sixth transistor T6. The first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor DT, and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting diode Del. The sixth transistor T6 is turned on according to the nth emission signal Em(n) with a low logic level provided via the nth emission line. When the sixth transistor T6 is turned on, the light-emitting diode Del emits light corresponding to the driving current generated by the driving transistor DT.

[0053] The nth emission signal EM(n) is applied to the gate of the seventh transistor T7, and a high-level voltage Vdd is applied to the first electrode of the seventh transistor T7. The first electrode of the seventh transistor T7 is connected to the first electrode of the fifth transistor T5, and the second electrode of the seventh transistor T7 is connected to the second capacitor electrode of the storage capacitor Cst. The seventh transistor T7 is turned on according to the nth emission signal Em(n) with a low logic level provided via the nth emission line. When the seventh transistor T7 is turned on, the data signal Vdata in the first electrode of the fourth transistor T4 is transmitted to the second capacitor electrode of the storage capacitor Cst via the fifth transistor T5.

[0054] The first capacitor electrode of the storage capacitor Cst is connected to the second electrode of the first transistor T1, and the second capacitor electrode of the storage capacitor Cst is connected to the second electrode of the seventh transistor T7. The connection node between the second electrode of the seventh transistor T7 and the second capacitor electrode of the storage capacitor Cst is defined as the voltage delivery node VDN for transmitting the reference signal Vref.

[0055] The anode of LED Del is connected to the second electrode of the sixth transistor T6, and a low-level voltage Vss is applied to the cathode of LED Del.

[0056] The reference voltage compensation section STRC includes a first compensation transistor TC1 and a second compensation transistor TC2.

[0057] The first compensation transistor TC1 has a gate for receiving the (n-1)th gate signal Scan(n-1), a first electrode connected to the compensation node STR, and a second electrode for receiving the reference signal Vref. The first compensation transistor TC1 applies the reference signal Vref to the compensation node STR according to the (n-1)th gate signal Scan(n-1).

[0058] The second compensation transistor TC2 has a gate for receiving the nth gate signal Scan(n), a first electrode connected to the compensation node STR, and a second electrode for receiving the reference signal Vref. The second compensation transistor TC2 applies the reference signal Vref to the compensation node STR according to the nth gate signal Scan(n).

[0059] The driving transistor DT is a four-terminal transistor. The gate DRT of the driving transistor DT is connected to the second electrode of the first transistor T1, the first capacitor electrode of the storage capacitor Cst, and the second electrode of the third transistor T3. The first electrode of the driving transistor DT is connected to the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The second electrode of the driving transistor DT is connected to the first electrode of the fourth transistor T4. The bottom shielding metal BSM of the third electrode of the driving transistor DT is connected to the first node N1. The first node N1 can be located at the first connection point CP1 between the bottom shielding metal BSM and the second capacitor electrode (see...). Figure 5 )middle.

[0060] The first connection portion CP1 is disposed in the circuit line region CA (see) excluding the sub-pixel SP defined by the gate line GL and the data line DL, and has an initialization line for the initialization signal Vini and a reference line for the reference signal Vref. Figure 5 In the section ), the second connection point CP2 of the anode of the light-emitting diode Del (see... Figure 5 Set in subpixel SP.

[0061] exist Figure 4 In this electroluminescent display device, the sub-pixels SP operate during the initialization period INI, sampling period SAM, hold period HLD, and emission period EMI. During the initialization period INI, the gate DRG of the driving transistor DT is initialized. During the sampling period SAM, the threshold voltage of the driving transistor DT is detected, and the light-emitting diode Del is initialized. During the hold period HLD, the data signal Vdata applied via the data line is held in the node. During the emission period EMI, the light-emitting diode Del emits light corresponding to the drive current generated by the driving transistor DT.

[0062] During the initialization period INI and the sampling period SAM, the nth emission signal Em(n) is not applied to the sub-pixel (the nth emission signal Em(n) is at a high logic level). Each of the (n-1)th gate signal Scan(n-1) and the nth gate signal Scan(n) has a low logic level for a horizontal time (1H). Furthermore, each of the initialization period INI and the sampling period SAM has a horizontal time (1H).

[0063] During the initialization period INI, the first transistor T1 is turned on by the (n-1)th gate signal Scan(n-1) applied via the (n-1)th gate line, which is a low logic level. The initialization signal Vini applied via the initialization line has a voltage lower than the high-level voltage Vdd applied via the first power supply line EVDD. As a result, the gate DRG of the driving transistor DT is initialized using the initialization signal Vini.

[0064] During the sampling period SAM, transistors T2, T3, and T4 are turned on by the nth gate signal Scan(n) applied via the nth gate line at a low logic level. Due to the turn-on operation of transistor T2, the light-emitting diode Del is initialized using the initialization signal Vini. The driving transistor DT is in a diode-connected state due to the turn-on operation of transistor T3. Due to the turn-on operation of transistor T3, the threshold voltage of the driving transistor DT is sampled (detected). Furthermore, the voltage applied to the first electrode of the driving transistor DT is charged into the gate DRG via transistor T3, resulting in the gate DRG having a high-level voltage Vdd and a threshold voltage Vth (Vdd + Vth). The data signal (i.e., the data voltage) Vdata applied via the data line is applied to the second electrode DRS of the driving transistor DT due to the turn-on operation of transistor T4.

[0065] During the initialization period INI and the sampling period SAM, the reference signal Vref is applied to the compensation node STR to reflect the voltage drop of the high-level voltage Vdd.

[0066] Figure 5 It is along Figure 3B A sectional view taken by line V-V'.

[0067] exist Figure 5 In this invention, an electroluminescent display device 200 according to an embodiment of the present invention includes a first substrate 210, a second substrate 270, a driving transistor DT, and a light-emitting diode Del. The first substrate 210 includes sub-pixels SP for displaying images using the driving transistor DT and the light-emitting diode Del, and a circuit line region CA having initialization lines and reference lines. Although in Figure 5 Only the driving transistor DT is disposed on the first substrate 210, but the first to seventh transistors T1 to T7, as well as the first compensation transistor TC1 and the second compensation transistor TC2 are disposed on the first substrate 210.

[0068] The first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 are respectively disposed in the sub-pixel SP and the circuit line region CA on the first substrate 210. The first substrate 210 may include transparent glass or flexible plastic, and the first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 may include metal. However, the materials of the first substrate 210 and the first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 are not limited to these.

[0069] The first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 minimize the back channel phenomenon due to the charge trapped in the first substrate 210, thereby preventing image retention or transistor degradation. During operation of the electroluminescent display device 200, the potentials of the first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 can change, thus affecting the threshold voltage of the driving transistor DT. When the first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 are in a floating state, the threshold voltage of the driving transistor DT can have various offset magnitudes, leading to degradation such as changes in brightness. As a result, the first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 are electrically connected to an electrode of the electroluminescent display device 200. For example, the first bottom shielding metal portion BSM1 and the second bottom shielding metal portion BSM2 can be connected to a capacitor electrode of the storage capacitor Cst.

[0070] Despite Figure 5 The first bottom shielding metal portion BSM1 of the sub-pixel SP and the second bottom shielding metal portion BSM2 of the circuit line region CA are shown as separate, but in the plan view, the first bottom shielding metal portion BSM1 of the sub-pixel SP and the second bottom shielding metal portion BSM2 of the circuit line region CA are connected to each other as one to form a single bottom shielding metal BSM.

[0071] A buffer layer 242 is disposed on a first bottom shielding metal portion BSM1 and a second bottom shielding metal portion BSM2 and on a first substrate 210. A semiconductor layer 214 is disposed in a sub-pixel SP on the buffer layer 242, and a gate insulating layer 243 is disposed on the semiconductor layer 214 and the buffer layer 242.

[0072] Semiconductor layer 214 may comprise an oxide semiconductor material such as indium zinc oxide (IGZO). Optionally, semiconductor layer 214 may comprise amorphous silicon or polycrystalline silicon. Semiconductor layer 214 has a channel region 214a of intrinsic semiconductor material and source regions 214b and drain regions 214c of doped semiconductor material located on both sides of channel region 214a.

[0073] The gate insulating layer 243 may be a single or double layer of inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0074] Gate 216a and first connection electrode 216b are respectively disposed in the sub-pixel SP and circuit line region CA on gate insulating layer 243, and interlayer insulating layer 244 is disposed on gate 216a, first connection electrode 216b and gate insulating layer 243. Gate 216a and first connection electrode 216b can be formed in the same layer from the same material using the same manufacturing process. Optionally, gate 216a and first connection electrode 216b can be formed from different materials using different manufacturing processes.

[0075] The gate 216a and the first connection electrode 216b may be formed of metallic materials such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al) and aluminum alloys, but the metallic materials are not limited to these.

[0076] The first connection electrode 216b is electrically connected to the second bottom shielding metal portion BSM2 located in the circuit line region CA via the first contact hole 249a in the buffer layer 242 and the gate insulating layer 243.

[0077] The first capacitor electrode portion 218a and the second capacitor electrode portion 218b are respectively disposed in the sub-pixel SP and the circuit line region CA on the interlayer insulating layer 244. Although the first capacitor electrode portion 218a and the second capacitor electrode portion 218b are in Figure 5 Although shown separately, the first capacitor electrode portion 218a and the second capacitor electrode portion 218b are connected to each other in the plan view to form the second capacitor electrode of the integrated storage capacitor Cst.

[0078] Although the first capacitor electrode portion 218a and the second capacitor electrode portion 218b may be formed of metallic materials, the present invention is not limited thereto.

[0079] A passivation layer 246 is disposed on the first capacitor electrode portion 218a, the second capacitor electrode portion 218b, and the interlayer insulating layer 244. A first electrode 222 and a second electrode 224 are disposed in a sub-pixel SP on the passivation layer 246, and a second connection electrode 226 is disposed in a circuit line region CA on the passivation layer 246. Furthermore, a data line DL is disposed on the passivation layer 246. The second connection electrode 226, the first electrode 222, and the second electrode 224 can be formed in the same layer using the same manufacturing process and the same material. Optionally, the second connection electrode 226, the first electrode 222, and the second electrode 224 can be formed using different manufacturing processes and different materials.

[0080] The passivation layer 246 may be formed of an organic material such as photoacryl, or may be a multilayer having inorganic and organic layers. The first electrode 222, the second electrode 224, and the second connecting electrode 226 may be formed of metallic materials such as chromium (Cr), molybdenum (Mo), tantalum (Ta), copper (Cu), titanium (Ti), aluminum (Al), and aluminum alloys, but the metallic materials are not limited to these.

[0081] The first electrode 222 and the second electrode 224 are electrically connected to the source region 214b and the drain region 214c, respectively, through a second contact hole 249b and a third contact hole 249c located in the gate insulating layer 243, the interlayer insulating layer 244, and the passivation layer 246. The second connection electrode 226 is electrically connected to the second capacitor electrode portion 218b through a fourth contact hole 249d in the passivation layer 246, and is electrically connected to the first connection electrode 216b through a fifth contact hole 249e in the interlayer insulating layer 244 and the passivation layer 246.

[0082] The second capacitor electrode portion 218b and the second bottom shielding metal portion BSM2 in the circuit line region CA are electrically connected to each other via the first connecting electrode 216b and the second connecting electrode 226. The second capacitor electrode portion 218b is integrally formed with the first capacitor electrode portion 218a in the sub-pixel SP to form the second capacitor electrode, and the second bottom shielding metal portion BSM2 is integrally formed with the first bottom shielding metal portion BSM1 in the sub-pixel SP to form the bottom shielding metal BSM. As a result, the bottom shielding metal BSM is electrically connected to the second capacitor electrode of the storage capacitor Cst via the first connecting electrode 216b and the second connecting electrode 226.

[0083] Semiconductor layer 214, gate 216a, first electrode 222, and second electrode 224 constitute the driving transistor DT. Although the driving transistor DT... Figure 5 While the structure is coplanar, the driving transistor DT may have other structures in other embodiments.

[0084] A planarization layer 248 is disposed on the driving transistor DT. The planarization layer 248 may be formed of an organic material such as optical acrylic, or may be a multilayer having inorganic and organic layers. The planarization layer 248 has a sixth contact hole 249f exposing the second electrode 224.

[0085] Anode 232 is disposed on planarization layer 248. Anode 232 is electrically connected to the second electrode 224 of driving transistor DT through sixth contact hole 249f. Anode 232 may have a single-layer structure or a multi-layer structure comprising a metallic material such as calcium (Ca), palladium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), or alloys thereof. Anode 232 is connected to the second electrode 224 of driving transistor DT, and a signal corresponding to a data signal is applied to anode 224.

[0086] A dike layer 252 is disposed in the boundary portion of the sub-pixel SP on the planarization layer 248. The dike layer 252 is a sidewall that divides the sub-pixel SP and is used to prevent the mixing of light of various colors between adjacent sub-pixels SP.

[0087] A light-emitting layer 234 is disposed on a portion of the inclined surface of the embankment layer 232 and on the anode 232. The light-emitting layer 234 may include a red light-emitting layer emitting red light in the red sub-pixel, a green light-emitting layer emitting green light in the green sub-pixel, and a blue light-emitting layer emitting blue light in the blue sub-pixel. In addition, the light-emitting layer 234 may include a white light-emitting layer emitting white light.

[0088] The light-emitting layer 234 may include a light-emitting material layer, an electron injection layer for injecting electrons from the cathode, an electron transport layer for transporting electrons to the light-emitting material layer, a hole injection layer for injecting holes from the anode, and a hole transport layer for transporting holes to the light-emitting material layer.

[0089] The cathode 236 is disposed on the light-emitting layer 234. The cathode may include a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a metallic material having a thickness that allows visible light to pass through. However, the material of the cathode 236 is not limited to these.

[0090] Encapsulation layer 262 is disposed on cathode 236. Encapsulation layer 262 may have a single-layer structure including an inorganic layer; a double-layer structure including an inorganic layer and an organic layer; or a three-layer structure including an inorganic layer, an organic layer, and an inorganic layer. The inorganic layer may include inorganic materials such as silicon nitride and silicon oxide, but the invention is not limited thereto. The organic layer may include organic materials such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyimide (PI), polyethylene sulfonate (PES), polyoxymethylene (POM), and polyarylate (PAR) and mixtures thereof, but the invention is not limited thereto.

[0091] The second substrate 270 is disposed on the encapsulation layer 262 and attached to the encapsulation layer 262 by an adhesive layer (not shown). The adhesive layer may include materials having relatively high adhesion, relatively high heat resistance, and relatively high moisture resistance. For example, the adhesive layer may include thermosetting resins such as epoxy resin compositions, acrylate compounds, and acrylic rubbers. Optionally, the adhesive layer may include a photocurable resin. When the adhesive layer includes a photocurable resin, the adhesive layer can be cured by irradiating the adhesive layer with light other than ultraviolet light.

[0092] The adhesive layer is attached to the first substrate 210 and the second substrate 270. In addition, the adhesive layer can be used as an encapsulation layer to prevent moisture from penetrating into the electroluminescent display device 200.

[0093] The second substrate 270 is an encapsulation cap for encapsulating the electroluminescent display device 200. The second substrate 270 may include glass or a protective film such as polystyrene (PS) film, polyethylene (PE) film, polyethylene naphthalate (PEN) film, and polyimide (PI) film.

[0094] In the electroluminescent display device 200 according to an embodiment of the present invention, since the bottom shielding metal BSM of the driving transistor DT is connected to the second capacitor electrode of the storage capacitor Cst, the threshold voltage change of the driving transistor DT due to the floating state of the bottom shielding metal BSM is prevented.

[0095] Furthermore, since the first connection part CP1 of the bottom shielding metal BSM is located in the circuit line area CA outside the sub-pixel SP, the light-emitting area of ​​the sub-pixel is expanded.

[0096] Figure 6 This is a plan view showing the sub-pixels of an electroluminescent display device according to a comparative example; Figure 7 It is along Figure 6 The cross-sectional view is taken along line VII-VII'. Illustrations of structures identical to those in the comparative examples of the present invention will be omitted.

[0097] exist Figure 6 In the comparative example, the electroluminescent display device includes a driving transistor DT and a light-emitting diode Del. A bottom shielding metal BSM of the driving transistor DT is connected to a second electrode 324 of the driving transistor DT, and a first connection portion CP1 between the bottom shielding metal BSM and the second electrode 324 is provided in a sub-pixel SP. A second connection portion CP2 between the driving transistor DT and the light-emitting diode Del is provided in the sub-pixel SP. Compared to the first connection portion CP1, the second connection portion CP2 can be provided in the lower portion of the sub-pixel SP in a planar view.

[0098] exist Figure 7 In the comparative example, the electroluminescent display device 300 includes a first substrate 310 and a second substrate 370, a driving transistor DT, and a light-emitting diode Del. The first substrate 310 includes sub-pixels SP that display images using the driving transistor DT and the light-emitting diode Del, and a circuit line region CA having initialization lines and reference lines. A bottom shielding metal BSM is disposed in the sub-pixels SP on the first substrate 310, and a buffer layer 342 is disposed on the bottom shielding metal BSM and on the first substrate 310. A semiconductor layer 314 is disposed in the sub-pixels SP on the buffer layer 342, and a gate insulating layer 343 is disposed on the semiconductor layer 314 and the buffer layer 342.

[0099] A gate 316a and a connecting electrode 316b are disposed in a sub-pixel SP on a gate insulating layer 343, and an interlayer insulating layer 344 is disposed on the gate 316a, the connecting electrode 316b and the gate insulating layer 343.

[0100] The connection electrode 316b is electrically connected to the bottom shielding metal BSM through the first contact hole 349a located in the buffer layer 342 and the gate insulating layer 343.

[0101] The first capacitor electrode portion 318a is disposed in the sub-pixel SP on the interlayer insulating layer 344. The first capacitor electrode portion 318a constitutes the second capacitor electrode of the storage capacitor Cst.

[0102] A passivation layer 346 is disposed on the first capacitor electrode portion 318a and the interlayer insulating layer 344. A first electrode 322 and a second electrode 324 are disposed in the sub-pixel SP on the passivation layer 346. Furthermore, a data line DL is disposed on the passivation layer 346.

[0103] The first electrode 322 and the second electrode 324 are electrically connected to the source region 314b and the drain region 314c, respectively, through a second contact hole 349b and a third contact hole 349c located in the gate insulating layer 343, the interlayer insulating layer 344, and the passivation layer 346. Furthermore, the second electrode 324 is electrically connected to the connection electrode 316b through a fourth contact hole 349d in the passivation layer 346. In the electroluminescent display device 300 according to the comparative example, the second electrode 324 of the driving transistor DT is electrically connected to the bottom shielding metal BSM in the sub-pixel SP.

[0104] A planarization layer 348 is disposed on the driving transistor DT, and an anode 332 is disposed on the planarization layer 348. The anode 332 is electrically connected to the second electrode 324 of the driving transistor DT through a sixth contact hole 349f. A dam layer 352 is disposed in the boundary portion of the sub-pixel SP on the planarization layer 348.

[0105] The light-emitting layer 334 is disposed on a portion of the inclined surface of the embankment layer 352 and on the anode 332, and the cathode 336 is disposed on the light-emitting layer 334.

[0106] The encapsulation layer 362 is disposed on the cathode 336, and the second substrate 370 is disposed on the encapsulation layer 362 and attached to the encapsulation layer 362 by means of an adhesive layer (not shown).

[0107] In the electroluminescent display device 300 according to the comparative example, a first connection portion CP1 between the bottom shielding metal BSM and the second electrode 324 of the driving transistor DT, and a second connection portion CP2 between the anode 332 of the light-emitting diode Del and the second electrode 324 of the driving transistor DT are provided in the sub-pixel SP. Specifically, compared to the first connection portion CP1, the second connection portion CP2 is provided in the lower portion of the sub-pixel SP in a plan view.

[0108] In the electroluminescent display device 200 according to an embodiment of the present invention, the arrangement freedom of the second connecting portion CP2 in the sub-pixel SP is increased compared to the electroluminescent display device 300 according to the comparative example.

[0109] According to Figure 5 In the electroluminescent display device 200 of the present invention, since the first connecting portion CP1 is provided in the circuit line region CA and the second connecting portion CP2 is provided in the sub-pixel SP, the light-emitting region has a first width d1.

[0110] According to Figure 7 In the comparative example of the electroluminescent display device 300, since the first connecting portion CP1 and the second connecting portion CP2 are provided in the sub-pixel SP, the light-emitting area has a second width d2 (d1>d2) that is smaller than the first width d1.

[0111] Due to comparison Figure 7 The second width d2 of the luminescent region, Figure 5 The first width d1 of the light-emitting area is increased, so the electroluminescent display device 200 according to the embodiment of the present invention has the following advantages compared with the electroluminescent display device 300 according to the comparative example.

[0112] First, due to the increased area of ​​the light-emitting region, a design margin for the anode is achieved and interference between adjacent sub-pixels is prevented.

[0113] In the electroluminescent display device 200 according to an embodiment of the present invention, the red, green, and blue light-emitting diodes of the red, green, and blue sub-pixels emit red, green, and blue light respectively, and have different luminous efficiencies. As a result, for white light obtained by mixing red, green, and blue light, the red, green, and blue emitting regions of the red, green, and blue sub-pixels have different areas.

[0114] The area of ​​the green emitting region can be smaller than that of the red emitting region but larger than that of the blue emitting region. The areas of the red, green, and blue emitting regions can be varied depending on the structure and materials.

[0115] In the electroluminescent display device 300 according to the comparative example, the light-emitting area of ​​the sub-pixel SP has a relatively small area. As a result, due to the relatively small light-emitting area of ​​the sub-pixel SP, sufficient design margin cannot be obtained for the green or blue light-emitting layer with a relatively large area, and the light-emitting layer may deteriorate.

[0116] In addition, a blue or green light-emitting layer can be placed on the interference limit line of the sub-pixel SP, thereby degrading the display quality due to optical interference between adjacent sub-pixels SP.

[0117] In the electroluminescent display device 200 according to an embodiment of the present invention, since the light-emitting area of ​​the sub-pixel SP is expanded, sufficient design margin of the light-emitting layer is obtained, and the light-emitting layer is prevented from being positioned on the interference limit line of the sub-pixel SP. As a result, display quality degradation caused by optical interference is prevented.

[0118] Second, in the electroluminescent display device 300 according to the comparative example, since the first connecting portion CP1 is disposed in the sub-pixel SP, sufficient space cannot be obtained for the first capacitor electrode portion 318a, and the area of ​​the first capacitor electrode portion 318a is reduced. As a result, sufficient capacitance of the storage capacitor Cst cannot be obtained.

[0119] In the electroluminescent display device 200 according to an embodiment of the present invention, the first connecting portion CP1 is not provided in the sub-pixel SP, thus providing sufficient space for the first capacitor electrode portion 218a, and the first capacitor electrode portion 218a is formed to have a predetermined area. As a result, sufficient capacitance of the storage capacitor Cst is obtained.

[0120] Third, compared with the electroluminescent display device 300 according to the comparative example, the voltage utilization rate of the data driving unit 130 is improved in the electroluminescent display device 200 according to the embodiment of the present invention.

[0121] Figure 8AThis is a graph showing the relationship between the data voltage applied to the bottom shielding metal and the brightness of the electroluminescent display device according to the comparative example; Figure 8A This is a graph showing the relationship between the data voltage applied to the bottom shielding metal and the brightness of the electroluminescent display device according to an embodiment of the present invention.

[0122] According to Figure 8A In the comparative example of the electroluminescent display device 300, by applying a data voltage (data signal) Vdata of about 4.5V to about 6.2V to the bottom shielding metal BSM, a brightness of about 0 nits to about 800 nits is obtained for blue light B, red light R, green light G and white light W.

[0123] According to Figure 8B In the electroluminescent display device 200 of the present invention, by applying a data voltage (data signal) Vdata of about 5.3V to about 6.1V to the bottom shielding metal BSM, a brightness of about 0 nits to about 800 nits is obtained for blue light B, red light R, green light G and white light W.

[0124] According to an embodiment of the present invention, the electroluminescent display device 200 uses a data voltage range of approximately 0.8V to display an image with a brightness of approximately 0 nits to approximately 800 nits, while the electroluminescent display device 300 according to a comparative example uses a data voltage range of approximately 1.7V to display an image with a brightness of approximately 0 nits to approximately 800 nits.

[0125] For example, when the data voltage Vdata output from the data drive unit 130 is fixed at approximately 5V, the electroluminescent display device 200 according to the embodiment of the present invention has a higher brightness than the electroluminescent display device 300 according to the comparative example.

[0126] Therefore, in the electroluminescent display device 200 according to an embodiment of the present invention, since the bottom shielding metal BSM is connected to the capacitor electrode located in the circuit line region CA rather than the storage capacitor Cst in the pixel SP, the area of ​​the light-emitting region in the sub-pixel SP is enlarged.

[0127] Furthermore, since the arrangement freedom of the second connecting portion CP2 increases with the increase in the arrangement of the light-emitting area, the design margin of the light-emitting layer increases, preventing interference between adjacent sub-pixels. As a result, the area of ​​the capacitor electrode is increased, and sufficient capacitance of the storage capacitor Cst is obtained.

[0128] Furthermore, due to the improved utilization of the data voltage range in the data drive section, images with higher brightness can be displayed for the data voltage applied to the bottom shield metal BSM.

[0129] Those skilled in the art will readily recognize that various modifications and variations can be made to this invention without departing from its spirit or scope. Therefore, this invention is intended to cover all modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate having sub-pixels and circuit line regions adjacent to the sub-pixels; The driving transistor in the sub-pixel; A first bottom shielding metal portion located below the driving transistor in the sub-pixel and a second bottom shielding metal portion located in the circuit line region; The first capacitor electrode portion in the sub-pixel and the second capacitor electrode portion in the circuit line region; as well as The light-emitting diode in the sub-pixel The second bottom shielding metal portion is electrically connected to the second capacitor electrode portion in the circuit line region.

2. The display device according to claim 1, wherein the driving transistor comprises: Semiconductor layer on the substrate; Gate insulating layer on the semiconductor layer; The gate on the gate insulating layer; Interlayer insulating layer on the gate; Passivation layer on the first capacitor electrode portion; as well as The first electrode and the second electrode are on the passivation layer.

3. The display device according to claim 2, further comprising a first connecting electrode and a second connecting electrode located in the circuit line region and electrically connecting the second bottom shielding metal portion and the second capacitor electrode portion.

4. The display device according to claim 3, wherein the first connection electrode is electrically connected to the second bottom shielding metal portion through a first contact hole in the gate insulating layer. The second connection electrode is electrically connected to the first connection electrode through a second contact hole in the gate insulating layer and the interlayer insulating layer, and is electrically connected to the second capacitor electrode portion through a third contact hole in the passivation layer.

5. The display device according to claim 4, wherein the first connection electrode and the gate are disposed in the same layer using the same process.

6. The display device according to claim 4, wherein the second connecting electrode is disposed in the same layer as the first electrode and the second electrode using the same process.

7. The display device according to claim 1, wherein the first bottom shielding metal portion and the second bottom shielding metal portion are connected to each other as a single unit.

8. The display device according to claim 1, wherein the first capacitor electrode portion and the second capacitor electrode portion are connected to each other as a single unit.

9. The display device according to claim 1, wherein the light-emitting diode comprises: anode; The light-emitting layer on the anode; as well as The cathode on the light-emitting layer.

10. The display device of claim 9, wherein the anode is electrically connected to a driving transistor in the sub-pixel.

11. The display device according to claim 1, wherein the first capacitor electrode portion and the second capacitor electrode portion constitute the second capacitor electrode of the storage capacitor, and the first capacitor electrode of the storage capacitor is connected to the gate of the driving transistor.

12. The display device according to claim 1, wherein a first connection portion between the second bottom shielding metal portion and the second capacitor electrode portion is provided in the circuit line region, and a second connection portion between the driving transistor and the anode of the light-emitting diode is provided in the sub-pixel.

13. The display device according to claim 1, further comprising a planarization layer located on the driving transistor and a dam layer disposed in the boundary portion of the sub-pixels on the planarization layer, wherein the light-emitting layer of the light-emitting diode is disposed on a portion of the inclined surface of the dam layer and on the anode of the light-emitting diode.

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