Display Substrate, Preparation Method Thereof, and Display Device

Abstract

The present invention provides a display substrate, comprising a plurality of pixel driving circuits; a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits in one-to-one correspondence; the pixel driving circuit includes a driving transistor, a threshold compensation transistor, a first reset transistor, and a data writing transistor; the gate of the driving transistor is connected to the threshold compensation transistor and the first reset transistor; the first pole of the driving transistor is connected to the data writing transistor; the second pole of the driving transistor is connected to the threshold compensation transistor and the light-emitting element; each transistor respectively includes a low-temperature polycrystalline silicon active region; and its first pole respectively includes a first heavily doped region, and its second pole respectively includes a second heavily doped region; the first pole of the threshold compensation transistor and / or the first reset transistor includes a first lightly doped region, and its second pole includes a second lightly doped region; the first lightly doped region is located between the first heavily doped region and the active region; the second lightly doped region is located between the second heavily doped region and the active region. It can improve the sand grain mura.

Description

Technical Field

[0001] The present invention belongs to the technical field of displays, and particularly relates to a display substrate, a preparation method thereof, and a display device. Background Art

[0002] In recent years, flexible LTPS (Low Temperature Poly-Silicon) OLED (Organic Light-Emitting Diode) small and medium-sized display products have become the mainstream in the market. In addition to the advantages of self-luminescence, light weight, energy conservation and environmental protection of OLED itself, they also have special advantages that many rigid substrate OLED display products and other flat panel display products do not have. However, there will be some image quality problems in LTPS OLED small and medium-sized display products, such as image sticking, copper bar turning green, low gray scale Mura, etc. Among them, Sandy mura is a relatively common and serious defect.

[0003] Sandy mura is a kind of Mura that can be observed with the naked eye in the gray scale picture and exists throughout the screen but cannot be measured and quantified by existing optical instruments. At present, Sandy mura is divided into two types, one is cluster Sandy mura; the other is granular Sandy mura.

[0004] According to analysis and research, it is found that Sandy mura is mainly caused by slight differences in the emission brightness between pixels, so that there will be slight differences in the emission brightness between pixels recognized by the human eye. The difference in the emission brightness between pixels is directly related to the pixel driving circuit. If the driving currents of each pixel by the pixel driving circuit are inconsistent, the emission brightness of each pixel will be different. Summary of the Invention

[0005] In view of the above problems, the present invention provides a display substrate, a preparation method thereof, and a display device. The display substrate can reduce the leakage current of the threshold compensation transistor and / or the first reset transistor, and at the same time can reduce the leakage difference of the threshold compensation transistor and / or the first reset transistor in different pixel driving circuits, so as to ensure that under the same data voltage, the gate voltage difference of the driving transistors in different pixel driving circuits is reduced, and further make the driving currents of different pixel driving circuits for different light-emitting elements tend to be consistent, so as to improve the brightness uniformity of different regions of the pure color picture displayed by the display substrate, and improve or avoid the appearance of Sandy mura defects in the display picture.

[0006] The present invention provides a display substrate, including a plurality of pixel driving circuits;

[0007] A plurality of light-emitting elements, connected to the plurality of pixel driving circuits in one-to-one correspondence;

[0008] The pixel driving circuit includes a driving transistor, a threshold compensation transistor, a first reset transistor and a data writing transistor;

[0009] The gate of the driving transistor is connected to the first electrode of the threshold compensation transistor and the first electrode of the first reset transistor; the first electrode of the driving transistor is connected to the second electrode of the data writing transistor; the second electrode of the driving transistor is connected to the second electrode of the threshold compensation transistor and the anode of the light emitting element;

[0010] The driving transistor, the threshold compensation transistor, the first reset transistor and the data writing transistor each include a low temperature polysilicon active region; and their first poles each include a first heavily doped region, and their second poles each include a second heavily doped region; the first heavily doped region and the second heavily doped region are located at opposite ends of the active region;

[0011] The first electrode of the threshold compensation transistor and / or the first reset transistor further includes a first lightly doped region, and the second electrode thereof further includes a second lightly doped region;

[0012] The first lightly doped region is located between the first heavily doped region and the active region; and the second lightly doped region is located between the second heavily doped region and the active region.

[0013] Optionally, further comprising a substrate;

[0014] The threshold compensation transistor and / or the first reset transistor comprises a first gate and a second gate;

[0015] The first gate and the second gate are stacked in sequence away from the substrate, and a first gate insulating layer is disposed between the first gate and the second gate;

[0016] Orthographic projections of the first gate and the second gate on the substrate overlap with an orthographic projection of the active region on the substrate.

[0017] Optionally, the first gate and the second gate are located on a side of the active region away from the substrate, and a second gate insulating layer is provided between the first gate and the active region.

[0018] Optionally, the pixel driving circuit further includes a storage capacitor, a first light emission control transistor, a second light emission control transistor and a second reset transistor;

[0019] The gate of the threshold compensation transistor and the gate of the data writing transistor are connected to the scan line; the first electrode of the data writing transistor is connected to the data line;

[0020] The gates of the first reset transistor and the second reset transistor are connected to a reset control line; the second poles of the first reset transistor and the second reset transistor are connected to a reset power supply terminal;

[0021] The first pole of the second reset transistor and the second pole of the second light-emitting control transistor are connected to the anode of the light-emitting element;

[0022] The gates of the second light-emitting control transistor and the first light-emitting control transistor are connected to a light-emitting control line; the first pole of the second light-emitting control transistor is connected to the second pole of the driving transistor;

[0023] The second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor; the first pole of the first light-emitting control transistor and the first electrode plate of the storage capacitor are connected to a first potential terminal; the second electrode plate of the storage capacitor is connected to the gate of the driving transistor;

[0024] The cathode of the light-emitting element is connected to a second potential terminal.

[0025] Optionally, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor each include a low-temperature polycrystalline silicon active region.

[0026] An embodiment of the present invention further provides a display device, including the above display substrate.

[0027] An embodiment of the present invention further provides a method for manufacturing a display substrate, including: preparing a plurality of pixel driving circuits;

[0028] Preparing a plurality of light-emitting elements;

[0029] Preparing the pixel driving circuit includes preparing a driving transistor, a threshold compensation transistor, a first reset transistor, and a data writing transistor;

[0030] Preparing the threshold compensation transistor and / or the first reset transistor includes: forming an intermediate pattern of an active layer made of a low-temperature polycrystalline silicon material;

[0031] Performing heavy doping on regions at opposite ends of the intermediate pattern of the active layer through a first masking process to form a first heavily doped region and a second heavily doped region;

[0032] Performing light doping on regions at opposite ends of the intermediate pattern of the active layer close to the first heavily doped region and the second heavily doped region through a second masking process to form a first lightly doped region, a second lightly doped region, and an active region located between the first lightly doped region and the second lightly doped region.

[0033] Optionally, the process of heavily doping the regions at the opposite ends of the active layer through the first masking process to form a first heavily doped region and a second heavily doped region includes:

[0034] Form an active layer intermediate pattern, a gate insulating layer, and a gate layer film on the substrate in sequence, and apply a photoresist on the gate layer film; use a first mask to expose and develop the photoresist, retain the photoresist in the region corresponding to the gate intermediate pattern, and remove the photoresist in the region outside the gate intermediate pattern;

[0035] Form the gate intermediate pattern through a single dry etching process;

[0036] Using the gate intermediate pattern as a mask, perform a heavy doping process on the regions of the active layer intermediate pattern that are not covered by the gate intermediate pattern at the opposite ends of the gate intermediate pattern to form the first heavily doped region and the second heavily doped region;

[0037] Remove the photoresist on the gate intermediate pattern through ashing and stripping processes.

[0038] Optionally, the process of lightly doping the regions near the first heavily doped region and the second heavily doped region at the opposite ends of the active layer intermediate pattern through the second masking process to form a first lightly doped region, a second lightly doped region, and an active region located between the first lightly doped region and the second lightly doped region includes:

[0039] Apply a photoresist on the gate intermediate pattern, use a second mask to expose and develop the photoresist, retain the photoresist in the region corresponding to the gate pattern, and remove the photoresist in the region outside the gate pattern;

[0040] Form the gate pattern through a single dry etching process;

[0041] Using the gate pattern as a mask, perform a light doping process on the regions of the active layer intermediate pattern that are not covered by the gate pattern at the opposite ends of the gate pattern to form the first lightly doped region and the second lightly doped region; the part located between the first lightly doped region and the second lightly doped region is the active region;

[0042] Remove the photoresist on the gate pattern through ashing and stripping processes.

[0043] Optionally, fabricating the pixel driving circuit further includes fabricating a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor;

[0044] Fabricating the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor includes:

[0045] An active layer intermediate pattern, a gate insulating layer, and a gate layer film are sequentially formed on a substrate, and a photoresist is coated on the gate layer film; the photoresist is exposed and developed using the first mask, and the photoresist in the area corresponding to the gate pattern is retained, while the photoresist in the area outside the gate pattern is removed.

[0046] The gate pattern is formed through a single dry etching process.

[0047] Using the gate pattern as a mask, a heavy doping process is performed on the areas of the active layer intermediate pattern that are not covered by the gate pattern at opposite ends of the gate pattern, to form the first heavily doped region and the second heavily doped region.

[0048] The photoresist on the gate pattern is removed through ashing and stripping processes.

[0049] The present invention also provides a display device, including the above-mentioned display substrate.

[0050] Advantages of the present invention: For the display substrate provided by the present invention, the first pole of the threshold compensation transistor and / or the first reset transistor can reduce the leakage current of the threshold compensation transistor and / or the first reset transistor by setting the first lightly doped region, and the second pole can reduce the leakage current difference of the threshold compensation transistor and / or the first reset transistor in different pixel driving circuits by setting the second lightly doped region. Thus, when the data voltage is the same, the gate voltage difference of the driving transistors in different pixel driving circuits is reduced, and then the driving currents of the driving transistors in different pixel driving circuits for different light-emitting elements tend to be consistent, so that the light-emitting brightness of different light-emitting elements tends to be consistent, improving the brightness uniformity of different regions of the pure color picture displayed on the display substrate, and improving or avoiding the problem of sand-like mura in the display picture.

[0051] For the display device provided by the present invention, by using the above-mentioned display substrate, the brightness uniformity of different regions of the pure color picture displayed by the display device is improved, and the problem of sand-like mura in the display picture of the display device is improved or avoided. Description of the Drawings

[0052] Figure 1 It is a circuit diagram of a 7T1C pixel driving circuit in the prior art;

[0053] Figure 2 It is a schematic process diagram of an LTPS transistor in a pixel driving circuit for preparing a liquid crystal display panel in the prior art;

[0054] Figure 3 It is a schematic process diagram of an LTPS transistor in another pixel driving circuit for preparing a liquid crystal display panel in the prior art;

[0055] Figure 4This is the circuit diagram of the pixel driving circuit in the display substrate according to the embodiment of the present invention;

[0056] Figure 5 is Figure 4 the structural cross-sectional view of the threshold compensation transistor and the first reset transistor in the pixel driving circuit;

[0057] Figure 6 is Figure 4 the working timing diagram of the pixel driving circuit;

[0058] Figure 7 This is the schematic diagram of the preparation process of the first heavily doped region and the second heavily doped region of the threshold compensation transistor and the first reset transistor in the display substrate according to the embodiment of the present invention;

[0059] Figure 8 This is the schematic diagram of the preparation process of the gate, the first lightly doped region, the second lightly doped region and the active region of the threshold compensation transistor and the first reset transistor in the display substrate according to the embodiment of the present invention.

[0060] The reference numerals therein are:

[0061] 1, active region; 2, first heavily doped region; 3, second heavily doped region; 4, first lightly doped region; 5, second lightly doped region; 6, substrate; 7, first gate; 8, second gate; 9, first gate insulating layer; 10, second gate insulating layer; 11, active layer intermediate pattern; 12, gate layer film; 13, photoresist; 14, gate intermediate pattern; 15, gate insulating layer; 16, heavily doped source; 17, gate pattern; 18, lightly doped source; 19, heavily doped drain; 20, lightly doped drain. Specific embodiments

[0062] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments for a display substrate, its manufacturing method and a display device.

[0063] In the disclosed technology, such as Figure 1As shown, the pixel driving circuit of the LTPS OLED display product is a 7T1C circuit. Among them, the seven transistors in the 7T1C circuit are all LTPS transistors. The source and drain of the LTPS transistor are heavily doped source and drain formed by a heavily doped process, and the leakage current of the LTPS transistor is relatively large. For example, in the 7T1C circuit, the large leakage of the first transistor T1' and the second transistor T2' is the main cause of the sand grain mura. The reason is that for the 7T1C circuits driving different pixels on the display panel, when the data voltage (Vdata) is the same, due to the difference in the leakage of the first transistor T1' and the second transistor T2' in different 7T1C circuits, the voltage at the N1 point in different 7T1C circuits also has a difference. This causes a difference in the driving current of different pixels (OLED element D'), resulting in a difference in the emission brightness of different pixels, and then leading to the sand grain mura phenomenon.

[0064] In the disclosed technology, the sand grain mura of the LTPO (Low Temperature Polycrystalline Oxide) OLED (Organic Light-Emitting Diode) display product is significantly less severe than that of the LTPS OLED display product because the LTPO transistor uses an active layer of IGZO (indium gallium zinc oxide) material and has a lower leakage current. However, the application of LTPO technology to small and medium-sized display products is not yet mature, and there are many image quality problems related to the IGZO process.

[0065] In addition, in the disclosed technology, in the pixel driving circuit of the liquid crystal display panel, there is a case where the transistor uses an LTPS (Low Temperature Poly-Silicon) active layer and forms a heavily doped source and drain and a lightly doped source and drain of the transistor through heavy doping and light doping respectively. However, the current manufacturing process of the transistor is as follows: Figure 2 and Figure 3 As shown,

[0066] Step S1': Sequentially form an active layer intermediate pattern 11, a gate insulating layer 15, and a gate layer film 12 on the substrate 6, and coat a photoresist 13 on the gate layer film 12; use a mask plate to expose and develop the photoresist 13, retain the photoresist 13 in the area corresponding to the gate intermediate pattern 14, and remove the photoresist in the area outside the gate intermediate pattern 14.

[0067] Step S2': Form the gate intermediate pattern 14 through a single wet etching or dry etching process.

[0068] Step S3': Using the middle gate pattern 14 as a mask, perform a heavy doping process on the regions of the middle active layer pattern 11 that are not covered by the middle gate pattern 14 at the opposite ends of the middle gate pattern 14 to form a heavily doped source 16 and a heavily doped drain 19;

[0069] Step S4': Remove part of the photoresist on the middle gate pattern by ashing, and then form a gate pattern 17 through a dry etching process;

[0070] Step S5': Using the gate pattern 17 as a mask, perform a light doping process on the middle active layer pattern that is not covered by the gate pattern 17 at the opposite ends of the gate pattern 17 to form a lightly doped source 18, a lightly doped drain 20, and an active region 1;

[0071] Step S6': Finally, remove the photoresist on the gate pattern 17 through ashing and stripping processes.

[0072] The process of forming the heavily doped source / drain and lightly doped source / drain of the LTPS transistor is completed through a single mask process. During this process, when etching to form the gate pattern, due to the complexity of the gate pattern and the large slope of the gate film layer edge caused by the wet etching process, it is difficult to repair the gate pattern during the subsequent dry etching process, which affects the subsequent film deposition process. In addition, it is very difficult to accurately adjust the optimal region width of the lightly doped source / drain through the subsequent dry etching process, thus affecting the overall uniformity of the display of the liquid crystal display panel.

[0073] In view of the above problems existing in the disclosed technology, an embodiment of the present invention provides a display substrate, as Figure 4 and Figure 5 shown, including a plurality of pixel driving circuits; a plurality of light-emitting elements D, which are connected to the plurality of pixel driving circuits in one-to-one correspondence; the pixel driving circuit includes a driving transistor T3, a threshold compensation transistor T2, a first reset transistor T1, and a data writing transistor T4; the gate of the driving transistor T3 is connected to the first pole of the threshold compensation transistor T2 and the first pole of the first reset transistor T1; the first pole of the driving transistor T3 is connected to the second pole of the data writing transistor T4; the second pole of the driving transistor T3 is connected to the second pole of the threshold compensation transistor T2 and the anode of the light-emitting element D; the driving transistor T3, the threshold compensation transistor T2, the first reset transistor T1, and the data writing transistor T4 each include a low-temperature polysilicon active region 1; and their first poles each include a first heavily doped region 2, and their second poles each include a second heavily doped region 3; the first heavily doped region 2 and the second heavily doped region 3 are located at opposite ends of the active region 1; the first pole of the threshold compensation transistor T2 and / or the first reset transistor T1 further includes a first lightly doped region 4, and its second pole further includes a second lightly doped region 5; the first lightly doped region 4 is located between the first heavily doped region 2 and the active region 1; the second lightly doped region 5 is located between the second heavily doped region 3 and the active region 1.

[0074] Among them, the pixel driving circuit further includes a storage capacitor C, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7; the gate of the threshold compensation transistor T2 and the gate of the data writing transistor T4 are connected to the scanning line Gate; the first pole of the data writing transistor T4 is connected to the data line; the data line provides a data voltage signal Vdata; the gate of the first reset transistor T1 and the gate of the second reset transistor T7 are connected to the reset control line Reset; the second pole of the first reset transistor T1 and the second pole of the second reset transistor T2 are connected to the reset power supply terminal Vini; the first pole of the second reset transistor T7 and the second pole of the second light-emitting control transistor T6 are connected to the anode of the light-emitting element D; the gate of the second light-emitting control transistor T6 and the gate of the first light-emitting control transistor T5 are connected to the light-emitting control line EM; the first pole of the second light-emitting control transistor T6 is connected to the second pole of the driving transistor T3; the second pole of the first light-emitting control transistor T5 is connected to the first pole of the driving transistor T3; the first pole of the first light-emitting control transistor T5 and the first electrode plate of the storage capacitor C are connected to the first potential terminal VDD; the second electrode plate of the storage capacitor C is connected to the gate of the driving transistor T3; the cathode of the light-emitting element D is connected to the second potential terminal VSS.

[0075] In this embodiment, the light-emitting device D may be an organic light-emitting diode (OLED); of course, the light-emitting device D may also be a micro inorganic light-emitting diode. Further, it may be a current-type light-emitting diode, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED). In this embodiment, the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T1, and the second reset transistor T7 are all P-type transistors.

[0076] In this embodiment, as Figure 6 shown, the driving method of the above pixel driving circuit may include the following stages:

[0077] Reset stage (t1): A low-level signal is written to the reset control line Reset, and high-level signals are written to the scan line Gate and the emission control line EM; the first reset transistor T1 and the second reset transistor T7 are turned on, and the initial voltage of the reset power supply terminal Vini is written to the gate of the driving transistor T3 through the first reset transistor T1, preparing for the writing of the data voltage signal Vdata of the next frame. The initial voltage of the reset power supply terminal Vini is written to the anode of the light-emitting device D through the second reset transistor T7 (the initial voltage ≤ the potential of the second potential terminal VSS), so that the light-emitting device D is no longer in the forward conduction state, and the internal electric field formed by the directional movement of impurity ions in the light-emitting device D gradually disappears, thereby restoring the characteristics of the light-emitting device D.

[0078] Data writing and threshold compensation stage (t2): A low-level signal is written to the scan line Gate, and high-level signals are written to the reset control line Reset and the emission control line EM; the data writing transistor T4 and the threshold compensation transistor T2 are turned on. The driving transistor T3 is connected by the threshold compensation transistor T2 to form a diode structure, and the data voltage signal Vdata written on the data line is written to the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off. The gate voltage of the driving transistor T3 is Vdata + Vth (Vth < 0, Vth is the threshold voltage of the driving transistor T3), and is stored in the storage capacitor C. The voltages of the first plate and the second plate of the storage capacitor C are Vdata + Vth and the potential Vdd of the first potential terminal VDD, respectively.

[0079] Emission stage (t3): A low-level signal is written to the emission control line EM, and high-level signals are written to the scan line Gate and the reset control line Reset. The first emission control transistor T5 and the second emission control transistor T6 are both turned on. The first pole of the driving transistor T3 is connected to the first potential terminal VDD, and the voltage of the first pole of the driving transistor T3 instantaneously changes from Vdata in the previous stage to Vdd. The light-emitting device D emits light under the drive of the driving transistor T3. At this time, the driving transistor T3 operates in the saturation region. The gate voltage of the driving transistor T3 is Vdata + Vth, and the voltage of the first pole of the driving transistor T3 is Vdd. Therefore, the voltage between the gate and the first pole of the driving transistor T3 is: Vgs = (Vdata + Vth) - Vdd until the reset stage of the next frame.

[0080] The emission current of the light-emitting device D is equal to the current I flowing through the driving transistor T3 D , and its expression is as follows:

[0081] I D = β(Vgs - Vth) 2

[0082] = β(Vdata + Vth - Vdd - Vth) 2

[0083] = β(Vdata - Vdd) 2 (1)

[0084] Wherein, μ n is the electron mobility of the driving transistor T3, C ox is the insulation capacitance per unit area, is the aspect ratio of the driving transistor T3.

[0085] In this embodiment, based on the above structure setting and the above driving process of the pixel driving circuit, the first pole of the threshold compensation transistor T2 and / or the first reset transistor T1 can reduce the leakage current of the threshold compensation transistor T2 and / or the first reset transistor T1 by setting the first lightly doped region 4, and the second pole can reduce the leakage current by setting the second lightly doped region 5. At the same time, the leakage current difference of the threshold compensation transistor T2 and / or the first reset transistor T1 in different pixel driving circuits can be reduced, so as to ensure that when the data voltage (Vdata) is the same, the gate voltage (i.e., the voltage at point N1) difference of the driving transistor T3 in different pixel driving circuits is reduced, and then the driving currents of different pixel driving circuits for different light-emitting elements D tend to be consistent, so that the light-emitting brightness of different light-emitting elements D tends to be consistent, improving the luminance uniformity of different regions of the pure color picture displayed on the display substrate, and improving or avoiding the sand-grain mura defect of the display picture.

[0086] Optionally, as Figure 5 shown, the display substrate further includes a substrate 6; the threshold compensation transistor and / or the first reset transistor includes a first gate 7 and a second gate 8; the first gate 7 and the second gate 8 are stacked in sequence away from the substrate 6, and a first gate insulating layer 9 is provided between the first gate 7 and the second gate 8; the orthographic projections of the first gate 7 and the second gate 8 on the substrate 6 overlap with the orthographic projection of the active region 1 on the substrate 6. That is, the threshold compensation transistor and / or the first reset transistor adopt a double-gate structure, so that the leakage current of the threshold compensation transistor and / or the first reset transistor can be further reduced, thereby further reducing the difference in the gate voltage (i.e., the voltage at point N1) of the driving transistor in different pixel driving circuits, and further making the driving currents of different pixel driving circuits for different light-emitting elements tend to be consistent, so that the light-emitting brightness of different light-emitting elements tends to be more consistent.

[0087] Optionally, the first gate 7 and the second gate 8 are located on the side of the active region 1 away from the substrate 6, and a second gate insulating layer 10 is provided between the first gate 7 and the active region 1. That is, the threshold compensation transistor and the first reset transistor in this embodiment adopt a top-gate transistor. Of course, the threshold compensation transistor and the first reset transistor can also adopt a bottom-gate transistor.

[0088] Optionally, in this embodiment, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor each include a low-temperature polysilicon active region. Moreover, the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are all set to a single-gate structure, that is, only one gate is provided for each of them.

[0089] Based on the above structure of the display substrate, an embodiment of the present invention further provides a method for manufacturing the display substrate, including: preparing a plurality of pixel driving circuits; preparing a plurality of light-emitting elements; preparing the pixel driving circuit includes preparing a driving transistor, a threshold compensation transistor, a first reset transistor, and a data writing transistor; preparing the threshold compensation transistor and / or the first reset transistor includes: forming an intermediate pattern of the active layer made of a low-temperature polysilicon material; performing heavy doping on regions at opposite ends of the intermediate pattern of the active layer through a first masking process to form a first heavily doped region and a second heavily doped region; performing light doping on regions at opposite ends of the intermediate pattern of the active layer close to the first heavily doped region and the second heavily doped region through a second masking process to form a first lightly doped region, a second lightly doped region, and an active region located between the first lightly doped region and the second lightly doped region.

[0090] Optionally, performing heavy doping on regions at opposite ends of the active layer through a first masking process to form a first heavily doped region and a second heavily doped region includes: as Figure 7 shown

[0091] Step S1: Sequentially form an intermediate pattern 11 of the active layer, a gate insulating layer (i.e., the second gate insulating layer 10), and a gate layer film 12 on a substrate 6, and apply a photoresist 13 on the gate layer film 12; use a first mask plate to expose and develop the photoresist 13, retain the photoresist 13 in the region corresponding to the intermediate gate pattern 14, and remove the photoresist in regions outside the intermediate gate pattern 14.

[0092] Among them, preparing the pixel driving circuit further includes preparing a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor; this step S1 is simultaneously used as the first step for preparing the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor.

[0093] In this step S1, in order to simultaneously prepare the corresponding film layers of the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor, while using the first mask plate to expose and develop the photoresist, retain the photoresist in the region corresponding to the gate pattern, and remove the photoresist in regions outside the gate pattern.

[0094] Step S2: Form the intermediate gate pattern 14 through a single dry etching process.

[0095] In this step, in order to simultaneously prepare the corresponding film layers, the gate patterns of the driving transistor, data writing transistor, first light-emitting control transistor, second light-emitting control transistor, and second reset transistor are formed through the same dry etching process.

[0096] Step S3: Using the gate intermediate pattern 14 as a mask, a heavy doping process is performed on the regions of the active layer intermediate pattern 11 that are not covered by the gate intermediate pattern 14 at opposite ends of the gate intermediate pattern 14, to form a first heavily doped region 2 and a second heavily doped region 3.

[0097] In this step, using the gate patterns of the driving transistor, data writing transistor, first light-emitting control transistor, second light-emitting control transistor, and second reset transistor as masks, a heavy doping process is performed on the regions of the active layer intermediate pattern that are not covered by the gate patterns at opposite ends of their gate patterns, to form the first heavily doped regions and second heavily doped regions of the driving transistor, data writing transistor, first light-emitting control transistor, second light-emitting control transistor, and second reset transistor.

[0098] Step S4: The photoresist on the gate intermediate pattern 14 is removed through ashing and stripping processes.

[0099] In this step, the photoresist on the gate patterns is simultaneously removed through ashing and stripping processes, thereby completing the preparation of the driving transistor, data writing transistor, first light-emitting control transistor, second light-emitting control transistor, and second reset transistor.

[0100] Optionally, through a second masking process, the regions of the opposite ends of the active layer intermediate pattern close to the first heavily doped region and the second heavily doped region are lightly doped to form a first lightly doped region, a second lightly doped region, and an active region located between the first lightly doped region and the second lightly doped region, including: as Figure 8 shown

[0101] Step S5: Apply photoresist on the gate intermediate pattern 14, use a second mask plate to expose and develop the photoresist, retain the photoresist 13 in the region corresponding to the gate pattern (i.e., the first gate 7 pattern), and remove the photoresist in the regions outside the gate pattern;

[0102] Step S6: Form a gate pattern (i.e., the first gate 7 pattern) through a single dry etching process;

[0103] Step S7: Using the gate pattern as a mask, a light doping process is performed on the regions of the active layer intermediate pattern 11 that are not covered by the gate pattern at opposite ends of the gate pattern, to form a first lightly doped region 4 and a second lightly doped region 5; the portion between the first lightly doped region 4 and the second lightly doped region 5 is the active region 1;

[0104] Step S8: Remove the photoresist on the gate pattern through ashing and stripping processes.

[0105] In this embodiment, the method for preparing the display substrate further includes sequentially depositing a first gate insulating layer and a second gate film layer on the substrate after completing Step S8, and then forming the patterns of the second gates of the threshold compensation transistor and / or the first reset transistor through a patterning process.

[0106] Optionally, in this embodiment, the light-emitting element can be prepared by using a conventional evaporation process, which will not be elaborated here.

[0107] In the preparation process of this display substrate, the first heavily doped region and the second heavily doped region of the threshold compensation transistor and / or the first reset transistor are formed through a first masking process, and then the gates, the first lightly doped region, the second lightly doped region, and the active region of the threshold compensation transistor and / or the first reset transistor are formed through a second masking process. Compared with the technical solution in the prior art where the LTPS transistor with both a heavily doped region and a lightly doped region in the liquid crystal display panel is prepared through a single masking process, in the present invention, by using two masking processes to prepare each film layer of the threshold compensation transistor and / or the first reset transistor, a good complex gate pattern can be formed, and at the same time, the widths of the first lightly doped region and the second lightly doped region can be ensured to be more accurate, thereby ensuring the overall uniformity of each film layer in the display substrate. Furthermore, it is beneficial to reduce the leakage current of the threshold compensation transistor and / or the first reset transistor, and at the same time, it is beneficial to reduce the leakage current difference between the threshold compensation transistors and / or the first reset transistors in different pixel driving circuits. Ensure that when the data voltage is the same, the gate voltage difference of the driving transistors in different pixel driving circuits is reduced, so that the driving currents of the driving transistors for different light-emitting elements tend to be consistent, so that the light-emitting brightness of different light-emitting elements tends to be consistent, and the brightness uniformity of different regions of the pure color picture displayed by the display substrate is improved, and the sand grain mura defect of the display picture is improved or avoided.

[0108] An embodiment of the present invention further provides a display device, including the display substrate in the above embodiment.

[0109] By using the display substrate in the above embodiment, the brightness uniformity of different regions of the pure color picture displayed by the display device is improved, and the sand grain mura defect of the display picture of the display device is improved or avoided.

[0110] The display device provided by the present invention can be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a monitor, a mobile phone, a navigator, etc.

[0111] It will be understood that the above embodiments are merely exemplary embodiments adopted for the purpose of illustrating the principles of the present invention, and the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A method for preparing a display substrate, characterized in that Including: Preparing a plurality of pixel driving circuits; Preparing a plurality of light-emitting elements; Preparing the pixel driving circuit includes preparing a driving transistor, a threshold compensation transistor, a first reset transistor, and a data writing transistor; Preparing the threshold compensation transistor and / or the first reset transistor includes: forming an intermediate pattern of an active layer of a low-temperature polycrystalline silicon material; Through a first masking process, the regions at opposite ends of the intermediate pattern of the active layer are heavily doped to form a first heavily doped region and a second heavily doped region; Through a second masking process, the regions at opposite ends of the intermediate pattern of the active layer near the first heavily doped region and the second heavily doped region are lightly doped to form a first lightly doped region, a second lightly doped region, and an active region located between the first lightly doped region and the second lightly doped region.

2. The manufacturing method of the display substrate according to claim 1, wherein The step of forming the first heavily doped region and the second heavily doped region by heavily doping the regions at opposite ends of the active layer through the first masking process includes: Sequentially forming an intermediate pattern of an active layer, a gate insulating layer, and a gate layer film on a substrate, and coating a photoresist on the gate layer film; using a first mask plate to expose and develop the photoresist, retaining the photoresist in the region corresponding to the intermediate gate pattern, and removing the photoresist in the regions other than the intermediate gate pattern; Forming the intermediate gate pattern through a single dry etching process; Using the intermediate gate pattern as a mask, performing a heavy doping process on the regions of the intermediate pattern of the active layer that are not covered by the intermediate gate pattern at opposite ends of the intermediate gate pattern to form the first heavily doped region and the second heavily doped region; Removing the photoresist on the intermediate gate pattern through an ashing and stripping process.

3. The manufacturing method of the display substrate according to claim 2, wherein, The step of forming the first lightly doped region, the second lightly doped region, and the active region located between the first lightly doped region and the second lightly doped region by lightly doping the regions at opposite ends of the intermediate pattern of the active layer near the first heavily doped region and the second heavily doped region through the second masking process includes: Coating a photoresist on the intermediate gate pattern, using a second mask plate to expose and develop the photoresist, retaining the photoresist in the region corresponding to the gate pattern, and removing the photoresist in the regions other than the gate pattern; Forming the gate pattern through a single dry etching process; Using the gate pattern as a mask, performing a light doping process on the regions of the intermediate pattern of the active layer that are not covered by the gate pattern at opposite ends of the gate pattern to form the first lightly doped region and the second lightly doped region; the portion located between the first lightly doped region and the second lightly doped region is the active region; Removing the photoresist on the gate pattern through an ashing and stripping process.

4. The method for preparing a display substrate according to claim 2, wherein, Preparing the pixel driving circuit further includes preparing a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor; Preparing the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor includes: An active layer intermediate pattern, a gate insulating layer, and a gate layer film are sequentially formed on a substrate, and a photoresist is coated on the gate layer film; the photoresist is exposed and developed using the first mask plate, the photoresist in the area corresponding to the gate pattern is retained, and the photoresist in the area other than the gate pattern is removed; The gate pattern is formed through a single dry etching process; Using the gate pattern as a mask, a heavy doping process is performed on the areas of the active layer intermediate pattern that are not covered by the gate pattern at opposite ends of the gate pattern to form the first heavily doped region and the second heavily doped region; The photoresist on the gate pattern is removed through ashing and stripping processes.

5. A display substrate prepared by using the preparation method according to any one of claims 1-4, including a plurality of pixel driving circuits; A plurality of light-emitting elements, which are connected to the plurality of pixel driving circuits in a one-to-one correspondence; The pixel driving circuit includes a driving transistor, a threshold compensation transistor, a first reset transistor, and a data writing transistor; The gate of the driving transistor is connected to the first pole of the threshold compensation transistor and the first pole of the first reset transistor; the first pole of the driving transistor is connected to the second pole of the data writing transistor; the second pole of the driving transistor is connected to the second pole of the threshold compensation transistor and the anode of the light-emitting element; The driving transistor, the threshold compensation transistor, the first reset transistor, and the data writing transistor each include a low-temperature polycrystalline silicon active region; and their first poles each include a first heavily doped region, and their second poles each include a second heavily doped region; the first heavily doped region and the second heavily doped region are located at opposite ends of the active region; Characterized in that the first pole of the threshold compensation transistor and / or the first reset transistor further includes a first lightly doped region, and its second pole further includes a second lightly doped region; The first lightly doped region is located between the first heavily doped region and the active region; the second lightly doped region is located between the second heavily doped region and the active region.

6. The display substrate according to claim 5, wherein It further includes a substrate; The threshold compensation transistor and / or the first reset transistor includes a first gate and a second gate; The first gate and the second gate are stacked in sequence away from the substrate, and a first gate insulating layer is provided between the first gate and the second gate; The orthographic projections of the first gate and the second gate on the substrate overlap with the orthographic projection of the active region on the substrate.

7. The display substrate according to claim 6, wherein The first gate and the second gate are located on the side of the active region away from the substrate, and a second gate insulating layer is provided between the first gate and the active region.

8. The display substrate according to claim 5, wherein The pixel driving circuit further includes a storage capacitor, a first light-emitting control transistor, a second light-emitting control transistor, and a second reset transistor; The gate of the threshold compensation transistor and the gate of the data writing transistor are connected to a scan line; the first pole of the data writing transistor is connected to a data line; The gate of the first reset transistor and the gate of the second reset transistor are connected to a reset control line; the second pole of the first reset transistor and the second pole of the second reset transistor are connected to a reset power supply terminal; The first pole of the second reset transistor and the second pole of the second light-emitting control transistor are connected to the anode of the light-emitting element; The gate of the second light-emitting control transistor and the gate of the first light-emitting control transistor are connected to the light-emitting control line; The first pole of the second light-emitting control transistor is connected to the second pole of the driving transistor; The second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor; the first pole of the first light-emitting control transistor and the first plate of the storage capacitor are connected to the first potential terminal; The second plate of the storage capacitor is connected to the gate of the driving transistor; The cathode of the light-emitting element is connected to the second potential terminal.

9. The display substrate according to claim 8, wherein The first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor each include a low-temperature polycrystalline silicon active region.

10. A display device, characterized in that, A display substrate including any one of claims 5-9.

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