Electrical amplifier

Abstract

An exemplary embodiment of the invention relates to an electrical amplifier (10) comprising a differential preamplifier (PA) having a first output port and a second output port, and a downstream amplifier stage (DAS) having a first output unit and a second output unit; wherein the first output unit is connected to the first output port of the differential preamplifier (PA) and the second output unit is connected to the second output port of the differential preamplifier (PA); and wherein a negative impedance converter is electrically located in at least one of said differential preamplifier (PA) and said downstream amplifier stage (DAS).

Description

TECHNICAL FIELD

[0001] The present invention relates to an electrical amplifier and to an apparatus comprising an electrical amplifier and a modulator. BACKGROUND

[0002] Fast analog drivers are key components in high-speed optical transceivers; however, as data rates increase beyond 40 Gb / s, it becomes increasingly difficult to implement low-power amplifiers and high-bandwidth driver circuits. Optical modulators require large driving currents or large voltage swings to achieve the necessary speed, which in turn pulls for large output buffers or large gain stages, both of which lead to higher power consumption and reduced bandwidth, further exacerbating the problem.

[0003] Several equalization techniques can be employed to extend the bandwidth of optical modulators, such as feed-forward equalization (hereinafter referred to as FFE method) or continuous-time linear equalization (hereinafter referred to as CTLE method), with the latter consuming less power; however, negative Miller capacitance (hereinafter referred to as NMC method) or inductive peaking is commonly used to counteract the parasitic capacitance of large transistors, as shown in Chinese patent application CN104617483 and in the paper by S. Sedighi et al. entitled "Low-Power 20-Gbs SiGe BiCMOS Driver with 2.5V Output Swing" in IEEE International Microwave Symposium Digest (2012).

[0004] The main drawback of using the FFE method and the CTLE method is that both reduce the low-frequency gain, so the bandwidth improvement comes at the expense of the electro-optic effect. Regarding inductive peaking, on-chip inductors can consume a large area, increasing the chip cost, and can couple to other sensitive parts of the circuit; therefore, inductance-free circuits can be desired. In this regard, a better approach is the negative Miller capacitance (NMC), in which two additional cross-coupled capacitors are used to neutralize the parasitic base-collector capacitance of the transistor. Since NMC is based on the positive feedback generated by the cross-coupled capacitors, stability is always an issue. Moreover, since the Miller effect is reduced, the bandwidth enhancement obtained decreases for higher values of the emitter feedback resistance.

[0005] Object of the present invention

[0006] In view of the above, it is an object of the present invention to provide an improved electrical amplifier.

[0007] It is a further object of the present invention to provide an improved apparatus comprising at least one electrical amplifier and at least one modulator. SUMMARY

[0008] An exemplary embodiment of the invention relates to an electrical amplifier comprising a differential preamplifier having a first output port and a second output port, and a downstream amplifier stage having a first output unit and a second output unit; wherein the first output unit is connected to the first output port of the differential preamplifier and the second output unit is connected to the second output port of the differential preamplifier; and wherein a negative impedance converter is electrically located in at least one of said differential preamplifier and said downstream amplifier stage.

[0009] The above exemplary embodiments of the invention can provide a large bandwidth and reduced stability problems. The basic idea is to use a negative capacitance which can neutralize not only the parasitic capacitance of the transistor of the preamplifier but also the load capacitance of the subsequent downstream amplifier stage.

[0010] The negative impedance converter is preferably configured to provide a negative capacitance.

[0011] The negative impedance converter can be electrically located in the differential preamplifier and apply a negative capacitance to the first output port and the second output port of the differential preamplifier.

[0012] The differential preamplifier preferably comprises a first and a second transistor.

[0013] The emitter of the first transistor can provide the first output port of the differential preamplifier.

[0014] The emitter of the second transistor can provide the second output port of the differential preamplifier.

[0015] The negative impedance converter preferably applies a negative capacitance to the emitters of the first and the second transistor.

[0016] The collector of the third transistor can be connected to the base of the fourth transistor.

[0017] The collector of the fourth transistor can be connected to the base of the third transistor.

[0018] The at least one capacitor preferably connects the emitters of the third and the fourth transistor.

[0019] The third transistor, the fourth transistor and the at least one capacitor preferably form at least part of said negative impedance converter or are at least part of said negative impedance converter.

[0020] The emitter of the first transistor is preferably connected to both the collector of the third transistor and the base of the fourth transistor. The emitter of the second transistor is preferably connected to both the collector of the fourth transistor and the base of the third transistor.

[0021] The base of the first transistor can form a first input port of the differential preamplifier.

[0022] The base of the second transistor can form a second input port of the differential preamplifier.

[0023] The emitters of the third and fourth transistors are preferably connected by means of the first and second capacitors.

[0024] The first and second capacitors are preferably connected in series.

[0025] The first and second capacitors can be variable.

[0026] The emitter of the first transistor can be connected to the base of the fourth transistor via a first resistor.

[0027] The emitter of the second transistor can be connected to the base of the third transistor via a second resistor.

[0028] Alternatively or additionally, the negative impedance converter can be electrically located in the downstream amplifier stage and can apply a negative capacitance to the downstream amplifier stage.

[0029] In the latter embodiment, the downstream amplifier can comprise the first and second transistors.

[0030] The emitter of at least one of the first and second transistors (of the downstream amplifier stage) preferably provides an output port of the downstream amplifier.

[0031] The negative impedance converter preferably couples the emitters of the first and second transistors of the downstream amplifier stage and applies a negative capacitance to the emitters of the first and second transistors.

[0032] The collector of the third transistor (of the downstream amplifier stage) is preferably connected to the base of the fourth transistor (of the downstream amplifier stage).

[0033] The collector of the fourth transistor is preferably connected to the base of the third transistor.

[0034] At least one capacitor (of the downstream amplifier stage) is preferably connected to the emitters of the third and fourth transistors.

[0035] The third transistor, the fourth transistor and the at least one capacitor preferably form at least part of or are at least part of a negative impedance converter of the downstream amplifier stage.

[0036] The emitter of the first transistor is preferably connected to both the collector of the third transistor and the base of the fourth transistor.

[0037] The emitter of the second transistor is preferably connected to both the collector of the fourth transistor and the base of the third transistor.

[0038] The emitter of the first transistor is preferably connected to the base of the fourth transistor via a first resistance.

[0039] The emitter of the second transistor is preferably connected to the base of the third transistor via a second resistance.

[0040] The bases of the third and fourth transistors are preferably connected via a third resistance.

[0041] The emitter of the first transistor can be connected to the base of the fourth transistor via a first auxiliary capacitor. The emitter of the second transistor can be connected to the base of the third transistor via a second auxiliary capacitor.

[0042] The bases of the third and fourth transistors are preferably connected via a third resistance and a fourth resistance.

[0043] The third and fourth resistances are preferably connected in series.

[0044] A midpoint between the third and fourth resistances is preferably connected to a voltage source which determines the current through the third and fourth transistors.

[0045] The emitters of the third and fourth transistors are preferably connected to ground via a resistor.

[0046] The base of the first transistor can form a first input port of a downstream amplifier stage.

[0047] The base of the second transistor can form a second input port of a downstream amplifier stage.

[0048] The negative impedance converter can comprise a first capacitor and a second capacitor. The first and second capacitors are preferably connected in series. The first and second capacitors are preferably variable.

[0049] The amplifier can comprise at least two differential preamplifiers.

[0050] The negative impedance converter is preferably located in both of the at least two differential preamplifiers.

[0051] The negative impedance converters are preferably each configured to provide a negative capacitance.

[0052] Each of the negative impedance converters can apply its negative capacitance to both output ports of the allocated differential preamplifier.

[0053] In all of the above configurations, the amplifier can comprise a single output port for driving a load in a single-ended configuration.

[0054] Alternatively or additionally, the amplifier can comprise two output ports for driving the load differentially.

[0055] Another embodiment of the invention relates to an apparatus comprising at least one electrical amplifier having a negative impedance converter and at least one modulator driven by the at least one amplifier.

[0056] The amplifier can drive the modulator in push-pull mode. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order that the manner in which the above-recited and other advantages of the present invention are obtained and thus can be understood in detail, a more particular description of the invention summarized above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be understood that the drawings are merely schematic and are not drawn to scale, that they are merely intended to aid in understanding the invention and are not intended to limit the scope of the invention, and that where appropriate the use of identical reference numerals in different figures serves to designate the same, similar or other pertinent items. It is to be understood that the figures are merely meant to aid in the description of the embodiments of the applications and are not meant in any way to limit the scope of the applications, and that the use of identical reference numerals in different figures serves to designate the same, similar or other pertinent items.

[0058] Figure 1 A first exemplary embodiment of an amplifier and apparatus according to the invention is shown,

[0059] Figure 2 A comparison is shown with a comparable amplifier without a negative impedance converter NIC, Figure 1 Achievable bandwidth of the amplifier (NIC approach),

[0060] Figure 3 A second exemplary embodiment of an amplifier and apparatus according to the invention is shown,

[0061] Figure 4 An equivalent circuit of the second exemplary embodiment is shown,

[0062] Figure 5 A third exemplary embodiment of an amplifier and apparatus according to the invention is shown,

[0063] Figure 6 An equivalent circuit of the third exemplary embodiment is shown,

[0064] Figure 7 A fourth exemplary embodiment of an amplifier and apparatus according to the invention is shown,

[0065] Figure 8 Gain dependence on maximum bandwidth of the fourth embodiment is shown with and without a negative impedance converter NIC,

[0066] Figure 9 A fifth exemplary embodiment of an amplifier and apparatus according to the invention is shown,

[0067] Figure 10 A sixth exemplary embodiment of an amplifier and apparatus according to the invention is shown, and

[0068] Figure 11 A seventh exemplary embodiment of an amplifier and device according to the present application is shown. DETAILED DESCRIPTION

[0069] The preferred embodiments of the present application will be best understood by reference to the drawings. It will be readily appreciated that the present application, as generally described and illustrated in the figures herein, can be varied extensively. Therefore, the following more detailed description of the exemplary embodiments of the present application, as represented in the figures, is not intended to limit the scope of the application as claimed, but is merely representative of presently preferred embodiments of the application.

[0070] Figure 1 A first embodiment of an electrical amplifier 10 according to the present application is shown, which is provided with a supply voltage V CC .

[0071] The amplifier 10 comprises a differential preamplifier PA having a first output port PAol and a second output port PAo2.

[0072] The downstream amplifier stage DAS comprises a first output unit OU1 and a second output unit OU2. The first output unit OU1 is connected to the first output port PAol of the differential preamplifier PA, and the second output unit OU2 is connected to the second output port PAo2 of the differential preamplifier PA.

[0073] The negative impedance converter NIC is electrically located in the differential preamplifier PA. The negative impedance converter NIC provides a negative capacitance, and applies the negative capacitance to the first output port PAol and the second output port PAo2 of the differential preamplifier PA.

[0074] The differential preamplifier PA comprises a first transistor T1 and a second transistor T2. The emitter of the first transistor T1 provides the first output port PAol of the differential preamplifier PA. The emitter of the second transistor T2 provides the second output port PAo2 of the differential preamplifier PA. The negative impedance converter NIC applies the negative capacitance to the emitters of the first transistor T1 and the second transistor T2.

[0075] The negative impedance converter NIC is formed by a third transistor T3, a fourth transistor T4 and a capacitor C NIC .

[0076] The collector of the third transistor T3 is connected to the base of the fourth transistor T4. The collector of the fourth transistor T4 is connected to the base of the third transistor T3. The emitters of the third transistor T3 and the fourth transistor T4 are connected by the capacitor C NIC .

[0077] In Figure 1In an exemplary embodiment, the emitter of the first transistor T1 is connected to both the collector of the third transistor T3 and the base of the fourth transistor T4. The emitter of the second transistor T2 is connected to both the collector of the fourth transistor T4 and the base of the third transistor T3.

[0078] The base of the first transistor T1 forms the first input port PAi1 of the differential preamplifier PA. The base of the second transistor T2 forms the second input port PAi2 of the differential preamplifier PA. Input ports PAi1 and PAi2 are differentially supplied with the input signal V. IN .

[0079] exist Figure 1 In the embodiment, each of the output units OU1 and OU2 includes transistors T5 / T6 and resistor R. GAIN and current source SI. Output units OU1 and OU2 are connected through capacitor C. DEG and resistor R DEG To couple.

[0080] The emitter of one of the transistors (here, transistor T6) provides the output port of the downstream amplifier DAS to which the load LOAD is connected.

[0081] The above reference Figure 1 The exemplary embodiments described provide large bandwidth with little or no stability issues. The basic idea is to use the negative capacitance of the negative impedance converter NIC, which neutralizes not only the parasitic capacitances of transistors T1 and T2, but also the entire load capacitance of the downstream amplifier stage DAS. Due to capacitor C... NIC The equivalent impedance Z seen at the collector of the first transistor T3 is across the two emitters of the cross-coupled transistors T3 and T4. NIC yes:

[0082]

[0083] The variables in the above equation and the variables in the below equation are defined in a separate list of the attached formula symbols.

[0084] If we use C LOAD This represents the equivalent load capacitance of the downstream amplifier stage DAS, which can, in principle, be increased by adding C. NIC =C LOAD To neutralize the capacitor.

[0085] Figure 1 The negative impedance converter NIC does not result in any significant power loss. Figure 1In the configuration shown, the minimum voltage at the base of transistor T1 is equal to the sum of the base-emitter voltage and the saturation voltage of the current mirror provided by current source SI. It is therefore possible to accommodate a negative impedance converter NIC over the emitter follower current mirror, as shown in Figure 1 without the need for additional voltage headroom, i.e. the power supply and total power consumption remain unchanged. Figure 1 The total transfer function of the amplifier is:

[0086]

[0087] As long as r e2 ≥ r e1 , stability is ensured because none of the coefficients will be negative. Assuming that transistors T1 and T2 have the same size r e = r e1 = r e2 , and considering that the pole determined by coefficient C4 is at very high frequencies, we can approximate equation (2) as:

[0088]

[0089] The frequency response of amplifier 10 with negative impedance converter NIC is:

[0090]

[0091] Figure 2 It is shown (based on equations (3) and (4)) that the maximum achievable bandwidth of amplifier 10 (using the NIC method) is Figure 1 compared to a comparable amplifier without negative impedance converter NIC but based on the NMC method. It can be seen that, at a certain gain, the NIC method is superior to the NMC method. To explain this, let us further simplify the previous equations, ignoring the effects of the gain resistance and the base inductance, and considering that the zero point determined by coefficient al is usually at very high frequencies:

[0092]

[0093] From equation (5), the maximum bandwidth is obtained when m = V2:

[0094]

[0095] The frequency response without negative impedance converter NIC can be approximated as:

[0096]

[0097] If we impose C NMC = C BC , the resulting bandwidth will be:

[0098]

[0099] We can now compare equations (6) and (8) to understand when the negative impedance converter NIC provides greater bandwidth:

[0100]

[0101] In the previous example, C BE = 5.5 C BC Therefore, the performance of the negative impedance converter NIC is superior to the NMC method when A < 17.3 dB. Since the single-stage gain in high-speed circuits never exceeds 20 dB, we can conclude that the NIC method is generally more advantageous than the NMC method. In fact, when the load capacitance at the gain node is also taken into account, the threshold gain will move to a higher value.

[0102] Figure 3 A second exemplary embodiment of the amplifier 10 according to the application is depicted. In this embodiment, two variable capacitors C VAR replace the two fixed capacitors CNIC in Figure 1 . The variable capacitors C VAR provide a variable inductance. Figure 4 The equivalent circuit is shown in . Implementing a variable inductance with the NMC method is not feasible, the output bandwidth being severely impacted by the well capacitance, while in the NIC method, the well capacitance is absorbed by the virtual ground thanks to the differential nature of the circuit. The variable capacitors can be used to modify the frequency behavior of the circuit. In fact, when m = V2 is chosen, a Butterworth filter shape is obtained, but other shapes (i.e. Bessel) or other frequency behaviors are possible.

[0103] Figure 5 A third exemplary embodiment of the amplifier 10 according to the application is depicted. Figure 5 The embodiment of includes two additional resistors R B . The emitter of the first transistor T1 is connected to the base of the fourth transistor T4 via a first resistor R B and the emitter of the second transistor T2 is connected to the base of the third transistor T3 via a second resistor R B .

[0104] In order to achieve a flatter gain and lower peaking, it is possible to adjust the value of k B . This can be achieved by introducing a resistor R B in series with the bases of the transistors T3 and T4, such that L B ' = T B · (r B + RB ), as Figure 6 shown in the equivalent circuit depicted in

[0105] Figure 7 A fourth exemplary embodiment of an amplifier 10 according to the application is depicted. Here, the negative impedance converter NIC is electrically located in the downstream amplifier stage DAS and applies a negative capacitance to the downstream amplifier stage DAS.

[0106] The downstream amplifier stage DAS comprises a first transistor T1 and a second transistor T2. The base of the first transistor T1 forms a first input port DASi1 of the downstream amplifier stage DAS; and the base of the second transistor T2 forms a second input port DASi2 of the downstream amplifier stage DAS. The emitter of one of the second transistors, here transistor T2, provides an output port of the downstream amplifier to which the load LOAD is connected.

[0107] The negative impedance converter NIC is coupled to the emitters of the first and second transistors T1, T2 of the downstream amplifier stage DAS and applies a negative capacitance to them.

[0108] The negative impedance converter NIC is formed by a third transistor T3, a fourth transistor T4 and a stacked capacitor formed by two capacitors C NIC connected in series. The collector of the third transistor T3 is connected to the base of the fourth transistor T4. The collector of the fourth transistor T4 is connected to the base of the third transistor T3. The two capacitors C NIC connect the emitters of the third and fourth transistors T3, T4.

[0109] In the embodiment of Figure 7 , the emitter of the first transistor T1 is connected to both the collector of the third transistor T3 and the base of the fourth transistor T4. The emitter of the second transistor T2 is connected to both the collector of the fourth transistor T4 and the base of the third transistor T3.

[0110] Figure 7 The embodiment of also allows to increase the bandwidth of a downstream modulator connected to the amplifier 10 as a load LOAD. Indeed, the NIC approach is advantageous in circuits driving heavy optical devices based on electro-optical effects, such as frequency modulators, EAMs, etc... as it can provide a low impedance driving circuit and an emitter follower. As mentioned above, the introduction of the NIC stage occurs without power dissipation.

[0111] This in turn means a reduction of the de-emphasis, which subsequently enhances the electro-optical effect. Indeed, for a circuit of Figure 7 without the NIC stage, we can write:

[0112]

[0113] Therefore, if we want to zero-point compensate for the poles R introduced by the load DEG C DEG =r e C LOAD The bandwidth will be expanded by a factor of 1+g m R DEG / 2, but the gain will decrease by the same factor. Therefore, either the electro-optic effect will decrease, or the voltage swing must be increased, thus requiring higher current or a higher gain resistor, which will again reduce the bandwidth. For Figure 7 For circuits with NIC level, ignoring inductive components, we can express the frequency response as:

[0114]

[0115] Since the maximum bandwidth 1.85ω0 is obtained when m=√2, we can simplify (11) to:

[0116]

[0117] Equation (12) shows that the zeros introduced by capacitive negative feedback must be compensated for by a time constant that is 1.85 times smaller. This means that, given the same C DEG The NIC method will require 1.85 times the smaller negative feedback resistor, corresponding to a larger 5.3dB (see [link]). Figure 8 ).

[0118] Figure 8 Demonstrating G at maximum bandwidth with and without a negative impedance converter NIC OUT .

[0119] Figure 9 A fifth exemplary embodiment of the amplifier 10 according to the present invention is depicted. The negative impedance converter NIC of this embodiment comprises two components with a value of N·R. D A resistor and a third resistor with a value of 2·RD.

[0120] The emitter of the first transistor T1 is connected to resistor NR. D One of them is connected to the base of the fourth transistor T4; and the emitter of the second transistor T2 is connected via resistor NR. D Another transistor is connected to the base of the third transistor T3. The bases of the third transistor T3 and the fourth transistor T4 are connected via the third resistor 2RD.

[0121] exist Figure 9 In some embodiments, a resistor divider may be used to reduce the collector-base voltage swing of the aforementioned pair, because the output voltage swing may be large enough to cause saturation of the cross-coupled pair. The resistor is connected at a DC level with... Figure 7the same way as in the embodiments described above, but in AC operation the voltage across the cross-coupled pair is reduced by a factor of (N+1). As long as the size of transistors T3 and T4 is (N+1) times the size of transistors T1 and T2 and if N • R D >>r e4 , the validity of equations (1) to (11) holds. It has to be noted that when C NIC = C LOAD / √2(N+1), the maximum bandwidth will be reached.

[0122] Figure 10 A sixth exemplary embodiment of an amplifier 10 according to the present application is depicted. Here, the emitter of the first transistor T1 is connected to the base of the fourth transistor T4 via a first auxiliary capacitor C D . The emitter of the second transistor T2 is connected to the base of the third transistor T3 via a second auxiliary capacitor C D .

[0123] Furthermore, the bases of the third transistor T3 and the fourth transistor T4 are connected via two resistors R BIAS . The resistors R BIAS are connected in series. The midpoint between the resistors R BIAS is connected to a voltage source determining the current in the third transistor T3 and the fourth transistor T4.

[0124] Furthermore, the emitters of the third transistor T3 and the fourth transistor T4 are connected to ground via a resistor R E instead of a current source.

[0125] If in the frequency range of interest, R E >>1 / (S • C NIC ), the scaling factor will be N = C B / C D .

[0126] As long as the size of transistors T3 and T4 is (N+1) times the size of transistors T1 and T2, the validity of equations (1) to (11) holds. When C NIC = C LOAD / √2(N+1), the maximum bandwidth will be reached.

[0127] Figure 11 A seventh exemplary embodiment of an amplifier 10 according to the present application is depicted. In this embodiment the amplifier comprises two differential preamplifiers PA1 and PA2. The two differential preamplifiers PA1 and PA2 are provided with a differential input signal V A and V B .

[0128] A negative impedance converter NIC is located in each of the differential preamplifiers PA1 and PA2. Each negative impedance converter NIC applies its negative capacitance to the output port PAol and PAo2 of the assigned differential preamplifier PA1 or PA2.

[0129] The load LOAD is connected between the output ports DASol and DASo2 of the downstream amplifier stage DAS.

[0130] In embodiments where Figure 11 the FFE circuit is integrated to further extend the bandwidth. Indeed, in a typical FFE circuit, two or more differential pairs are connected to the same output node. To increase the speed, the NMC approach cannot be used here, as two or more different signals would act on the cross-connected capacitor, so an inductive peaking or a cascode stage is used. The latter approach requires a larger power supply, or a reduced voltage swing, given the transistor stack.

[0131] In the embodiments discussed above with reference to Figures 1 to 11 the common integration of the amplifier (driver) and the electro-optical modulator would result in the best speed improvement, assuming no additional parasitic elements (such as pad / wire stray capacitance and inductance) at the output node.

[0132] In the embodiments discussed above with reference to Figures 1 to 11 all circuits can be implemented in various technologies (CMOS, BJT, etc.).

[0133] In the embodiments discussed above with reference to Figures 1 to 11 the load LOAD can be connected to only one output (single-ended configuration), or, where possible, to both outputs (differentially) (i.e. a push-pull modulator).

[0134] The operating principle described above by way of example can be applied to any type of device comprising an amplifier and an optical modulator (e.g. a phase modulator, an amplitude modulator, a polarization modulator, a frequency injection modulator, a depletion modulator, etc.).

[0135] The common integration of the amplifier (driver) and the electro-optical modulator can generally provide the best performance, assuming no additional parasitic elements (such as pad / wire stray capacitance and inductance), which would otherwise degrade the RF signal on the modulator electrodes and interfere with the propagation delay on the high-speed connection of the delay compensation loop.

[0136] The various embodiments and aspects of the embodiments of the invention disclosed herein are not to be taken as the only possible order of sequences and / or context in which the execution of the described processes can take place. All such sequences and / or contexts are intended to be implicitly disclosed with regard to every embodiment and aspect presented herein. Any order and / or context in which the execution of the described processes can take place is contemplated herein as being a description of the present invention. All single integrals are to be read as including pluralities (and vice versa) where the context and use permit. All enumerated options with the word "and" should be taken as including the word "or" (and vice versa) where the context and use permit, as well as any combination thereof.

[0137] In the drawings and specification, there have been disclosed multiple embodiments of the invention. Applicant desires to cover all alternatives fairly falling within the description and equivalents thereof, as well as modifications in the described embodiments, and in addition, any additional embodiments created by any combination, subcombination, addition, substitution, equivalence, improvement, enhancement, or modification also covered by the description. These additional embodiments form part of the present disclosure, and as such, Applicant can submit further patent claims regarding these additional embodiments at a later stage of the litigation.

[0138] Furthermore, Applicant desires to emphasize that each feature of each of the following dependent claims can be combined with any of the existing independent claims, as well as any other existing dependent claim(s), regardless of the existing claim structure.

[0139] Thus, Applicant can submit further patent claims directed to other claim combinations at a later stage of the litigation.

[0140] For example, the apparatus of claims 25 and 26 can incorporate the features (in any combination) of any of claims 2 to 24.

[0141] Furthermore, the amplifier of claim 1 can incorporate the features of any, some or all of dependent claims 2 to 24. In other words, each dependent claim can refer to any other dependent claim, regardless of the current claim structure and the order in which the dependent claims are listed below.

[0142] List of formula symbols:

[0143] τ B Base transit time

[0144] r B Base resistance

[0145] r e Small signal emitter resistance

[0146] g m Transistor transconductance

[0147] C LOAD Equivalent load capacitance of downstream amplifier stage

[0148] C BESmall-signal base-emitter capacitance

[0149] C BC Small-signal base-collector capacitance

[0150] C DEG Differential pair emitter negative feedback capacitance

[0151] C GAIN Gain stage collector parasitic capacitance

[0152] C OUT Equivalent output load capacitance

[0153] C NMC Cross-coupled base-collector capacitance for Miller effect compensation (negative Miller capacitance)

[0154] C NIC Equivalent negative impedance converter emitter capacitance

[0155] R GAIN Gain stage collector resistance

[0156] R DEG Differential pair emitter negative feedback resistance

Claims

1. An electrical amplifier, comprising: A differential preamplifier, the differential preamplifier having a first output port and a second output port; and A downstream amplifier stage, the downstream amplifier stage having a first output unit and a second output unit; in, The first output unit is connected to the first output port of the differential preamplifier, and the second output unit is connected to the second output port of the differential preamplifier; and The negative impedance converter is configured to provide negative capacitance. Its features are, The negative impedance converter is electrically located in the differential preamplifier and applies the negative capacitance to the first output port and the second output port of the differential preamplifier; The differential preamplifier includes a first transistor and a second transistor. The emitter of the first transistor provides the first output port of the differential preamplifier; The emitter of the second transistor provides the second output port of the differential preamplifier; and The negative impedance converter applies the negative capacitance to the emitters of the first transistor and the second transistor.

2. The electrical amplifier according to claim 1, in, The collector of the third transistor is connected to the base of the fourth transistor; The collector of the fourth transistor is connected to the base of the third transistor; At least one capacitor is connected to the emitters of the third and fourth transistors; and The third transistor, the fourth transistor, and the at least one capacitor form at least a portion of the negative impedance converter or at least a portion of the negative impedance converter.

3. The electrical amplifier according to claim 2, in, The emitter of the first transistor is connected to both the collector of the third transistor and the base of the fourth transistor; and The emitter of the second transistor is connected to both the collector of the fourth transistor and the base of the third transistor.

4. The electrical amplifier according to claim 1, in, The base of the first transistor forms the first input port of the differential preamplifier; and The base of the second transistor forms the second input port of the differential preamplifier.

5. The electrical amplifier according to claim 2, in, The emitter of the third transistor and the emitter of the fourth transistor are connected through a first capacitor and a second capacitor; and The first and second capacitors are connected in series.

6. The electrical amplifier according to claim 5, The first capacitor and the second capacitor are variable.

7. The electrical amplifier according to claim 2, in, The emitter of the first transistor is connected to the base of the fourth transistor via a first resistor; and The emitter of the second transistor is connected to the base of the third transistor via a second resistor.

8. The electrical amplifier according to claim 1, in, An electrical ground configured to provide negative capacitance is located in the downstream amplifier stage, and the negative capacitance is applied to the downstream amplifier stage.

9. The electrical amplifier according to claim 8, in, The downstream amplifier stage includes a first transistor and a second transistor; Wherein, the emitter of at least one of the first transistor and the second transistor provides the output port of the downstream amplifier stage; and The negative impedance converter couples the emitters of the first and second transistors of the downstream amplifier stage and applies the negative capacitance to the emitters of the first and second transistors.

10. The electrical amplifier according to claim 1, in, The amplifier includes at least two differential preamplifiers; The negative impedance converter is located in two of the at least two differential preamplifiers; The amplifier includes at least two downstream amplifier stages; Wherein, one of the at least two downstream amplifier stages is connected to one of the at least two differential preamplifiers; Wherein, one of the at least two downstream amplifier stages is connected to the other of the at least two differential preamplifiers; and The at least two downstream amplifier stages are connected to the same load.

11. The electrical amplifier according to claim 1, in, Each of the negative impedance converters is configured to provide a negative capacitance; and Each of the negative impedance converters applies its negative capacitance to the two output ports of the assigned differential preamplifier.

12. The electrical amplifier according to claim 1, The amplifier includes an output port for driving loads in a single-ended configuration.

13. The electrical amplifier according to claim 1, The amplifier includes two output ports for differentially driving the load.

14. An apparatus comprising at least one electrical amplifier and at least one modulator, wherein the electrical amplifier is the electrical amplifier according to claim 1, and the modulator is driven by the electrical amplifier.

15. The device according to claim 14, The electrical amplifier drives the modulator in a push-pull mode.

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