Dynamic random access memory chip testing method and device
The chip testing method for DRAM devices addresses the issue of plate node noise by applying controlled voltages and waiting times to detect and identify defective cells with reduced storage capacity.
Patent Information
- Application Number
- CN202110050366.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-14
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2041-01-14
AI Technical Summary
As DRAM devices shrink, they become more sensitive to bit line-bit line noise, particularly at the plate node, affecting data storage capacity, necessitating a method to detect defective cells caused by plate node noise voltage.
A chip testing method involving multiple stages of initialization, writing '1', waiting, and reading '1' by applying specific voltages to the plate node, including an initialization voltage, a first voltage greater than this, and a second voltage less than the initialization voltage, with varying waiting times based on temperature, to detect defective cells.
The method effectively identifies defective cells by reducing the storage node potential and bit line voltage difference, enabling detection of cells with poor data storage capacity due to plate node noise.
Smart Images
Figure CN114765049B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing method and device for a dynamic random access memory. Background Art
[0002] DRAM refers to dynamic random access memory. DRAM cells have the advantages of small area and large capacity. Through proper packaging, DRAM can have a high data rate. For these reasons, large-capacity main memory still uses DRAM as the basic unit.
[0003] The equivalent circuit of a DRAM memory cell is as follows: Figure 1 As shown in the figure, it consists of a transistor and a capacitor. Of the two electrodes that make up the capacitor, the electrode that applies voltage can be called a plate node, and the electrode on the other side that stores data is called a storage node. The data of each storage cell is determined by the charge stored in the capacitor, and the transistor controls the access of the data. When the word line is selected and the transistor is turned on, the charge stored in the capacitor changes the bit line voltage through charge sharing, and then the small change in the bit line voltage is amplified by the sensitive amplifier circuit to read the data.
[0004] However, as the size of DRAM devices continues to shrink, in order to obtain the maximum cell density, it is best to use an open bit line structure. The corresponding DRAM memory array is as follows Figure 2 As shown, the intersection of each row and column is a storage cell, and the plate nodes of all storage cells can be connected together. The open bit line structure is very sensitive to bit line-bit line noise because the switch bit lines are very close. In addition, the voltage noise on the plate node cannot be ignored. This voltage noise is generated locally, and although it will disappear after a short time, it will still affect the data storage capacity of the storage cell. Therefore, when performing chip testing, it is necessary to detect bad cells with reduced storage capacity due to plate node noise. Summary of the invention
[0005] In order to solve the above problems, the present invention provides a chip testing method and device for a dynamic random access memory, which can detect defective cells caused by plate node noise voltage.
[0006] In a first aspect, the present invention provides a chip testing method for a dynamic random access memory, comprising:
[0007] applying an initialization voltage to the plate node and precharging a selected column of bit lines;
[0008] Opening the selected word line to write "1" to the target cell, and applying a first voltage greater than the initialization voltage to the plate node during the process of writing "1" to the target cell;
[0009] After writing "1" in the target cell, turning off the word line, and applying a second voltage less than the initialization voltage to the plate node;
[0010] After waiting for a set time, read the target unit;
[0011] Whether the target cell is normal is determined according to the reading result. If "1" can be read, the target cell is a normal cell. If "1" cannot be read, the target cell is a defective cell.
[0012] Optionally, the initialization voltage is recorded as V p , the first voltage is V p +ΔV p , the second voltage is V p -ΔV p , where ΔV p represents the noise voltage at the plate node.
[0013] Optionally, if the temperature is lower than 25° C., the waiting time is set to 1 second; if the temperature is higher than 25° C., the waiting time is set to 64 ms.
[0014] In a second aspect, the present invention provides a chip testing device for a dynamic random access memory, comprising:
[0015] A variable voltage module, used for applying an initialization voltage to the plate nodes;
[0016] A write module is used to precharge a selected column of bit lines, open the selected word line to write "1" to the target cell, and after writing "1", close the word line;
[0017] Correspondingly, the variable voltage module is further used to apply a first voltage greater than the initialization voltage to the plate node during the process of writing "1" to the target cell, and, after writing "1" to the target cell, apply a second voltage less than the initialization voltage to the plate node;
[0018] A reading module, used for reading the target unit after waiting for a set time;
[0019] The judgment module is used to judge whether the target unit is normal according to the reading result. If "1" can be read, the target unit is a normal unit; if "1" cannot be read, the target unit is a bad unit.
[0020] Optionally, the initialization voltage is recorded as V p , the first voltage is Vp +ΔV p , the second voltage is V p -ΔV p , where ΔV p represents the noise voltage at the plate node.
[0021] Optionally, if the temperature is lower than 25° C., the waiting time is set to 1 second; if the temperature is higher than 25° C., the waiting time is set to 64 ms.
[0022] The chip testing method and device of the dynamic random access memory provided by the present invention include multiple stages of initialization, writing "1", waiting, and reading "1". By changing the voltage applied to the plate node, the potential of the storage node is reduced, and the bit line voltage difference is further reduced, so that bad units with poor data storage capacity caused by the plate node noise voltage can be detected. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is an equivalent circuit diagram of a DRAM cell in the prior art;
[0024] Figure 2 A DRAM array having an open bit line structure according to the prior art;
[0025] Figure 3 A schematic diagram of a flow chart of a dynamic random access memory chip testing method provided by an embodiment of the present invention;
[0026] Figure 4 is a comparison diagram of the bit line voltage, storage node voltage and plate node voltage at different stages of the test method;
[0027] Figure 5 A schematic diagram of the structure of a chip testing device for a dynamic random access memory provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0029] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0030] Generally, during the write / read process of a DRAM cell, the bit line is precharged first, and the voltage after the bit line is precharged is recorded as V bl After writing "1" into the memory cell, the bit line voltage is recorded as V blD1 , which is passed to the storage node. Ideally, the storage node voltage V s =V blD1 The voltage at the plate node is V p , then the voltage difference between the capacitors is V blD1 -V p At this time, turn on the transistor. When the charge on the capacitor and the charge on the bit line reach equilibrium, the bit line voltage will rise slightly. This slightly rising voltage is recorded as ΔV bl .
[0031] ΔV bl =C s (V s -V bl ) / (C s +C b )=C s (V blD1 -V bl ) / (C s +C b )(Formula 1)
[0032] Among them C s Represents the capacitance of the unit capacitor, V s Represents the storage node voltage, V bl Represents the bit line precharge voltage, C b Indicates the parasitic capacitance of the bit line. ΔV bl It will affect the performance of the bit line amplifier circuit and directly determine the reading result. Based on the above discussion, by reducing V s , which can reduce ΔV bl , thereby detecting ΔV bl A storage cell with insufficient amplitude.
[0033] Figure 3 The flowchart of a chip testing method of a dynamic random access memory provided by an embodiment of the present invention. It should be noted that, in this embodiment, the dynamic random access memory adopts an open bit line structure, and the plate nodes of all storage units are connected together. Figure 3 As shown, the method includes:
[0034] Step 301, applying an initialization voltage to the plate node and precharging a selected column of bit lines.
[0035] At this time, the word line is closed, the transistor is disconnected, and the plate node voltage is recorded as V p , the bit line voltage is precharged to V bl .
[0036] Step 302, open the selected word line to write "1" to the target cell, and apply a first voltage greater than the initialization voltage to the plate node during the process of writing "1" to the target cell.
[0037] Select a row of word lines, turn on the word line, turn on the transistor, and the bit line voltage is V blD1 , the voltage is transmitted through the transistor, and the storage node voltage becomes V blD1 , the first voltage applied is recorded as V p +ΔV p , where ΔV p Represents the noise voltage at the plate node and is an input voltage variable.
[0038] Step 303, after writing "1" in the target cell, the word line is turned off, and a second voltage less than the initialization voltage is applied to the plate node.
[0039] After the word line is turned off, the second voltage applied is recorded as V p -ΔV p , where ΔV p Represents the noise voltage of the plate node. Due to the presence of capacitors, the plate node voltage will not change suddenly.
[0040] Step 304, after waiting for a set time, read the target unit.
[0041] After a period of waiting, the plate node voltage becomes V p -ΔV p According to the law of conservation of charge, the voltage V s becomes V blD1 -2ΔV p That is, the potential of the storage node decreases by 2ΔV p In this case, when the data of the target cell is read, the ΔV bl The waiting time is related to the test environment temperature. For example, in a low temperature environment (temperature below 25°C), the waiting time is 1 second, and in a high temperature environment (temperature above 25°C), the waiting time is 64 milliseconds. Figure 4 The bit line voltage, storage node voltage and plate node voltage at different stages are shown.
[0042] Step 305, judging whether the target cell is normal according to the reading result, if "1" can be read, the target cell is a normal cell, if "1" cannot be read, the target cell is a bad cell.
[0043] Due to the reduction of V s ,Data cannot be read from bad cells with poor storage capacity, so bad cells can be detected.
[0044] The chip testing method of the dynamic random access memory provided by the embodiment of the present invention includes multiple stages of initialization, writing "1", waiting, and reading "1". By changing the voltage applied to the plate node, the potential of the storage node is reduced, and the bit line voltage difference is further reduced, so that bad units with poor data storage capacity caused by the plate node noise voltage can be detected.
[0045] On the other hand, the embodiment of the present invention also provides a chip testing device for a dynamic random access memory, such as Figure 5 As shown, the device comprises:
[0046] A variable voltage module 501, used to apply an initialization voltage to the plate node;
[0047] The write module 502 is used to precharge a selected column of bit lines, open the selected word line to write "1" to the target cell, and close the word line after writing "1";
[0048] Correspondingly, the variable voltage module 501 is further used to apply a first voltage greater than the initialization voltage to the plate node during the process of writing "1" to the target cell, and, after writing "1" to the target cell, apply a second voltage less than the initialization voltage to the plate node;
[0049] The reading module 503 is used to read the target unit after waiting for a set time;
[0050] The judgment module 504 is used to judge whether the target cell is normal according to the reading result. If "1" can be read, the target cell is a normal cell; if "1" cannot be read, the target cell is a bad cell.
[0051] Furthermore, the initialization voltage applied by the variable voltage module 501 is denoted as V p , the first voltage is V p +ΔV p , the second voltage is V p -ΔV p , where ΔV p Indicates the noise voltage of the plate node. After writing "1", the waiting time is related to the test environment temperature, for example, waiting for 1 second in a low temperature environment (temperature below 25°C) and waiting for 64 milliseconds in a high temperature environment (temperature above 25°C).
[0052] The chip testing device of the dynamic random access memory provided by the embodiment of the present invention can detect defective cells with poor data storage capacity caused by the plate node noise voltage by changing the voltage applied to the plate node, reducing the storage node voltage, and further reducing the bit line voltage difference.
[0053] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
[0054] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A chip testing method for a dynamic random access memory, characterized in that: The dynamic random access memory adopts an open bit line structure, and the plate nodes of all storage units are connected together. The method includes: applying an initialization voltage to the plate node and precharging a selected column of bit lines; Opening the selected word line to write "1" to the target cell, and applying a first voltage greater than the initialization voltage to the plate node during the process of writing "1" to the target cell; After writing "1" in the target cell, turning off the word line, and applying a second voltage less than the initialization voltage to the plate node; After waiting for a set time, read the target unit; Determine whether the target unit is normal according to the reading result. If "1" can be read, the target unit is a normal unit. If "1" cannot be read, the target unit is a bad unit. The first voltage is , the second voltage is , Represents the initialization voltage, represents the noise voltage at the plate node.
2. The method according to claim 1, characterized in that If the temperature is lower than 25℃, the waiting time is set to 1s; if the temperature is higher than 25℃, the waiting time is set to 64ms.
3. A chip testing device for a dynamic random access memory, characterized in that: The dynamic random access memory adopts an open bit line structure, and the plate nodes of all storage units are connected together. The device includes: A variable voltage module, used for applying an initialization voltage to the plate nodes; A write module is used to precharge a selected column of bit lines, open the selected word line to write "1" to the target cell, and close the word line after writing "1"; Correspondingly, the variable voltage module is further used to apply a first voltage greater than the initialization voltage to the plate node during the process of writing "1" to the target cell, and, after writing "1" to the target cell, apply a second voltage less than the initialization voltage to the plate node; A reading module, used for reading the target unit after waiting for a set time; A judgment module, used for judging whether the target unit is normal according to the reading result, if "1" can be read, the target unit is a normal unit, if "1" cannot be read, the target unit is a bad unit; The first voltage is , the second voltage is , Represents the initialization voltage, represents the noise voltage at the plate node.
4. The device according to claim 3, characterized in that If the temperature is lower than 25℃, the waiting time is set to 1s; if the temperature is higher than 25℃, the waiting time is set to 64ms.