A method and system for accelerating the periodogram algorithm of OFDM radar based on FPGA

Abstract

The present invention discloses a method and system for accelerating an OFDM radar periodogram algorithm based on an FPGA. This invention relates to the field of digital communications technology and primarily addresses the issues of slow calculation speed and low radar refresh rate associated with the OFDM radar periodogram algorithm. The system comprises an FPGA modulation unit, a radar signal preprocessing unit, and a radar signal postprocessing unit. By utilizing an existing FPGA-based OFDM transmitter, a radar signal preprocessing unit is added to the existing FPGA modulation unit, and a radar signal postprocessing unit is implemented in the CPU, thereby implementing some steps of the periodogram algorithm. The calculations in the FPGA utilize pipeline operations, significantly improving the refresh rate of the OFDM radar.

Description

Technical Field

[0001] The present invention relates to the field of digital communication technology, mainly to digital OFDM radar signal processing, and in particular to a method and system for accelerating an OFDM radar periodogram algorithm based on FPGA. Background Art

[0002] Wireless sensing and wireless communication systems are typically designed independently, occupying different frequency bands. However, spectrum resources have become increasingly scarce in recent years. Furthermore, with the development of the transportation and drone industries, the demand for accurate sensing information from communication systems has increased. This has made research on the integration of communication and perception a hot topic both domestically and internationally. Due to the widespread use of OFDM signals in communication systems, OFDM communication and perception integration holds broad application prospects.

[0003] The OFDM radar periodogram algorithm, which can simultaneously obtain target range and velocity while ensuring orthogonality between these two methods, offers significant advantages over other radar algorithms, such as cross-correlation. However, implementing the OFDM radar periodogram algorithm on a CPU is extremely time-consuming, significantly reducing the radar refresh rate. Summary of the Invention

[0004] To address these issues, this paper proposes a method and system for accelerating an OFDM radar periodogram algorithm using an FPGA. This method uses an FPGA to implement the time-complexity portions of signal processing, significantly improving signal processing speed through a pipeline architecture. While the algorithm's space-complexity portions, where FPGA acceleration is less effective, are still handled by the CPU, reducing FPGA resource usage.

[0005] The technical solution of the present invention is:

[0006] A system for accelerating an OFDM radar periodogram algorithm based on an FPGA includes an OFDM modulation unit, a radar signal preprocessing unit, and a radar signal postprocessing unit. The radar signal preprocessing unit is added to the FPGA, and the radar signal postprocessing unit is implemented in the CPU.

[0007] The radar signal preprocessing unit includes a timing control module, a time domain synchronization symbol removal module, a first serial-to-parallel conversion module, a first FFT module, a first parallel-to-serial conversion module, a frequency domain synchronization symbol removal module, a frequency domain phase division module, a second serial-to-parallel conversion module, a first IFFT module, and a second parallel-to-serial conversion module;

[0008] The timing control module is configured to clear the OFDM symbol count and the time domain sampling point count in response to receiving a frame start signal output by the frame structure control module of the OFDM modulation unit; and

[0009] Acquire radio frequency received data and generate OFDM symbol numbers and time domain sampling point numbers used in subsequent radar signal processing; wherein the radio frequency received data is received by the radio frequency unit and then enters the FPGA and is first input into the timing control module;

[0010] The time domain synchronization symbol removal module is configured to remove time domain OFDM synchronization equalization symbols that cannot be used for radar operations in OFDM time domain symbols;

[0011] The first serial-to-parallel conversion module is configured to convert the signal output by the time domain synchronization symbol removal module into a parallel signal and then input the parallel signal into the first FFT module;

[0012] The first FFT module is configured to perform FFT transformation on each OFDM symbol after removing the CP to obtain OFDM frequency domain symbols, and the output data is input into the first parallel-to-serial conversion module;

[0013] The first parallel-to-serial conversion module is configured to convert the parallel data output by the FFT into serial data, and the output data is input into the frequency domain division module as a dividend;

[0014] The frequency domain synchronization symbol removal module is configured to remove OFDM synchronization equalization symbols that cannot be used for radar operations from the OFDM frequency domain symbols to be modulated after constellation mapping, and the output data is input into the frequency domain division module as a divisor;

[0015] The frequency domain division module is configured to perform corresponding division on the subcarriers of each OFDM frequency domain symbol, and the output data is input into the second serial-to-parallel conversion module;

[0016] The second serial-to-parallel conversion module is configured to convert the serial data input from the frequency domain division module into parallel data again, and the output data is input into the IFFT module;

[0017] The IFFT module is configured to perform an IFFT operation on each OFDM frequency domain symbol input by the IFFT module and subjected to frequency domain division;

[0018] The second parallel-to-serial conversion module is configured to convert the output data of the IFFT module into serial data and then input the serial data into the radar data buffer area of the CPU through DMA.

[0019] In some embodiments, the timing control module includes a first counter and a second counter. In response to the arrival of a frame start signal from the frame structure control module, the two counters are cleared; for each sampled data from the radio frequency unit, the first counter is incremented by 1, and when the first counter overflows and returns to zero, the second counter is incremented by 1.

[0020] In some embodiments, the frequency domain division module performs complex division between subcarriers on the received OFDM frequency domain symbols and the frequency domain symbols before IFFT from the OFDM modulation unit. The complex division is implemented by multiplying the dividend by the conjugate of the divisor and then multiplying by the inverse of the square modulus of the divisor. The frequency domain division module includes a data selector, a complex conjugate module, a complex square modulus inverse module, a first complex multiplier and a second complex multiplier. The complex square modulus inverse module uses an inverse square root fast algorithm to quickly calculate the inverse of the complex square modulus.

[0021] In some embodiments, in the system for accelerating OFDM radar periodogram algorithm based on FPGA, the radar signal post-processing unit is configured to perform FFT and modulus square operations on the data output by the FPGA.

[0022] In some embodiments, the OFDM modulation unit includes a data scrambling module, a frame structure control module, a constellation mapping module, a third serial-to-parallel conversion module, a second IFFT module, and a third parallel-to-serial conversion module;

[0023] FPGA obtains the communication data to be sent from the CPU's send data buffer through DMA, sends it to the data scrambling module for data scrambling processing, and then enters the frame structure control module;

[0024] The frame structure control module is configured to output a frame start signal at the beginning of each frame, perform OFDM symbol counting and subcarrier counting, and output the current modulated OFDM symbol number and subcarrier number;

[0025] The data output by the frame structure control module passes through the constellation mapping module and the third serial-to-parallel conversion module and enters the input end of the second IFFT module; the second IFFT module is implemented by the IP core and is configured to add carrier frequency and CP; the output of the IFFT module is converted into serial data by the third parallel-to-serial conversion module and then input into the RF unit for RF transmission and reception.

[0026] A method for accelerating an OFDM radar periodogram algorithm based on FPGA is also provided, comprising: an OFDM modulation unit, a radar signal preprocessing unit, and a radar signal postprocessing unit, wherein the radar signal preprocessing unit is added to the FPGA, and the radar signal postprocessing unit is implemented in the CPU;

[0027] The radar signal preprocessing unit includes a timing control module, a time domain synchronization symbol removal module, a first serial-to-parallel conversion module, a first FFT module, a first parallel-to-serial conversion module, a frequency domain synchronization symbol removal module, a frequency domain phase division module, a second serial-to-parallel conversion module, a first IFFT module, and a second parallel-to-serial conversion module;

[0028] The timing control module is configured to clear the OFDM symbol count and the time domain sampling point count in response to receiving a frame start signal output by the frame structure control module of the OFDM modulation unit; and

[0029] Acquire radio frequency received data and generate OFDM symbol numbers and time domain sampling point numbers used in subsequent radar signal processing; wherein the radio frequency received data is received by the radio frequency unit and then enters the FPGA and is first input into the timing control module;

[0030] The time domain synchronization symbol removal module is configured to remove time domain OFDM synchronization equalization symbols that cannot be used for radar operations in OFDM time domain symbols;

[0031] The first serial-to-parallel conversion module is configured to convert the signal output by the time domain synchronization symbol removal module into a parallel signal and then input the parallel signal into the first FFT module;

[0032] The first FFT module is configured to perform FFT transformation on each OFDM symbol after removing the CP to obtain OFDM frequency domain symbols, and the output data is input into the first parallel-to-serial conversion module;

[0033] The first parallel-to-serial conversion module is configured to convert the parallel data output by the FFT into serial data, and the output data is input into the frequency domain division module as a dividend;

[0034] The frequency domain synchronization symbol removal module is configured to remove OFDM synchronization equalization symbols that cannot be used for radar operations from the OFDM frequency domain symbols to be modulated after constellation mapping, and the output data is input into the frequency domain division module as a divisor;

[0035] The frequency domain division module is configured to perform corresponding division on the subcarriers of each OFDM frequency domain symbol, and the output data is input into the second serial-to-parallel conversion module;

[0036] The second serial-to-parallel conversion module is configured to convert the serial data input from the frequency domain division module into parallel data again, and the output data is input into the IFFT module;

[0037] The IFFT module is configured to perform an IFFT operation on each OFDM frequency domain symbol input by the IFFT module and subjected to frequency domain division;

[0038] The second parallel-to-serial conversion module is configured to convert the output data of the IFFT module into serial data and then input the serial data into the radar data buffer area of the CPU through DMA.

[0039] The timing control module includes a first counter and a second counter. In response to the frame start signal from the frame structure control module, the two counters are cleared. For each sampled data from the radio frequency unit, the first counter is incremented by 1. When the first counter overflows and returns to zero, the second counter is incremented by 1.

[0040] The frequency domain division module performs complex division between subcarriers on the received OFDM frequency domain symbols and the frequency domain symbols before IFFT from the OFDM modulation unit. The complex division is implemented by multiplying the dividend by the conjugate of the divisor and then multiplying it by the inverse of the square modulus of the divisor. The frequency domain division module includes a data selector, a complex conjugate module, a complex square modulus inverse module, a first complex multiplier and a second complex multiplier. The complex square modulus inverse module uses an inverse square root fast algorithm to quickly calculate the inverse of the complex square modulus.

[0041] The radar signal post-processing unit is configured to perform FFT and modulus square operations on the data output by the FPGA.

[0042] The OFDM modulation unit includes a data scrambling module, a frame structure control module, a constellation mapping module, a third serial-to-parallel conversion module, a second IFFT module, and a third parallel-to-serial conversion module;

[0043] FPGA obtains the communication data to be sent from the CPU's send data buffer through DMA, sends it to the data scrambling module for data scrambling processing, and then enters the frame structure control module;

[0044] The frame structure control module is configured to output a frame start signal at the beginning of each frame, perform OFDM symbol counting and subcarrier counting, and output the current modulated OFDM symbol number and subcarrier number;

[0045] The data output by the frame structure control module passes through the constellation mapping module and the third serial-to-parallel conversion module and enters the input end of the second IFFT module; the second IFFT module is implemented by the IP core and is configured to add carrier frequency and CP; the output of the IFFT module is converted into serial data by the third parallel-to-serial conversion module and then input into the RF unit for RF transmission and reception.

[0046] So far, the present invention has completed all the processes of the periodogram algorithm.

[0047] The present invention has the following beneficial effects: it divides the periodogram algorithm into two steps: radar preprocessing and radar postprocessing. It uses an FPGA to implement the radar preprocessing function in a pipelined manner, thereby improving the speed of the OFDM radar periodogram algorithm. The memory-intensive radar postprocessing portion is still executed on the CPU, reducing FPGA resource consumption. Furthermore, the present invention utilizes the signal output by the existing OFDM modulation unit for radar operations, facilitating integration with existing FPGA and ASIC designs of OFDM transmitters. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is the flow chart of the OFDM radar periodogram algorithm;

[0049] Figure 2 It is a structural schematic diagram of the present invention;

[0050] Figure 3 This is the FPGA structure diagram of the existing OFDM modulation unit;

[0051] Figure 4 FPGA structure diagram of the present invention;

[0052] Figure 5 is a structural diagram of the timing control module of the present invention;

[0053] Figure 6 1 is a structural diagram of the frequency domain division module of the present invention;

[0054] Figure 7 is a flow chart of a radar signal post-processing unit of the present invention;

[0055] In the figure: OFDM modulation unit 1: data scrambling module 11, frame structure control module 12, constellation mapping module 13, third serial-to-parallel conversion module 14, second IFFT module 15, third parallel-to-serial conversion module 16;

[0056] Radar signal preprocessing unit 2: timing control module 21: first counter 211 and second counter 212, time domain synchronization symbol removal module 22, first serial-to-parallel conversion module 23, first FFT module 24, first parallel-to-serial conversion module 25, frequency domain synchronization symbol removal module 26, frequency domain division module 27, data selector 271, complex conjugate module 272, complex modulus square reciprocal module 273, first complex multiplier 274 and second complex multiplier 275, second serial-to-parallel conversion module 28, first IFFT module 29, and second parallel-to-serial conversion module 2A;

[0057] Radar signal post-processing unit 3. DETAILED DESCRIPTION

[0058] The present invention will be further described below in conjunction with the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0059] In the description of the present invention, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0060] In the description of the present invention, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0061] like Figure 1 , the principle of the periodogram algorithm is as follows:

[0062] Use a matrix to represent an OFDM frame:

[0063]

[0064] Each row of this matrix corresponds to data on a subcarrier, and each column corresponds to data on an OFDM frequency domain symbol after constellation mapping.

[0065] The received signal can also be represented as a matrix after removing CP and FFT transformation:

[0066]

[0067] In the above formula, H represents the number of reflecting targets, Δf is the subcarrier spacing, and T O is the length of each OFDM symbol. Each target has a distance d h , the distance is converted into the corresponding signal delay τ h .f D,h is the Doppler shift, is the unknown random phase shift. b h Attenuation for each target.

[0068] The influence of communication information can be eliminated by dividing the subcarriers:

[0069]

[0070] Using FFT and IFFT, we can match the corresponding sinusoidal signals to obtain the Doppler frequency shift and delay:

[0071]

[0072] This step performs a zero-filling operation before performing FFT and IFFT to improve the resolution of the radar periodogram. Per With N Per The number of points in FFT and IFFT after filling with 0. After calculating FFT and IFFT, the square of the result modulo is used to get Per F The matrix is the desired periodogram.

[0073] Radar targets correspond to peaks in the periodogram. If If a peak is found at , the target distance can be obtained as:

[0074]

[0075] The speed is:

[0076]

[0077] like Figure 2 The present invention uses an FPGA to implement the time-complexity components of signal processing, employing a pipeline structure to increase signal processing speed. The components of the algorithm with high spatial complexity and less FPGA acceleration are still processed on the CPU, reducing FPGA resource usage. Specifically, leveraging the existing OFDM modulation unit 1, a radar signal preprocessing unit 2 is added to the FPGA, and a radar signal postprocessing unit 3 is implemented on the CPU.

[0078] like Figure 3The existing OFDM modulation unit 1 includes a data scrambling module 11, a frame structure control module 12, a constellation mapping module 13, a third serial-to-parallel conversion module 14, a second IFFT module 15, and a third parallel-to-serial conversion module 16. The process is as follows: The FPGA obtains the communication data to be transmitted from the CPU's transmit data buffer via DMA and enters the data scrambling module 11 for data scrambling. The purpose of data scrambling is to transform the data into pseudo-random data, thereby ensuring the performance of the synchronizer and equalizer at the communication receiving end. After scrambling, the data enters the frame structure control module 12. This module outputs a frame start signal at the beginning of each frame, counts OFDM symbols and subcarriers, and outputs the current modulated OFDM symbol and subcarrier sequence numbers. This module also adds synchronization training symbols and equalization training symbols to the beginning of the frame. The data output by the frame structure control module 12 passes through the constellation mapping module 13 and the third serial-to-parallel conversion module 14 and enters the input of the second IFFT module 15. The second IFFT module 15 is implemented as an IP core and has the functions of adding carrier frequencies and CPs. The output of the IFFT15 module is converted into serial data by the third parallel-to-serial conversion module 16 and then input into the radio frequency unit for radio frequency transmission and reception.

[0079] like Figure 4The FPGA portion of the present invention adds a radar signal preprocessing unit 2 based on the existing OFDM transmitter. This unit includes: a timing control module 21, a time domain synchronization symbol removal module 22, a first serial-to-parallel conversion module 23, a first FFT module 24, a first parallel-to-serial conversion module 25, a frequency domain synchronization symbol removal module 26, a frequency domain division module 27, a second serial-to-parallel conversion module 28, a first IFFT module 29, and a second parallel-to-serial conversion module 2A. Its workflow is as follows: when RF transmission begins, the RF unit synchronously begins RF reception. After entering the FPGA, the RF received data is first input into the timing control module 21. This module is responsible for recovering the OFDM symbol sequence number and the time domain sampling point sequence number to facilitate subsequent radar processing. After receiving the frame start signal output by the frame structure control module 12, this module will reset the OFDM symbol count and the time domain sampling point count, and will begin counting after receiving the first IQ data sampled from the RF transceiver. The data output by the timing control module 21 is fed into the time-domain synchronization symbol removal module 22, which is responsible for removing time-domain OFDM synchronization equalization symbols that cannot be used for radar operations. Its operation involves obtaining the OFDM symbol sequence numbers from the timing control module 21 and setting the OFDM symbols numbered 0 and 1 in each frame, known as OFDM synchronization equalization training symbols, as invalid symbols, preventing them from being fed into subsequent modules. The output signal is converted to a parallel signal by the first serial-to-parallel conversion module 23 and then fed into the first FFT module 24. Implemented as an IP core, the first FFT module 24 performs CP removal on each OFDM symbol, performing an FFT transform after CP removal to obtain an OFDM frequency-domain symbol. The output of the first FFT module 24 is fed into the first parallel-to-serial conversion module 25, which converts the FFT output's parallel data into serial data, reducing the number of complex dividers required by the frequency-domain division module 27 and thus its size. The frequency-domain division module 27 performs a corresponding division on the subcarriers of each OFDM frequency-domain symbol. The dividend is the output of the first parallel-to-serial conversion module 25, and the divisor is the output of the frequency domain synchronization symbol removal module 26. This module is responsible for removing OFDM synchronization equalization symbols that cannot be used for radar operations from the constellation-mapped OFDM frequency domain symbols to be modulated. It operates by obtaining the OFDM symbol sequence numbers from the frame structure control module 12 and pipeline synchronization by the constellation mapping module 13, setting the first and second OFDM symbols of each frame (i.e., the OFDM synchronization equalization symbols) to invalid symbols. This module also sets the unused DC subcarrier of each frame to 1 to prevent subsequent divisors from being zero. This module includes a one-symbol FIFO buffer at its output interface to handle the time difference between transmitted and received data. The data output by the frequency domain division module 27 is then input into the second serial-to-parallel conversion module 28, which converts the serial data back into parallel data and inputs it into the IFFT module 29. The IFFT module 29 performs an IFFT operation on each OFDM frequency domain symbol that has undergone frequency domain division.The output of the IFFT29 module is converted into serial data by the second parallel-to-serial conversion module 2A and then input into the radar data buffer area of the CPU through DMA.

[0080] like Figure 5 The timing control module 21 consists of a first counter 211 and a second counter 212. The first counter 211 is a time-domain sampling point number counter, with a maximum count equal to the number of FFT points + the CP length - 1. The second counter 212 is an OFDM symbol number counter, with a maximum count equal to the frame length - 1. Both counters are reset upon the arrival of the start-of-frame signal from the frame structure control module 12. For each sampled data from the RF unit, the first counter 211 increments by 1. When the first counter 211 overflows and returns to zero, the second counter 212 increments by 1.

[0081] like Figure 6 Frequency-domain division module 27 includes a data selector 271, a complex conjugate module 272, a complex modular square reciprocal module 273, a first complex multiplier 274, and a second complex multiplier 275. Complex modular square reciprocal module 273 uses a fast inverse square root algorithm to quickly calculate the complex modular square reciprocal. The input signal "subcarrier number" for frequency-domain division module 27 is the time-domain sampling point number generated by the timing control module 21 and synchronized by the time-domain synchronization symbol removal module 22, the first serial-to-parallel conversion module 23, the first FFT module 24, and the first parallel-to-serial conversion module 25.

[0082] like Figure 7 The CPU part of the present invention only needs to perform radar signal post-processing unit 3, including two steps: performing FFT and square of the modulus on the data output by FPGA. Figure 1 All the steps in the above are performed on the CPU. Compared with the present invention, the CPU needs to calculate M times of N-point FFT and M times of N Per The IFFT requires an additional 8MN fixed-point multiplications and 2MN fixed-point divisions to process the complex division of frequency-domain subcarriers. Furthermore, each step in the CPU must be completed before the previous one, which significantly slows down processing.

[0083] The principle of accelerating radar periodogram calculations in the present invention is to implement the steps of removing synchronization symbols, removing CP, FFT, element-wise division, and performing IFFT on each OFDM symbol in the periodogram algorithm on an FPGA. These steps rely only on the data of a single OFDM symbol, and thus can greatly accelerate signal processing speed using pipeline operations without consuming a large amount of FPGA resources. At the same time, these operations themselves can be calculated in parallel on the FPGA, further accelerating the process. The steps of performing FFT on each subcarrier and calculating the square of the modulus in the periodogram algorithm rely on the data of the entire frame. Implementing them on an FPGA results in limited speed improvements, and when the frame length is long, a large amount of FPGA resources are consumed, so this part is left to be implemented on the CPU.

[0084] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media, including but not limited to magnetic disk storage, CD-ROM, optical storage, etc., containing computer-usable program code.

[0085] The present application is described with reference to the flowcharts and / or block diagrams of the methods, device systems, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0086] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0088] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A system for accelerating OFDM radar periodogram algorithm based on FPGA, characterized in that: include: An OFDM modulation unit (1), a radar signal pre-processing unit (2) and a radar signal post-processing unit (3), wherein the radar signal pre-processing unit (2) is added to the FPGA and the radar signal post-processing unit (3) is implemented in the CPU; The radar signal preprocessing unit (2) comprises a timing control module (21), a time domain synchronization symbol removal module (22), a first serial-to-parallel conversion module (23), a first FFT module (24), a first parallel-to-serial conversion module (25), a frequency domain synchronization symbol removal module (26), a frequency domain phase division module (27), a second serial-to-parallel conversion module (28), a first IFFT module (29) and a second parallel-to-serial conversion module (2A); the timing control module (21) is configured to receive a frame signal output by a frame structure control module (12) of an OFDM modulation unit (1) in response to the frame signal received by the frame structure control module (12). A start signal is provided to clear the OFDM symbol count and the time domain sampling point count; and the radio frequency receiving data is obtained to generate the OFDM symbol sequence number and the time domain sampling point sequence number used for subsequent radar signal processing; wherein the radio frequency receiving data is received by the radio frequency unit and then enters the FPGA and is first input into the timing control module (21); the time domain synchronization symbol removal module (22) is configured to remove the time domain OFDM synchronization equalization symbol that cannot be used for radar operation in the OFDM time domain symbol; the first serial-to-parallel conversion module (23) is configured to remove the time domain synchronization symbol removal module (22) The output signal is converted into a parallel signal and then input into a first FFT module (24); the first FFT module (24) is configured to remove the CP of each OFDM symbol and then perform FFT transformation to obtain an OFDM frequency domain symbol, and the output data is input into a first parallel-to-serial conversion module (25); the first parallel-to-serial conversion module (25) is configured to convert the parallel data output by the FFT into serial data, and the output data is input into a frequency domain division module (27) as a dividend; the frequency domain synchronization symbol removal module (26) is configured to remove the OFDM synchronization equalization symbol that cannot be used for radar operation in the OFDM frequency domain symbol to be modulated after constellation mapping, and the output data is input into a frequency domain division module (27) as a divisor; the frequency domain division module (27) is configured to perform corresponding division on the subcarriers of each OFDM frequency domain symbol, and the output data is input into a second serial-to-parallel conversion module (28); the second serial-to-parallel conversion module (28) is configured to perform a frequency domain division module (27) The input serial data is converted into parallel data again, and the output data is input into an IFFT (29) module; the IFFT (29) module is configured to perform an IFFT operation on each OFDM frequency domain symbol input into the IFFT (29) module after frequency domain division; a second parallel-to-serial conversion module (2A) is configured to convert the output data of the IFFT (29) module into serial data, and then input the data into a radar data buffer area of the CPU through DMA; The radar signal post-processing unit (3) is configured to perform FFT and modulus square operations on data output by the FPGA.

2. The system for accelerating OFDM radar periodogram algorithm based on FPGA according to claim 1, characterized in that: The timing control module (21) comprises a first counter (211) and a second counter (212). In response to the arrival of a frame start signal from the frame structure control module (12), the two counters are reset to zero; for each sampled data from the radio frequency unit, the first counter (211) is incremented by 1, and when the first counter (211) overflows and returns to zero, the second counter (212) is incremented by 1.

3. The system for accelerating OFDM radar periodogram algorithm based on FPGA according to claim 1, characterized in that The frequency domain division module (27) performs complex division between subcarriers on the received OFDM frequency domain symbols and the frequency domain symbols before IFFT from the OFDM modulation unit (1), and the complex division is realized by multiplying the dividend by the conjugate of the divisor and then multiplying by the inverse of the divisor modulus square; the frequency domain division module (27) includes a data selector (271), a complex conjugate module (272), a complex modulus square inverse module (273), a first complex multiplier (274) and a second complex multiplier (275); wherein the complex modulus square inverse module (273) uses an inverse square root fast algorithm to perform a fast calculation of the complex modulus square inverse.

4. The system for accelerating OFDM radar periodogram algorithm based on FPGA according to claim 1, characterized in that: The OFDM modulation unit (1) comprises a data scrambling module (11), a frame structure control module (12), a constellation mapping module (13), a third serial-to-parallel conversion module (14), a second IFFT module (15), and a third parallel-to-serial conversion module (16); The FPGA obtains the communication data to be sent from the CPU's sending data buffer through DMA, and sends it to the data scrambling module (11) for data scrambling processing, and then enters the frame structure control module (12); A frame structure control module (12) is configured to output a frame start signal at the beginning of each frame, perform OFDM symbol counting and subcarrier counting, and output a currently modulated OFDM symbol number and subcarrier number; The data outputted by the frame structure control module (12) enters the input end of the second IFFT module (15) through the constellation mapping module (13) and the third serial-to-parallel conversion module (14); the second IFFT module (15) is implemented by an IP core and is configured to add a carrier frequency and a CP; the output of the IFFT (15) module is converted into serial data by the third parallel-to-serial conversion module (16) and then input into the radio frequency unit for radio frequency transmission and reception.

5. A method for accelerating OFDM radar periodogram algorithm based on FPGA, characterized in that: include: An OFDM modulation unit (1), a radar signal pre-processing unit (2) and a radar signal post-processing unit (3), wherein the radar signal pre-processing unit (2) is added to the FPGA and the radar signal post-processing unit (3) is implemented in the CPU; The radar signal preprocessing unit (2) comprises a timing control module (21), a time domain synchronization symbol removal module (22), a first serial-to-parallel conversion module (23), a first FFT module (24), a first parallel-to-serial conversion module (25), a frequency domain synchronization symbol removal module (26), a frequency domain phase division module (27), a second serial-to-parallel conversion module (28), a first IFFT module (29) and a second parallel-to-serial conversion module (2A); the timing control module (21) is configured to clear the OFDM symbol count and the time domain sampling point count in response to receiving a frame start signal output by the frame structure control module (12) of the OFDM modulation unit (1). number; and obtaining radio frequency received data, generating an OFDM symbol number and a time domain sampling point number used in subsequent radar signal processing; wherein the radio frequency received data is received by the radio frequency unit and then enters the FPGA and is first input into the timing control module (21); the time domain synchronization symbol removal module (22) is configured to remove the time domain OFDM synchronization equalization symbol that cannot be used for radar operation in the OFDM time domain symbol; the first serial-to-parallel conversion module (23) is configured to convert the signal output by the time domain synchronization symbol removal module (22) into a parallel signal and then input it into the first FFT module (24); the first FFT module (24) is configured After removing the CP of each OFDM symbol, an FFT transformation is performed to obtain an OFDM frequency domain symbol, and the output data is input into a first parallel-to-serial conversion module (25); the first parallel-to-serial conversion module (25) is configured to convert the parallel data output by the FFT into serial data, and the output data is input into a frequency domain division module (27) as a dividend; the frequency domain synchronization symbol removal module (26) is configured to remove the OFDM synchronization equalization symbol that cannot be used for radar operation in the OFDM frequency domain symbol to be modulated after constellation mapping, and the output data is input into the frequency domain division module (27) as a divisor; the frequency domain division module (27) is configured to remove the OFDM synchronization equalization symbol that cannot be used for radar operation in the OFDM frequency domain symbol to be modulated after constellation mapping, and the output data is input into the frequency domain division module (27) as a divisor; The subcarriers of the OFDM frequency domain symbols are divided correspondingly, and the output data is input into the second serial-to-parallel conversion module (28); the second serial-to-parallel conversion module (28) is configured to convert the serial data input by the frequency domain division module (27) into parallel data again, and the output data is input into the IFFT (29) module; the IFFT (29) module is configured to perform an IFFT operation on each OFDM frequency domain symbol input by the IFFT (29) module after the frequency domain division; the second parallel-to-serial conversion module (2A) is configured to convert the output data of the IFFT (29) module into serial data, and then input the data into the radar data buffer area of the CPU through DMA; The radar signal post-processing unit (3) is configured to perform FFT and modulus square operations on data output by the FPGA.

6. The method for accelerating the OFDM radar periodogram algorithm based on FPGA according to claim 5, wherein: The timing control module (21) comprises a first counter (211) and a second counter (212). In response to the arrival of a frame start signal from the frame structure control module (12), the two counters are reset to zero; for each sampled data from the radio frequency unit, the first counter (211) is incremented by 1, and when the first counter (211) overflows and returns to zero, the second counter (212) is incremented by 1.

7. The method for accelerating the OFDM radar periodogram algorithm based on FPGA according to claim 5, wherein: The frequency domain division module (27) performs complex division between subcarriers on the received OFDM frequency domain symbols and the frequency domain symbols before IFFT from the OFDM modulation unit (1), and the complex division is realized by multiplying the dividend by the conjugate of the divisor and then multiplying by the inverse of the divisor modulus square; the frequency domain division module (27) includes a data selector (271), a complex conjugate module (272), a complex modulus square inverse module (273), a first complex multiplier (274) and a second complex multiplier (275); wherein the complex modulus square inverse module (273) uses an inverse square root fast algorithm to perform a fast calculation of the complex modulus square inverse.

8. The method for accelerating the OFDM radar periodogram algorithm based on FPGA according to claim 5, wherein: The OFDM modulation unit (1) comprises a data scrambling module (11), a frame structure control module (12), a constellation mapping module (13), a third serial-to-parallel conversion module (14), a second IFFT module (15), and a third parallel-to-serial conversion module (16); The FPGA obtains the communication data to be sent from the CPU's sending data buffer through DMA, and sends it to the data scrambling module (11) for data scrambling processing, and then enters the frame structure control module (12); A frame structure control module (12) is configured to output a frame start signal at the beginning of each frame, perform OFDM symbol counting and subcarrier counting, and output a currently modulated OFDM symbol number and subcarrier number; The data outputted by the frame structure control module (12) enters the input end of the second IFFT module (15) through the constellation mapping module (13) and the third serial-to-parallel conversion module (14); the second IFFT module (15) is implemented by an IP core and is configured to add a carrier frequency and a CP; the output of the IFFT (15) module is converted into serial data by the third parallel-to-serial conversion module (16) and then input into the radio frequency unit for radio frequency transmission and reception.

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