Display panel and display device

Abstract

The present application provides a display panel and a display device, wherein the display panel includes a substrate and a thin film transistor layer arranged on the substrate, the thin film transistor layer includes an active layer and a metal layer stacked together, the active layer includes an active segment and a conductor segment connected to the active segment; wherein the present application provides an overlapping portion connected to the metal layer on the conductor segment, and a conductor sub-portion located between the overlapping portion and the active segment, and a groove is provided on the conductor sub-portion, thereby reducing the overall area of the conductor sub-portion, thereby weakening the diffusion of carriers to the active segment, and improving the stability of the thin film transistor layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Oxide thin film transistors (TFTs) are considered to be one of the most promising next-generation thin film transistors due to their low process temperature, high mobility, transparency to visible light, ability to prepare large-area high-quality thin films at room temperature, compatibility with existing production line equipment, and ability to be manufactured on flexible substrates.

[0003] Typically, a thin-film transistor (TFT) includes a gate, an active layer, a source electrode, and a drain electrode. The source and drain electrodes are located at opposite ends of the active layer and contact the active layer. In practical applications, a top-gate structure has lower parasitic capacitance than a bottom-gate structure, making it more suitable for large-scale applications. In existing top-gate structures, before the source / drain electrodes are fabricated, the source and drain contact regions of the active layer are typically subjected to a conductorization process to improve the connection characteristics of the active layer to the source and drain contact regions. However, the conductorized carriers in the active layer overlap region can diffuse into the active layer channel region, causing a short-channel effect and, to a certain extent, affecting the stability of the thin-film transistor. Summary of the Invention

[0004] The embodiments of the present application provide a display device to alleviate the deficiencies in the related art.

[0005] To achieve the above functions, the technical solutions provided in the embodiments of the present application are as follows:

[0006] An embodiment of the present application provides a display panel, comprising:

[0007] substrate;

[0008] a thin film transistor layer disposed on the substrate, the thin film transistor layer comprising an active layer and a metal layer stacked together, the active layer comprising an active segment and a conductor segment connected to the active segment;

[0009] The conductor segment includes a lap portion connected to the metal layer, and a conductor sub-portion located between the lap portion and the active segment, and a groove is formed on the conductor sub-portion.

[0010] In the display panel provided in the embodiment of the present application, the metal layer includes a source electrode and a drain electrode spaced apart from each other;

[0011] The overlapping portion includes a first overlapping portion in contact with the source electrode and a second overlapping portion in contact with the drain electrode, and the active section is located between the first overlapping portion and the second overlapping portion;

[0012] The conductor sub-section includes a first conductor sub-section located between the first lap portion and the active section, and a second conductor sub-section located between the second lap portion and the active section;

[0013] Wherein, a first groove is formed on the first conductor sub-part, and a second groove is formed on the second conductor sub-part.

[0014] In the display panel provided in the embodiment of the present application, the thin film transistor layer further includes an insulating layer located between the active layer and the metal layer, the insulating layer being provided with a first through-hole corresponding to the first overlapping portion and the first conductor sub-portion, and a second through-hole corresponding to the second overlapping portion and the second conductor sub-portion, the source electrode being connected to the first overlapping portion through the first through-hole, and the drain electrode being connected to the second overlapping portion through the second through-hole;

[0015] The orthographic projection of the first groove on the substrate is located within the orthographic projection of the first through hole on the substrate, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the second through hole on the substrate.

[0016] In the display panel provided in the embodiment of the present application, a sidewall of the source electrode close to the first groove is coplanar with a sidewall of the first groove away from the active section; and / or

[0017] A sidewall of the drain electrode close to the second groove is coplanar with a sidewall of the second groove away from the active section.

[0018] In the display panel provided in the embodiment of the present application, the sidewall of the first through hole close to the active section is coplanar with the sidewall of the first groove close to the active section; and / or

[0019] A sidewall of the second through hole close to the active section is coplanar with a sidewall of the second groove close to the active section.

[0020] In the display panel provided in the embodiment of the present application, the metal layer further includes a gate located on a side of the insulating layer away from the active layer, the gate is located between the source and the drain, and the gate is arranged corresponding to the active segment.

[0021] In the display panel provided in the embodiment of the present application, in a direction perpendicular to the substrate, the cross-sectional shape of the groove is one of circular, rectangular or polygonal.

[0022] In the display panel provided in the embodiment of the present application, the thickness of the groove is less than or equal to the thickness of the active layer.

[0023] In the display panel provided in the embodiment of the present application, the thickness of the groove is equal to the thickness of the active layer;

[0024] The conductor sub-section includes a first side adjacent to the lap portion, a second side adjacent to the active section, a third side adjacent to the first side or the second side, and a fourth side adjacent to the first side or the second side;

[0025] Wherein, the distance from any point in the groove to the third side is greater than 1 micron, and the distance from any point in the groove to the fourth side is greater than 1 micron.

[0026] An embodiment of the present application provides a display device, comprising any of the display panels described above.

[0027] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device, by providing an overlapping portion connected to the metal layer on the conductor segment in the thin film transistor layer, and a conductor sub-portion located between the overlapping portion and the active segment, and a groove is provided on the conductor sub-portion, thereby reducing the overall area of the conductor sub-portion, thereby weakening the diffusion of carriers to the active segment, and improving the stability of the thin film transistor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a schematic cross-sectional view of a conventional display panel;

[0030] Figure 2 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0031] Figure 3 A first top view of the active layer provided in an embodiment of the present application;

[0032] Figure 4 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0033] Figure 5 A second top view of the active layer provided in an embodiment of the present application;

[0034] Figure 6A flowchart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0035] 7A to 7D for Figure 6 The structural process flow chart of panel production is shown in the figure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0037] The embodiments of the present application provide a display panel and a display device. Detailed descriptions are provided below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0038] See also Figures 2 to 7D , an embodiment of the present application provides a display panel and a display device, wherein the display panel 1 includes:

[0039] Base 10;

[0040] a thin film transistor layer 20 disposed on the substrate 10, the thin film transistor layer 20 including an active layer 21 and a metal layer 23 stacked together, the active layer 21 including an active segment 211 and a conductor segment 212 connected to the active segment 211;

[0041] The conductor segment 212 includes a lap portion 212A connected to the metal layer 23 and a conductor sub-portion 212B located between the lap portion 212A and the active segment 211 . A groove 212C is defined in the conductor sub-portion 212B.

[0042] It is understandable that, currently, in existing display panels, such as Figure 11 is a schematic cross-sectional view of an existing display panel 1, which includes a substrate 10 and a buffer layer 30, an active layer 21, a gate insulating layer 22, a gate 23A, a passivation layer 50, a source electrode 23B, and a drain electrode 23C stacked on the substrate 10; wherein the active layer 21 includes an active segment 211 corresponding to the gate 23A, a first overlapping portion 212A1 in contact with the source electrode 23B, and a second overlapping portion 212A2 in contact with the drain electrode 23C. In the illustrated panel structure, before the source 23B and the drain 23C are manufactured, it is usually necessary to perform a conductorization process on the first overlapping portion 212A1 and the second overlapping portion 212A2 of the active layer 21 to improve the connection characteristics of the active layer 21 to the contact area of the source 23B and the drain 23C. However, the conductorized carriers located in the overlapping portion 212A of the active layer 21 will diffuse to the active section 211 of the active layer 21, causing a short channel effect, and will affect the stability of the thin film transistor layer 20 to a certain extent.

[0043] Continuing from the above, this embodiment provides a lap portion 212A connected to the metal layer 23 and a conductor sub-portion 212B located between the lap portion 212A and the active segment 211 on the conductor segment 212 in the thin film transistor layer 20, and a groove 212C is provided on the conductor sub-portion 212B. The groove 212C is used to prevent the carriers in the lap portion 212A from diffusing toward the active segment 211 after the conductorization process of the active layer 21, thereby improving the stability of the thin film transistor layer 20.

[0044] In one embodiment, please combine Figure 2 and Figure 3 ;in, Figure 2 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application; Figure 3 This is a first top view of the active layer provided in an embodiment of the present application.

[0045] This embodiment provides a display panel 1, which includes but is not limited to one of a light-emitting diode (LED) and an organic light-emitting diode display panel 1 (OLED), and this embodiment does not impose specific restrictions on this.

[0046] In this embodiment, the display panel 1 includes a substrate 10, a buffer layer 30, and a thin film transistor layer 20 located on a side of the buffer layer 30 away from the substrate 10; wherein the thin film transistor layer 20 includes an active layer 21 and a metal layer 23 that are stacked.

[0047] The substrate 10 includes a first substrate (not shown in the figure), a spacer layer (not shown in the figure) and a second substrate (not shown in the figure) stacked in sequence, wherein the first substrate and the second substrate may include a rigid substrate or a flexible substrate. When the first substrate and the second substrate are both rigid substrates, the material may be metal or glass. When the first substrate and the second substrate are both flexible substrates, the material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, silicone resin, polyimide resin, and polyamide resin. The material of the spacer layer includes but is not limited to silicon nitride (SiN x ), silicon oxide (SiO x ) and other materials with water absorption properties. This embodiment does not limit the materials of the first substrate, the second substrate and the spacer layer.

[0048] The active layer 21 includes but is not limited to an oxide active layer 21, and the material of the active layer 21 includes but is not limited to indium gallium zinc oxide (IGZO). The material of the metal layer 23 includes at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W).

[0049] Among them, the active layer 21 includes an active segment 211 and a conductor segment 212 connected to the active segment 211, the conductor segment 212 includes a lap portion 212A connected to the metal layer 23, and a conductor sub-portion 212B located between the lap portion 212A and the active segment 211, and a groove 212C is provided on the conductor sub-portion 212B; specifically, in the existing display panel 1 structure, it is usually necessary to perform a conductorization process on the lap portion of the active layer 21 to improve the connection characteristics of the active layer 21 to the contact area of the metal layer 23, and after the active layer 21 is conductorized, the carriers in the lap portion 212A tend to diffuse toward the active segment 211, and the groove 212C is used to prevent the carriers in the lap portion 212A from diffusing toward the active segment 211 after the conductorization process of the active layer 21, thereby improving the stability of the thin film transistor layer 20.

[0050] Furthermore, in the direction perpendicular to the substrate 10, the cross-sectional shape of the groove 212C includes but is not limited to one of a circle, a rectangle or a polygon, and the thickness of the groove 212C is less than or equal to the thickness of the active layer 21, that is, the groove 212C can be one of a groove structure or a through-hole structure; specifically, in this embodiment, the technical solution of the present application is illustrated by taking the cross-sectional shape of the groove 212C as a rectangle and the thickness of the groove 212C equal to the thickness of the active layer 21 as an example; and in specific implementation, the thickness of the groove 212C can be set according to specific needs or experience.

[0051] Preferably, the conductor sub-section 212B includes a first side (not marked in the figure) adjacent to the overlapping portion 212A, a second side (not marked in the figure) adjacent to the active section 211, a third side (not marked in the figure) adjacent to the first side or the second side, and a fourth side (not marked in the figure) adjacent to the first side or the second side; wherein, a distance D1 from any point in the groove 212C to the third side is greater than 1 micron, and a distance D2 from any point in the groove 212C to the fourth side is greater than 1 micron. Greater than 1 micron. It can be understood that before the metal layer 23 is produced, the overlapping portion 212A of the active layer 21 needs to be subjected to a conductor process so as to improve the connection characteristics of the active layer 21 to the contact area of the metal layer 23. In this embodiment, the distance from any point in the groove 212C to the third side is set to be greater than 1 micron, and the distance from any point in the groove 212C to the fourth side is set to be greater than 1 micron, thereby maintaining the conductive path of the carriers and making the thin film transistor layer 20 stable during operation.

[0052] It should be noted that this embodiment does not impose any specific restrictions on the number of the grooves 212C. This embodiment reduces the overall area of the conductor sub-section 212B by setting the grooves 212C in the conductor segment 212, thereby weakening the diffusion of carriers to the active segment 211 and improving the stability of the thin film transistor layer 20.

[0053] Furthermore, in this embodiment, the metal layer 23 includes a source 23B and a drain 23C arranged at intervals, and the source 23B and the drain 23C are connected to the overlapping portion 212A of the active layer 21; specifically, the overlapping portion 212A includes a first overlapping portion 212A1 in contact with the source 23B, and a second overlapping portion 212A2 in contact with the drain 23C, and the active section 211 is located between the first overlapping portion 212A1 and the second overlapping portion 212A2; the conductor sub-section 212B includes a first conductor sub-section 212B1 located between the first overlapping portion 212A1 and the active section 211, and a second conductor sub-section 212B2 located between the second overlapping portion 212A2 and the active section 211; wherein, a first groove 212C1 is provided on the first conductor sub-section 212B1, and a second groove 212C2 is provided on the second conductor sub-section 212B2.

[0054] It can be understood that in this embodiment, the conductor sub-section 212B includes a first conductor sub-section 212B1 located between the first overlapping section 212A1 and the active section 211, and a second conductor sub-section 212B2 located between the second overlapping section 212A2 and the active section 211. A first groove 212C1 is provided on the first conductor sub-section 212B1, thereby reducing the overall area of the first conductor sub-section 212B1. At the same time, a second groove 212C2 is provided on the second conductor sub-section 212B2, thereby reducing the overall area of the second conductor sub-section 212B2, thereby weakening the diffusion of carriers to the active section 211 and improving the stability of the thin film transistor layer 20.

[0055] Preferably, in this embodiment, the active section 211 further includes a first transition section close to the first conductor sub-section 212B1 and a second transition section close to the second conductor sub-section 212B2. Along the first direction X, the length of the orthographic projection of the first transition section on the substrate 10 is less than the length of the orthographic projection of the first conductor sub-section 212B1 on the substrate 10, and the length of the orthographic projection of the second transition section on the substrate 10 is less than the length of the orthographic projection of the second conductor sub-section 212B2 on the substrate 10. It should be noted that the first direction is Figure 3 The direction of X.

[0056] It can be understood that, in this embodiment, by setting the first transition section and the second transition section on the active layer 21, the conductive path of the carriers in the active layer 21 is reduced, thereby ensuring that the effective length of the active section 211 is not affected, thereby alleviating the diffusion of carriers to the active section 211 and improving the stability of the thin film transistor layer 20; at the same time, along the first direction X, the length of the positive projection of the first transition section on the substrate 10 is set to be smaller than the length of the positive projection of the first conductor sub-section 212B1 on the substrate 10, and the length of the positive projection of the second transition section on the substrate 10 is set to be smaller than the length of the positive projection of the second conductor sub-section 212B2 on the substrate 10, thereby maintaining the conductive path of the carriers in the conductor segment 212, so that the thin film transistor layer 20 remains stable during operation.

[0057] Furthermore, in this embodiment, the thin film transistor layer 20 also includes an insulating layer 22 located between the active layer 21 and the metal layer 23, and the orthographic projection of the insulating layer 22 on the substrate 10 covers the first transition section and the second transition section, that is, the first transition section and the second transition section are non-conductorized parts of the active layer 21.

[0058] The insulating layer 22 is provided with a first through hole corresponding to the first overlapping portion 212A1 and the first conductor sub-portion 212B1, and a second through hole corresponding to the second overlapping portion 212A2 and the second conductor sub-portion 212B2, the source 23B is connected to the first overlapping portion 212A1 through the first through hole, and the drain 23C is connected to the second overlapping portion 212A2 through the second through hole; wherein, the orthographic projection of the first groove 212C1 on the substrate 10 is located within the orthographic projection of the first through hole on the substrate 10, and the second groove 212C2 is located on the substrate 10. The orthographic projection of the first groove 212C1 is located within the orthographic projection of the second through hole on the substrate 10; specifically, the width of the orthographic projection of the first groove 212C1 on the substrate 10 is smaller than the width of the orthographic projection of the first through hole on the substrate 10, thereby controlling the size of the first groove 212C1, and the width of the orthographic projection of the second groove 212C2 on the substrate 10 is smaller than the width of the orthographic projection of the second through hole on the substrate 10, thereby controlling the size of the second groove 212C2, thereby maintaining the conductive path of the carriers in the conductor segment 212, and making the thin film transistor layer 20 stable during operation.

[0059] Furthermore, the sidewall of the source 23B close to the first groove 212C1 is coplanar with the sidewall of the first groove 212C1 away from the active section 211. Specifically, the angle between the sidewall of the source 23B close to the first groove 212C1 and the substrate 10 is equal to the angle between the sidewall of the first groove 212C1 away from the active section 211 and the substrate 10; the sidewall of the drain 23C close to the second groove 212C2 is coplanar with the sidewall of the second groove 212C2 away from the active section 211. Specifically, the angle between the sidewall of the drain 23C close to the second groove 212C2 and the substrate 10 is equal to the angle between the sidewall of the second groove 212C2 away from the active section 211 and the substrate 10.

[0060] It can be understood that, in this embodiment, the side wall of the source 23B close to the first groove 212C1 is coplanar with the side wall of the first groove 212C1 away from the active section 211, and the side wall of the drain 23C close to the second groove 212C2 is coplanar with the side wall of the second groove 212C2 away from the active section 211. Therefore, the first groove 212C1, the source 23B, the second groove 212C2 and the drain 23C can be manufactured in the same process, thereby maximizing the reduction of the process flow of the display panel 1 and saving production costs.

[0061] Furthermore, the metal layer 23 also includes a gate 23A located on the side of the insulating layer 22 away from the active layer 21, and the gate 23A is located between the source 23B and the drain 23C, and the gate 23A is arranged corresponding to the active section 211, that is, the active layer 21, the insulating layer 22 and the gate 23A are stacked in sequence. In this embodiment, the insulating layer 22 is used as the gate 23A insulating layer 22 as an example to illustrate the technical solution of the present application; it can be understood that in this embodiment, the source 23B, the drain 23C and the gate 23A are located in the same film layer and can be manufactured in the same process, thereby maximizing the reduction of the process flow of the display panel 1 and saving production costs.

[0062] It should be noted that, in this embodiment, the active layer 21, the insulating layer 22 and the gate 23A are stacked, and the source 23B, the drain 23C and the gate 23A are located in the same film layer for illustration only. This embodiment does not impose any specific restrictions on the positions of the source 23B, the drain 23C and the gate 23A.

[0063] In another embodiment, please combine Figure 4 and Figure 5;in, Figure 4 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application; Figure 5 This is a second top view of the active layer provided in an embodiment of the present application.

[0064] In this embodiment, the structure of the display panel 1 is similar to / identical to that of the display panel 1 provided in the above embodiment. For details, please refer to the description of the display panel 1 in the above embodiment, which will not be repeated here. The only difference between the two is:

[0065] The side wall of the first through hole close to the active section 211 is coplanar with the side wall of the first groove 212C1 close to the active section 211. Specifically, the angle between the side wall of the first through hole close to the active section 211 and the substrate 10 is equal to the angle between the side wall of the first groove 212C1 close to the active section 211 and the substrate 10. The side wall of the second through hole close to the active section 211 is coplanar with the side wall of the second groove 212C2 close to the active section 211. Specifically, the angle between the side wall of the second through hole close to the active section 211 and the substrate 10 is equal to the angle between the side wall of the second groove 212C2 close to the active section 211 and the substrate 10.

[0066] It can be understood that, in this embodiment, the side wall of the first through hole close to the active section 211 is coplanar with the side wall of the first groove 212C1 close to the active section 211, thereby minimizing the overall area of the first conductor sub-section 212B1. At the same time, the side wall of the second through hole close to the active section 211 is coplanar with the side wall of the second groove 212C2 close to the active section 211, thereby minimizing the overall area of the second conductor sub-section 212B2. Compared with the above embodiment, this embodiment further weakens the diffusion of carriers to the active section 211, thereby improving the stability of the thin film transistor layer 20.

[0067] It should be noted that, in this embodiment, the display panel 1 further includes a light-shielding layer 40 located between the buffer layer 30 and the substrate 10, the orthographic projection of the active layer 21 on the substrate 10 is located within the orthographic projection of the light-shielding layer 40 on the substrate 10, the insulating layer 22 is further provided with a third through hole corresponding to the light-shielding layer 40, the buffer layer is provided with a fourth through hole corresponding to the light-shielding layer 40, and the drain 23C is connected to the light-shielding layer 40 through the third through hole and the fourth through hole; it can be understood that the light-shielding layer 40 can block the light directed to the active layer 21, thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the active layer 21, thereby maintaining the stability of the display panel 1 during operation.

[0068] The present application also provides a method for manufacturing a display panel. Figure 2 、 Figure 3 、 Figure 6 as well as 7A to 7D The manufacturing method of the display panel comprises the following steps:

[0069] Step 100: providing a substrate 10, including providing a first substrate, and sequentially forming a spacer layer, a second substrate and a light shielding layer 40 on the first substrate; Figure 7A shown.

[0070] Among them, the material of the light-shielding layer 40 includes but is not limited to metal or opaque non-metal. In this embodiment, the material of the light-shielding layer 40 is preferably a metal material. The light-shielding layer 40 includes a first metal sublayer, a second metal sublayer and a third metal sublayer stacked. The material of the first metal sublayer and the material of the third metal sublayer include but are not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni). The thickness of the first metal sublayer and the thickness of the third metal sublayer are both The material of the second metal sub-layer includes but is not limited to copper (Cu) or copper alloy, and the thickness of the second metal sub-layer is Specifically, in this embodiment, a first metal layer 23 is deposited on the substrate 10, and a first yellow light process is used to pattern the first metal layer 23 by wet etching, thereby forming a light shielding layer 40 pattern with routing and light shielding functions.

[0071] Step 200: forming a buffer layer 30, an active layer 21 and an insulating layer 22 on the light shielding layer 40 in sequence, wherein the active layer 21 includes an active segment 211; Figure 7B shown.

[0072] The buffer layer 30 includes but is not limited to a single layer of silicon nitride (Si3N4), a single layer of silicon dioxide (SiO2), a single layer of silicon oxynitride (SiON x ), or a double-layer structure of the above film layers, the preparation method of the buffer layer 30 includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), and the thickness of the buffer layer 30 is

[0073] The active layer 21 includes but is not limited to an oxide semiconductor layer. The material of the oxide semiconductor layer includes but is not limited to indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO) or indium gallium zinc titanium oxide (IGZTO). Specifically, the oxide semiconductor layer is deposited on the buffer layer 30 by physical vapor deposition (PVD), and the oxide semiconductor layer is patterned by a second yellow light process to form the active layer 21. The thickness of the active layer 21 is

[0074] The material of the insulating layer 22 includes but is not limited to silicon oxide (SiOx), and the preparation method of the insulating layer 22 includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), wherein the oxygen content can be controlled by the PECVD process. The thickness of the insulating layer 22 is

[0075] Step 300: Patterning the insulating layer 22 and the buffer layer 30, forming a first through hole, a second through hole, and a third through hole in the insulating layer 22, and forming a fourth through hole corresponding to the third through hole in the buffer layer 30. Simultaneously, performing a first conductorization process on the active layer 21 to form conductor segments 212 located on both sides of the active segment 211 and connected to the active segment 211, wherein the conductor segment 212 includes a lap portion 212A and a conductor sub-portion 212B located between the lap portion 212A and the active segment 211; Figure 7C shown.

[0076] The method of patterning the insulating layer 22 includes but is not limited to a third yellow light process, and the angle between the sidewall of the fourth through hole and the substrate 10 is equal to the angle between the sidewall of the third through hole and the substrate 10 .

[0077] Step 400: forming a second metal layer 23 on the insulating layer 22, patterning the second metal layer 23 to form a source electrode 23B, a gate electrode 23A, and a drain electrode 23C spaced apart from each other, and patterning the active layer 21 to form a groove 212C on the conductor sub-portion 212B; Figure 7D shown.

[0078] The method for forming the second metal layer 23 on the insulating layer 22 includes physical vapor deposition (PVD). Specifically, the second metal layer 23 includes a fourth metal sublayer and a fifth metal sublayer stacked together. The material of the fourth metal sublayer includes but is not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni). The thickness of the fourth metal sublayer is The material of the fifth metal sublayer includes but is not limited to copper (Cu) or copper alloy, and the thickness of the fifth metal sublayer is

[0079] In step 400, a fourth yellow light process is used to pattern the second metal layer 23, and the two layers of metal wiring are etched using a wet etching process to form a source 23B, a gate 23A and a drain 23C that are spaced apart, and the gate 23A is arranged corresponding to the active segment 211; it can be understood that in this embodiment, the source 23B, the drain 23C and the gate 23A are located in the same film layer and can be manufactured in the same process, thereby maximizing the reduction of the process flow of the display panel 1 and saving production costs.

[0080] Specifically, the overlapping portion 212A includes a first overlapping portion 212A1 in contact with the source 23B, and a second overlapping portion 212A2 in contact with the drain 23C, the active section 211 is located between the first overlapping portion 212A1 and the second overlapping portion 212A2, the conductor sub-section 212B includes a first conductor sub-section 212B1 located between the first overlapping portion 212A1 and the active section 211, and a second conductor sub-section 212B2 located between the second overlapping portion 212A2 and the active section 211, wherein a first groove 212C1 is provided on the first conductor sub-section 212B1, and a second groove 212C2 is provided on the second conductor sub-section 212B2.

[0081] Further, the first through hole corresponds to the first overlapping portion 212A1 and the first conductor sub-portion 212B1, the second through hole corresponds to the second overlapping portion 212A2 and the second conductor sub-portion 212B2, the source 23B is connected to the first overlapping portion 212A1 through the first through hole, and the drain 23C is connected to the second overlapping portion 212A2 through the second through hole, wherein the orthographic projection of the first groove 212C1 on the substrate 10 is located within the orthographic projection of the first through hole on the substrate 10, and the orthographic projection of the second groove 212C2 on the substrate 10 is located within the orthographic projection of the second through hole on the substrate 10.

[0082] Preferably, the sidewall of the source 23B close to the first groove 212C1 is coplanar with the sidewall of the first groove 212C1 away from the active section 211. Specifically, the angle between the sidewall of the source 23B close to the first groove 212C1 and the substrate 10 is equal to the angle between the sidewall of the first groove 212C1 away from the active section 211 and the substrate 10; the sidewall of the drain 23C close to the second groove 212C2 is coplanar with the sidewall of the second groove 212C2 away from the active section 211. Specifically, the angle between the sidewall of the drain 23C close to the second groove 212C2 and the substrate 10 is equal to the angle between the sidewall of the second groove 212C2 away from the active section 211 and the substrate 10.

[0083] It can be understood that, in this embodiment, the side wall of the source 23B close to the first groove 212C1 is coplanar with the side wall of the first groove 212C1 away from the active section 211, and the side wall of the drain 23C close to the second groove 212C2 is coplanar with the side wall of the second groove 212C2 away from the active section 211. Therefore, the first groove 212C1, the source 23B, the second groove 212C2 and the drain 23C can be manufactured in the same process, thereby maximizing the reduction of the process flow of the display panel 1 and saving production costs.

[0084] Continuing from the above, in this embodiment, the conductor sub-section 212B includes a first conductor sub-section 212B1 located between the first overlapping portion 212A1 and the active section 211, and a second conductor sub-section 212B2 located between the second overlapping portion 212A2 and the active section 211. A first groove 212C1 is provided on the first conductor sub-section 212B1, thereby reducing the overall area of the first conductor sub-section 212B1. At the same time, a second groove 212C2 is provided on the second conductor sub-section 212B2, thereby reducing the overall area of the second conductor sub-section 212B2, thereby weakening the diffusion of carriers to the active section 211 and improving the stability of the thin film transistor layer 20.

[0085] In this embodiment, the method for manufacturing the display panel further includes the following steps:

[0086] Step 500 : etching the insulating layer 22 to form a channel region structure of the gate 23A / the gate 23A insulating layer 22 / the active layer 21 in a self-aligned manner, and performing a second conductorization process on the active layer 21 .

[0087] Step 600: forming a passivation layer 50 on the source electrode 23B, the drain electrode 23C and the gate electrode 23A; Figure 2 shown.

[0088] The material of the passivation layer 50 includes but is not limited to silicon dioxide (SiO2), and the thickness of the passivation layer 50 is

[0089] This embodiment provides a display device, which includes the display panel described in any of the above embodiments.

[0090] It can be understood that the display panel has been described in detail in the above embodiments and will not be repeated here.

[0091] In specific applications, the display device can be a display screen of a smartphone, tablet computer, laptop computer, smart bracelet, smart watch, smart glasses, smart helmet, desktop computer, smart TV or digital camera, and can even be used on electronic devices with flexible display screens.

[0092] In summary, the present application proposes a display panel and a display device, wherein the display panel includes a substrate and a thin film transistor layer arranged on the substrate, the thin film transistor layer includes an active layer and a metal layer stacked together, the active layer includes an active segment and a conductor segment connected to the active segment; wherein, the present application provides an overlapping portion connected to the metal layer on the conductor segment, and a conductor sub-portion located between the overlapping portion and the active segment, and a groove is provided on the conductor sub-portion, thereby reducing the overall area of the conductor sub-portion, thereby weakening the diffusion of carriers to the active segment, and improving the stability of the thin film transistor layer.

[0093] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0094] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: substrate; a thin film transistor layer disposed on the substrate, the thin film transistor layer comprising an active layer and a metal layer stacked together, the active layer comprising an active segment and a conductor segment connected to the active segment, the active segment comprising a transition segment adjacent to the conductor segment, the transition segment being a non-conductorized portion of the active layer; The conductor segment includes a lap portion connected to the metal layer, and a conductor sub-portion located between the lap portion and the active segment. A groove is provided on the conductor sub-portion, and the length of the conductor sub-portion's orthographic projection on the substrate is greater than the length of the transition segment's orthographic projection on the substrate.

2. The display panel according to claim 1, wherein: The metal layer includes a source electrode and a drain electrode that are spaced apart; The overlapping portion includes a first overlapping portion in contact with the source electrode and a second overlapping portion in contact with the drain electrode, and the active section is located between the first overlapping portion and the second overlapping portion; The conductor sub-section includes a first conductor sub-section located between the first lap portion and the active section, and a second conductor sub-section located between the second lap portion and the active section; Wherein, a first groove is formed on the first conductor sub-part, and a second groove is formed on the second conductor sub-part.

3. The display panel according to claim 2, wherein: The thin film transistor layer further includes an insulating layer located between the active layer and the metal layer, the insulating layer being provided with a first through-hole corresponding to the first overlapping portion and the first conductor sub-portion, and a second through-hole corresponding to the second overlapping portion and the second conductor sub-portion, the source electrode being connected to the first overlapping portion through the first through-hole, and the drain electrode being connected to the second overlapping portion through the second through-hole; The orthographic projection of the first groove on the substrate is located within the orthographic projection of the first through hole on the substrate, and the orthographic projection of the second groove on the substrate is located within the orthographic projection of the second through hole on the substrate.

4. The display panel according to claim 3, wherein: A sidewall of the source electrode close to the first groove is coplanar with a sidewall of the first groove away from the active section; and / or A sidewall of the drain electrode close to the second groove is coplanar with a sidewall of the second groove away from the active section.

5. The display panel according to claim 3, wherein: A sidewall of the first through hole close to the active section is coplanar with a sidewall of the first groove close to the active section; and / or A sidewall of the second through hole close to the active section is coplanar with a sidewall of the second groove close to the active section.

6. The display panel according to claim 3, wherein: The metal layer further includes a gate located on a side of the insulating layer away from the active layer. The gate is located between the source and the drain, and is arranged corresponding to the active segment.

7. The display panel according to claim 1, wherein: In a direction perpendicular to the substrate, a cross-sectional shape of the groove is one of circular, rectangular or polygonal.

8. The display panel according to claim 1, wherein: The thickness of the groove is less than or equal to the thickness of the active layer.

9. The display panel according to claim 8, wherein: The thickness of the groove is equal to the thickness of the active layer; The conductor sub-section includes a first side adjacent to the lap portion, a second side adjacent to the active section, a third side adjacent to the first side or the second side, and a fourth side adjacent to the first side or the second side; Wherein, the distance from any point in the groove to the third side is greater than 1 micron, and the distance from any point in the groove to the fourth side is greater than 1 micron.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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