An LDPC decoding method, device, equipment and readable storage medium

Abstract

The present invention discloses an LDPC decoding method, device, equipment and computer-readable storage medium, belonging to the field of decoding, and is used for LDPC decoding of data stored in NAND. When performing LDPC encoding and decoding, it is necessary to pad some data with zeros. Considering that during the decoding process, the data at the zero-padding positions in the variable nodes itself has a definite value and relatively high credibility. If a relatively complex decoding algorithm is used to update the prior probability and posterior probability of the zero-padding positions in the variable nodes, the decoding efficiency will inevitably be reduced. Therefore, in the decoding process of this application, a preset optimization update algorithm is used to update the prior probability and posterior probability of the zero-padding positions in the variable nodes. By setting a suitable preset optimization update algorithm, the amount of computation can be greatly reduced. On the one hand, the number of error corrections within a limited number of iterations can be increased, and on the other hand, the working efficiency is improved and the energy consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of decoding, and in particular to an LDPC decoding method. The present invention also relates to an LDPC decoding device, equipment, and computer-readable storage medium. Background Art

[0002] After data is stored in NAND, there is a certain probability of error. Therefore, it is necessary to encode the data before storage and decode the stored data to restore the data. During the decoding process, "data that has errors due to storage" will be corrected. LDPC (Low Density Parity Check Code) has become the mainstream error correction algorithm for NAND flash due to its excellent performance close to the Shannon limit and low decoding complexity. However, the existing LDPC algorithms have not been optimized specifically for the characteristics of NAND. The LDPC decoding method results in low working efficiency during the decoding process, with fewer error corrections within a limited number of iterations and high energy consumption.

[0003] Therefore, how to provide a solution to the above technical problems is an issue that those skilled in the art need to solve currently. Summary of the Invention

[0004] The object of the present invention is to provide an LDPC decoding method, which can, on the one hand, increase the number of error corrections within a limited number of iterations, and on the other hand, improve the working efficiency and reduce the energy consumption. Another object of the present invention is to provide an LDPC decoding device, equipment, and computer-readable storage medium, which can, on the one hand, increase the number of error corrections within a limited number of iterations, and on the other hand, improve the working efficiency and reduce the energy consumption.

[0005] To solve the above technical problems, the present invention provides an LDPC decoding method, including:

[0006] Padding zeros to the NAND bit information to be decoded and initializing it to obtain the initial probability value LLR of the variable nodes corresponding to each bit information;

[0007] Using a preset type of decoding method and the initial probability value to update the prior probability of the variable nodes corresponding to the non-padded zeros bit information, and using a preset optimization update algorithm to update the prior probability of the variable nodes corresponding to the padded zeros bit information;

[0008] Using the preset type of decoding method and the prior probability to update the check nodes;

[0009] Using the decoding method of the preset type and updating the posterior probability of the variable node corresponding to the bit information of the non-zero-padding bits by the check node, and updating the posterior probability of the variable node corresponding to the bit information of the zero-padding bits by the preset optimization update algorithm;

[0010] Determine whether the decoding is successful according to the updated variable node.

[0011] Preferably, the updating the prior probability of the variable node corresponding to the bit information of the zero-padding bits by the preset optimization update algorithm is specifically:

[0012] Keep the prior probability of the variable node corresponding to the bit information of the zero-padding bits unchanged;

[0013] The updating the posterior probability of the variable node corresponding to the bit information of the zero-padding bits by the preset optimization update algorithm is specifically:

[0014] Keep the posterior probability of the variable node corresponding to the bit information of the zero-padding bits unchanged.

[0015] Preferably, the decoding method of the preset type is the low-density parity-check code LDPC belief propagation BP decoding algorithm.

[0016] Preferably, the determining whether the decoding is successful according to the updated variable node is specifically:

[0017] Judge whether the check vector obtained according to the hard decision result of the updated variable node is an all-zero vector;

[0018] If so, the decoding is successful;

[0019] If not, execute the steps of updating the prior probability of the variable node corresponding to the bit information of the non-zero-padding bits by the decoding method of the preset type and the initial probability value, and updating the prior probability of the variable node corresponding to the bit information of the zero-padding bits by the preset optimization update algorithm.

[0020] Preferably, the judging whether the check vector obtained according to the hard decision result of the updated variable node is an all-zero vector is specifically:

[0021] Perform a hard decision on the variable node after the posterior probability is updated to obtain a hard decision value;

[0022] Dot-multiply the information sequence obtained by restoring the hard decision value with the check matrix to obtain a check vector;

[0023] Judge whether the check vector is an all-zero vector.

[0024] Preferably, after determining whether the check vector obtained based on the hard decision result of the updated variable node is an all-zero vector, before performing the step of updating the prior probability of the variable node corresponding to the non-zero-supplemented bit information by using the preset type of decoding method and the initial probability value, and updating the prior probability of the variable node corresponding to the zero-supplemented bit information by using the preset optimization update algorithm, this LDPC decoding method further includes:

[0025] If it is not an all-zero vector, increment the iteration count with an initial value of zero and determine whether the iteration count reaches a preset threshold;

[0026] If it does not reach, perform the step of updating the prior probability of the variable node corresponding to the non-zero-supplemented bit information by using the preset type of decoding method and the initial probability value, and updating the prior probability of the variable node corresponding to the zero-supplemented bit information by using the preset optimization update algorithm;

[0027] If it reaches, determine that the decoding fails.

[0028] Preferably, after determining whether the iteration count reaches a preset threshold, this LDPC decoding method further includes:

[0029] If it reaches, control the prompt to prompt that the decoding fails.

[0030] To solve the above technical problems, the present invention also provides an LDPC decoding device, including:

[0031] An initialization module, configured to zero-fill and initialize the NAND bit information to be decoded to obtain the initial probability value LLR of the variable node corresponding to each bit information;

[0032] A first update module, configured to update the prior probability of the variable node corresponding to the non-zero-supplemented bit information by using the preset type of LDPC decoding method and the initial probability value, and update the prior probability of the variable node corresponding to the zero-supplemented bit information by using the preset optimization update algorithm;

[0033] A second update module, configured to update the check node by using the preset type of LDPC decoding method and the prior probability;

[0034] A third update module, configured to update the posterior probability of the variable node corresponding to the non-zero-supplemented bit information by using the preset type of LDPC decoding method and the check node, and update the posterior probability of the variable node corresponding to the zero-supplemented bit information by using the preset optimization update algorithm;

[0035] A judgment module, configured to determine whether the decoding is successful according to the updated variable node.

[0036] To solve the above technical problems, the present invention also provides an LDPC decoding device, including:

[0037] A memory for storing a computer program;

[0038] A processor for implementing the steps of the LDPC decoding method as described above when executing the computer program.

[0039] To solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the LDPC decoding method as described above are implemented.

[0040] The present invention provides an LDPC decoding method. Affected by the NAND physical structure and the SSD control chip algorithm, when performing LDPC encoding and decoding, it is necessary to fill some data with zeros. Considering that during the decoding process, the data at the zero-filled positions in the variable nodes has a definite value and a relatively high reliability. If a relatively complex decoding algorithm is used to update the prior probability and the posterior probability of the zero-filled positions in the variable nodes, the decoding efficiency will surely be reduced. Therefore, in the decoding process of this application, a preset optimized update algorithm is used to update the prior probability and the posterior probability of the zero-filled positions in the variable nodes. By setting a suitable preset optimized update algorithm, the amount of computation can be greatly reduced. On the one hand, the number of error corrections within a limited number of iterations can be increased, and on the other hand, the working efficiency is improved and the energy consumption is reduced.

[0041] The present invention also provides an LDPC decoding device, equipment, and computer-readable storage medium, which have the same beneficial effects as the above LDPC decoding method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 A flowchart of an LDPC decoding method provided by the present invention;

[0044] Figure 2 A schematic diagram of LDPC data and NAND data provided by the present invention;

[0045] Figure 3 A schematic diagram of the structure of an LDPC decoding device provided by the present invention;

[0046] Figure 4 Schematic structural diagram of an LDPC decoding device provided by the present invention. Specific embodiments

[0047] The core of the present invention is to provide an LDPC decoding method, which can, on the one hand, increase the number of error corrections within a limited number of iterations, and on the other hand, improve work efficiency and reduce energy consumption; another object of the present invention is to provide an LDPC decoding device, equipment, and computer-readable storage medium, which can, on the one hand, increase the number of error corrections within a limited number of iterations, and on the other hand, improve work efficiency and reduce energy consumption.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0049] Please refer to Figure 1 , Figure 1 Schematic flowchart of an LDPC decoding method provided by the present invention. The LDPC decoding method includes:

[0050] S101: Pad zeros to the NAND bit information to be decoded and initialize it to obtain the initial probability value LLR of the variable node corresponding to each bit information.

[0051] Specifically, considering the technical problems in the above background art, the present application proposes an optimized LDPC decoding method. In the initial stage of decoding, NAND bit information needs to be received from the storage device, and then the NAND bit information is initialized to obtain information nodes and used as initial variable nodes. The variable nodes can serve as the data basis for subsequent steps.

[0052] To better illustrate the embodiments of the present invention, please refer to Figure 2 , Figure 2 Schematic diagram of LDPC data and NAND data provided by the present invention. LDPC (Low Density Parity Check Code) is a linear block code based on a parity-check matrix and has been widely used due to its strong error correction ability. Theoretically, a completely random LDPC code has the best error correction performance. However, the parity-check matrix of a QC (Quasi-Cyclic)-LDPC code has a quasi-cyclic characteristic, and the distribution of non-zero elements in the entire matrix is very regular, with the characteristic of low hardware implementation complexity.

[0053] Among them, QC-LDPC first constructs and optimizes the index matrix, and then expands it according to the expansion coefficient. Let the code length be N, the number of parity bits be M, and the number of information bits be K (N = M + K). The parity-check matrix H is an M×N binary matrix, and the index matrix P is an M P ×N P matrix, where M = M P ×L, N = N P ×L, K = K P ×L, and L is the expansion coefficient. The code length N, the number of parity bits M, and the number of information bits K of QC-LDPC are all integer multiples of the expansion coefficient L. For the convenience of hardware implementation, generally L is an integer power of 2, such as 64, 128, 256, etc. However, affected by the NAND physical structure and the SSD (Solid State Disk) control chip algorithm, the actual length K' of the data that needs to be protected when writing into NAND is generally not an integer multiple of L. Define the difference ΔK = K - K' (K ≥ K'). Therefore, during LDPC encoding and decoding, it is necessary to pad ΔK bits of data with zeros. For specific details, please refer to Figure 2 , during LDPC encoding, the encoder needs to pad ΔK bits of data with zeros. However, after encoding is completed, the ΔK bits of data are not actually written into the NAND flash. When reading data from the NAND flash, during LDPC decoding, the decoder needs to pad ΔK bits of data with zeros. After decoding is successful, the information of the padded ΔK bits of data is not passed back to the SSD main controller.

[0054] Specifically, the process of initializing the variable nodes can specifically include two steps. The first step is to first pad the NAND bit information with zeros so that the sum of the information bit length of the data stored in NAND and the zero-padding bit length is equal to the LDPC data information bit length K. The second step is to perform numerical conversion on each bit of the zero-padded data (including parity bits, information bits, and zero-padding bits). The conversion process is specifically to add a preset value of Y 1s after each bit of data to obtain the form of X111… (X is the data of this bit itself, which is 0 or 1), and then convert the array X111… corresponding to this bit of data into a "signed decimal number" in the way of "converting the first bit to a positive or negative sign and the remaining bits to decimal values". Thus, the initialization is completed.

[0055] Among them, the value of the preset value Y can be set independently, and the embodiments of the present invention do not limit this here.

[0056] S102: Update the prior probability of the variable nodes corresponding to the bit information of the non-zero-padded bits using a preset type of decoding method and the initial probability value, and update the prior probability of the variable nodes corresponding to the bit information of the zero-padded bits using a preset optimization update algorithm;

[0057] S103: Update the check nodes using a preset type of decoding method and the prior probability;

[0058] S104: Use a preset type of decoding method and check nodes to update the posterior probability of variable nodes corresponding to non-zero-bit bit information, and use a preset optimization update algorithm to update the posterior probability of variable nodes corresponding to zero-filled-bit bit information;

[0059] Specifically, during the decoding process, multiple iterations are required. The process of each iteration can be simply understood as updating the prior probability and posterior probability of each bit of data in the variable nodes. However, since this application takes into account that during the decoding process, the data of the zero-filled bits in the variable nodes itself has a definite value and high credibility. If a relatively complex decoding algorithm is used to update the prior probability and posterior probability of the zero-filled bits in the variable nodes, it will inevitably reduce the decoding efficiency. Therefore, in this application during the decoding process, a preset optimization update algorithm is used to update the prior probability and posterior probability of the zero-filled bits in the variable nodes, so as to reduce the calculation amount, improve the decoding efficiency, increase the number of error corrections within a limited number of iterations, and reduce energy consumption.

[0060] Among them, the preset optimization update algorithm can be of various types, and the embodiments of the present invention do not limit it here.

[0061] S105: Determine whether the decoding is successful according to the updated variable nodes;

[0062] Specifically, after updating the variable nodes, it is possible to determine whether the decoding is successful according to the updated variable nodes, so as to automatically complete LDPC decoding.

[0063] The present invention provides an LDPC decoding method. Affected by the NAND physical structure and the SSD control chip algorithm, during LDPC encoding and decoding, it is necessary to fill some data with zeros. Considering that during the decoding process, the data of the zero-filled bits in the variable nodes itself has a definite value and high credibility. If a relatively complex decoding algorithm is used to update the prior probability and posterior probability of the zero-filled bits in the variable nodes, it will inevitably reduce the decoding efficiency. Therefore, in this application during the decoding process, a preset optimization update algorithm is used to update the prior probability and posterior probability of the zero-filled bits in the variable nodes. By setting a suitable preset optimization update algorithm, the operation amount can be greatly reduced. On the one hand, the number of error corrections within a limited number of iterations can be increased, and on the other hand, the working efficiency is improved and the energy consumption is reduced.

[0064] Based on the above embodiments:

[0065] As a preferred embodiment, specifically, using the preset optimization update algorithm to update the prior probability of the variable node corresponding to the zero-filled-bit bit information is:

[0066] Keep the prior probability of the variable node corresponding to the bit information with zero-padding unchanged;

[0067] Update the posterior probability of the variable node corresponding to the bit information with zero-padding by using a preset optimization update algorithm, specifically:

[0068] Keep the posterior probability of the variable node corresponding to the bit information with zero-padding unchanged.

[0069] Specifically, considering that during the decoding process, the variable node corresponding to the bit information with zero-padding itself has a definite value and high reliability, and the data with zero-padding is actually self-defined 0 data which does not need to change itself. Therefore, in the embodiments of the present invention, when updating the prior probability and posterior probability of each bit of data in the variable node, use the LDPC decoding method of a preset type to update the prior probability and posterior probability of the variable node corresponding to the bit information without zero-padding, and keep the variable node corresponding to the bit information with zero-padding unchanged during the update process of the prior probability and posterior probability, so as to reduce the amount of computation, increase the number of error corrections, and reduce the energy consumption to the greatest extent.

[0070] Of course, in addition to this method, other types of preset optimization update algorithms can also be used to update the prior probability and posterior probability of the data with zero-padding, and the embodiments of the present invention do not limit this here.

[0071] As a preferred embodiment, the decoding method of the preset type is the low-density parity-check code LDPC belief propagation BP decoding algorithm.

[0072] Specifically, the BP (Belief Propagation) decoding algorithm has advantages such as low computational complexity and fast operation speed.

[0073] Of course, in addition to the BP decoding algorithm, the decoding method of the preset type can also be other types, and the embodiments of the present invention do not limit this here.

[0074] The currently widely used LDPC decoding algorithm is the BP decoding algorithm, and the most typical ones in the BP decoding algorithm include: LLR (Log-Likelihood Ratio)-BP decoding algorithm, MS (Min-Sum), and its derivative algorithms, etc. The LLR-BP decoding algorithm is the logarithmic domain BP algorithm and also the standard decoding algorithm. Although the decoding performance of this algorithm is relatively good, a large number of addition operations and look-up table calculations of the hyperbolic tangent function are required during the decoding iterative operation, which has a high complexity and is not easy to be applied and implemented. There are many existing LDPC decoding algorithms at present, and most of them are optimized based on the belief propagation decoding algorithm. These include the MS (Min-Sum) algorithm, NMS (Normalized Min-Sum) algorithm, bias algorithm, and so on. The optimized algorithm has a simple structure. It eliminates the cumbersome calculation of the hyperbolic tangent function, replaces the original complex exponential and logarithmic operations with simple comparison and addition operations, and greatly reduces the computational complexity at the cost of sacrificing a little decoding performance.

[0075] As a preferred embodiment, specifically determining whether the decoding is successful according to the updated variable nodes is as follows:

[0076] Determine whether the check vector obtained according to the hard decision result of the updated variable nodes is an all-zero vector;

[0077] If so, the decoding is successful;

[0078] If not, perform the steps of updating the prior probability of the variable nodes corresponding to the bit information of the non-zero-complemented bits by using a preset type of decoding method and the initial probability value, and updating the prior probability of the variable nodes corresponding to the bit information of the zero-complemented bits by using a preset optimization update algorithm.

[0079] Specifically, after updating the variable nodes, it can be determined whether the decoding is successful by judging whether "the check vector obtained according to the hard decision result of the updated variable nodes is an all-zero vector". This judgment method has a high accuracy and a small amount of calculation.

[0080] Of course, in addition to this judgment method, other types of judgment methods can also be used according to the updated variable nodes to judge whether the decoding is successful. The embodiments of the present invention do not make limitations here.

[0081] Specifically, when the check vector obtained according to the hard decision result of the updated variable nodes is an all-zero vector, it means that all the error data of the information bits in the data stored in the NAND have been corrected, that is, the decoding is successful.

[0082] Specifically, when the check vector obtained according to the hard decision result of the updated variable node is not an all-zero vector, it indicates that there is still data with uncorrected information bits in the data stored in the NAND. At this time, step S102 can be returned to perform iteration again to correct the error.

[0083] As a preferred embodiment, determining whether the check vector obtained according to the hard decision result of the updated variable node is an all-zero vector is specifically as follows:

[0084] Perform hard decision on the variable node after updating the posterior probability to obtain a hard decision value;

[0085] Dot-multiply the information sequence obtained by restoring the hard decision value with the parity-check matrix to obtain a check vector;

[0086] Determine whether the check vector is an all-zero vector.

[0087] Specifically, hard decision actually converts the data at each position into binary data 0 or 1 to obtain a hard decision value. Therefore, the hard decision value can be restored to an information sequence, and whether the check is successful can be determined by analyzing this information sequence. Specifically, the method is to determine whether the check vector obtained by dot-multiplying the information sequence with the parity-check matrix is an all-zero vector.

[0088] Among them, the specific determination method in the embodiment of the present invention has high accuracy and small calculation amount.

[0089] As a preferred embodiment, the preset type of decoding method is the Min-Sum (MS) decoding algorithm.

[0090] Specifically, the MS (Min-Sum) decoding algorithm has advantages such as small calculation amount and fast speed.

[0091] Specifically, the following takes the Min-Sum method as an example to describe the LDPC decoding method in the embodiment of the present invention:

[0092] The LDPC code length is N, the parity-check bit length is M, and the information bit length is K, where N = M + K.

[0093] The SSD includes an information bit length of K', and it is defined that ΔK = K - K' (K ≥ K'), then the data bit length N' stored in the NAND = N - ΔK.

[0094] S201: Receive NAND bit information and initialize the information node L n ;

[0095] S202: Update the prior probability of the variable node;

[0096]

[0097] S203: Update the check node message

[0098]

[0099] S204: Update the posterior probability of the variable node;

[0100]

[0101] S205: Hard decision;

[0102]

[0103] S206: Determine whether the checksum (the information sequence multiplied by the check matrix) is an all-zero vector. If it is an all-zero vector, the decoding is successful;

[0104] S207: Determine whether the number of iterations has reached a preset threshold. If so, the decoding fails. Otherwise, repeat S202 - S206.

[0105] Where i is the number of iterations, n = 0, 1, 2, …, N - 1; m = 0, 1, 2, …, M - 1; L n : The initial log-domain likelihood ratio LLR value of the variable node vn; P n : The ending LLR value of the variable node vn; The hard decision value of the variable node vn; M(n): The set of check nodes connected to the variable node vn; N(m): The set of variable nodes connected to the check node cm; The LLR value of the i-th round from the variable node vn to the check node cm; The LLR value of the i-th round from the check node cm to the variable node vn.

[0106] Of course, in addition to this decoding algorithm, the BP decoding algorithm can also be of other types, which are not limited in the embodiments of the present invention.

[0107] As a preferred embodiment, after determining whether the check vector obtained according to the hard decision result of the updated variable node is an all-zero vector, before performing the steps of updating the prior probability of the variable node corresponding to the non-zero-bit bit information using a preset type of decoding method and the initial probability value, and updating the prior probability of the variable node corresponding to the zero-filled-bit bit information using a preset optimization update algorithm, the LDPC decoding method further includes:

[0108] If it is not an all-zero vector, increment the iteration number with an initial value of zero and determine whether the iteration number has reached a preset threshold;

[0109] If not, perform the steps of updating the prior probability of the variable node corresponding to the bit information of the non-zero-padding bits by using a preset type of decoding method and the initial probability value, and updating the prior probability of the variable node corresponding to the bit information of the zero-padding bits by using a preset optimization update algorithm;

[0110] If so, determine that the decoding fails.

[0111] Specifically, considering that the number of iterations required for decoding in some abnormal cases is very large, and it may even never succeed in decoding. In this case, in order to avoid a large number of unnecessary iterative calculations, a preset threshold for the number of iterations is set in the embodiments of the present invention. As long as the decoding has not been successful after the number of iterations reaches this preset threshold, then it can be determined that the decoding fails.

[0112] As a preferred embodiment, after determining whether the number of iterations reaches the preset threshold, the LDPC decoding method further includes:

[0113] If so, control the prompt device to prompt that the decoding fails.

[0114] Specifically, in order to facilitate the staff to timely discover the situation of decoding failure and handle it, in the embodiments of the present invention, the prompt device can be controlled to prompt that the decoding fails.

[0115] Among them, the prompt device can be of various types. For example, it can be a voice announcer, etc. The embodiments of the present invention do not limit this here.

[0116] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of an LDPC decoding device provided by the present invention. The LDPC decoding device includes:

[0117] An initialization module 31, configured to perform zero-padding and initialization on the NAND bit information to be decoded, and obtain the initial probability value LLR of the variable node corresponding to each bit information;

[0118] A first update module 32, configured to update the prior probability of the variable node corresponding to the bit information of the non-zero-padding bits by using a preset type of LDPC decoding method and the initial probability value, and update the prior probability of the variable node corresponding to the bit information of the zero-padding bits by using a preset optimization update algorithm;

[0119] A second update module 33, configured to update the check node by using a preset type of LDPC decoding method and the prior probability;

[0120] A third update module 34, configured to update the posterior probability of the variable node corresponding to the bit information of the non-zero-padding bits by using a preset type of LDPC decoding method and the check node, and update the posterior probability of the variable node corresponding to the bit information of the zero-padding bits by using a preset optimization update algorithm;

[0121] A judgment module 35, configured to determine whether decoding is successful according to the updated variable nodes.

[0122] For the introduction of the LDPC decoding device provided by the embodiments of the present invention, please refer to the embodiments of the LDPC decoding method described above, and the embodiments of the present invention will not be elaborated herein.

[0123] Please refer to Figure 4 , Figure 4 FIG. is a schematic structural diagram of an LDPC decoding device provided by the present invention. The LDPC decoding device includes:

[0124] A memory 41, configured to store a computer program;

[0125] A processor 42, configured to implement the steps of the LDPC decoding method in the foregoing embodiments when executing the computer program.

[0126] For the introduction of the LDPC decoding device provided by the embodiments of the present invention, please refer to the embodiments of the LDPC decoding method described above, and the embodiments of the present invention will not be elaborated herein.

[0127] The present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the LDPC decoding method in the foregoing embodiments are implemented.

[0128] For the introduction of the computer-readable storage medium provided by the embodiments of the present invention, please refer to the embodiments of the LDPC decoding method described above, and the embodiments of the present invention will not be elaborated herein.

[0129] In the present specification, the embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the method part. It should also be noted that in this specification, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0130] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LDPC decoding method, characterized in that, Including: Padding zeros to the NAND bit information to be decoded and initializing it to obtain the initial probability value LLR of the variable nodes corresponding to each bit information; Updating the prior probability of the variable nodes corresponding to the non-padded zeros bit information using a preset type of decoding method and the initial probability value, and updating the prior probability of the variable nodes corresponding to the padded zeros bit information using a preset optimization update algorithm; Updating the check nodes using the preset type of decoding method and the prior probability; Updating the posterior probability of the variable nodes corresponding to the non-padded zeros bit information using the preset type of decoding method and the check nodes, and updating the posterior probability of the variable nodes corresponding to the padded zeros bit information using the preset optimization update algorithm; Determining whether the decoding is successful based on the updated variable nodes; The specific method of updating the prior probability of the variable nodes corresponding to the padded zeros bit information using the preset optimization update algorithm is: Keeping the prior probability of the variable nodes corresponding to the padded zeros bit information unchanged; The specific method of updating the posterior probability of the variable nodes corresponding to the padded zeros bit information using the preset optimization update algorithm is: Keeping the posterior probability of the variable nodes corresponding to the padded zeros bit information unchanged.

2. The LDPC decoding method according to claim 1, wherein The preset type of decoding method is the low-density parity-check code LDPC belief propagation BP decoding algorithm.

3. The LDPC decoding method according to claim 1, wherein The specific method of determining whether the decoding is successful based on the updated variable nodes is: Judging whether the check vector obtained from the hard decision result of the updated variable nodes is an all-zero vector; If so, the decoding is successful; If not, execute the step of updating the prior probability of the variable nodes corresponding to the non-padded zeros bit information using the preset type of decoding method and the initial probability value, and updating the prior probability of the variable nodes corresponding to the padded zeros bit information using the preset optimization update algorithm.

4. The LDPC decoding method according to claim 3, wherein The specific method of judging whether the check vector obtained from the hard decision result of the updated variable nodes is an all-zero vector is: Performing a hard decision on the variable nodes after the posterior probability is updated to obtain a hard decision value; Dot-multiplying the information sequence obtained by restoring the hard decision value with the parity-check matrix to obtain a check vector; Judging whether the check vector is an all-zero vector.

5. The LDPC decoding method according to claim 4, wherein After judging whether the check vector obtained from the hard decision result of the updated variable nodes is an all-zero vector, and before executing the step of updating the prior probability of the variable nodes corresponding to the non-padded zeros bit information using the preset type of decoding method and the initial probability value, and updating the prior probability of the variable nodes corresponding to the padded zeros bit information using the preset optimization update algorithm, this LDPC decoding method further includes: If it is not an all-zero vector, increment the iteration count with an initial value of zero and judge whether the iteration count reaches a preset threshold; If not, execute the step of updating the prior probability of the variable nodes corresponding to the non-padded zeros bit information using the preset type of decoding method and the initial probability value, and updating the prior probability of the variable nodes corresponding to the padded zeros bit information using the preset optimization update algorithm; If it reaches, determine that the decoding fails.

6. The LDPC decoding method according to claim 5, wherein After determining whether the number of iterations reaches a preset threshold, the LDPC decoding method further includes: If it reaches, control the prompt to indicate decoding failure.

7. An LDPC decoding device, characterized in that, It includes: An initialization module, configured to zero-fill and initialize the NAND bit information to be decoded to obtain the initial probability value LLR of the variable nodes corresponding to each bit information; A first update module, configured to update the prior probability of the variable nodes corresponding to the bit information of the non-zero-filled bits by using a preset type of LDPC decoding method and the initial probability value, and update the prior probability of the variable nodes corresponding to the bit information of the zero-filled bits by using a preset optimization update algorithm; A second update module, configured to update the check nodes by using the preset type of LDPC decoding method and the prior probability; A third update module, configured to update the posterior probability of the variable nodes corresponding to the bit information of the non-zero-filled bits by using the preset type of LDPC decoding method and the check nodes, and update the posterior probability of the variable nodes corresponding to the bit information of the zero-filled bits by using the preset optimization update algorithm; A judgment module, configured to determine whether the decoding is successful according to the updated variable nodes; Specifically, the third update module is configured to: Keep the prior probability of the variable nodes corresponding to the bit information of the zero-filled bits unchanged; Keep the posterior probability of the variable nodes corresponding to the bit information of the zero-filled bits unchanged.

8. An LDPC decoding device, characterized in that, It includes: A memory, configured to store a computer program; A processor, configured to implement the steps of the LDPC decoding method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the LDPC decoding method according to any one of claims 1 to 6 are implemented.

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