Signal correction for serial interfaces

Abstract

This application relates to signal correction for serial interfaces. A signal correction circuitry is described that improves the integrity of data transmitted over a serial data interface without interrupting communication between connected devices. The signal correction circuitry includes edge correction circuitry that accelerates rising and falling edges of a data signal. The signal correction circuitry also includes DC compensation circuitry that boosts the level of the data signal.

Description

Technical Field

[0001] This application relates to signal correction for serial interfaces. Background Technology

[0002] There are various transport protocols used for transmitting serial data between connected devices. Examples of such protocols include the DisplayPort standard, the High Definition Multimedia Interface (HDMI) standard, the Serial ATA standard, the Peripheral Component Interconnect High Speed ​​(PCI-E) standard, the Universal Serial Bus (USB) standard, the Hypertransport protocol, the InfiniBand protocol, the XAUI protocol, and the Ethernet protocol. Each of these protocols has evolved over time to include multiple generations of protocols, and for at least some protocols, there are multiple versions within each generation. Serial interfaces can be implemented using single-ended or differential signaling according to any of these standards. An example of this serial interface is... Figure 1 It is displayed in the middle.

[0003] Serial interface 102 connects upstream device 104 to downstream device 106 using differential signaling, where serial data is represented using signal lines of opposite polarities designated DP and DM. Although many serial interfaces are bidirectional, interface 102 is depicted as unidirectional for simplicity. It is well known that the integrity of signals transmitted through this interface decreases as the frequency or data rate of the signal and / or the length of the transmission line increases. See also... Figure 2A and 2B To understand.

[0004] Figure 2A and 2B It is a representation of the "eye mask compliance" test, in which multiple, one-unit-interval (UI) signal captures (equivalent to one clock cycle) of serial data streams (e.g., signals on signal lines DP and DM) are superimposed. Figure 2A This indicates that the test passed, meaning signals 202 and 204 did not intrude into the boundaries of the fault area (cover) in the middle (206) of the eye and above and below the eye (208 and 210). For example, this might be for an interface containing very short transmission lines. On the other hand, Figure 2B This indicates a test failure where signals 212 and 214 violated the boundary of cover 206. Such signal degradation can occur, for example, when the interface signal lines are too long for the frequency or data rate of the serial data signal.

[0005] Signal degradation issues on serial interfaces are typically addressed by introducing one or more repeaters between the connected devices. For example, see... Figure 3A repeater 302 is used between connected devices 304 and 306. A repeater (e.g., a re-driver or re-timer) is a device that restores signal integrity when data is transmitted between connected devices. A repeater may include components such as a receiver, equalizer, and transmitter, and may require complex detection and control, interrupting communication between connected devices, introducing unwanted delays, and resulting in additional power consumption and system costs. Summary of the Invention

[0006] According to a specific category of embodiments, a circuit includes an interface configured for parallel connection with a differential transmission line. The differential transmission line includes a first signal line and a second signal line. An edge correction circuit system is configured to detect signal crossings on the first and second signal lines, and in response to detecting the signal crossings, pulls one of the first and second signal lines up to a first reference voltage for a predetermined time period, and pulls the other of the first and second signal lines down to a second reference voltage for the same predetermined time period. A level correction circuit system is configured to, after the predetermined time period and for at least one bit duration, increase the signal level on the one of the first and second signal lines pulled up to the first reference voltage by a predetermined amount.

[0007] According to a specific embodiment, the differential transmission line is configured to operate according to a serial data transmission protocol. The serial data transmission protocol has a first operating mode corresponding to a first operating speed and a second operating mode corresponding to a second operating speed. The circuitry includes an enable circuitry system configured to enable the edge correction circuitry system and the level correction circuitry system when the differential transmission line is configured for the first operating mode, and to disable the edge correction circuitry system and the level correction circuitry system when the differential transmission line is configured for the second operating mode.

[0008] According to a more specific implementation, the serial data transmission protocol is the Universal Serial Bus (USB) 2.0 protocol, and the first operating mode is high-speed operation.

[0009] According to another, more specific embodiment, the enable circuitry is configured to detect whether the differential transmission line is operating in the first mode or the second mode, and if the differential transmission line is operating in the first mode, then an enable signal is generated. According to even more specific embodiments, the enable circuitry is configured to detect whether the differential transmission line is operating in the first mode or the second mode by referring to one or more signals associated with the training of the differential transmission line or by referring to serial data transmitted on the differential transmission line.

[0010] According to another, more specific implementation, the interface provides overvoltage protection during the second operating mode.

[0011] In another specific implementation of this type of implementation, the predetermined time period is configurable.

[0012] According to another specific implementation, the predetermined amount is configurable.

[0013] According to yet another specific embodiment, the level correction circuit system is configured to boost the signal level on one of the first and second signal lines pulled up to the first reference voltage until a subsequent signal crossover is detected.

[0014] According to another type of embodiment, a transmission line includes a first signal line and a second signal line. An edge correction circuit system is configured to detect signal crossings on the first and second signal lines, and in response to detecting the signal crossings, pulls one of the first and second signal lines up to a first reference voltage for a predetermined time period, and pulls the other of the first and second signal lines down to a second reference voltage for the same predetermined time period. A level correction circuit system is configured to increase the signal level on the one of the first and second signal lines pulled up to the first reference voltage by a predetermined amount after the predetermined time period and for at least one bit duration. Neither the edge correction circuit system nor the level correction circuit system interrupts data transmission on the first and second signal lines.

[0015] According to a particular embodiment, the transmission line is configured to operate according to a serial data transmission protocol. The serial data transmission protocol has a first operating mode corresponding to a first operating speed and a second operating mode corresponding to a second operating speed. The transmission line includes an enable circuitry configured to enable the edge correction circuitry and the level correction circuitry when the transmission line is configured for the first operating mode, and to disable the edge correction circuitry and the level correction circuitry when the transmission line is configured for the second operating mode.

[0016] According to a more specific implementation, the serial data transmission protocol is the Universal Serial Bus (USB) 2.0 protocol, and the first operating mode is high-speed operation.

[0017] According to another, more specific embodiment, the enable circuitry is configured to detect whether the transmission line is operating in the first mode or the second mode, and if the transmission line is operating in the first mode, then an enable signal is generated. According to even more specific embodiments, the enable circuitry is configured to detect whether the transmission line is operating in the first mode or the second mode by referring to one or more signals associated with the training of the transmission line or by referring to serial data transmitted on the transmission line.

[0018] According to another, more specific implementation, the overvoltage protection circuit system is configured to provide overvoltage protection during the second operating mode.

[0019] In another specific implementation of this type of implementation, the predetermined time period is configurable.

[0020] According to another specific implementation, the predetermined amount is configurable.

[0021] According to another specific embodiment, the level correction circuit system is configured to boost the signal level on one of the first and second signal lines pulled up to the first reference voltage until a subsequent signal crossover is detected.

[0022] According to another particular embodiment, the transmission line includes at least one additional example of the edge correction circuit system and at least one additional example of the level correction circuit system.

[0023] A further understanding of the nature and advantages of the various embodiments can be achieved by referring to the rest of the specification and the accompanying drawings. Attached Figure Description

[0024] Figure 1 Describe two devices connected by a differential transmission line.

[0025] Figure 2A and 2B Explain the success and failure of the blindfold compliance test.

[0026] Figure 3 Describe two devices connected by multiple differential transmission lines and intervention repeaters.

[0027] Figure 4 The invention describes two devices connected by a differential transmission line having an associated signal correction circuit system enabled by this disclosure.

[0028] Figure 5 This is a simplified schematic diagram of a specific implementation of the signal correction circuit system enabled by this disclosure.

[0029] Figure 6This is a timing diagram illustrating the operation of a specific implementation of the signal correction circuit system enabled by this disclosure. Detailed Implementation

[0030] Reference will now be made in detail to specific embodiments. Examples of these embodiments are illustrated in the accompanying drawings. It should be noted that these examples are described for illustrative purposes and are not intended to limit the scope of this disclosure. Rather, alternatives, modifications, and equivalents of the described embodiments are included within the scope of this disclosure as defined by the appended claims. Furthermore, specific details are provided to facilitate a thorough understanding of the described embodiments. Some embodiments within the scope of this disclosure may be practiced without some or all of these details. Moreover, well-known features may not have been described in detail for clarity.

[0031] This disclosure describes a signal correction circuit system that improves the integrity of data transmitted via a serial data interface without interrupting communication between connected devices. According to some embodiments, the signal correction circuit system includes an edge correction circuit system that accelerates the rising and falling edges of the data signal. According to some embodiments, the signal correction circuit system also includes a DC compensation circuit system that raises the level of the data signal. Examples will be illustrative.

[0032] Figure 4 This is a simplified block diagram of the system, in which signal correction circuitry system 402 improves the integrity of data transmitted between upstream device 404 and downstream device 406 via a serial interface. (Similar to...) Figure 3 In contrast to the repeater insertion depicted in the diagram, the connection of data transmission lines DP and DM to the signal correction circuit system 402 actually parallels the signal correction circuit system with the serial interface, thereby allowing the transmission lines DP and DM to remain continuous between the connected devices and thus not interrupt the data signal as a repeater would.

[0033] It should be noted that, depending on the length and / or characteristics of the interface's transmission line, a single example of such a signal correction circuit system may be insufficient to maintain signal integrity. Therefore, embodiments in which more than one example of the signal correction circuit system enabled by this disclosure can be integrated at different points along the interface's transmission line are considered.

[0034] As will be discussed, one type of implementation involves a serial interface implemented according to USB 2.0. However, it should be noted that implementations for other generations and / or versions of USB and several other serial data protocols should also be considered, such as DisplayPort, HDMI, Serial ATA, PCI-E, Hypertransport, InfiniBand, XAUI, and Ethernet protocols and their various versions.

[0035] It should also be noted that various differential signaling protocols exist that can be used with the embodiments enabled by this disclosure, such as differential stub-line series termination logic (SSTL), differential high-speed transceiver logic (HSTL), low-voltage differential signaling (LVDS), differential low-voltage positive emitter coupled logic (LVPECL), and low-swing differential signaling (RSDS), as well as other differential digital signaling protocols. Furthermore, embodiments using single-ended serial interface protocols are considered, such as low-voltage transistor-to-transistor logic (LVTTL) and low-voltage complementary metal-oxide-semiconductor (LVCMOS) for PCI, and other single-ended serial interface protocols. However, for clarity and not limitation, differential signaling should be assumed to be used.

[0036] Return to reference Figure 4 Consider that not all operating modes of transmission line 408 require an implementation of signal correction circuitry system 402. For example, a particular version of a serial data protocol may have multiple operating modes characterized by different data rates. It is also possible that transmission line 408 passes one or more blindfold compliance tests at lower data rates but fails one or more blindfold compliance tests at higher data rates. In such implementations, the ability to enable and disable signal correction circuitry system 402 based on operating mode may be useful.

[0037] Therefore, according to some implementations, speed detection logic 410 detects the data rate that will be used for data transmission between devices 404 and 406, and asserts or de-asserts the assertion enable signal EN depending on the detected rate. According to a particular implementation, the data rate may be detected by logic 410 "snipping" or "listening" to the handshake signal between the connected devices during link training. However, it should be noted that other information may be used. For example, the data rate of the incoming data itself may be detected. In another instance, the magnitude or oscillation of the data signal may be used (possibly in conjunction with handshake listening). More generally, any information that can be used to identify the mode of operation and / or the data rate at which the connected devices are communicating may be used for this purpose.

[0038] It should also be noted that Figure 4 Only the downstream transmission path from device 404 to device 406 is shown. However, it will be understood that the upstream transmission path may contain substantially the same circuitry for serial data transmission from device 406 to device 404. According to some embodiments, logic 410 may be integrated with signal correction circuitry 402. Alternatively, logic 410 may be implemented separately from circuitry 402. Furthermore, signal correction circuitry 402 and / or logic 410 may be integrated with the serial interface to varying degrees.

[0039] According to an implementation where the serial data interface is a specific type of USB 2.0 interface, the signal correction circuitry system 402 is configured to be disabled for low-speed and full-speed operation of the interface (i.e., with maximum data rates of 1.5 and 12 Mbps respectively), and enabled for high-speed operation (i.e., with a maximum data rate of 480 Mbps). Specific implementations of the signal correction circuitry system suitable for use in such implementations are described in... Figure 5 It is displayed in the middle.

[0040] Figure 5 The signal correction circuit system 500 includes an edge correction circuit system 502 and a DC compensation circuit system 504. As will be discussed, when the enable signal EN is asserted (e.g., high), the differential signal lines DP and DM are connected to the circuit systems 502 and 504 via input switches 506 and 508. Switches 506 and 508 also provide overvoltage protection against higher voltages on DP and DM during low-speed and full-speed operation (during which no signal correction is performed).

[0041] Edge correction circuitry system 502 accelerates the rise and fall times of signals on DP and DM by pulling signals up or down to corresponding reference voltages, shown as Vref and ground in the depicted example. Signals on DP are pulled up or down via switch 506 and one or more of switches 510 and 512. Similarly, signals on DM are pulled up or down via switch 508 and one or more of switches 514 and 516. Different reference voltages may be used depending on the application in which the serial interface is deployed. When a serial interface is installed, the reference voltage can be configured (it may be independent of other system voltages). The appropriate range of configurability for the reference voltage will depend on the generation and / or version of the serial data protocol and the application in which the interface is installed. In the context of USB 2.0, an example of a suitable range for Vref is approximately 0.4 to 0.6 volts.

[0042] Signal correction is provided by edge correction circuitry system 502 for a configurable time period (e.g., less than one UI), after which signal correction is taken over by DC compensation circuitry system 504. The correction performed by DC compensation circuitry system 504 ensures that the signal levels on DP and DM remain sufficiently high, regardless of the number of UIs in which the signal remains in a given state. The boost provided by circuitry system 504 can be configured when the serial interface is installed, for example, based on measured actual losses. A suitable range of configurability will depend on the generation and / or version of the serial data protocol and the application in which the interface is installed. An example of a suitable range in the context of USB 2.0 is 0 to 100 mV, for example, in 20 mV steps.

[0043] The operating time of the edge correction circuitry system 502 is determined by delay elements 518 and 520 and can be configured when the serial interface is installed. A suitable range for the configurability of the delay will depend on the generation and / or version of the serial data protocol, the application in which the interface is installed, and the typical bit or UI duration (e.g., the delay may correspond to a specific portion of a bit or the UI duration). In the context of USB 2.0, an example of a suitable range for the delay time is approximately 0.5 to 1.0 ns. Typically, the delay introduced by delay elements 518 and 520 will be the same. However, it is possible to consider that the delay described therein may be different implementations. For example, if the losses introduced by DP and DM are different, then different delays may be introduced to account for this.

[0044] Now refer to Figure 6 The signal timing diagram provides a more detailed description of the operation of the signal correction circuit system 500. Comparators 522 and 524 (which may be differential receivers including equalization) detect when the signals on DP and DM cross, thereby indicating the transition of the differential signal. This results in an assertion of EN_DP_RISE or EN_DM_RISE (depending on which signal is rising) during the assertion period when dlym or dlyp is held (520 dly or 518 dly, respectively, determined by delay elements 520 and 518). As can be seen, the assertion of EN_DP_RISE causes DP to be pulled up to Vref (via switch 510) and DM to be pulled down to ground (via switch 516). Similarly, the assertion of EN_DM_RISE causes DM to be pulled up to Vref (via switch 514) and DP to be pulled down to ground (via switch 512). As mentioned above, the assertion of any signal is temporary, as determined by the delay element associated with the other half of the edge correction circuitry system 502.

[0045] According to a specific implementation plan and such Figure 6 As illustrated in the timing diagram, comparators 522 and 524 are configured with offsets so that signal crossovers on DP and DM are detected early. This compensates for the delay associated with the comparators themselves. For example, if the comparator delay is 1 ns, then the offset of each of the comparators can be set such that the output of the comparator (e.g., OUTP or OUTM) switches 0.3 ns before the actual signal crossover.

[0046] After a delay determined by delay elements 518 or 520 (depending on which signal is rising), either the asserted EN_DP_RISE or EN_DM_RISE is de-asserted, thereby disabling the edge correction circuitry system 502. The DC compensation circuitry system 504 is then enabled, providing a configurable voltage boost by connecting either DP or DM (depending on which pair of signals OUTP / dlyp or OUTM / dlym is asserted) to the current source 526 via switch 530 or switch 532 (two n-channel devices). For example, if both OUTP and dlyp are asserted (and therefore the signal on DP is asserted long enough), then EN_DP_DC is de-asserted and switch 530 is turned on. Similarly, if both OUTM and dlym are asserted, then EN_DM_DC is de-asserted and switch 532 is turned on. When the signals on DP and DM change, both EN_DP_DC and EN_DM_DC are asserted, and the current source 526 is not connected to DP or DM, but sends its current to ground through switch 534 and resistor 528. That is, the signal correction performed by DC compensation circuit system 504 is disabled to support the signal correction performed by edge correction circuit system 502.

[0047] As mentioned above, the voltage boost provided by current source 526 can be configured to suit specific applications. And as referenced... Figure 5 and 6 As understood from the foregoing description, once the DC compensation circuitry system 504 is enabled, it will continue to provide its voltage boost to one or the other of the DP or DM until the next signal transition.

[0048] As those skilled in the art will appreciate, the signal correction circuitry system enabled by this disclosure can be implemented to consume less power than a typical repeater without interrupting signal transmission between connected devices.

[0049] The various implementations described herein can be implemented using any of a variety of standard or proprietary CMOS processes. Additionally, it should be noted that implementations employing a wider range of semiconductor materials and manufacturing processes are also considered, including, for example, GaAs, SiGe, etc. The signal correction circuitry system described herein can be represented (but is not limited to) in software (object code or machine code in non-transitory computer-readable media), at different stages of compilation, as one or more netlists (e.g., SPICE netlists), in analog languages, in hardware description languages ​​(e.g., Verilog, VHDL), through a set of semiconductor processing masks, and as a partially or fully implemented semiconductor device (e.g., ASIC). Some implementations may be standalone integrated circuits, while others may be integrated with an associated serial interface.

[0050] Those skilled in the art will understand that changes may be made to the form and details of the embodiments described herein without departing from the scope of this disclosure. Furthermore, although various advantages, aspects, and objectives have been described with reference to various embodiments, the scope of this disclosure should not be limited by such advantages, aspects, and objectives. Rather, the scope of this disclosure should be determined with reference to the appended claims.

Claims

1. A circuit comprising: An interface configured for parallel connection with a differential transmission line comprising a first signal line and a second signal line; An edge correction circuit system is configured to detect signal crossings on the first and second signal lines, and in response to detecting the signal crossings, pulls one of the first and second signal lines up to a first reference voltage for a predetermined time period, and pulls the other of the first and second signal lines down to a second reference voltage for the same predetermined time period. A level correction circuit system configured to increase the signal level on one of the first and second signal lines pulled up to the first reference voltage by a predetermined amount after the predetermined time period and for at least one bit duration. and An enable circuit system is configured to enable or disable the edge correction circuit system and the level correction circuit system.

2. The circuit of claim 1, wherein the differential transmission line is configured to operate according to a serial data transmission protocol having a first operating mode corresponding to a first operating speed and a second operating mode corresponding to a second operating speed, and wherein the enable circuit system is configured to enable the edge correction circuit system and the level correction circuit system when the differential transmission line is configured for the first operating mode, and to disable the edge correction circuit system and the level correction circuit system when the differential transmission line is configured for the second operating mode.

3. The circuit according to claim 2, wherein the serial data transmission protocol is the Universal Serial Bus (USB) 2.0 protocol, and wherein the first operating mode is high-speed operation.

4. The circuit of claim 2, wherein the enable circuit system is configured to detect whether the differential transmission line is operating in the first mode or the second mode, and if the differential transmission line is operating in the first mode, then an enable signal is generated.

5. The circuit of claim 4, wherein the enable circuit system is configured to detect whether the differential transmission line is operating in the first mode or the second mode by referring to one or more signals associated with training of the differential transmission line or by referring to serial data transmitted on the differential transmission line.

6. The circuit of claim 2, wherein the interface provides overvoltage protection during the second operating mode.

7. The circuit according to claim 1, wherein the predetermined time period is configurable.

8. The circuit of claim 1, wherein the predetermined amount is configurable.

9. The circuit of claim 1, wherein the level correction circuit system is configured to boost the signal level on one of the first and second signal lines pulled up to the first reference voltage until a subsequent signal crossover is detected.

10. A transmission line system comprising: First signal line and second signal line; An edge correction circuit system is configured to detect signal crossings on the first and second signal lines, and in response to detecting the signal crossings, pulls one of the first and second signal lines up to a first reference voltage for a predetermined time period, and pulls the other of the first and second signal lines down to a second reference voltage for the same predetermined time period. A level correction circuit system configured to increase the signal level on one of the first and second signal lines pulled up to the first reference voltage by a predetermined amount after the predetermined time period and for at least one bit duration. and An enable circuit system is configured to enable or disable the edge correction circuit system and the level correction circuit system; Neither the edge correction circuit system nor the level correction circuit system interrupts the first and Data transmission on the second signal line.

11. The system of claim 10, wherein the system is configured to operate according to a serial data transmission protocol having a first operating mode corresponding to a first operating speed and a second operating mode corresponding to a second operating speed, and wherein the enable circuit system is configured to enable the edge correction circuit system and the level correction circuit system when the system is configured for the first operating mode, and to disable the edge correction circuit system and the level correction circuit system when the system is configured for the second operating mode.

12. The system of claim 11, wherein the serial data transmission protocol is the Universal Serial Bus (USB) 2.0 protocol, and wherein the first operating mode is high-speed operation.

13. The system of claim 11, wherein the enable circuit system is configured to detect whether the system is operating in the first mode or the second mode, and if the system is operating in the first mode, then an enable signal is generated.

14. The system of claim 13, wherein the enable circuitry is configured to detect whether the system is operating in the first mode or the second mode by referring to one or more signals associated with training of the system or by referring to serial data transmitted on the system.

15. The system of claim 11, further comprising an overvoltage protection circuit system configured to provide overvoltage protection during the second operating mode.

16. The system of claim 10, wherein the predetermined time period is configurable.

17. The system of claim 10, wherein the predetermined amount is configurable.

18. The system of claim 10, wherein the level correction circuitry is configured to boost the signal level on one of the first and second signal lines pulled up to the first reference voltage until a subsequent signal crossover is detected.

19. The system of claim 10, further comprising at least one additional example of the edge correction circuit system and at least one additional example of the level correction circuit system.

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