Instruction processing method, processor, device and storage medium

Abstract

The embodiments of the present application disclose an instruction processing method, processor, device and storage medium, which can be applied to the field of computer technology. The method includes: in response to the target pipeline executing the target branch instruction, determining the target prediction path corresponding to the target branch instruction; in response to the target prediction path being an incorrect path, re-determining the target path corresponding to the target branch instruction; in response to the target instruction information of each target instruction on the target path being stored in the preset cache space, obtaining each target instruction information from the preset cache space, and executing each target instruction based on each target instruction information. By adopting the embodiments of the present application, when the predicted path of the branch instruction is an incorrect path, the time consumed in obtaining and executing instructions on the correct path can be reduced, thereby improving instruction processing efficiency and having high applicability.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction processing method, processor, device, and storage medium. Background Art

[0002] During pipeline execution of instructions, a branch instruction must be predicted. If the prediction fails, the pipeline must be flushed and the next instruction on the correct path must be retrieved, which consumes significant time. Furthermore, the need to retrieve the correct path for the branch instruction also causes subsequent pipeline stages to remain idle, reducing instruction processing efficiency. Summary of the Invention

[0003] The embodiments of the present application provide an instruction processing method, processor, device, and storage medium, which can reduce the time consumed in obtaining and executing instructions corresponding to the correct path when the predicted path of the branch instruction is an incorrect path, thereby improving instruction processing efficiency and having high applicability.

[0004] In one aspect, an embodiment of the present application provides an instruction processing method, the method comprising:

[0005] In response to the target pipeline executing the target branch instruction, determining a target predicted path corresponding to the target branch instruction;

[0006] In response to the target predicted path being an incorrect path, re-determining a target path corresponding to the target branch instruction, the target path being a correct path corresponding to the target branch instruction;

[0007] In response to target instruction information of each target instruction on the target path being stored in a preset cache space, obtaining each target instruction information from the preset cache space, and executing each target instruction based on the target instruction information;

[0008] The command information in the above-mentioned preset cache space is determined based on the following method:

[0009] In response to any pipeline executing any branch instruction, a prediction path corresponding to the branch instruction is determined, and instruction information of each instruction on the prediction path is stored in the preset cache space.

[0010] On the other hand, an embodiment of the present application further provides a processor, comprising a branch prediction unit, an instruction cache unit, and an execution unit;

[0011] The branch prediction unit is configured to, in response to the target pipeline executing the target branch instruction, determine a target predicted path corresponding to the target branch instruction; and in response to the target predicted path being an incorrect path, re-determine a target path corresponding to the target branch instruction, so that the target path is a correct path corresponding to the target branch instruction;

[0012] The execution unit is configured to, in response to the target instruction information of each target instruction on the target path being stored in the instruction cache unit, obtain each target instruction information from the instruction cache unit, and execute each target instruction based on the target instruction information;

[0013] The branch prediction unit is further configured to determine a prediction path corresponding to a branch instruction in response to any pipeline executing any branch instruction; and the instruction cache unit is configured to store instruction information of each instruction on the prediction path.

[0014] On the other hand, an embodiment of the present application provides an instruction processing device, the device comprising:

[0015] a branch prediction module, configured to determine a target prediction path corresponding to a target branch instruction in response to a target pipeline executing the target branch instruction;

[0016] a branch judgment module, configured to, in response to the target predicted path being an incorrect path, re-determine a target path corresponding to the target branch instruction, the target path being a correct path corresponding to the target branch instruction;

[0017] an instruction processing module, configured to, in response to target instruction information of each target instruction on the target path being stored in a preset cache space, obtain each target instruction information from the preset cache space, and execute each target instruction based on the target instruction information;

[0018] The command information in the above-mentioned preset cache space is determined based on the following method:

[0019] In response to any pipeline executing any branch instruction, a prediction path corresponding to the branch instruction is determined, and instruction information of each instruction on the prediction path is stored in the preset cache space.

[0020] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the instruction processing method provided by the embodiment of the present application.

[0021] In an embodiment of the present application, by caching the instruction information of each instruction on the predicted path of each branch instruction, when the predicted path corresponding to a branch instruction is an incorrect path, the instruction on the correct path corresponding to the branch instruction can be directly obtained from the preset cache space, thereby quickly filling the pipeline, improving instruction processing efficiency, and saving instruction processing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a flowchart of the instruction processing method provided in the embodiment of the present application;

[0024] Figure 2 This is a schematic diagram of the structure of the preset cache space provided in an embodiment of the present application;

[0025] Figure 3 This is a schematic diagram of a flow chart of the instruction processing method provided in an embodiment of the present application;

[0026] Figure 4 is a schematic diagram of the structure of the processor provided in an embodiment of the present application;

[0027] Figure 5 It is a structural diagram of the instruction processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] See also Figure 1 , Figure 1 This is a flow chart of the instruction processing method provided in the embodiment of the present application. Figure 1 As shown, the instruction processing method provided in the embodiment of the present application may specifically include the following steps:

[0030] Step S11: In response to the target pipeline executing the target branch instruction, determine the target predicted path corresponding to the target branch instruction.

[0031] In the embodiment of the present application, the target pipeline is the currently executing pipeline. When executing various instructions for the target pipeline, the instruction fetch unit (IFU) can obtain the starting instruction based on the boot address, and decode and analyze the starting instruction to execute the starting instruction based on the decoded instruction information. In addition, during the decoding, analysis, and execution of the starting instruction, the instruction address of the next instruction to be executed is determined by the program counter (PC).

[0032] To ensure continuous pipeline execution, the starting address of the initial instruction must be entered into the instruction counter before the pipeline begins execution. As instructions are executed, the CPU automatically updates the instruction counter, incrementing it by an amount equal to the number of bytes in the instruction, so that the instruction counter always contains the address of the next instruction to be executed.

[0033] Among them, the pipeline often includes branch instructions. When executing a branch instruction, it is often necessary to determine the correct path of the branch instruction in order to further execute the instructions on the correct path. Therefore, when the target pipeline executes the target branch instruction, it is necessary to determine the target predicted path of the target branch instruction.

[0034] The predicted path for any branch instruction in any pipeline can be determined using a branch predictor. A branch instruction is an instruction that changes the pipeline flow. If the branch instruction succeeds, the next instruction to be executed is changed.

[0035] In the embodiment of the present application, the target branch instruction may be any conditional branch instruction in the target pipeline.

[0036] Step S12: In response to the target predicted path being an incorrect path, re-determine the target path corresponding to the target branch instruction.

[0037] In some feasible implementations, determining the target predicted path corresponding to the target branch instruction may also be regarded as determining the instruction address of the next instruction to be executed after the target branch instruction.

[0038] When the target predicted path of the target branch instruction is an incorrect path, such as when the next instruction to be executed is determined to be an incorrect instruction based on the instruction address of the next instruction to be executed after the target branch instruction, it is necessary to clear the target pipeline and re-determine the correct path corresponding to the target branch instruction (for the convenience of description, referred to as the target path below), that is, to re-determine the instruction address of the next instruction to be executed after the target branch instruction.

[0039] Step S13 : In response to the target instruction information of each target instruction on the target path being stored in the preset cache space, each target instruction information is acquired from the preset cache space, and each target instruction is executed based on the target instruction information.

[0040] In some feasible implementations, after re-determining the target path corresponding to the target branch instruction, it may be determined whether target instruction information of each target instruction on the target path is stored in a preset cache space.

[0041] If the preset cache space stores target instruction information of each target instruction on the target path, there is no need to re-obtain the target instruction on the target path from the instruction cache (iCache) based on the instruction fetch unit. Instead, the target instruction information of each target instruction on the target path can be directly obtained from the preset cache space, so that each target instruction on the target path can be executed directly based on the target instruction information.

[0042] If the target instruction information of each target instruction on the target path is not stored in the preset cache space, it is necessary to re-obtain each target instruction on the target path from the instruction cache through the instruction fetch unit, decode each target instruction and execute each target instruction based on the target instruction information of each target instruction obtained through decoding.

[0043] In some feasible implementations, for most conditional branch instructions, the instructions on their false path may be used in the current pipeline or in other pipelines. For example, the instructions on the false path corresponding to a certain conditional branch instruction may become the instructions on the correct path corresponding to other conditional branch instructions. In other words, the instructions on the false path corresponding to a certain conditional branch instruction may become the instructions on the correct path corresponding to other conditional branch instructions.

[0044] In this case, the instruction information of each instruction in the preset cache space is determined based on the following method:

[0045] In response to any pipeline executing any branch instruction, a prediction path corresponding to the branch instruction is determined, and instruction information of each instruction on the prediction path is stored in a preset cache space.

[0046] That is, for any pipeline, when the pipeline executes any branch instruction, it is necessary to determine the predicted path corresponding to the branch instruction through the branch predictor, and store the instruction information of each instruction on the predicted path into a preset cache space.

[0047] Among them, any branch instruction of any of the above pipelines is also a conditional branch instruction.

[0048] Among them, the instruction information of each instruction on the prediction path can be the result information obtained after decoding and analyzing each instruction on the prediction path, or it can be related information used to describe each instruction on the prediction path. The specific information can be determined based on the actual application scenario requirements and is not limited here.

[0049] Optionally, for any branch instruction, before storing instruction information for each instruction on the predicted path of the branch instruction in a predetermined cache space, a probability of the correct path corresponding to the branch instruction, as predicted by the branch predictor, can be determined. If the probability of correctness is greater than a certain value, it indicates that the predicted path determined this time is likely to be the correct path corresponding to the branch instruction, and furthermore, it indicates that the correct path corresponding to the branch instruction will likely be correctly predicted with a high probability when the branch instruction is encountered again in the future. Therefore, it is not necessary to store the instruction information for each instruction on the predicted path in the predetermined cache space.

[0050] If the correct probability is less than or equal to a certain value, it means that the predicted path determined this time is likely to be the wrong path corresponding to the branch instruction, and further indicates that when the branch instruction is encountered again in the future, the predicted path determined based on the branch predictor is likely to be an wrong path. In this case, the instruction information of each instruction on the predicted path can be determined and stored in the preset cache space.

[0051] Optionally, for any branch instruction, if the instruction information of each instruction on the predicted path is directly stored in the preset cache space after the predicted path corresponding to the branch instruction is determined, then after the instruction information of each instruction on the predicted path of the branch instruction is stored in the preset cache space, the correctness of the predicted path can be further determined.

[0052] If the predicted path corresponding to the branch instruction is the correct path, it means that the correct path corresponding to the branch instruction can be correctly predicted when the branch instruction is encountered again in the future. Therefore, the instruction information of each instruction on the predicted path of the branch instruction stored in the preset cache space can be cleared. If the predicted path corresponding to the branch instruction is the wrong path, it means that the predicted path determined when the branch instruction is encountered again in the future is the wrong path. Therefore, there is no need to clear the instruction information of each instruction on the predicted path of the branch instruction stored in the preset cache space. Among them, the preset storage space and the pipeline are independent of each other. When the pipeline is cleared, there is no need to clear the data in the preset cache space.

[0053] In some feasible implementations, for each branch instruction, when the instruction information of each instruction on the predicted path of the branch instruction is stored in a preset cache space, the instruction address of the first instruction on the predicted path can be determined, and the instruction address of the first instruction can be used as the base address (basepc) corresponding to each instruction on the predicted path of the branch instruction.

[0054] Furthermore, the base address corresponding to the predicted path and the instruction information of each instruction on the predicted path may be associated and stored in a preset cache space.

[0055] The base address corresponding to the predicted path and the instruction information for each instruction on the predicted path can be stored in the same location in the preset cache space, so that the base address and the instruction information for each instruction are stored in association. For example, they can be stored in the same cache node or the same page table entry in the preset cache space. The specific location can be determined based on actual application scenarios and is not limited here.

[0056] Optionally, for any predicted path corresponding to a branch instruction, when the base address corresponding to the predicted path and the instruction information of each instruction on the predicted path are associated and stored in a preset cache space, the maximum offset (maxoffset) corresponding to the predicted path can also be associated and stored.

[0057] For any branch instruction corresponding to a predicted path, the maximum offset corresponding to the predicted path is used to indicate the number of instructions on the predicted path. Based on the base address and maximum offset corresponding to the predicted path, the instruction addresses of the instructions on the predicted path corresponding to the branch instruction can be determined.

[0058] As an example, see Figure 2 , Figure 2 This is a schematic diagram of the structure of the preset cache space provided by the embodiment of the present application. Figure 2 As shown, the preset cache space may include multiple cache nodes, each of which may be used to store instruction information of each instruction on the predicted path corresponding to a branch instruction. The number of cache nodes in the preset cache space may be determined based on the storage capacity of the preset cache space and the cache capacity of each cache node, and may be configured based on actual application scenario requirements without any restrictions. Figure 2 A cache node in the , for any branch instruction, can decode and analyze each instruction in the predicted path corresponding to the branch instruction to obtain instruction information for each instruction. Further, a base address is determined based on the instruction address of the first instruction, and a maximum offset is determined based on the number of instructions. Thus, the instruction information, base address, and maximum offset corresponding to the predicted path corresponding to the branch instruction are stored in the same cache node.

[0059] In some feasible implementations, when determining whether the preset cache space stores target instruction information of the target instruction on the target path of the target branch instruction, the target instruction address of the first target instruction executed after the target branch instruction may be determined.

[0060] Furthermore, the target instruction address of the first target instruction executed after the target branch instruction is matched with each base address in the preset cache space. If the preset cache space stores a target base address that matches the target instruction address of the first target instruction executed after the target branch instruction, it indicates that the instruction information associated with the target base address is the target instruction information of each target instruction on the target path corresponding to the target branch instruction. Conversely, if the preset cache space does not store a target base address that matches the target instruction address of the first target instruction executed after the target branch instruction, it indicates that the preset cache space does not store the target instruction information of the target instructions on the target path corresponding to the target branch instruction.

[0061] Furthermore, when the preset cache space stores target instruction information of each target instruction on the target path corresponding to the target branch instruction, each instruction information associated with the target base address can be obtained, so that each target instruction can be executed based on the each instruction information associated with the target base address.

[0062] Furthermore, during the execution of each target instruction corresponding to the target branch instruction, a target maximum offset associated with the target base address in the preset cache space may be determined. Furthermore, based on the target maximum offset and the target instruction address of the first target instruction executed after the target branch instruction, the instruction address of the next instruction to be executed after the execution of each target instruction is determined.

[0063] Among them, if the instruction address of the first target instruction executed after the target branch instruction is redirectpc, and the target maximum offset is maxoffset, then the execution address of the next instruction to be executed after executing each target instruction is redirectPC+maxoffset.

[0064] Based on this, in the process of executing each target instruction corresponding to the target branch instruction, the instruction to be executed can be obtained based on the instruction address of the next instruction to be executed after executing each target instruction, and the instruction to be executed can be further decoded and analyzed to execute the instruction to be executed after the execution of each target instruction is completed.

[0065] In an embodiment of the present application, for the target pipeline, after determining the target prediction path corresponding to the target branch instruction, if the target prediction path is an incorrect path, the instruction address of the first instruction on the target prediction path can also be determined, and the instruction address of the first instruction on the target prediction path can be matched with each base address in the preset cache space.

[0066] If the preset cache space stores a base address that matches the instruction address of the first instruction on the target prediction path, the correct path corresponding to the target branch instruction is re-determined. If the preset cache space does not store a base address that matches the instruction address of the first instruction on the target prediction path, the instruction information of each instruction on the target prediction path and the base address and maximum offset corresponding to the target prediction path can be determined, and then the instruction information of each instruction on the target prediction path and the base address and maximum offset corresponding to the target prediction path are associated and stored in the preset cache space, so that when the target prediction path is the correct path corresponding to other branch instructions of the target pipeline or the correct path of branch instructions of other pipelines, the instruction information of each instruction corresponding to the correct path can be obtained from the preset cache space, thereby further reducing the time consumption of instruction acquisition and decoding analysis.

[0067] The following combination Figure 3 The instruction processing method provided in the embodiment of the present application is further explained. Figure 3 This is a schematic diagram of a flow chart of the instruction processing method provided in the embodiment of the present application. Figure 3 As shown, the instruction fetch unit (IFU) normally fetches instructions according to the boot address. When the instruction of the target pipeline flows to the decoder, it is found that the target pipeline executes a conditional branch instruction, and the branch predictor determines the predicted path corresponding to the conditional branch instruction.

[0068] The instruction information storage of each instruction on the predicted path corresponding to the conditional branch instruction and the corresponding base address and maximum offset are stored in the preset cache space, or it is determined according to the accuracy prediction module whether to store the instruction information storage of each instruction on the predicted path and the corresponding base address and maximum offset are stored in the preset cache space.

[0069] The preset cache space may be a Wrong Path Instruntion Buffer (WPIB) or other data storage structures, which are not limited here.

[0070] Furthermore, when executing instructions on the predicted path, it is determined whether the predicted path is correct. If so, the instruction information for each instruction on the predicted path, as well as the corresponding base address (base pc) and maximum offset (maxoffset) stored in the WPIB, is cleared. If not, instruction redirection is performed to re-determine the instruction address (redirect pc) of the instruction executed after the conditional branch instruction.

[0071] If the redirect pc matches any base pc in the WPIB, the multiplexer mux retrieves the instruction information corresponding to the base pc that matches the redirect pc and passes it to the instruction dispatch module and subsequent pipeline stages. If the redirect pc does not match any base pc in the WPIB, the multiplexer mux retrieves the instructions on the correct path through the IFU.

[0072] During the execution of each instruction on the predicted path, the address of the next instruction to be executed (redirectpc+maxoffset) is determined based on redirectpc and the maximum offset that matches redirectpc. Based on this instruction address, the next instruction to be executed is retrieved through the IFU and decoded and analyzed. If the instruction is not a conditional branch instruction, execution continues with the next instruction. If the instruction is a conditional branch instruction, the prediction method for the instruction is determined and the implementation process described above is repeated.

[0073] In an embodiment of the present application, by caching the instruction information of each instruction on the predicted path of each branch instruction, when the predicted path corresponding to a branch instruction is an incorrect path, the instruction on the correct path corresponding to the branch instruction can be directly obtained from the preset cache space, thereby quickly filling the pipeline, improving instruction processing efficiency, and saving instruction processing time.

[0074] See also Figure 4 , Figure 4 : is a structural diagram of the processor provided in an embodiment of the present application. Wherein, the processor 40 in the embodiment of the present application can be a general-purpose processor, such as a general-purpose microprocessor or central processing unit (CPU) used in a desktop computer, a laptop computer, a system-on-chip (SoC) or other computers. Alternatively, the processor 40 can be a special-purpose processor, including but not limited to a digital signal processor (DSP), an image processor, a graphics processor, a network processor, a communication processor, a cryptographic processor, a coprocessor, an embedded processor and a controller (e.g., a microcontroller). The processor can have any of various complex instruction set computing (CISC) architectures, reduced instruction set computing (RISC) architectures, very long instruction word (VLIW) architectures, hybrid architectures, other types of architectures, or a combination of different architectures (e.g., different processor cores can have different architectures).

[0075] Figure 4The processor 40 shown may include a branch prediction unit 41, an instruction cache unit 42, and an execution unit 43. The processor 40 may also include at least one communication bus 44. The communication bus 44 is used to implement connection and communication between these components.

[0076] In the embodiment of the present application, the branch prediction unit 41 is configured to, in response to the target pipeline executing the target branch instruction, determine a target predicted path corresponding to the target branch instruction; and in response to the target predicted path being an incorrect path, re-determine a target path corresponding to the target branch instruction, so that the target path is a correct path corresponding to the target branch instruction.

[0077] The execution unit 43 is configured to, in response to the target instruction information of each target instruction on the target path stored in the instruction cache unit 42, obtain each target instruction information from the instruction cache unit 42, and execute each target instruction based on the target instruction information;

[0078] The branch prediction unit 41 is further configured to determine a prediction path corresponding to any branch instruction in response to any pipeline executing any branch instruction; and the instruction cache unit 42 is configured to store instruction information of each instruction on the prediction path.

[0079] In some feasible implementations, the instruction cache unit 42 is configured to:

[0080] Determine the instruction address of the first instruction on the predicted path;

[0081] Determine the instruction address of the first instruction as the base address corresponding to the predicted path;

[0082] The base address corresponding to the predicted path and the instruction information of each instruction on the predicted path are associated and stored.

[0083] In some feasible implementations, the instruction cache unit 42 is configured to:

[0084] determining a target instruction address of a first target instruction, and matching the target instruction address with each stored base address;

[0085] In response to the target base address matching the target instruction address being stored, target instruction information of each of the target instructions is determined to be stored.

[0086] In some feasible implementations, the instruction cache unit 42 is further configured to:

[0087] Determine a maximum offset corresponding to the predicted path, where the maximum offset is used to indicate the number of instructions on the predicted path;

[0088] The maximum offset corresponding to the predicted path is stored, and the maximum offset corresponding to the predicted path is associated with the base address corresponding to the predicted path and instruction information of each instruction.

[0089] In some feasible implementations, the instruction cache unit 42 is further configured to:

[0090] Determining a target maximum offset stored in association with the target base address;

[0091] determining, based on the target maximum offset and the target instruction address of the first target instruction, an instruction address of a next instruction to be executed after executing each of the target instructions;

[0092] The processor further includes an instruction fetch unit, configured to fetch the instruction to be executed based on the instruction address of the instruction to be executed;

[0093] The execution unit 43 is configured to continue executing the instructions to be executed after executing each of the target instructions.

[0094] In some feasible implementations, the processor further includes an instruction fetch unit, and the instruction fetch unit is further configured to obtain each of the target instructions in response to the target instruction information of each of the target instructions not being stored in the instruction cache unit 42;

[0095] The execution unit 43 is further configured to execute the target instructions.

[0096] In some feasible implementations, the instruction cache unit 42 is further configured to clear instruction information of each instruction on the predicted path in response to the predicted path being a correct path.

[0097] In a specific implementation, the processor 40 can execute the above-mentioned functions through its built-in functional modules. Figure 1 For the implementation methods provided in each step, please refer to the implementation methods provided in the above steps for details, which will not be repeated here.

[0098] Among them, the instruction cache unit can also be Figure 1 The preset cache space in Figure 3 The instruction cache (WPIB) shown is not limited here.

[0099] See also Figure 5 , Figure 5 Schematic diagram of the structure of the instruction processing device provided in the embodiment of the present application. The instruction processing device provided in the embodiment of the present application includes:

[0100] A branch prediction module 51 is configured to determine a target prediction path corresponding to a target branch instruction in response to a target pipeline executing the target branch instruction;

[0101] a branch determination module 52 for re-determining a target path corresponding to the target branch instruction in response to the target predicted path being an incorrect path, the target path being a correct path corresponding to the target branch instruction;

[0102] an instruction processing module 53 for, in response to target instruction information of each target instruction on the target path being stored in a preset cache space, obtaining each target instruction information from the preset cache space, and executing each target instruction based on the target instruction information;

[0103] The instruction information in the above-mentioned preset cache space is determined based on the instruction cache module:

[0104] In response to any pipeline executing any branch instruction, a prediction path corresponding to the branch instruction is determined, and instruction information of each instruction on the prediction path is stored in the preset cache space.

[0105] In some feasible implementations, the instruction cache module is configured to:

[0106] determining an instruction address of a first instruction on the predicted path;

[0107] Determining the instruction address of the first instruction as the base address corresponding to the predicted path;

[0108] The base address corresponding to the predicted path and the instruction information of each instruction on the predicted path are associated and stored in the preset cache space.

[0109] In some feasible implementations, the instruction cache module is configured to:

[0110] Determining a target instruction address of a first target instruction, and matching the target instruction address with each base address in the preset cache space;

[0111] In response to the preset cache space storing a target base address that matches the target instruction address, it is determined that the preset cache space stores target instruction information of each target instruction.

[0112] In some feasible implementations, the instruction cache module is further configured to:

[0113] Determining a maximum offset corresponding to the predicted path, where the maximum offset is used to indicate the number of instructions on the predicted path;

[0114] The maximum offset corresponding to the predicted path is stored in the preset cache space, and the maximum offset corresponding to the predicted path is associated with the base address corresponding to the predicted path and instruction information of each instruction.

[0115] In some feasible implementations, during the execution of each of the above target instructions, the instruction processing module 53 is configured to:

[0116] Determining a target maximum offset stored in the preset cache space in association with the target base address;

[0117] determining, based on the target maximum offset and the target instruction address of the first target instruction, an instruction address of a next instruction to be executed after executing each target instruction;

[0118] The instructions to be executed are acquired based on the instruction addresses of the instructions to be executed, and the instructions to be executed are continued to be executed after each of the target instructions is executed.

[0119] In some feasible implementations, during the execution of each of the above target instructions, the instruction processing module 53 is further configured to:

[0120] In response to the target instruction information of each target instruction not being stored in the preset cache space, each target instruction is acquired by an instruction fetch unit and executed.

[0121] In some feasible implementations, after storing the instruction information of each instruction on the predicted path into the preset cache space, the instruction cache module is further configured to:

[0122] In response to the predicted path being a correct path, instruction information of each instruction on the predicted path in the preset cache space is cleared.

[0123] In a specific implementation, the above instruction processing device can execute the above instructions through its built-in functional modules. Figure 1 For the implementation methods provided in each step, please refer to the implementation methods provided in the above steps for details, which will not be repeated here.

[0124] The present invention also provides a computer-readable storage medium that stores a computer program and is executed by a processor to implement Figure 1 For the methods provided in each step, please refer to the implementation methods provided in the above steps for details, which will not be repeated here.

[0125] The above-mentioned computer-readable storage medium can be the internal storage unit of the instruction processing device, processor or other electronic device provided in any of the aforementioned embodiments, such as the hard disk or memory of the electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk equipped on the electronic device, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. The above-mentioned computer-readable storage medium can also include a magnetic disk, an optical disk, a read-only memory (read-only memory, ROM) or a random access memory (random access memory, RAM), etc. Further, the computer-readable storage medium can also include both the internal storage unit of the electronic device and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0126] The present invention provides a computer program product, which includes a computer program, which is executed by a processor. Figure 1 The methods provided in each step.

[0127] The terms "first," "second," and the like in the claims, specification, and drawings of this application are used to distinguish different objects, not to describe a specific order. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or processor that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or processors. Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The presence of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0128] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the above description generally describes the components and steps of each example according to their functions. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0129] The above disclosure is only a preferred embodiment of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A method for processing an instruction, characterized in that: The method comprises: In response to the target pipeline executing a target branch instruction, determining a target predicted path corresponding to the target branch instruction; In response to the target predicted path being an incorrect path, re-determining a target path corresponding to the target branch instruction, the target path being a correct path corresponding to the target branch instruction; In response to target instruction information of each target instruction on the target path being stored in a preset cache space, acquiring each target instruction information from the preset cache space, and executing each target instruction based on each target instruction information; The instruction information in the preset cache space is determined based on the following method: In response to any pipeline executing any branch instruction, determining a predicted path corresponding to the branch instruction, determining the instruction address of the first instruction on the predicted path; determining the instruction address of the first instruction as a base address corresponding to the predicted path; and associating the base address corresponding to the predicted path with instruction information of each instruction on the predicted path and storing it in the preset cache space; The step of determining whether the preset cache space stores target instruction information of each target instruction includes: Determining a target instruction address of a first target instruction, and matching the target instruction address with each base address in the preset cache space; In response to the preset cache space storing a target base address that matches the target instruction address, it is determined that the preset cache space stores target instruction information of each target instruction.

2. The method according to claim 1, characterized in that The method further comprises: Determining a maximum offset corresponding to the predicted path, where the maximum offset is used to indicate the number of instructions on the predicted path; The maximum offset corresponding to the predicted path is stored in the preset cache space, and the maximum offset corresponding to the predicted path is associated with the base address corresponding to the predicted path and instruction information of each instruction.

3. The method according to claim 2, characterized in that During the execution of each target instruction, the method further includes: Determining a target maximum offset stored in the preset cache space in association with the target base address; determining, based on the target maximum offset and the target instruction address of the first target instruction, an instruction address of a next instruction to be executed after executing each target instruction; The instructions to be executed are acquired based on the instruction addresses of the instructions to be executed, and the instructions to be executed are continued to be executed after each of the target instructions is executed.

4. The method according to claim 1, wherein The method further comprises: In response to the target instruction information of each target instruction not being stored in the preset cache space, each target instruction is acquired by an instruction fetch unit and executed.

5. The method according to claim 1, wherein After storing the instruction information of each instruction on the predicted path in the preset cache space, the method further includes: In response to the predicted path being a correct path, instruction information of each instruction on the predicted path in the preset cache space is cleared.

6. A processor, characterized in that: Includes branch prediction unit, instruction cache unit and execution unit; The branch prediction unit is configured to, in response to a target pipeline executing a target branch instruction, determine a target predicted path corresponding to the target branch instruction; and in response to the target predicted path being an incorrect path, re-determine a target path corresponding to the target branch instruction, wherein the target path is a correct path corresponding to the target branch instruction; The execution unit is configured to, in response to the target instruction information of each target instruction on the target path being stored in the instruction cache unit, obtain each target instruction information from the instruction cache unit, and execute each target instruction based on the target instruction information; The branch prediction unit is further configured to determine a predicted path corresponding to any branch instruction in response to any pipeline executing any branch instruction; the instruction cache unit is configured to determine an instruction address of a first instruction on the predicted path; determine the instruction address of the first instruction as a base address corresponding to the predicted path; and associate and store the base address corresponding to the predicted path with instruction information of each instruction on the predicted path; When the instruction cache unit determines that the preset cache space stores the target instruction information of each target instruction, it is configured to: determining a target instruction address of a first target instruction, and matching the target instruction address with each stored base address; In response to the target base address matching the target instruction address being stored, it is determined that target instruction information of each target instruction is stored.

7. The processor according to claim 6, wherein: The instruction cache unit is further configured to: Determining a maximum offset corresponding to the predicted path, where the maximum offset is used to indicate the number of instructions on the predicted path; A maximum offset corresponding to the predicted path is stored, where the maximum offset corresponding to the predicted path is associated with a base address corresponding to the predicted path and instruction information of each instruction.

8. The processor according to claim 7, wherein: The instruction cache unit is further configured to: determining a target maximum offset stored in association with the target base address; determining, based on the target maximum offset and the target instruction address of the first target instruction, an instruction address of a next instruction to be executed after executing each target instruction; The processor further includes an instruction fetch unit, configured to fetch the instruction to be executed based on an instruction address of the instruction to be executed; The execution unit is configured to continue executing the to-be-executed instructions after executing each of the target instructions.

9. The processor according to claim 6, wherein: The processor further includes an instruction fetch unit, wherein the instruction fetch unit is further configured to obtain each target instruction in response to the target instruction information of each target instruction not being stored in the instruction cache unit; The execution unit is further configured to execute each of the target instructions.

10. The processor according to claim 6, wherein: The instruction cache unit is further configured to clear instruction information of each instruction on the predicted path in response to the predicted path being a correct path.

11. An instruction processing device, characterized in that: The device comprises: a branch prediction module, configured to determine a target prediction path corresponding to a target branch instruction in response to a target pipeline executing the target branch instruction; a branch judgment module, configured to, in response to the target predicted path being an incorrect path, re-determine a target path corresponding to the target branch instruction, wherein the target path is a correct path corresponding to the target branch instruction; an instruction processing module, configured to, in response to target instruction information of each target instruction on the target path being stored in a preset cache space, obtain each target instruction information from the preset cache space, and execute each target instruction based on each target instruction information; The instruction information in the preset cache space is determined by the instruction cache module based on the following method: In response to any pipeline executing any branch instruction, determining a predicted path corresponding to the branch instruction, determining the instruction address of the first instruction on the predicted path; determining the instruction address of the first instruction as a base address corresponding to the predicted path; and associating the base address corresponding to the predicted path with instruction information of each instruction on the predicted path and storing it in the preset cache space; When the instruction cache module determines that the preset cache space stores target instruction information of each target instruction, it is configured to: Determining a target instruction address of a first target instruction, and matching the target instruction address with each base address in the preset cache space; In response to the preset cache space storing a target base address that matches the target instruction address, it is determined that the preset cache space stores target instruction information of each target instruction.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method according to any one of claims 1 to 5.

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