A method, device, equipment and medium for automatically adjusting a sending end equalization value
By automatically detecting and writing PCIe device information during the BIOS boot phase, the automatic adjustment of the sender load balancer value is achieved, which solves the problem of increased maintenance costs caused by manually setting BIOS options and improves production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2022-05-27
- Publication Date
- 2026-07-03
Smart Images
Figure CN114816885B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of PCIe device technology, and specifically to a method, apparatus, device, and medium for automatically adjusting the equalization value at the transmitting end. Background Technology
[0002] BIOS (Basic Input Output System) is a program embedded in a ROM chip on the computer motherboard. It initializes the various central processing units (CPU), chipsets, and input / output devices on the server motherboard during the boot process, providing the lowest-level and most direct hardware settings and control for the computer. PCIe link training is completed during the BIOS boot phase.
[0003] To compensate for signal loss and other effects caused by high-speed signals in the transmission channel, dynamic equalization (TxEQ) has been used since PCIe 3.0 to automatically configure and optimize the equalization settings of the transmitter and receiver for different situations, so as to obtain the best signal quality at the receiver. Transmitter equalization (TxEQ) is implemented through a third-order FIR filter. The weight of each order is called the Cursor coefficient, and different combinations of de-emphasis and pre-overshoot are called Presets. There are a total of 11 Presets, P0-P10. The adjustment of the TxEQ value is implemented in the Recovery state of the link training between the system root port and the PCIe device. The Recovery state includes four sub-states: Phase 0, Phase 1, Phase 2, and Phase 3, which are also the four stages in which dynamic equalization occurs. The adjustment of the PCIe device's TxEQ value mainly occurs in Phase 3. While the system root port adjusts its own RxEQ to obtain the optimal setting, it also adjusts the TxEQ settings of the PCIe device port by sending different Preset or Cursor value requests. Once the combination of the RxEQ value of the system root port and the TxEQ value of the PCIe device reaches an optimal setting, exit Phase 3.
[0004] In actual testing on the Intel Whitley platform, it was still found that some PCIe network cards, after being automatically configured and adjusted using dynamic equalization methods, still exhibited a small number of correctable errors when used in the system. In such cases, signal engineers need to test based on actual applications to find a set of optimal TxEQ PreCursor and PostCursor values to fix these correctable errors in PCIe network cards, thus preventing the generation of uncorrectable errors due to an excessive number of correctable errors.
[0005] The optimal TxEQ PreCursor and PostCursor values need to be correctly set during the BIOS boot process. Generally, the PreCursor and PostCursor values for TxEQ differ for different network cards, and the location of these settings in the BIOS Setup interface also varies depending on whether it's a Gen3 or Gen4 network card. First, locate the corresponding PCIe root port in the BIOS Setup interface and change the corresponding Gen3 Override mode or Gen4 Override mode to Manual mode. Then, set the corresponding Ph3 TxEq precursor and Ph3 TxEq PostCursor values to the adjusted values, save, and restart the system for the adjusted TxEQ values to take effect. This requires server testing, production, or maintenance personnel to set different BIOS options for different network card configurations. Furthermore, setting these options requires restarting the server, increasing the cost of configuration changes, verification, production, and maintenance. Summary of the Invention
[0006] For server testing, production, or maintenance personnel, setting different BIOS options for different network card configurations, and requiring server restarts after option settings, which increases the cost of configuration changes, testing, production, and maintenance timeliness, this invention provides a method, apparatus, device, and medium for automatically adjusting the sender balance value.
[0007] The technical solution of this invention is:
[0008] In a first aspect, the present invention provides a method for automatically adjusting the equalization value at the transmitting end, comprising the following steps:
[0009] When the BIOS starts PCIe link training, it iterates through and checks whether there is a PCIe device connected to the PCIe root port on the CPU side.
[0010] When a PCIe device is detected, pre-write values to the secondary bus register and auxiliary bus register of each PCIe root port;
[0011] Read the manufacturer code and device code of the PCIe device connected to the secondary bus;
[0012] The read manufacturer code and device code are compared with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted;
[0013] When the comparison results match, the write function is called to write the sender equalization value and make the written sender equalization value effective.
[0014] Determine if the traversal is complete;
[0015] If so, then it's over;
[0016] If not, proceed as follows: Iterate through and check if any PCIe devices are connected to the PCIe root port on the CPU side.
[0017] The equalization value determined here needs to be written to the signal engineer for confirmation.
[0018] Furthermore, before the step of checking whether a PCIe device is connected to the CPU's PCIe root port during BIOS startup for PCIe link training, the following steps are included:
[0019] Read the error-correctable status in the registers of each PCIe device, and identify the PCIe devices with error-correctable registers as the PCIe devices whose transmitter equalization values need to be adjusted.
[0020] Furthermore, when a PCIe device is detected, the steps for pre-writing values to the secondary bus register and auxiliary bus register of each PCIe root port include:
[0021] When a PCIe device is detected, read the bus base value and bus limit value of the root port where each PCIe device is located;
[0022] The secondary bus register of each PCIe root port is pre-written with the bus bottom value incremented by 1, and the auxiliary bus register is pre-written with the bus limit value.
[0023] Furthermore, when the comparison results are consistent, the steps of calling the write function to write the optimized sender equalization value and making the written sender equalization value effective include:
[0024] When the comparison results match, the write function is called to write the optimized sender equalization value.
[0025] Perform link retraining on the PCIe root port's PCIe link to make the written sender equalization value effective.
[0026] Furthermore, the method also includes:
[0027] After the equalization value at the transmitting end is adjusted, the signal quality of the current PCIe link is tested.
[0028] If the signal quality of the PCIe link does not meet the predetermined standard, the equalization value of the PCIe link's transmitting end will be readjusted.
[0029] Secondly, the present invention provides a device for automatically adjusting the equalization value of the transmitting end, including an interface detection module, a register writing module, a code reading module, a comparison module, an adjustment module, and a judgment module;
[0030] The interface detection module is used to traverse and detect whether a PCIe device is connected to the PCIe root port on the CPU side when the BIOS starts PCIe link training.
[0031] The write register module is used to prewrite values to the secondary bus register and auxiliary bus register of each PCIe root port when a PCIe device is detected.
[0032] The code reading module is used to read the manufacturer code and device code of the PCIe device connected to the secondary bus;
[0033] The comparison module is used to compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted;
[0034] The adjustment module is used to call the write function to write the sender equalization value when the comparison results are consistent, and to make the written sender equalization value effective.
[0035] The judgment module is used to determine whether the detection module has completed its traversal; if not, it outputs information to the interface detection module.
[0036] Furthermore, the device also includes a confirmation module, which is used to read the error-correctable status in the registers of each PCIe device and identify the PCIe device corresponding to the error-correctable register as the PCIe device whose transmitter equalization value needs to be adjusted.
[0037] Furthermore, the write register module includes a read unit and a write-ahead unit;
[0038] The reading unit is used to read the bus base value and bus limit value of the root port where each PCIe device is located when a connected PCIe device is detected.
[0039] The write-ahead unit is used to prewrite the bus bottom value plus 1 to the secondary bus register of each PCIe root port and to prewrite the bus limit value to the auxiliary bus register.
[0040] Furthermore, the adjustment module includes an execution unit and a triggering unit;
[0041] The execution unit is used to call the write function to write the optimized sender equalization value when the comparison results are consistent;
[0042] The triggering unit is used to retrain the PCIe link on the PCIe root port to make the written sender equalization value effective.
[0043] Furthermore, the device also includes a verification module; the verification module is used to perform signal quality detection on the current PCIe link after the equalization value of the transmitting end is adjusted, and to determine whether the signal quality of the PCIe link meets the predetermined standard; if not, it outputs information to the adjustment module to readjust the equalization value of the transmitting end of the PCIe link.
[0044] Thirdly, the present invention also provides an electronic device, the electronic device comprising:
[0045] At least one processor; and,
[0046] A memory communicatively connected to the at least one processor; wherein,
[0047] The memory stores computer program instructions executable by at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method of automatically adjusting the transmitter equalization value as described in the first aspect.
[0048] Fourthly, the present invention also provides a non-transitory computer-readable storage medium storing computer instructions that cause the computer to execute the method for automatically adjusting the equalization value at the transmitting end as described in the first aspect.
[0049] As can be seen from the above technical solutions, the present invention has the following advantages: The method of automatically adjusting the equalization value of the PCIe device's transmitting end by detecting PCIe device information can be designed in the BIOS startup stage. When PCIe device information is detected, the program writes the optimization data of the equalization value of the transmitting end provided by the signal engineer, thereby realizing automatic adjustment of the equalization value of the transmitting end. First, it can avoid the complex operation of manual settings for different PCIe devices by test engineers, production or customer maintenance. Second, it can avoid the need for a second restart through the BIOS Setup interface, thus saving testing, production and maintenance time.
[0050] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects.
[0051] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description
[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0053] Figure 1 This is a schematic flowchart of a method according to an embodiment of the present invention.
[0054] Figure 2 This is a schematic flowchart of a method according to another embodiment of the present invention.
[0055] Figure 3 This is a schematic block diagram of an apparatus according to an embodiment of the present invention. Detailed Implementation
[0056] In actual testing on the Intel Whitley platform, some PCIe network cards, even after automatic configuration adjustments using dynamic balancing, still exhibited a small number of correctable errors when used in the system. To address this, signal engineers need to test based on actual applications to find an optimal set of TxEQ PreCursor and PostCursor values. This is used to correct these correctable errors in PCIe network cards, preventing the generation of uncorrectable errors due to an excessive number of correctable errors. These optimal TxEQ PreCursor and PostCursor values need to be correctly set during BIOS startup. Generally, the TxEQ PreCursor and PostCursor values differ for different network cards, and the location of these settings in the BIOS Setup interface also varies for different Gen3 or Gen4 network cards. First, locate the corresponding PCIe root port in the BIOS Setup interface and change the Gen3 Override mode or Gen4 Override mode to Manual mode. Then, set the Ph3 TxEq precursor and Ph3 TxEqPostcursor values accordingly, save, and restart the system for the adjusted TXEQ values to take effect. This requires server testing, production, or maintenance personnel to configure different BIOS options for different network card configurations. Furthermore, restarting the server after setting these options increases the cost of configuration changes, testing, production, and maintenance. To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.
[0057] like Figure 1 As shown in the figure, an embodiment of the present invention provides a method for automatically adjusting the equalization value at the transmitting end, comprising the following steps:
[0058] Step 1: When the BIOS starts PCIe link training, it checks whether there is a PCIe device connected to the PCIe root port on the CPU side.
[0059] Step 2: When a PCIe device is detected, prewrite values to the secondary bus register and auxiliary bus register of each PCIe root port;
[0060] Step 3: Read the manufacturer code and device code of the PCIe device connected to the secondary bus;
[0061] Step 4: Compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted;
[0062] Step 5: When the comparison results match, call the write function to write the sender equalization value and make the written sender equalization value effective;
[0063] It should be noted here that after step 5 is completed, step S6 needs to be executed: determine whether the traversal is complete;
[0064] If yes, end; if no, proceed to step 1.
[0065] The equalization value determined here needs to be confirmed by the engineer writing the signal.
[0066] like Figure 2 As shown, in some embodiments, step 2, when a PCIe device is detected, includes the step of pre-writing values to the secondary bus register and auxiliary bus register of each PCIe root port, which includes:
[0067] Step 21: When a PCIe device is detected, read the bus base value and bus limit value of the root port where each PCIe device is located;
[0068] Step 22: Prewrite the bus bottom value by 1 to the secondary bus register of each PCIe root port and prewrite the bus limit value to the auxiliary bus register.
[0069] In the corresponding step 5, when the comparison results are consistent, the steps of calling the write function to write the optimized sender equalization value and making the written sender equalization value effective include:
[0070] Step 51: When the comparison results match, call the write function to write the optimized sender equalization value;
[0071] Step 52: Perform link retraining on the PCIe root port of this PCIe link to make the written sender equalization value effective.
[0072] In other words, this embodiment of the invention adjusts the TXEQ value for certain PCIe devices during the PCIe link initialization phase of the BIOS boot process. PCIe devices are distinguished primarily by identifying the device's VendorID and DeviceID. However, during the BIOS boot process, the BIOS cannot directly read the PCIe device's VendorID and DeviceID. Therefore, special processing is required from the BIOS, implemented as follows:
[0073] 1) First, check if a PCIe device is connected to the PCIe root port on each CPU.
[0074] 2) Then read the bus base value and bus limit value of the root port of each PCIe device.
[0075] 3) Pre-write the bus base value +1 to the Secondary bus register of each PCIe root port, and pre-write the bus limit value to its Subordinate Bus register.
[0076] 4) Read the VendorID and DeviceID of the PCIE device connected to the PCIE Secondary Bus.
[0077] 5) Compare the obtained VendorID and deviceID with the PCIe device VendorID and DeviceID whose TXEQ value needs to be adjusted. If they match, execute the Phase 3 TXEQ value writing function to write the appropriate TXEQ value measured by the signal engineer. If they do not match, do not execute.
[0078] 6) Perform Link Retraining on the PCIe root port PCIe link to make the written TXEQ value effective;
[0079] 7) Traverse all PCIe root ports of each CPU and adjust the TXEQ value for all devices connected to that PCIe port.
[0080] The method of automatically adjusting the TXEQ value of a PCIe device by detecting PCIe device information involves the BIOS reading the PCIe device's VendorID and DeviceID by writing to the Secondary bus and Subordinate bus registers of the PCIe root port during the PCIe link training initialization phase. This VendorID and DeviceID are compared with the TXEQ values of the PCIe device whose value needs to be adjusted. If they match, the Phase 3 TXEQ value writing function is executed to perform Link Retraining on the PCIe root port PCIe link, making the written TXEQ value effective. This achieves the goal of optimizing the TXEQ value of a specific PCIe device during the BIOS boot process without modifying BIOS options or restarting the system.
[0081] This invention provides a method for automatically adjusting the equalization value at the transmitting end, comprising the following steps:
[0082] S1: Read the error-correctable status in the registers of each PCIe device, and identify the PCIe devices with error-correctable registers as the PCIe devices whose transmitter equalization values need to be adjusted.
[0083] S2: When the BIOS starts PCIe link training, it iterates through and checks whether there is a PCIe device connected to the PCIe root port on the CPU side.
[0084] S3: When a PCIe device is detected, prewrite values to the secondary bus register and auxiliary bus register of each PCIe root port;
[0085] S4: Read the manufacturer code and device code of the PCIe device connected to the secondary bus;
[0086] S5: Compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted;
[0087] S6: When the comparison results are consistent, call the write function to write the sender equalization value and make the written sender equalization value effective.
[0088] This invention provides a method for automatically adjusting the equalization value at the transmitting end, comprising the following steps:
[0089] S1: Read the error-correctable status in the registers of each PCIe device, and identify the PCIe devices with error-correctable registers as the PCIe devices whose transmitter equalization values need to be adjusted.
[0090] S2: When the BIOS starts PCIe link training, it iterates through and checks whether there is a PCIe device connected to the PCIe root port on the CPU side.
[0091] S3: When a PCIe device is detected, prewrite values to the secondary bus register and auxiliary bus register of each PCIe root port;
[0092] S4: Read the manufacturer code and device code of the PCIe device connected to the secondary bus;
[0093] S5: Compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted;
[0094] S6: When the comparison results are consistent, call the write function to write the sender equalization value and make the written sender equalization value effective;
[0095] S7: After the equalization value of the transmitting end is adjusted, the signal quality of the current PCIe link is detected;
[0096] S8: If the signal quality of the PCIE link does not meet the predetermined standard, the equalization value of the PCIE link's transmitting end will be readjusted.
[0097] like Figure 3 As shown, this embodiment of the invention provides an apparatus for automatically adjusting the equalization value of the transmitting end, including an interface detection module, a register writing module, a code reading module, a comparison module, and an adjustment module;
[0098] The interface detection module is used to traverse and detect whether a PCIe device is connected to the PCIe root port on the CPU side when the BIOS starts PCIe link training.
[0099] The write register module is used to prewrite values to the secondary bus register and auxiliary bus register of each PCIe root port when a PCIe device is detected.
[0100] The code reading module is used to read the manufacturer code and device code of the PCIe device connected to the secondary bus;
[0101] The comparison module is used to compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted;
[0102] The adjustment module is used to call the write function to write the sender equalization value when the comparison results are consistent, and to make the written sender equalization value effective.
[0103] It should be noted that after the adjustment of this invention is completed, it is necessary to determine that all PCIe devices have been adjusted before the execution ends. This device also includes a judgment module, which is used to determine whether the detection module has completed the traversal; if not, it outputs information to the interface detection module.
[0104] In some embodiments, the device further includes a confirmation module, which is used to read the error-correctable status in the registers of each PCIe device and identify the PCIe device corresponding to the error-correctable register as the PCIe device whose transmitter equalization value needs to be adjusted.
[0105] In some embodiments, the write register module includes a read unit and a write-ahead unit;
[0106] The reading unit is used to read the bus base value and bus limit value of the root port where each PCIe device is located when a connected PCIe device is detected.
[0107] The write-ahead unit is used to prewrite the bus bottom value plus 1 to the secondary bus register of each PCIe root port and to prewrite the bus limit value to the auxiliary bus register.
[0108] In some embodiments, the adjustment module includes an execution unit and a triggering unit;
[0109] The execution unit is used to call the write function to write the optimized sender equalization value when the comparison results are consistent;
[0110] The triggering unit is used to retrain the PCIe link on the PCIe root port to make the written sender equalization value effective.
[0111] In some embodiments, the device further includes a verification module; the verification module is used to perform signal quality detection on the current PCIe link after the equalization value of the transmitting end is adjusted, and to determine whether the signal quality of the PCIe link meets the predetermined standard; if not, it outputs information to the adjustment module to readjust the equalization value of the transmitting end of the PCIe link.
[0112] This invention also provides an electronic device, comprising: a processor, a communication interface, a memory, and a bus, wherein the processor, communication interface, and memory communicate with each other via the bus. The bus can be used for information transmission between the electronic device and sensors. The processor can call logical instructions in the memory to execute the following method: Step 1: When the BIOS starts PCIe link training, it iterates and checks whether there is a PCIe device connected to the PCIe root port on the CPU side; Step 2: When a PCIe device is detected, pre-write values to the secondary bus register and auxiliary bus register of each PCIe root port; Step 3: Read the manufacturer code and device code of the PCIe device connected to the secondary bus; Step 4: Compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose transmitter equalization value needs to be adjusted; Step 5: When the comparison result is consistent, call the write function to write the transmitter equalization value and make the written transmitter equalization value effective.
[0113] In some specific embodiments, the processor can call logical instructions in memory to execute the following method: Step 21: When a PCIe device is detected, read the bus base value and bus limit value of the root port where each PCIe device is located; Step 22: Pre-write the bus base value plus 1 to the secondary bus register of each PCIe root port and pre-write the bus limit value to the auxiliary bus register.
[0114] In some specific embodiments, the processor can call logical instructions in memory to execute the following method: Step 51: When the comparison results are consistent, call the write function to write the optimized sender equalization value; Step 52: Perform link retraining on the PCIe root port of the PCIe link to make the written sender equalization value effective.
[0115] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0116] This invention provides a non-transitory computer-readable storage medium storing computer instructions that cause a computer to execute the method provided in the above-described method embodiments. For example, the instructions include: Step 1: When the BIOS starts PCIe link training, it iterates through and checks whether a PCIe device is connected to the PCIe root port on the CPU side; Step 2: When a PCIe device is detected, pre-write values to the secondary bus register and auxiliary bus register of each PCIe root port; Step 3: Read the manufacturer code and device code of the PCIe device connected to the secondary bus; Step 4: Compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose transmitter equalization value needs to be adjusted; Step 5: When the comparison results match, call the write function to write the transmitter equalization value and make the written transmitter equalization value effective.
[0117] In some specific embodiments, the program instructions executed by the processor in the readable storage medium can specifically implement the following steps: Step 21: When a PCIe device is detected, read the bus base value and bus limit value of the root port where each PCIe device is located; Step 22: Pre-write the bus base value plus 1 to the secondary bus register of each PCIe root port and pre-write the bus limit value to the auxiliary bus register.
[0118] In some specific embodiments, the program instructions executed by the processor in the readable storage medium can specifically implement the following steps: Step 51: When the comparison results are consistent, call the write function to write the optimized sender equalization value; Step 52: Perform link retraining on the PCIE link of the PCIE root port to make the written sender equalization value effective.
[0119] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.
Claims
1. A method for automatically adjusting the equalization value at the transmitting end, characterized in that, Includes the following steps: When the BIOS starts PCIe link training, it iterates through and checks whether there is a PCIe device connected to the PCIe root port on the CPU side. When a PCIe device is detected, pre-write values to the secondary bus register and auxiliary bus register of each PCIe root port; Read the manufacturer code and device code of the PCIe device connected to the secondary bus; The read manufacturer code and device code are compared with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted; When the comparison results match, the write function is called to write the sender equalization value and make the written sender equalization value effective. When a PCIe device is detected, the steps for pre-writing values to the secondary bus register and auxiliary bus register of each PCIe root port include: When a PCIe device is detected, read the bus base value and bus limit value of the root port where each PCIe device is located; The secondary bus register of each PCIe root port is pre-written with the bus bottom value incremented by 1, and the auxiliary bus register is pre-written with the bus limit value.
2. The method for automatically adjusting the equalization value at the transmitting end according to claim 1, characterized in that, Before the BIOS initiates PCIe link training, the process of checking whether a PCIe device is connected to the CPU's PCIe root port includes the following steps: Read the error-correctable status in the registers of each PCIe device, and identify the PCIe devices with error-correctable registers as the PCIe devices whose transmitter equalization values need to be adjusted.
3. The method for automatically adjusting the equalization value at the transmitting end according to claim 1, characterized in that, When the comparison results match, the steps of calling the write function to write the sender's equalization value and making the written sender's equalization value effective also include: Determine if the traversal is complete; If so, then it's over; If not, proceed as follows: Iterate through and check if any PCIe devices are connected to the PCIe root port on the CPU side.
4. The method for automatically adjusting the equalization value at the transmitting end according to claim 1, characterized in that, When the comparison results match, the steps of calling the write function to write the optimized sender equalization value and making the written sender equalization value effective include: When the comparison results match, the write function is called to write the optimized sender equalization value. Perform link retraining on the PCIe root port's PCIe link to make the written sender equalization value effective.
5. The method for automatically adjusting the equalization value at the transmitting end according to claim 1, characterized in that, The method also includes: After the equalization value at the transmitting end is adjusted, the signal quality of the current PCIe link is tested. If the signal quality of the PCIe link does not meet the predetermined standard, the equalization value of the PCIe link's transmitting end will be readjusted.
6. A device for automatically adjusting the equalization value at the transmitting end, characterized in that, It includes an interface detection module, a register write module, a code reading module, a comparison module, and an adjustment module; The interface detection module is used to traverse and detect whether a PCIe device is connected to the PCIe root port on the CPU side when the BIOS starts PCIe link training. The write register module is used to prewrite values to the secondary bus register and auxiliary bus register of each PCIe root port when a PCIe device is detected. The code reading module is used to read the manufacturer code and device code of the PCIe device connected to the secondary bus; The comparison module is used to compare the read manufacturer code and device code with the manufacturer code and device code of the PCIe device whose sender equalization value needs to be adjusted; The adjustment module is used to call the write function to write the sender equalization value when the comparison results are consistent, and to make the written sender equalization value effective. When a PCIe device is detected, the steps for pre-writing values to the secondary bus register and auxiliary bus register of each PCIe root port include: When a PCIe device is detected, read the bus base value and bus limit value of the root port where each PCIe device is located; The secondary bus register of each PCIe root port is pre-written with the bus bottom value incremented by 1, and the auxiliary bus register is pre-written with the bus limit value.
7. The apparatus for automatically adjusting the equalization value at the transmitting end according to claim 6, characterized in that, The device also includes a judgment module; The judgment module is used to determine whether the detection module has completed its traversal; if not, it outputs information to the interface detection module.
8. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores computer program instructions executable by at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method for automatically adjusting the transmitter equalization value as described in any one of claims 1 to 5.
9. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions that cause the computer to perform the method of automatically adjusting the transmitter equalization value as described in any one of claims 1 to 5.