A method, system, device, and medium for monitoring power management chips.

Abstract

This application relates to a method, system, device, and medium for monitoring a power management chip. The method includes: receiving server power-on information; configuring the power management chip to a non-write-protected mode; polling the non-volatile register via a basic input / output system to obtain first power management information, wherein the first power management information includes error information used to confirm a fault in the power management chip; determining whether the power management chip has malfunctioned based on the first power management information; and, in response to a fault in the power management chip, shutting down a channel of the power management chip via the basic input / output system. This method can accurately detect faulty power management chips and avoid situations where the server cannot boot normally due to a power management chip malfunction during normal operation.

Description

Technical Field

[0001] This application relates to the field of memory monitoring technology, and in particular to a method, system, device and medium for monitoring power management chips. Background Technology

[0002] Previously, the power supply for DDR5 (Double Data Rate 5) memory was provided by a separate memory power supply circuit on the motherboard. Currently, the power management chip is integrated into the memory to manage and monitor the power of DDR5 memory.

[0003] PECI over MCTP (Platform Environment Control Interface over Management Component Transport Protocol) is a communication protocol that encapsulates the PECI protocol on top of the MCTP protocol. PECI over MCTP allows the transmission and execution of PECI commands on the PCI Express bus via the Management Component Transport Protocol. Through PECI over MCTP, administrators can monitor and manage processors and other hardware components via the PCI Express bus, including obtaining information such as temperature, voltage, and frequency, as well as configuring and controlling their operating status. PECI over MCTP provides a unified management interface, enabling processors and hardware components from different manufacturers to be managed using the same communication protocol. This simplifies system management complexity and improves system interoperability and scalability. The underlying hardware of PECI over MCTP uses the PCIe protocol, so its speed is much faster than the single-bus PECI protocol, and it has higher bandwidth.

[0004] In current Intel platform hardware designs, the power status signals (PSS) of every four dual in-line memory (DIM) modules are connected to a complex programmable logic device (CPL), which in turn connects to a baseboard management controller (BLC). This allows the BLC to detect the PSS signals. When the memory is functioning correctly, the PSS signal is high; when the power management chip malfunctions, the BLC can detect that the PSS signal is pulled low. However, the BLC cannot pinpoint exactly which specific DIM module's power management chip has failed.

[0005] Furthermore, if a power management chip malfunctions while the server is running normally, the server will immediately shut down. If a command is sent or the power button is pressed manually to turn it on at this time, the server will not be able to boot up normally because the power status signal is in a power failure state.

[0006] Based on this, this patent proposes a method, system, device, and medium for monitoring power management chips that can accurately detect faulty power management chips and prevent the server from failing to boot normally when the power management chip fails during normal operation. Summary of the Invention

[0007] Therefore, it is necessary to provide a method, system, device, and medium for monitoring power management chips that can accurately detect faulty power management chips and prevent servers from failing to boot normally when power management chips malfunction.

[0008] In a first aspect, a method for monitoring a power management chip is provided, applied to a system for monitoring a power management chip, wherein the power management chip includes a non-volatile register, and the method includes:

[0009] Step 10: Receive the server power-on information and configure the power management chip to non-write-protected mode;

[0010] Step 20: Poll the non-volatile register through the basic input / output system to obtain first power management information, wherein the first power management information includes error information used to confirm that the power management chip has failed;

[0011] Step 30: Determine whether the power management chip has malfunctioned based on the first power management information;

[0012] Step 40: In response to a fault in the power management chip, the first power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued by the baseboard management controller.

[0013] Step 401: Obtain the channel information of the memory module where the power management chip is located, wherein the channel information represents the connection information between the memory module and the basic input / output system, and the memory module is connected to the basic input / output system through a serial bus;

[0014] Step 402: Based on the channel information, shut down the fault channel of the memory module through the basic input / output system.

[0015] In one embodiment, determining whether the power management chip has malfunctioned based on the first power management information includes:

[0016] Step 410: In response to the absence of a fault in the power management chip, the memory module is powered on normally via the basic input / output system to initialize the memory module;

[0017] Step 420: In response to the completion of the memory module initialization, configure the power management chip to write-protected mode;

[0018] Step 430: Poll the non-volatile register through the basic input / output system to obtain second power management information, wherein the second power management information includes error information used to confirm that the power management chip has failed;

[0019] Step 440: Determine whether the power management chip has malfunctioned based on the second power management information;

[0020] Step 4501: In response to the power management chip not malfunctioning, enter the server self-test program;

[0021] Step 4502: In response to the server's self-test completion, the power management chip is monitored through the baseboard management controller.

[0022] In one embodiment, the method further includes:

[0023] The baseboard management controller detects whether the server has completed its self-test.

[0024] A high level on a general-purpose input / output pin confirms that the server self-test is complete.

[0025] A low level on a general-purpose input / output pin indicates that the server self-test has not been completed.

[0026] In one embodiment, determining whether the power management chip has malfunctioned based on the second power management information includes:

[0027] Step 4510: In response to a fault in the power management chip, the second power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued through the baseboard management controller. Steps 401 to 402 are repeated.

[0028] Step 4520: Restart the server via the baseboard management controller, and repeat steps 10 to 4520.

[0029] In one embodiment, monitoring of the power management chip via a baseboard management controller includes:

[0030] Receive the acquisition command sent by the baseboard management controller;

[0031] The central processing unit polls the power management chip to obtain the current voltage, current, and temperature values ​​of the power management chip.

[0032] The current voltage value, current current value, and current temperature value are compared with the voltage threshold, current threshold, and temperature threshold, respectively, to obtain the voltage comparison result, current comparison result, and temperature comparison result.

[0033] Based on the voltage comparison results, current comparison results, and temperature comparison results, determine whether to generate an alarm message;

[0034] In response to the voltage comparison result being that the current voltage value is greater than the voltage threshold, and / or the current comparison result being that the current current value is greater than the current threshold, and / or the temperature comparison result being that the current temperature value is greater than the temperature threshold, an alarm message is generated;

[0035] The alarm information includes voltage alarm information, current alarm information, and temperature alarm information.

[0036] In one embodiment, the non-volatile register includes a status register, which includes a periodic status register and an error logging register.

[0037] In one embodiment, the method further includes:

[0038] Based on a communication protocol, the baseboard management controller sends an acquisition command to the central processing unit, wherein the communication protocol allows the transmission and execution of the acquisition command on a high-speed serial computer expansion bus via a management component transmission protocol.

[0039] Secondly, a system for monitoring a power management chip is provided, including a central processing unit (CPU), an integrated southbridge, a baseboard management controller, and a memory module. The CPU manages a basic input / output system, and the memory module includes a hub, a temperature sensor, a power management chip, and a register clock driver.

[0040] The temperature sensor, power management chip, and register clock driver are respectively connected to the central processing unit via the hub;

[0041] The first end of the integrated southbridge is connected to the central processing unit, and the second end of the integrated southbridge is connected to the first end of the baseboard management controller;

[0042] The second terminal of the substrate management controller is connected to the central processing unit.

[0043] Thirdly, a computer device is provided, the computer device including one or more processors; and a memory associated with the one or more processors, the memory for storing program instructions, which, when read and executed by the one or more processors, perform the steps of the method as described in any one of the first aspects above.

[0044] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the steps of the method as described in any one of the first aspects above.

[0045] The aforementioned method for monitoring power management chips is applied to a system that monitors power management chips. It directly monitors the power management chip of a single memory module through the basic input / output system, shutting down the channel of the memory module where the faulty power management chip is located. This avoids the situation where the baseboard management controller, when monitoring multiple power management chips through complex programmable logic devices during server startup, cannot identify the specific location of the faulty power management chip, and also avoids the situation where the server cannot boot normally after the power management chip fails during normal operation. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating a method for monitoring a power management chip in one embodiment;

[0047] Figure 2 This is a connection diagram of a system for monitoring a power management chip in one embodiment.

[0048] Figure 3 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] Example 1

[0051] In one embodiment, such as Figure 1 As shown, a method for monitoring a power management chip is provided, applied to a system for monitoring a power management chip, wherein the power management chip includes a non-volatile register, and the method includes:

[0052] Step 10: Receive the server power-on information and configure the power management chip to non-write-protected mode;

[0053] Step 20: Poll the non-volatile register through the basic input / output system to obtain first power management information, wherein the first power management information includes error information used to confirm that the power management chip has failed;

[0054] Step 30: Determine whether the power management chip has malfunctioned based on the first power management information;

[0055] Step 40: In response to a fault in the power management chip, the first power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued by the baseboard management controller.

[0056] Step 401: Obtain the channel information of the memory module where the power management chip is located, wherein the channel information represents the connection information between the memory module and the basic input / output system, and the memory module is connected to the basic input / output system through a serial bus;

[0057] Step 402: Based on the channel information, shut down the fault channel of the memory module through the basic input / output system.

[0058] Specifically, the non-volatile register of the power management chip can be set in the memory module. After shutting down the channel of the memory module, the faulty power management chip can be replaced. The power status signal in the non-volatile register can be set to a signal indicating a normal power status through the basic input / output system. The replaced memory module can then be powered on again through the voltage regulator in the central processing unit.

[0059] Specifically, the error information of the faulty power management chip is sent to the baseboard management controller through the basic input / output system. Upon receiving the information, the baseboard management controller generates a log and issues an alarm.

[0060] Specifically, in the system for monitoring power management chips, a single power management chip is directly monitored through the basic input / output system. The channel of the faulty power management chip is shut down. This avoids the situation where the baseboard management controller cannot identify the specific location of the faulty power management chip when monitoring multiple power management chips through complex programmable logic devices during the server startup process, and also avoids the situation where the server cannot start normally after the power management chip fails during normal operation.

[0061] In one embodiment, determining whether the power management chip has malfunctioned based on the first power management information includes:

[0062] Step 410: In response to the absence of a fault in the power management chip, the memory module is powered on normally via the basic input / output system to initialize the memory module;

[0063] Step 420: In response to the completion of the memory module initialization, configure the power management chip to write-protected mode;

[0064] Step 430: Poll the non-volatile register through the basic input / output system to obtain second power management information, wherein the second power management information includes error information used to confirm that the power management chip has failed;

[0065] Step 440: Determine whether the power management chip has malfunctioned based on the second power management information;

[0066] Step 4501: In response to the power management chip not malfunctioning, enter the server self-test program;

[0067] Step 4502: In response to the server's self-test completion, the power management chip is monitored through the baseboard management controller.

[0068] Specifically, after the memory module completes initialization, the power management chip is polled a second time, so that the memory module containing the faulty power management chip is shielded by the basic input / output system during the power-on process, further preventing the server from failing to power on normally when the power management chip fails during normal operation.

[0069] In one embodiment, the method further includes:

[0070] The baseboard management controller detects whether the server has completed its self-test.

[0071] A high level on a general-purpose input / output pin confirms that the server self-test is complete.

[0072] A low level on a general-purpose input / output pin indicates that the server self-test has not been completed.

[0073] Specifically, the baseboard management controller detects the general-purpose input / output pins and determines whether the server has completed its self-test based on whether the pins are at a high or low level, so that the power management chip can be monitored by the base management controller.

[0074] Specifically, this general-purpose input / output (GPIO) pin is set to low level by default. After the self-test is completed, the Basic Input / Output System (PIS) sets this GPIO pin to high level as a sign that the server self-test is complete. When the IPS detects that the GPIO pin is high, it confirms that the self-test is complete.

[0075] In one embodiment, determining whether the power management chip has malfunctioned based on the second power management information includes:

[0076] Step 4510: In response to a fault in the power management chip, the second power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued through the baseboard management controller. Steps 401 to 402 are repeated.

[0077] Step 4520: Restart the server via the baseboard management controller, repeating steps 10 to 4520. Specifically, during the server startup process, if the power management chip malfunctions during the second polling, the channel of the faulty memory module is shut down, and the server is restarted via the baseboard management controller, repeating the first and second polling steps. This ensures that the faulty power management chip is shielded by the basic input / output system during startup, preventing the server from failing to boot normally when the power management chip malfunctions during normal operation.

[0078] In one embodiment, monitoring the power management chip via a baseboard management controller includes:

[0079] Receive the acquisition command sent by the baseboard management controller;

[0080] The central processing unit polls the power management chip to obtain the current voltage, current, and temperature values ​​of the power management chip.

[0081] The current voltage value, current current value, and current temperature value are compared with the voltage threshold, current threshold, and temperature threshold, respectively, to obtain the voltage comparison result, current comparison result, and temperature comparison result.

[0082] Based on the voltage comparison results, current comparison results, and temperature comparison results, determine whether to generate an alarm message;

[0083] In response to the voltage comparison result being that the current voltage value is greater than the voltage threshold, and / or the current comparison result being that the current current value is greater than the current threshold, and / or the temperature comparison result being that the current temperature value is greater than the temperature threshold, an alarm message is generated;

[0084] The alarm information includes voltage alarm information, current alarm information, and temperature alarm information.

[0085] Specifically, the baseboard management controller sends an acquisition command to the central processing unit, which compares the obtained current voltage, current and temperature values ​​with the voltage threshold, current threshold and temperature threshold in the non-volatile register, respectively, to determine whether to generate alarm and prompt information. This helps to find the cause of the power management chip failure and avoids the situation where the power management chip fails when the server is running normally, requiring manual power-on after the server is shut down.

[0086] In one embodiment, the non-volatile register includes a status register, which includes a periodic status register and an error logging register.

[0087] Specifically, the error log register records the power management chip status for each power-down sequence. When a power-down command is generated automatically due to a fault, the power management chip will write it into the register. The error log register will be updated during the power-down cycle. The cycle status register will be dynamically updated at a specific frequency to indicate the current, voltage, temperature, and other statuses of each module inside the power management chip at this time.

[0088] In one embodiment, the method further includes:

[0089] Based on the communication protocol, the baseboard management controller sends an acquisition command to the central processing unit, wherein the communication protocol allows the transmission and execution of the acquisition command on a high-speed serial computer expansion bus via the management component transmission protocol.

[0090] Specifically, the baseboard management controller periodically sends the acquisition command to the central processing unit via PECI over MCTP.

[0091] Specifically, the baseboard management controller communicates with the central processing unit via PECI over MCTP, eliminating the need for additional hardware design of I3C (Improved Inter-Integrated Circuit, a serial bus interface) circuits to connect the baseboard management controller and memory, thus saving costs and achieving the speed standard for real-time monitoring.

[0092] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0093] Example 2

[0094] In one embodiment, such as Figure 2As shown, a system for monitoring a power management chip is provided, including a central processing unit (CPU), an integrated southbridge, a baseboard management controller, and a memory module. The CPU manages the basic input / output system, and the memory module includes a hub, a temperature sensor, a power management chip, and a register clock driver.

[0095] The temperature sensor, power management chip, and register clock driver are respectively connected to the central processing unit via the hub;

[0096] The first end of the integrated southbridge is connected to the central processing unit, and the second end of the integrated southbridge is connected to the first end of the baseboard management controller;

[0097] The second terminal of the substrate management controller is connected to the central processing unit.

[0098] Specifically, the temperature sensor, power management chip, and register clock driver are each connected to the hub via local I3C, and the hub is connected to the multiplexer via the I3C bus. One end of the multiplexer is connected to the central processing unit, and the other end is connected to the baseboard management controller. The device select pin of the multiplexer is connected to a complex programmable logic device, so that all devices of the local dual in-line memory modules are visible as terminal devices on the I3C bus.

[0099] Specifically, the first end of the integrated southbridge is connected to the central processing unit via a direct media interface, the underlying hardware of which is also a PCIe bus; the second end of the integrated southbridge is connected to the first end of the baseboard management controller via a PCIe bus; and the second end of the baseboard management controller is connected to the central processing unit via a PECI bus.

[0100] Specifically, the baseboard management controller uses PECI over MCTP to send PECI commands to the central processing unit (CPU) to read and write registers via the integrated southbridge, allowing the CPU to access the power management chip. After reading the relevant data from the power management chip, the CPU then transmits the data back to the baseboard management controller via the PECI bus.

[0101] Example 3

[0102] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0103] Step 10: Receive the server power-on information and configure the power management chip to non-write-protected mode;

[0104] Step 20: Poll the non-volatile register through the basic input / output system to obtain first power management information, wherein the first power management information includes error information used to confirm that the power management chip has failed;

[0105] Step 30: Determine whether the power management chip has malfunctioned based on the first power management information;

[0106] Step 40: In response to a fault in the power management chip, the first power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued by the baseboard management controller.

[0107] Step 401: Obtain the channel information of the memory module where the power management chip is located, wherein the channel information represents the connection information between the memory module and the basic input / output system, and the memory module is connected to the basic input / output system through a serial bus;

[0108] Step 402: Based on the channel information, shut down the fault channel of the memory module through the basic input / output system.

[0109] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0110] Step 410: In response to the absence of a fault in the power management chip, the memory module is powered on normally via the basic input / output system to initialize the memory module;

[0111] Step 420: In response to the completion of the memory module initialization, configure the power management chip to write-protected mode;

[0112] Step 430: Poll the non-volatile register through the basic input / output system to obtain second power management information, wherein the second power management information includes error information used to confirm that the power management chip has failed;

[0113] Step 440: Determine whether the power management chip has malfunctioned based on the second power management information;

[0114] Step 4501: In response to the power management chip not malfunctioning, enter the server self-test program;

[0115] Step 4502: In response to the server's self-test completion, the power management chip is monitored through the baseboard management controller.

[0116] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0117] The baseboard management controller detects whether the server has completed its self-test.

[0118] A high level on a general-purpose input / output pin confirms that the server self-test is complete.

[0119] A low level on a general-purpose input / output pin indicates that the server self-test has not been completed.

[0120] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0121] Step 4510: In response to a fault in the power management chip, the second power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued through the baseboard management controller. Steps 401 to 402 are repeated.

[0122] Step 4520: Restart the server via the baseboard management controller, and repeat steps 10 to 4520.

[0123] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0124] Receive the acquisition command sent by the baseboard management controller;

[0125] The central processing unit polls the power management chip to obtain the current voltage, current, and temperature values ​​of the power management chip.

[0126] The current voltage value, current current value, and current temperature value are compared with the voltage threshold, current threshold, and temperature threshold, respectively, to obtain the voltage comparison result, current comparison result, and temperature comparison result.

[0127] Based on the voltage comparison results, current comparison results, and temperature comparison results, determine whether to generate an alarm message;

[0128] In response to the voltage comparison result being that the current voltage value is greater than the voltage threshold, and / or the current comparison result being that the current current value is greater than the current threshold, and / or the temperature comparison result being that the current temperature value is greater than the temperature threshold, an alarm message is generated;

[0129] The alarm information includes voltage alarm information, current alarm information, and temperature alarm information.

[0130] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0131] The non-volatile register includes a status register, which includes a periodic status register and an error recording register.

[0132] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0133] Based on the communication protocol, the baseboard management controller sends an acquisition command to the central processing unit, wherein the communication protocol allows the transmission and execution of the acquisition command on a high-speed serial computer expansion bus via the management component transmission protocol.

[0134] When the program instructions are read and executed by the one or more processors, they can also perform operations corresponding to the steps in the above method embodiments, as described above, and will not be repeated here. (Reference) Figure 3 This exemplifies the architecture of a computer device, which may include a processor 310, a video display adapter 311, a disk drive 312, an input / output interface 313, a network interface 314, and a memory 320. The processor 310, video display adapter 311, disk drive 312, input / output interface 313, network interface 314, and memory 320 can communicate with each other via a communication bus 330.

[0135] The processor 310 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to achieve the technical solution provided in this application.

[0136] The memory 320 can be implemented as a read-only memory (ROM), random access memory (RAM), static storage device, dynamic storage device, etc. The memory 320 can store the operating system 321 for controlling the operation of the computer device 300, and the basic input / output system (BIOS) 322 for controlling the low-level operations of the computer device 300. Additionally, it can store a web browser 323, data storage management 324, and an icon font processing system 325, etc. The aforementioned icon font processing system 325 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when the technical solution provided in this application is implemented through software or firmware, the relevant program code is stored in the memory 320 and is called and executed by the processor 310.

[0137] Input / output interface 313 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0138] Network interface 314 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0139] Bus 330 includes a pathway for transmitting information between various components of the device, such as processor 310, video display adapter 311, disk drive 312, input / output interface 313, network interface 314, and memory 320.

[0140] In addition, the computer device 300 can also obtain information on specific acquisition conditions from the virtual resource object acquisition condition information database 341 for condition judgment, etc.

[0141] It should be noted that although the computer device 300 described above only shows a processor 310, a video display adapter 311, a disk drive 312, an input / output interface 313, a network interface 314, a memory 320, and a bus 330, in specific implementations, the computer device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0142] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, cloud server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0143] Example 4

[0144] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0145] Step 10: Receive the server power-on information and configure the power management chip to non-write-protected mode;

[0146] Step 20: Poll the non-volatile register through the basic input / output system to obtain first power management information, wherein the first power management information includes error information used to confirm that the power management chip has failed;

[0147] Step 30: Determine whether the power management chip has malfunctioned based on the first power management information;

[0148] Step 40: In response to a fault in the power management chip, the first power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued by the baseboard management controller.

[0149] Step 401: Obtain the channel information of the memory module where the power management chip is located, wherein the channel information represents the connection information between the memory module and the basic input / output system, and the memory module is connected to the basic input / output system through a serial bus;

[0150] Step 402: Based on the channel information, shut down the fault channel of the memory module through the basic input / output system.

[0151] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0152] Step 410: In response to the absence of a fault in the power management chip, the memory module is powered on normally via the basic input / output system to initialize the memory module;

[0153] Step 420: In response to the completion of the memory module initialization, configure the power management chip to write-protected mode;

[0154] Step 430: Poll the non-volatile register through the basic input / output system to obtain second power management information, wherein the second power management information includes error information used to confirm that the power management chip has failed;

[0155] Step 440: Determine whether the power management chip has malfunctioned based on the second power management information;

[0156] Step 4501: In response to the power management chip not malfunctioning, enter the server self-test program;

[0157] Step 4502: In response to the server's self-test completion, the power management chip is monitored through the baseboard management controller.

[0158] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0159] The baseboard management controller detects whether the server has completed its self-test.

[0160] A high level on a general-purpose input / output pin confirms that the server self-test is complete.

[0161] A low level on a general-purpose input / output pin indicates that the server self-test has not been completed.

[0162] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0163] Step 4510: In response to a fault in the power management chip, the second power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued through the baseboard management controller. Steps 401 to 402 are repeated.

[0164] Step 4520: Restart the server via the baseboard management controller, and repeat steps 10 to 4520.

[0165] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0166] Receive the acquisition command sent by the baseboard management controller;

[0167] The central processing unit polls the power management chip to obtain the current voltage, current, and temperature values ​​of the power management chip.

[0168] The current voltage value, current current value, and current temperature value are compared with the voltage threshold, current threshold, and temperature threshold, respectively, to obtain the voltage comparison result, current comparison result, and temperature comparison result.

[0169] Based on the voltage comparison results, current comparison results, and temperature comparison results, determine whether to generate an alarm message;

[0170] In response to the voltage comparison result being that the current voltage value is greater than the voltage threshold, and / or the current comparison result being that the current current value is greater than the current threshold, and / or the temperature comparison result being that the current temperature value is greater than the temperature threshold, an alarm message is generated;

[0171] The alarm information includes voltage alarm information, current alarm information, and temperature alarm information.

[0172] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0173] The non-volatile register includes a status register, which includes a periodic status register and an error recording register.

[0174] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0175] Based on the communication protocol, the baseboard management controller sends an acquisition command to the central processing unit, wherein the communication protocol allows the transmission and execution of the acquisition command on a high-speed serial computer expansion bus via the management component transmission protocol.

[0176] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0177] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for monitoring a power management chip, applied to a system for monitoring a power management chip, wherein the power management chip includes a non-volatile register, characterized in that, The method includes: Step 10: Receive the server power-on information and configure the power management chip to non-write-protected mode; Step 20: Poll the non-volatile register through the basic input / output system to obtain first power management information, wherein the first power management information includes error information used to confirm that the power management chip has failed; Step 30: Determine whether the power management chip has malfunctioned based on the first power management information; Step 40: In response to a fault in the power management chip, the first power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued by the baseboard management controller. Step 401: Obtain the channel information of the memory module where the power management chip is located, wherein the channel information represents the connection information between the memory module and the basic input / output system, and the memory module is connected to the basic input / output system through a serial bus; Step 402: Based on the channel information, shut down the fault channel of the memory module through the basic input / output system; The step of determining whether the power management chip has malfunctioned based on the first power management information includes: Step 410: In response to the absence of a fault in the power management chip, the memory module is powered on normally via the basic input / output system to initialize the memory module; Step 420: In response to the completion of the memory module initialization, configure the power management chip to write-protected mode; Step 430: Poll the non-volatile register through the basic input / output system to obtain second power management information, wherein the second power management information includes error information used to confirm that the power management chip has failed; Step 440: Determine whether the power management chip has malfunctioned based on the second power management information; Step 4501: In response to the power management chip not malfunctioning, enter the server self-test program; Step 4502: In response to the server's self-test completion, the power management chip is monitored through the baseboard management controller; Determining whether the power management chip has malfunctioned based on the second power management information includes: Step 4510: In response to a fault in the power management chip, the second power management information is transmitted to the baseboard management controller, and a log is generated and an alarm is issued through the baseboard management controller. Steps 401 to 402 are repeated. Step 4520: Restart the server via the baseboard management controller, and repeat steps 10 to 4520.

2. The method according to claim 1, characterized in that, The method further includes: The baseboard management controller detects whether the server has completed its self-test. A high level on a general-purpose input / output pin confirms that the server self-test is complete. A low level on a general-purpose input / output pin indicates that the server self-test has not been completed.

3. The method according to claim 1, characterized in that, Monitoring the power management chip via a baseboard management controller includes: Receive the acquisition command sent by the baseboard management controller; The central processing unit polls the power management chip to obtain the current voltage, current, and temperature values ​​of the power management chip. The current voltage value, current current value, and current temperature value are compared with the voltage threshold, current threshold, and temperature threshold, respectively, to obtain the voltage comparison result, current comparison result, and temperature comparison result. Based on the voltage comparison results, current comparison results, and temperature comparison results, determine whether to generate an alarm message; In response to the voltage comparison result being that the current voltage value is greater than the voltage threshold, and / or the current comparison result being that the current current value is greater than the current threshold, and / or the temperature comparison result being that the current temperature value is greater than the temperature threshold, an alarm message is generated; The alarm information includes voltage alarm information, current alarm information, and temperature alarm information.

4. The method according to any one of claims 1-3, characterized in that, The non-volatile register includes a status register, which includes a periodic status register and an error recording register.

5. The method according to claim 3, characterized in that, The method further includes: Based on a communication protocol, the baseboard management controller sends an acquisition command to the central processing unit, wherein the communication protocol allows the transmission and execution of the acquisition command on a high-speed serial computer expansion bus via a management component transmission protocol.

6. A system for implementing the method of monitoring a power management chip according to claim 1, characterized in that, It includes a central processing unit (CPU), an integrated southbridge, a baseboard management controller, and a memory module. The CPU manages the basic input / output system, and the memory module includes a hub, a temperature sensor, a power management chip, and a register clock driver. The temperature sensor, power management chip, and register clock driver are respectively connected to the central processing unit via the hub; The first end of the integrated southbridge is connected to the central processing unit, and the second end of the integrated southbridge is connected to the first end of the baseboard management controller; The second terminal of the substrate management controller is connected to the central processing unit.

7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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