Array substrate, display panel and display device

Abstract

The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device, which can reduce the occurrence of transistor leakage in the array substrate and improve the display image quality of the display panel. Among them, an array substrate includes a plurality of pixel driving circuits, and the pixel driving circuit at least includes a compensation transistor. Among them, an active layer arranged on one side of the substrate includes an active layer pattern of the compensation transistor, and the active layer pattern of the compensation transistor includes two channel regions and a conductive area connected between the two channel regions. A first gate layer arranged on the side of the active layer away from the substrate includes a first gate signal line, and the first gate signal line overlaps with the positive projection of the two channel regions on the substrate. A second gate layer arranged on the side of the first gate layer away from the substrate includes a voltage stabilization pattern, and the voltage stabilization pattern is configured to receive a power supply voltage signal, and the voltage stabilization pattern overlaps with the positive projection of the conductive area on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] The display panel includes pixels arranged in an array, and each pixel includes an electrically connected pixel driving circuit and a light-emitting device. The pixel driving circuit controls the light brightness and light-emitting time of the light-emitting device by controlling the conduction and cutoff of its internal transistor. The connection points between the transistors and the circuits inside the pixel driving circuit are easily affected by other electromagnetic signals, causing voltage offset at the transistors or connection points, resulting in leakage. Summary of the invention

[0003] In order to overcome the above-mentioned defects in the prior art, the present invention provides an array substrate, a display panel and a display device, which can reduce the occurrence of transistor leakage in the array substrate and improve the display image quality of the display panel.

[0004] On the one hand, the present invention provides an array substrate, including a plurality of pixel driving circuits arranged in an array, wherein the pixel driving circuits at least include compensation transistors. The array substrate includes: a substrate, an active layer, a first gate layer, and a second gate layer. Among them, the active layer arranged on one side of the substrate includes an active layer pattern of the compensation transistor, and the active layer pattern of the compensation transistor includes two channel regions and a conductive region located between the two channel regions. The first gate layer arranged on the side of the active layer away from the substrate includes a first gate signal line, and the orthographic projection of the first gate signal line on the substrate overlaps with the orthographic projection of the two channel regions on the substrate. The second gate layer arranged on the side of the first gate layer away from the substrate includes a voltage stabilizing pattern, which is configured to receive a power supply voltage signal, and the orthographic projection of the voltage stabilizing pattern on the substrate overlaps with the orthographic projection of the conductive region on the substrate.

[0005] The voltage stabilizing pattern receives a power supply voltage signal to form a stable voltage, and the conductive area overlapping with the voltage stabilizing pattern is affected by the stable voltage. When affected by external factors, the voltage fluctuation of the conductive area is weakened. Correspondingly, the voltage change of the two ends of the first channel area and the second channel area connected to the conductive area is weakened, which can reduce the leakage of the dual-gate thin-film transistor, improve the driving current control quality of the pixel driving circuit, and improve the quality of the display screen of the display panel accordingly.

[0006] In some embodiments, the two channel regions include a first channel region and a second channel region. The active layer pattern of the compensation transistor includes a first pattern and a second pattern connected to each other, the first pattern extends along a first direction, the second pattern extends along a second direction, the first direction and the second direction intersect, the first channel region is located on the first pattern, the second channel region is located on the second pattern, and the conductive region is located at the connection position of the first pattern and the second pattern.

[0007] The first gate signal line includes a first gate signal main line and at least one first extension portion connected to the first gate signal main line, the first gate signal main line extends along a first direction, and the first extension portion extends along a second direction; the orthographic projection of the first gate signal main line on the substrate overlaps with the orthographic projection of the second pattern on the substrate, and the orthographic projection of the first extension portion on the substrate overlaps with the orthographic projection of the first pattern on the substrate.

[0008] In some embodiments, the pixel driving circuit further includes a capacitor, the first gate layer further includes a first plate of the capacitor, the second gate layer further includes a second plate of the capacitor, and the orthographic projection of the second plate on the substrate overlaps with the orthographic projection of the first plate on the substrate. The voltage stabilizing pattern is connected to the second plate, and the voltage stabilizing pattern is located on a side of the second plate close to the first gate signal line.

[0009] In some embodiments, an orthographic projection of the first gate signal main line on the substrate and an orthographic projection of the first extension portion on the substrate form at least one corner, and an orthographic projection of the voltage stabilization pattern on the substrate is located within the corner.

[0010] In some embodiments, the array substrate further includes: a first insulating layer disposed between the active layer and the first gate layer, a second insulating layer disposed between the first gate layer and the second gate layer, a third insulating layer disposed on the side of the second gate layer away from the substrate, and a first source-drain metal layer disposed on the side of the third insulating layer away from the substrate. The first source-drain metal layer includes a first connection terminal and a first connection pattern, and the first connection terminal is connected to the active layer through a via hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer. The first connection pattern includes a first end, a first connection line, and a second end connected in sequence, and the first end is connected to the active layer through a via hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer. The second gate layer also includes at least one shielding pattern, and the orthographic projection of the shielding pattern on the substrate is located between the adjacent first connection terminal and the first end of the connection pattern; the shielding pattern is configured to receive a constant voltage signal.

[0011] In some embodiments, the pixel driving circuit further includes a write transistor, the active layer includes an active layer pattern of the write transistor, the first connection end is connected to the active layer pattern of the write transistor, the first end of the first connection pattern is connected to the active layer pattern of the compensation transistor, and the second end of the first connection pattern is connected to the first plate of the capacitor.

[0012] In some embodiments, the second gate layer further includes an initialization signal line, and the shielding pattern is connected to the initialization signal line.

[0013] In some embodiments, the initialization signal line includes a first initialization signal line connected to the shielding pattern. The pixel driving circuit also includes a first reset transistor, the active layer includes an active layer pattern of the first reset transistor, and the first initialization signal line is electrically connected to the active layer pattern of the first reset transistor.

[0014] In some embodiments, the array substrate further comprises: a fourth insulating layer disposed on a side of the first source-drain metal layer away from the substrate, and a second source-drain metal layer disposed on a side of the fourth insulating layer away from the substrate. The second source-drain metal layer comprises a data line and a power supply voltage signal line, and the data line is connected to the first connection end.

[0015] In some embodiments, the first source-drain metal layer further includes a plurality of second connection patterns, the second connection pattern includes a third end, a second connection line, and a fourth end connected in sequence, the third end is connected to the second plate of the capacitor through a via penetrating the third insulating layer; the fourth end is connected to the power supply voltage signal line through a via penetrating the fourth insulating layer. The pixel driving circuit further includes a first enabling transistor, the active layer includes an active layer pattern of the first enabling transistor, and the fourth end of the second connection pattern is connected to the active layer pattern of the first enabling transistor through a via penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

[0016] In some embodiments, the pixel driving circuit further includes a second enabling transistor, and the active layer includes an active layer pattern of the second enabling transistor. The first gate layer further includes an enabling signal line, and the orthographic projection of the enabling signal line on the substrate overlaps with the orthographic projection of the active layer pattern of the first enabling transistor on the substrate and the orthographic projection of the active layer pattern of the second enabling transistor on the substrate.

[0017] In some embodiments, the pixel driving circuit further comprises a second reset transistor, the active layer comprises an active layer pattern of the second reset transistor, and the initialization signal line further comprises a second initialization signal line connected to the active layer pattern of the second reset transistor.

[0018] In some embodiments, the first gate layer further includes a first reset signal line and a second reset signal line, and the orthographic projection of the first reset signal line on the substrate overlaps with the orthographic projection of the active layer pattern of the first reset transistor on the substrate. The orthographic projection of the second reset signal line on the substrate overlaps with the orthographic projection of the active layer pattern of the second reset transistor on the substrate.

[0019] In some embodiments, the pixel driving circuit further includes a driving transistor, the active layer includes an active layer pattern of the driving transistor, and an orthographic projection of the active layer pattern of the driving transistor on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate.

[0020] In another aspect, the present invention provides a display panel including: an array substrate as described in any one of the embodiments in the above aspect.

[0021] In some embodiments, the display panel also includes: an anode layer arranged on the array substrate, the anode layer including multiple anodes, a light-emitting layer arranged on the side of the anode layer away from the substrate, a cathode layer arranged on the side of the light-emitting layer away from the substrate, and an encapsulation layer arranged on the side of the cathode layer away from the substrate.

[0022] The array substrate has the function of stabilizing the voltage of the conductive area of ​​the compensation transistor and stabilizing the voltage at the junction. The display panel using the array substrate has the same function as the above array substrate. Accordingly, the display panel can significantly improve the display picture quality.

[0023] In yet another aspect, the present invention provides a display device comprising: a display panel according to any one of the embodiments in the yet another aspect.

[0024] The display device of the present invention has the same beneficial effects as the above-mentioned display panel, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A structural diagram of a display device provided by an embodiment of the present invention;

[0027] Figure 2 A structural diagram of a display panel provided by an embodiment of the present invention;

[0028] Figure 3 A partial cross-sectional view of a display panel provided by an embodiment of the present invention;

[0029] Figure 4 A structural diagram of an active layer provided by an embodiment of the present invention;

[0030] Figure 5 A structural diagram of a first gate layer provided by an embodiment of the present invention;

[0031] Figure 6 A structural diagram of an active layer and a first gate layer provided in an embodiment of the present invention;

[0032] Figure 7 A structural diagram of a second gate layer provided by an embodiment of the present invention;

[0033] Figure 8 A structural diagram of an active layer, a first gate layer and a second gate layer provided in an embodiment of the present invention;

[0034] Fig. 9 A circuit diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0035] Fig.10 A partial cross-sectional view of another display panel provided by an embodiment of the present invention;

[0036] Fig.11 A structural diagram of another active layer and a first gate layer provided for an embodiment of the present invention;

[0037] Fig.12 A structural diagram of another active layer provided by an embodiment of the present invention;

[0038] Fig.13 A partial structural diagram of another active layer provided by an embodiment of the present invention;

[0039] Fig.14 A structural diagram of another first gate layer provided by an embodiment of the present invention;

[0040] Fig.15 A partial structural diagram of another first gate layer provided by an embodiment of the present invention;

[0041] Fig.16 A partial structural diagram of another active layer and a first gate layer provided for an embodiment of the present invention;

[0042] Fig.17 A structural diagram of another active layer, a first gate layer and a second gate layer provided for an embodiment of the present invention;

[0043] Fig.18 A partial structural diagram of another active layer, a first gate layer and a second gate layer provided for an embodiment of the present invention;

[0044] Fig.19 A structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0045] Fig. 20 for Fig.19 Cross-section view along the AA direction;

[0046] Fig.21 A structural diagram of another second gate layer provided by an embodiment of the present invention;

[0047] Fig. 22 A structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0048] Fig.23 A structural diagram of a first source-drain metal layer provided in an embodiment of the present invention;

[0049] Fig.24 A structural diagram of another pixel driving circuit and a second source-drain metal layer provided by an embodiment of the present invention;

[0050] Fig.25 A structural diagram of another array arrangement of pixel driving circuits provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example", etc. are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present invention. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0055] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices being configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0058] Some embodiments of the present invention provide a display device, for example, the display device may be a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a car computer, a wearable display device, etc. The embodiments of the present invention do not specifically limit the specific form of the display device. Specifically, Figure 1 As shown, the display device 1000 is a mobile phone, and the display device 1000 includes a display panel 100 .

[0059] In some embodiments, Figure 2 As shown, the display panel 100 includes a display area AA (Active Area, referred to as AA area; also referred to as an effective display area) and a peripheral area BB located at least on one side of the display area AA. In the display area AA, a plurality of pixels P' and a plurality of signal lines arranged in an array are provided. Each pixel P' includes a plurality of sub-pixels SP'. The sub-pixel SP' is the smallest unit for the display panel 100 to display a picture. Each sub-pixel SP' can display a single color, such as red (R), green (G) or blue (B). By adjusting the brightness (grayscale) of the sub-pixels SP' of different colors, the display of multiple colors can be realized through color combination and superposition, thereby realizing full-color display of the display panel 100.

[0060] In some embodiments, each sub-pixel SP' includes a light emitting device and a pixel driving circuit 60 for driving the light emitting device to emit light. All pixel driving circuits 60 in the display panel 100 are also arranged in an array.

[0061] Among them, the light-emitting device can be an organic light-emitting diode (OLED), a micro organic light-emitting diode (Micro OLED), a quantum dot organic light-emitting diode (QLED), a mini light-emitting diode (Mini LED) or a micro light-emitting diode (Micro LED).

[0062] The pixel driving circuit 60 may include a plurality of transistors and capacitors. For example, the transistor may be a thin film transistor (TFT), a field effect transistor (eg, an oxide thin film transistor), or other switching devices with the same characteristics. In the embodiments of the present invention, thin film transistors are used as examples.

[0063] In some embodiments of the present invention, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiments of the present invention can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0064] In some embodiments, Figure 2 As shown, the plurality of signal lines include a plurality of scanning signal lines GL, a plurality of data lines DL, a plurality of reset signal lines Rst, a plurality of enable signal lines EM, a plurality of initialization signal lines Vinit, and a plurality of power supply voltage signal lines VDD. Exemplarily, the plurality of scanning signal lines GL, the plurality of enable signal lines EM, and the plurality of initialization signal lines Vinit are arranged along the row arrangement direction of the sub-pixels SP', and the plurality of data lines DL and the plurality of power supply voltage signal lines VDD are arranged along the column arrangement direction of the sub-pixels SP'. Each pixel driving circuit 60 is electrically connected to the scanning signal lines GL, the data lines DL, the reset signal lines, the enable signal lines EM, the initialization signal lines Vinit, and the power supply voltage signal lines VDD.

[0065] In some embodiments, Figure 3As shown, the display panel 100 includes an array substrate 10, a light-emitting device layer 20 and an encapsulation layer 30. The array substrate 10 includes: a substrate 40 and a driving circuit layer 50 disposed on the substrate 40, and the driving circuit layer 50 includes a functional layer and an insulating layer located between adjacent functional layers. The functional layer may include an active layer 61, a first gate layer 62, a second gate layer 63, a first source-drain metal layer 64 and a second source-drain metal layer 65, etc. The active layer 61, the first gate layer 62, the second gate layer 63 and the first source-drain metal layer 64 are used to form a plurality of pixel driving circuits 60 in the display panel 100, the light-emitting device layer 20 is disposed on a side of the driving circuit layer 50 away from the substrate 40, and the encapsulation layer 30 is disposed on a side of the light-emitting device layer 20 away from the substrate 40.

[0066] In some examples, the substrate 40 may include a base 41 and a buffer layer (Buffer) 42. The base 41 may be a silicon substrate or may be a flexible material such as polyimide (PI) or saturated polyester (PET), the buffer layer 42 is disposed on the base 41, and the driving circuit layer 50 is disposed on the side of the buffer layer 42 away from the base 41.

[0067] In some examples, the driving circuit layer 50 may include: an active layer 61 disposed on one side of the substrate 40, a first gate layer 62 disposed on a side of the active layer 61 away from the substrate 40, and a second gate layer 63 disposed on a side of the first gate layer 62 away from the substrate 40. The active layer 61 may be made of polycrystalline silicon (P-Si), and the active layer 61 includes active layer patterns of each transistor of the pixel driving circuit 60, and the active layer pattern of each transistor includes a channel region Sg.

[0068] Figure 4 The active layer patterns of the transistors included in a pixel driving circuit are schematically shown, for example: a first active layer pattern AL1, a second active layer pattern AL2, a third active layer pattern AL3, a fourth active layer pattern AL4, a fifth active layer pattern AL5, a sixth active layer pattern AL6 and a seventh active layer pattern AL7.

[0069] In some embodiments, in the display area, multiple sub-pixels are arranged in an array, multiple pixel driving circuits are also arranged in an array, and the active layer 61 includes active layer patterns of each transistor in the multiple pixel driving circuits. For example, the active layer includes Figure 4 The active layer pattern of the transistor of the pixel driving circuit shown is used as a unit, and the pattern is replicated in an array of rows and columns.

[0070] The first gate layer 62 and the second gate layer 63 include a plurality of signal lines, wherein Figure 5 and Figure 6As shown, the first gate layer 62 includes a plurality of signal lines and a first electrode plate Cst1 of the capacitor. The plurality of signal lines may be, for example, a scan signal line GL, a reset signal line Rst, and an enable signal line EM. The plurality of signal lines located in the first gate layer 62 pass through the active layer pattern of each transistor, and the position where the plurality of signal lines located in the first gate layer 62 overlap with the active layer pattern of each transistor is the gate pattern Cp of each transistor.

[0071] For example, Figure 6 As shown, the first reset signal line Rst1 passes through the first active layer pattern AL1, and the overlapping portion of the first reset signal line Rst1 and the first active layer pattern AL1 is the first gate pattern Cp1.

[0072] The scan signal line GL passes through the second active layer pattern AL2 and the fourth active layer pattern AL4. The overlapped portion of the scan signal line GL and the second active layer pattern AL2 is the second gate pattern Cp2. The overlapped portion of the scan signal line GL and the fourth active layer pattern AL4 is the fourth gate pattern Cp4.

[0073] The first electrode plate Cst1 passes through the third active layer pattern AL3, and the overlapping portion of the first electrode plate Cst1 and the third active layer pattern AL3 is the third gate pattern Cp3.

[0074] The enable signal line EM passes through the fifth active layer pattern AL5 and the sixth active layer pattern AL6 , and the overlapping portion of the enable signal line EM and the fifth active layer pattern AL5 is the fifth gate pattern Cp5 , and the overlapping portion of the enable signal line EM and the sixth active layer pattern AL6 is the sixth gate pattern Cp6 .

[0075] The second reset signal line Rst2 passes through the seventh active layer pattern AL7, and an overlapping portion of the second reset signal line Rst2 and the seventh active layer pattern AL7 is a seventh gate pattern Cp7.

[0076] In some embodiments, Figure 7 As shown, the second gate layer 63 includes a plurality of signal lines and a second plate Cst2 of the capacitor, and the plurality of signal lines includes an initialization signal line Vinit.

[0077] It should be noted that "passing through" in the present invention means that the orthographic projection of the former on the substrate overlaps with the orthographic projection of the latter on the substrate. For example, each signal line of the first gate layer 62 passes through the active layer pattern of the corresponding transistor, which means that the orthographic projection of each signal line of the first gate layer 62, such as the scanning signal line GL, on the substrate overlaps with the orthographic projection of the second active layer pattern AL2 on the substrate.

[0078] In some embodiments, the pixel driving circuit 60 includes a plurality of transistors and capacitors. The pixel driving circuit 60 may be a circuit including 2T1C, 7T1C, or 6T1C, wherein T represents a thin film transistor, and the number before T represents the number of thin film transistors, and C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 thin film transistors and 1 capacitor. The following is an introduction to the pixel driving circuit in the 7T1C mode.

[0079] For example, Figure 8 and Fig. 9 As shown, Figure 8 is a layout of a pixel driving circuit 60 in 7T1C mode, Fig. 9 for Figure 8 7T1C mode pixel driving circuit 60 includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first enabling transistor T5, a second enabling transistor T6, a second reset transistor T7 and a capacitor Cst.

[0080] Among them, the control electrode of the first reset transistor T1 is electrically connected to the first reset signal terminal r1, the first electrode of the first reset transistor T1 is electrically connected to the first initialization signal terminal v1, the second electrode of the first reset transistor T1 is electrically connected to the first node N1, the first reset signal terminal r1 is electrically connected to the first reset signal line Rst1, and the first initialization signal terminal v1 is electrically connected to the first initialization signal line Vinit1.

[0081] The control electrode of the compensation transistor T2 is electrically connected to the scan signal terminal g, the first electrode of the compensation transistor T2 is electrically connected to the third node N3, the second electrode of the compensation transistor T2 is electrically connected to the first node N1, and the scan signal terminal g is electrically connected to the scan signal line GL.

[0082] The control electrode of the driving transistor T3 is electrically connected to the first node N1 , the first electrode of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode of the driving transistor T3 is electrically connected to the third node N3 .

[0083] The first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, the second plate Cst2 of the capacitor Cst is electrically connected to the first voltage signal terminal vdd, and the first voltage signal terminal vdd is electrically connected to the power supply voltage signal line VDD.

[0084] The control electrode of the write transistor T4 is electrically connected to the scan signal terminal g, the first electrode of the write transistor T4 is electrically connected to the data signal terminal d, the second electrode of the write transistor T4 is electrically connected to the second node N2, and the data signal terminal d is electrically connected to the data line DL.

[0085] The control electrode of the first enable transistor T5 is electrically connected to the light emitting control signal terminal em, the first electrode of the first enable transistor T5 is electrically connected to the first voltage signal terminal vdd, the second electrode of the first enable transistor T5 is electrically connected to the second node N2, and the light emitting control signal terminal em is electrically connected to the enable signal wiring EM.

[0086] The control electrode of the second enabling transistor T6 is electrically connected to the light emitting control signal terminal em, the first electrode of the second enabling transistor T6 is electrically connected to the third node N3 , and the second electrode of the second enabling transistor T6 is electrically connected to the anode of the light emitting device 30 .

[0087] The control electrode of the second reset transistor T7 is electrically connected to the second reset signal terminal r2, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal terminal v2, the second electrode of the second reset transistor T7 is electrically connected to the second electrode of the second enable transistor T6 and the connection point N4 of the anode of the light-emitting device 30, the cathode of the light-emitting device 30 is electrically connected to the second voltage signal terminal vss, the second initialization signal terminal v2 is electrically connected to the second initialization signal line Vinit2, the second reset signal terminal r2 is electrically connected to the second reset signal line Rst2, and the second voltage signal terminal vss is electrically connected to the second voltage signal line, wherein the second voltage signal line transmits a low-level signal, for example, the voltage of the low-level signal can be zero.

[0088] The specific working process of each transistor is as follows: in the data writing stage, the compensation transistor T2 and the writing transistor T4 are turned on under the control of the scanning signal received at the scanning signal terminal g, and the data signal received at the data signal terminal v is written into the first node N1, so as to form a threshold voltage compensation for the driving transistor T3. When it is turned off, the voltage of the first node N1 is the sum of the data signal and the threshold voltage of the driving transistor T3, and the voltage of the first node N1 can control the magnitude of the driving current passing through the driving transistor T3.

[0089] In the light-emitting stage, the compensation transistor T2 and the write transistor T4 are cut off under the control of the first scanning signal, the first enable transistor T5 and the second enable transistor T6 are turned on under the control of the enable signal received at the light-emitting control signal terminal em, the driving transistor T3 is turned on and generates a driving current, and the driving current is transmitted to the light-emitting device 30. The light-emitting device 30 emits light under the control of the driving current. The size of the driving current affects the brightness of the light. That is to say, the voltage of the first node N1 can control the brightness of the light-emitting device 30, that is, it can control the grayscale of the sub-pixel, thereby affecting the quality of the entire display screen.

[0090] It should be noted that the first node N1, the second node N2 and the third node N3 in the embodiment of the present invention do not represent actual existing components, but represent the confluence points of related circuit connections in the layout of the pixel driving circuit 60, that is, the first node N1, the second node N2 and the third node N3 are nodes formed by the equivalent confluence points of related circuit electrical connections in the circuit diagram.

[0091] In some embodiments, some transistors in the pixel driving circuit are dual-gate thin film transistors, and the active layer pattern of the dual-gate thin film transistor is as follows: Figure 4 The second active layer pattern AL2 shown in FIG. 1 includes two channel regions: a first channel region Sg1 and a second channel region Sg2, and a conductive region Cr located between the two channel regions. Figure 8 As shown, the dual-gate thin film transistor has two second gate patterns Cp2: a first second gate pattern Cp2a and a second second gate pattern Cp2b. The orthographic projections of the two second gate patterns Cp2 on the substrate correspond to two channel regions respectively. The two second gate patterns Cp2 receive the same signal. For example, two positions in a first gate signal line pass through the active layer pattern of the dual-gate thin film transistor, wherein the first gate signal line is located in the first gate layer 62. The two positions on the first gate signal line are two gate patterns CP2 of the dual-gate thin film transistor. The first gate signal line passes through the dual At the active layer pattern of the double-gate thin film transistor, the position where the active layer pattern of the double-gate thin film transistor (the second active layer pattern AL2) overlaps with the first gate signal line once is the first channel region, the first gate signal line passes through the active layer pattern of the double-gate thin film transistor for the second time, the position where the active layer pattern of the double-gate thin film transistor (the second active layer pattern AL2) overlaps with the first gate signal line again is the second channel region, the active layer pattern of the double-gate thin film transistor between the first channel region and the second channel region is the conductive region Cr, and the projections of the conductive region Cr and the signal lines of the first gate layer 62 on the substrate do not overlap.

[0092] In some examples, the compensation transistor T2 is a dual-gate thin film transistor, and the active layer pattern of the compensation transistor T2 is the active layer pattern of the dual-gate thin film transistor, for example Figure 4 The active layer pattern AL2 of the second transistor shown is the active layer pattern of the dual-gate thin film transistor. Figure 8As shown, the active layer 61 includes an active layer pattern of the compensation transistor T2, and the active layer pattern of the compensation transistor T2 includes two channel regions: a first channel region and a second channel region, and a conductive region Cr located between the two channel regions, and the conductive region Cr connects the two channel regions. The first gate layer 62 includes a first gate signal line XL, and the positive projection of the first gate signal line XL on the substrate overlaps with the positive projection of the two channel regions on the substrate. The overlapping position of the first gate signal line XL and the first channel region of the active layer pattern of the compensation transistor T2 is the first second gate pattern Cp2a, and the overlapping position of the first gate signal line XL and the second channel region of the active layer pattern of the compensation transistor T2 is the second second gate pattern Cp2b. Among them, the first gate signal line XL can be, for example, a scanning signal line GL.

[0093] The conductive area Cr of the compensation transistor T2 will produce voltage fluctuations when affected by an external electric field or signal. During the voltage fluctuation of the conductive area Cr, the channel area Sg position is affected by the voltage at both ends of the conductive area Cr to cause leakage, and then the compensation transistor T2 has leakage in the pixel driving circuit 60. The voltage at the first node N1 fluctuates due to the leakage of the compensation transistor T2, and the driving transistor T3 is affected by the voltage of the first node N1 to cause the driving current to fluctuate, resulting in unstable luminous brightness of the light-emitting device, and then the display picture quality of the display panel 100 is reduced.

[0094] Based on this, on one hand, some embodiments of the present invention provide an array substrate 10, such as Fig.10 As shown, the array substrate 10 includes a substrate 40, an active layer 61, a first gate layer 62 and a second gate layer 63. The positions of the film layers of the array substrate 10 are consistent with those in the above embodiment and are not described in detail herein.

[0095] like Fig.11 As shown, the array substrate 10 includes a plurality of pixel driving circuits arranged in an array, and the pixel driving circuit 60 includes at least a compensation transistor T2.

[0096] like Fig.12 As shown, taking the pixel driving circuit of "7T1C" as an example, the active layer includes: the active layer pattern of the first reset transistor is the first active layer pattern AL1, the active layer pattern of the compensation transistor is the second active layer pattern AL2, the active layer pattern of the driving transistor is the third active layer pattern AL3, the active layer pattern of the write transistor is the fourth active layer pattern AL4, the active layer pattern of the first enable transistor is the fifth active layer pattern AL5, the active layer pattern of the second enable transistor is the sixth active layer pattern AL6, and the active layer pattern of the second reset transistor is the seventh active layer pattern AL7.

[0097] The film structure of the compensation transistor T2 is introduced below.

[0098] In some embodiments, Fig.13 As shown, the active layer pattern (second active layer pattern AL2) of the compensation transistor includes two channel regions Sg, and the two channel regions Sg include a first channel region Sg1 and a second channel region Sg2. The active layer pattern of the compensation transistor includes a first pattern 61a and a second pattern 61b connected to each other, the first pattern 61a extends along a first direction X, and the second pattern 61b extends along a second direction Y, the first direction X and the second direction Y intersect, the first channel region Sg1 is located on the first pattern 61a, the second channel region Sg2 is located on the second pattern 61b, and the conductive region Cr is located at the connection position of the first pattern 61a and the second pattern 61b.

[0099] In some examples, the first pattern 61a and the second pattern 61b of the active layer pattern of the compensation transistor form a bent shape, for example, the pattern is "L" shaped, the overlapping position of the first pattern 61a and a first gate signal line XL is the first channel region Sg1, the first gate signal line XL that overlaps with the first pattern 61a also overlaps with the second pattern 61b, and the overlapping position of the second pattern 61b and the first gate signal line XL is the second channel region Sg2. The position where the first pattern 61a and the second pattern 61b are connected is the conductive region Cr, or in other words, the active layer 61 between the first channel region Sg1 and the second channel region Sg2 is the conductive region Cr, and the conductive region Cr does not overlap with the first gate signal line XL or the first electrode Cst1.

[0100] In some embodiments, Fig.14 , Fig.15 and Fig.16 As shown, the first gate signal line XL includes a first gate signal main line 62a and at least one first extension portion 62b connected to the first gate signal main line 62a, the first gate signal main line 62a extends along a first direction X, and the first extension portion 62b extends along a second direction Y. The orthographic projection of the first gate signal main line 62a on the substrate overlaps with the orthographic projection of the second pattern 61b on the substrate, and the orthographic projection of the first extension portion 62b on the substrate overlaps with the orthographic projection of the first pattern 61a on the substrate.

[0101] In some examples, such as Fig.16As shown, the first gate signal line XL may be, for example, a scanning signal line GL, which includes a first gate signal main line 62a extending along a first direction X and a first extension portion 62b extending along a second direction Y. The first gate signal main line 62a passes through the second pattern 61b, and the overlapping portion of the first gate signal main line 62a with the second pattern 61b is the first second gate pattern Cp2a of the dual-gate thin film transistor; the first extension portion 62b passes through the first pattern 61a, and the overlapping portion of the first extension portion 62b with the first pattern 61a is the second second gate pattern Cp2b of the dual-gate thin film transistor.

[0102] In some embodiments, Fig.16 As shown, the orthographic projection of the first gate signal main line 62a on the substrate 40 and the orthographic projection of the first extension portion 62b on the substrate 40 form at least one corner Ar, and the opening of the corner Ar is close to the first electrode plate.

[0103] like Fig.11 , Fig.12 and Fig.16 As shown, the active layer includes an active layer pattern of the compensation transistor T2, that is, the second active layer pattern AL2 in the figure. Figure 4 , Figure 6 ,exist Fig.11 , Fig.12 , the difference between the active layer pattern of the compensation transistor T2 is that the positive projection of the conductive region Cr on the substrate 40 is located on the positive projection side of the positive projection of the first gate signal line XL on the substrate close to the positive projection of the active layer of the driving transistor T3, and is located on the positive projection side of the active layer pattern (fourth active layer pattern AL4) close to the writing transistor T4. That is, the relative position of the conductive region Cr changes, so as to facilitate the setting of the voltage stabilization pattern mentioned below.

[0104] like Fig.17 and Fig.18 As shown, the second gate layer 63 includes a voltage stabilizing pattern 66, which is configured to receive a power supply voltage signal, and the orthographic projection of the voltage stabilizing pattern 66 on the substrate 40 overlaps with the orthographic projection of the conductive region of the active layer pattern of the compensation transistor T2 on the substrate 40. The orthographic projection of the voltage stabilizing pattern 66 on the substrate 40 is located inside the corner Ar.

[0105] In some examples, the voltage stabilizing pattern 66 is located in the second gate layer 63, and the voltage stabilizing pattern 66 overlaps with the conductive area in the active layer 61, which is equivalent to the voltage stabilizing pattern 66 and the conductive area of ​​the active layer pattern of the compensation transistor T2 forming a capacitor. The voltage stabilizing pattern 66 receives the power supply voltage signal, thereby maintaining a stable voltage. The conductive area of ​​the compensation transistor T2 overlapping with the voltage stabilizing pattern 66 is affected by the stable voltage. When affected by external factors, the voltage fluctuation of the conductive area is weakened, and the conductive area can maintain a constant voltage. Accordingly, the voltage change of the two ends of the first channel area and the second channel area connected to the conductive area is weakened. When the second transistor T2 is turned off, a large voltage difference will not be formed between the first electrode and the second electrode, which can reduce the leakage phenomenon of the dual-gate thin film transistor, improve the driving current control quality of the pixel driving circuit 60, and the quality of the display screen of the display panel is correspondingly improved.

[0106] The active layer pattern of the compensation transistor T2 and the structural design of the first gate signal line XL make the compensation transistor T2 a dual-gate transistor, and the voltage stabilizing pattern 66 overlaps with the exposed conductive area and does not interfere with the first gate signal line XL.

[0107] The corner Ar opens toward the second electrode plate Cst2, that is, the first extension portion 62b extends along the second direction Y and is close to the second electrode plate Cst2, so as to expose the conductive area and place the voltage stabilizing pattern 66 electrically connected to the second electrode plate Cst2. By placing the voltage stabilizing pattern 66 in the corner Ar, the overall size of the pixel driving circuit 60 layout can be kept constant, the pixel size of the display panel is not affected, and the picture clarity of the display panel 100 remains unchanged.

[0108] See also Fig.25 A first gate signal line XL includes a first gate signal main line 62a and a plurality of first extensions 62b, and one first extension 62b corresponds to a first pattern 61a of a compensation transistor in a pixel driving circuit.

[0109] It should be noted that Figures 4 to 8 , Figure 12 to Figure 24 The pattern of each film layer is introduced by taking the area where a pixel driving circuit is located (called a pixel unit) as an example. In the display area, multiple sub-pixels are arranged in an array, and multiple pixel driving circuits are also arranged in an array. In each pixel unit, the pattern of each film layer is as follows. Fig. 20 As shown, Fig.11 FIG25 shows a structural diagram of the active layer and the first gate layer of two pixel units, and FIG26 shows a schematic diagram of the film layer structure of two pixel units. It can be seen that the patterns of each film layer are arranged in a periodic regular pattern.

[0110] In some examples, such as Figure 3 or Fig.10As shown, the driving circuit layer 50 further includes a first source-drain metal layer 64 , and the first source-drain metal layer 64 includes a plurality of connection terminals 66 and a plurality of connection patterns 67 .

[0111] In some examples, the array substrate 10 further includes: a first insulating layer 51 disposed between the active layer 61 and the first gate layer 62, a second insulating layer 52 disposed between the first gate layer 62 and the second gate layer 63, a third insulating layer 53 disposed on the side of the second gate layer 63 away from the substrate 40, a first source-drain metal layer 64 disposed on the side of the third insulating layer 53 away from the substrate 40, and a fourth insulating layer 54 disposed on the side of the first source-drain metal layer 64 away from the substrate 40. The first insulating layer 51, the second insulating layer 52, the third insulating layer 53 and the fourth insulating layer 54 insulate the functional layers from each other, a flat layer 55 is further disposed on the side of the fourth insulating layer 54 away from the substrate 40, and a light-emitting device layer 20 is disposed on the side of the flat layer 55 away from the substrate 40.

[0112] In some examples, the array substrate 10 further includes a second source-drain metal layer 65 disposed on a side of the fourth insulating layer 54 away from the substrate 40 , and the second source-drain metal layer 65 includes a data line and a power supply voltage signal line.

[0113] In some embodiments, Fig. 9 and Fig.19 As shown, the active layer patterns of some transistors of the pixel driving circuit 60 are electrically connected to the signal lines of the first gate layer 62 and / or the second gate layer 63, the first electrode plate Cst1, and the second electrode plate Cst2 through the connection pattern 67. The active layer patterns of some transistors of the pixel driving circuit 60 are electrically connected to the data line or the power supply voltage signal line through the connection terminal 68.

[0114] In some embodiments, the pixel driving circuit 60 further includes a write transistor T4, a first electrode of the write transistor T4 is electrically connected to a data signal terminal (data line), and a first electrode plate Cst1 is electrically connected to a second electrode of the compensation transistor T2; wherein the first electrode of the write transistor T4 is connected to the data line via a connection terminal 68, and the first electrode plate Cst1 is connected to the second electrode of the compensation transistor T2 via a connection pattern 67. The connection pattern 67 includes a first connection pattern 67a, and the first connection pattern 67a is used to connect the first electrode plate Cst1 and the second electrode of the compensation transistor T2; the connection terminal 68 includes a first connection terminal 68a, and the first connection terminal 68a is used to connect the first electrode of the write transistor T4 to the data line. wherein the first source-drain metal layer 64 includes a first connection terminal 68a and a first connection pattern 67a.

[0115] Among them, Fig.19 and Fig. 20 As shown, Fig. 20 yes Fig.19In the cross-sectional view of the pixel driving circuit 60 shown in the AA direction, the first connection terminal 68a is connected to the active layer 61 through a via hole penetrating the first insulating layer 51, the second insulating layer 52 and the third insulating layer 53. For example, the active layer 61 includes an active layer pattern of the write transistor T4, and the first connection terminal 68a is connected to the active layer pattern of the write transistor T4. Specifically, the first connection terminal 68a is connected to the active layer pattern of the write transistor T4 through a via hole penetrating the first insulating layer 51, the second insulating layer 52 and the third insulating layer 53.

[0116] The first connection pattern 67a includes a first end O1, a first connection line L1, and a second end O2 connected in sequence. The first end O1 of the first connection pattern 67a is connected to the active layer pattern of the compensation transistor T2, and the second end O2 of the first connection pattern 67a is connected to the first electrode plate Cst1 of the capacitor. Specifically, the first end O1 is connected to the active layer 61 through a via hole penetrating the first insulating layer 51, the second insulating layer 52, and the third insulating layer 53. For example, the first end O1 is connected to the active layer pattern of the compensation transistor T2 through a via hole penetrating the first insulating layer 51, the second insulating layer 52, and the third insulating layer 53, and the second end O2 is connected to the first electrode plate Cst1 through a via hole penetrating the second insulating layer 52 and the third insulating layer 53. The first end O1 and the second end O2 are electrically connected through the first connection line L1 located at the first source-drain metal layer.

[0117] In some embodiments, Fig.19 and Fig. 20 As shown, in the layout of the pixel driving circuit 60, the first connection terminal 68a is located at one side of the first terminal O1. In the array-arranged pixel driving circuit 60, the first connection terminal 68a and the first terminal O1 are arranged at intervals in a certain direction.

[0118] The first connection terminal 68a is configured to receive a signal from the data line. The voltage of the first connection terminal 68a varies with the signal waveform transmitted by the data line. An electric field is formed at the first connection terminal 68a to affect the first terminal O1. Specifically, the first terminal O1 is electrically connected to the first electrode plate Cst1 of the capacitor. The first terminal O1 is affected by the electric field and generates voltage fluctuations. Accordingly, the voltage of the first electrode plate Cst1 changes accordingly, and then the potential storage function of the capacitor is affected, and the capacitor exhibits leakage.

[0119] The first connection pattern 67a is a junction of the active layer pattern of the compensation transistor T2, the active layer pattern of the driving transistor T3 and the first electrode plate Cst1. Fig. 9In other words, the voltage of the first terminal O1 is the voltage of the first node N1. If the voltage of the first node N1 fluctuates, the driving current of the driving transistor T3 fluctuates, and the light emitting brightness of the light emitting device EL connected to the pixel driving circuit 60 is unstable, resulting in color distortion of the display screen of the display panel 100 and degradation of the quality of the display screen.

[0120] Based on this, the second gate layer 63 of the array substrate 100 proposed in the embodiment of the present invention is as follows: Fig.21 and Fig. 22 As shown, in addition to the voltage stabilizing pattern 66, at least one shielding pattern 69 is included. The orthographic projection of the shielding pattern 69 on the substrate is located between the adjacent first connecting end 68a and the first end O1 of the first connecting pattern 67a. The shielding pattern 69 is configured to receive a constant voltage signal.

[0121] In some examples, the shielding pattern 69 isolates the electric field generated by the first connection terminal 68a from the first terminal O1. In the array-arranged pixel driving circuit 60, a shielding pattern 69 is provided between each first connection terminal 68a and the first terminal O1, so that the orthographic projection of the first terminal O1 on the substrate is located between the orthographic projections of the two shielding patterns 69 on the substrate.

[0122] The shielding pattern 69 isolates the influence of the external electric field on the first end O1, thereby improving the voltage stability of the first end O1. That is, the voltage of the first node N1 is stable, the light emitting device corresponding to the first node N1 has stable light brightness, the display panel has high color fidelity, and the display image quality is high.

[0123] In some embodiments, Fig.21 and Fig. 22 As shown, the second gate layer 63 further includes an initialization signal line, and the shielding pattern 69 is connected to the initialization signal line.

[0124] Exemplarily, the initialization signal line transmits an initialization signal, and the initialization signal is a constant voltage signal. The shielding pattern 69 is connected to the initialization signal line to provide a stable voltage. At the same time, the initialization signal line and the shielding pattern 69 are both in the second gate layer 63, that is, the shielding pattern 69 is between the first end O1 of the via that passes through the first insulating layer, the second insulating layer and the third insulating layer, which is beneficial for the shielding pattern 69 to produce a better electric field shielding effect on the first end O1.

[0125] In some embodiments, Fig.21 and Fig. 22 As shown, the initialization signal line includes a first initialization signal line Vinit1 , and the first initialization signal line Vinit1 is connected to the shielding pattern 69 .

[0126] Exemplarily, in the layout of the pixel driving circuit 60 , the initialization signal line includes a first initialization signal line Vinit1 , and the first end O1 is close to the first initialization signal line Vinit1 , so the shielding pattern 69 is connected to the first initialization signal line Vinit1 .

[0127] In some embodiments, Fig. 22 As shown, the pixel driving circuit 60 further includes a first reset transistor T1 , the active layer 61 includes an active layer pattern of the first reset transistor T1 , and the first initialization signal line Vinit1 is electrically connected to the active layer pattern of the first reset transistor T1 .

[0128] For example, Fig.23 As shown, the connection pattern 67 also includes a second connection pattern 67b, and the second connection pattern 67b includes a third terminal O3, a fourth terminal O4 and a second connection line L2, wherein the third terminal O3 passes through a via hole of the third insulating layer to be connected to the first initialization signal line, and the fourth terminal O4 passes through a via hole of the first insulating layer, the second insulating layer and the third insulating layer to be connected to the active layer pattern of the first reset transistor, and the third terminal O3 and the fourth terminal O4 are electrically connected by the second connection line L2 located in the first source-drain metal layer 64.

[0129] In some embodiments, Fig.24 As shown, the second source-drain metal layer 65 includes a power voltage signal line VDD and a data line DL. Exemplarily, a plurality of power voltage signal lines VDD and a plurality of data lines DL are arranged alternately, and each pixel driving circuit 60 passes through a power voltage signal line VDD and a data line DL.

[0130] The data line DL is connected to the first connection end 68 a . For example, the first connection end 68 a is electrically connected to the data line DL through a via hole penetrating the fourth insulating layer.

[0131] In some embodiments, Fig. 22 , Fig.23 and Fig.24 As shown, the pixel driving circuit 60 also includes a first enabling transistor T5, the active layer 61 includes an active layer pattern of the first enabling transistor T5, the fifth end O5 of the third connection pattern 67c is connected to the second electrode plate Cst2 through a via hole penetrating the third insulating layer, and the sixth end O6 is connected to the active layer pattern of the first enabling transistor T5 through a via hole penetrating the first insulating layer, the second insulating layer and the third insulating layer.

[0132] Exemplarily, the fifth terminal O5 is connected to the second electrode Cst2 through a via penetrating the third insulating layer, and the sixth terminal O6 is connected to the power supply voltage signal line VDD and electrically connected to the active layer pattern of the first enabling transistor T5, thereby connecting the active layer pattern of the first enabling transistor T5 to the power supply voltage signal line VDD.

[0133] In some embodiments, Fig. 22 As shown, the pixel driving circuit 60 further includes a second enabling transistor T6, and the active layer 61 includes an active layer pattern of the second enabling transistor T6. The first gate layer 62 further includes an enabling signal line EM, and the orthographic projection of the enabling signal line EM on the substrate overlaps with the orthographic projection of the active layer pattern of the first enabling transistor T5 on the substrate and the orthographic projection of the active layer pattern of the second enabling transistor T6 on the substrate.

[0134] In some examples, the enable signal line EM passes through the active layer pattern of the first enable transistor T5, wherein the overlapped position of the enable signal line EM and the active layer pattern of the first enable transistor T5 is the gate pattern of the first enable transistor T5. The enable signal line EM passes through the active layer pattern of the second enable transistor T6, wherein the overlapped position of the enable signal line EM and the active layer pattern of the second enable transistor T6 is the gate pattern of the second enable transistor T6.

[0135] In some embodiments, Fig. 22 As shown, the pixel driving circuit 60 further includes a second reset transistor T7, and the active layer 61 includes an active layer pattern of the second reset transistor T7. The initialization signal line further includes a second initialization signal line Vinit2, and the second initialization signal line Vinit2 is electrically connected to the active layer pattern of the second reset transistor T7.

[0136] In some examples, such as Fig. 22 and Fig.23 As shown, the connection pattern 67 further includes a fourth connection pattern 67d, and the fourth connection pattern 67d includes a seventh terminal O7, an eighth terminal O8 and a fourth connection line L4. The seventh terminal O7 passes through a via hole of the third insulating layer and is connected to the second initialization signal line, and the eighth terminal O8 passes through a via hole of the first insulating layer, the second insulating layer and the third insulating layer and is connected to the active layer pattern of the second reset transistor T7.

[0137] In some embodiments, Fig. 22 As shown, the first gate layer 62 further includes a first reset signal line Rst1 and a second reset signal line Rst2. The orthographic projection of the first reset signal line Rst1 on the substrate overlaps with the orthographic projection of the active layer pattern of the first reset transistor T1 on the substrate. The orthographic projection of the second reset signal line Rst2 on the substrate overlaps with the orthographic projection of the active layer pattern of the second reset transistor T2 on the substrate.

[0138] In some examples, the first reset signal line Rst1 passes through the first reset transistor T1, and the overlap position of the first reset signal line Rst1 and the active layer pattern of the first reset transistor T1 is the gate pattern of the first reset transistor T1. The second reset signal line Rst2 passes through the second reset transistor T2, and the overlap position of the second reset signal line Rst2 and the active layer pattern of the second reset transistor T2 is the gate pattern of the second reset transistor T2.

[0139] It should be noted that the first reset signal line Rst1 and the second reset signal line Rst2 are relative to the layout of a pixel driving circuit 60. Specifically, in two adjacent pixel driving circuits 60 in the column direction, the second reset signal line Rst2 of one pixel driving circuit 60 is the first reset signal line Rst1 of the other adjacent pixel driving circuit 60.

[0140] In some embodiments, Fig. 22 As shown, the pixel driving circuit 60 further includes a driving transistor T3, the active layer 61 includes an active layer pattern of the driving transistor T3, and the orthographic projection of the active layer pattern of the driving transistor T3 on the substrate overlaps with the orthographic projection of the first electrode plate Cst1 on the substrate.

[0141] In some examples, the first electrode plate Cst1 passes through the active layer pattern of the driving transistor T3, and the overlapping position of the first electrode plate Cst1 and the active layer pattern of the driving transistor T3 is the gate pattern of the driving transistor T3. The first electrode plate Cst1 is connected to the second end, and the orthographic projection of the second electrode plate Cst2 on the substrate overlaps with the orthographic projection of the first electrode plate Cst1 on the substrate, so the second electrode plate Cst2 is provided with a through hole for the second end to pass through.

[0142] On the other hand, Fig.10 As shown, some embodiments of the present invention provide a display panel 100 , and the display panel 100 includes: an array substrate 10 according to any one of the embodiments in the above aspect.

[0143] The array substrate 10 has the function of stabilizing the voltage of the conductive area of ​​the compensation transistor T2 and the voltage at the first node N1. The display panel 100 using the array substrate 10 has the same function as the above array substrate 10. Accordingly, the display panel 100 can significantly improve the display image quality.

[0144] In some embodiments, the display panel 100 further includes: an anode layer 21 disposed on the array substrate 10, a light emitting layer 22 disposed on a side of the anode layer 21 away from the substrate 40, a cathode layer 23 disposed on a side of the light emitting layer 22 away from the substrate 40, and an encapsulation layer 30 disposed on a side of the cathode layer 23 away from the substrate 40. The anode layer 21 includes a plurality of anodes 21a.

[0145] In some examples, an anode layer 21 is provided on the array substrate 10, and the anode layer 21 includes a plurality of anodes 21a, and each pixel driving circuit 60 is electrically connected to an anode 21a. A light-emitting layer 22 and a cathode layer 23 are sequentially provided on the side of the anode layer 21 away from the array substrate 10, and the anode layer 21, the light-emitting layer 22 and the cathode layer 23 are the light-emitting device layer 20. The light-emitting device layer 20 is provided with an encapsulation layer 30 away from the array substrate 10, and the encapsulation layer 30 is used to protect the light-emitting device layer 20 and prevent water and oxygen corrosion of the light-emitting device layer 20 by the external environment.

[0146] In yet another aspect, some embodiments of the present invention provide a display device, comprising the display panel provided by any one of the embodiments in the above-mentioned other aspect.

[0147] The display device of the present invention has the same beneficial effects as the above-mentioned display panel, which will not be described in detail here.

[0148] The display device provided by the embodiments of the present invention can be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0149] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: The invention comprises a plurality of pixel driving circuits arranged in an array, wherein the pixel driving circuits at least comprise a compensation transistor; and the array substrate comprises: substrate; an active layer disposed on one side of the substrate, the active layer comprising an active layer pattern of the compensation transistor, the active layer pattern of the compensation transistor comprising two channel regions and a conductive region located between the two channel regions; A first gate layer disposed on a side of the active layer away from the substrate, the first gate layer comprising a first gate signal line, an orthographic projection of the first gate signal line on the substrate overlapping with an orthographic projection of the two channel regions on the substrate; A second gate layer is disposed on a side of the first gate layer away from the substrate, the second gate layer includes a voltage stabilizing pattern, the voltage stabilizing pattern is configured to receive a power supply voltage signal, and an orthographic projection of the voltage stabilizing pattern on the substrate overlaps with an orthographic projection of the conductive area on the substrate.

2. The array substrate according to claim 1, characterized in that: The two channel regions include a first channel region and a second channel region; The active layer pattern of the compensation transistor includes a first pattern and a second pattern connected to each other, the first pattern extends along a first direction, the second pattern extends along a second direction, the first direction and the second direction intersect, the first channel region is located on the first pattern, the second channel region is located on the second pattern, and the conductive region is located at a connection position between the first pattern and the second pattern; The first gate signal line includes a first gate signal main line and at least one first extension portion connected to the first gate signal main line, the first gate signal main line extends along the first direction, and the first extension portion extends along the second direction; the orthographic projection of the first gate signal main line on the substrate overlaps with the orthographic projection of the second pattern on the substrate, and the orthographic projection of the first extension portion on the substrate overlaps with the orthographic projection of the first pattern on the substrate.

3. The array substrate according to claim 2, characterized in that: The pixel driving circuit further includes a capacitor; The first gate layer also includes a first plate of the capacitor; The second gate layer further includes a second plate of the capacitor, wherein an orthographic projection of the second plate on the substrate overlaps an orthographic projection of the first plate on the substrate; The voltage stabilizing pattern is connected to the second electrode plate, and the voltage stabilizing pattern is located on a side of the second electrode plate close to the first gate signal line.

4. The array substrate according to claim 3, characterized in that: The orthographic projection of the first gate signal main line on the substrate and the orthographic projection of the first extension portion on the substrate form at least one corner, and the orthographic projection of the voltage stabilizing pattern on the substrate is located inside the corner.

5. The array substrate according to claim 4, characterized in that: The array substrate further includes: a first insulating layer disposed between the active layer and the first gate layer; a second insulating layer disposed between the first gate layer and the second gate layer; A third insulating layer disposed on a side of the second gate layer away from the substrate; a first source-drain metal layer disposed on a side of the third insulating layer away from the substrate; the first source-drain metal layer comprises a first connection end and a first connection pattern, the first connection end is connected to the active layer through a via hole penetrating the first insulating layer, the second insulating layer and the third insulating layer; the first connection pattern comprises a first end, a first connection line and a second end connected in sequence, the first end is connected to the active layer through a via hole penetrating the first insulating layer, the second insulating layer and the third insulating layer; The second gate layer further includes at least one shielding pattern, the orthographic projection of the shielding pattern on the substrate is located between the adjacent first connecting ends and the first end of the connecting pattern; the shielding pattern is configured to receive a constant voltage signal.

6. The array substrate according to claim 5, characterized in that: The pixel driving circuit further includes a write transistor, the active layer includes an active layer pattern of the write transistor, and the first connection terminal is connected to the active layer pattern of the write transistor; A first end of the first connection pattern is connected to the active layer pattern of the compensation transistor, and a second end of the first connection pattern is connected to the first plate of the capacitor.

7. The array substrate according to claim 5 or 6, characterized in that: The second gate layer further includes an initialization signal line, and the shielding pattern is connected to the initialization signal line.

8. The array substrate according to claim 7, characterized in that: The initialization signal line includes a first initialization signal line, and the first initialization signal line is connected to the shielding pattern; The pixel driving circuit further includes a first reset transistor, the active layer includes an active layer pattern of the first reset transistor, and the first initialization signal line is electrically connected to the active layer pattern of the first reset transistor.

9. The array substrate according to claim 8, characterized in that: The array substrate further comprises: a fourth insulating layer disposed on a side of the first source-drain metal layer away from the substrate; A second source-drain metal layer is disposed on a side of the fourth insulating layer away from the substrate, the second source-drain metal layer comprising a data line and a power supply voltage signal line; The data line is connected to the first connection end.

10. The array substrate according to claim 9, characterized in that: The first source-drain metal layer further includes a plurality of second connection patterns, the second connection pattern includes a third end, a second connection line and a fourth end connected in sequence, the third end is connected to the second plate of the capacitor through a via hole penetrating the third insulating layer; the fourth end is connected to the power supply voltage signal line through a via hole penetrating the fourth insulating layer; The pixel driving circuit also includes a first enabling transistor, the active layer includes an active layer pattern of the first enabling transistor, and the fourth end of the second connecting pattern is connected to the active layer pattern of the first enabling transistor through the via hole that passes through the first insulating layer, the second insulating layer and the third insulating layer.

11. The array substrate according to claim 10, characterized in that: The pixel driving circuit further includes a second enabling transistor, and the active layer includes an active layer pattern of the second enabling transistor; The first gate layer further includes an enable signal line, and an orthographic projection of the enable signal line on the substrate overlaps with an orthographic projection of the active layer pattern of the first enable transistor on the substrate and an orthographic projection of the active layer pattern of the second enable transistor on the substrate.

12. The array substrate according to claim 11, characterized in that: The pixel driving circuit further includes a second reset transistor, and the active layer includes an active layer pattern of the second reset transistor; The initialization signal line further includes a second initialization signal line connected to the active layer pattern of the second reset transistor.

13. The array substrate according to claim 12, characterized in that: The first gate layer also includes a first reset signal line and a second reset signal line; The orthographic projection of the first reset signal line on the substrate overlaps with the orthographic projection of the active layer pattern of the first reset transistor on the substrate; An orthographic projection of the second reset signal line on the substrate overlaps with an orthographic projection of the active layer pattern of the second reset transistor on the substrate.

14. The array substrate according to claim 12 or 13, characterized in that: The pixel driving circuit further includes a driving transistor, the active layer includes an active layer pattern of the driving transistor, and an orthographic projection of the active layer pattern of the driving transistor on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate.

15. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 14.

16. The display panel according to claim 15, characterized in that: The display panel further includes: An anode layer disposed on the array substrate, the anode layer comprising a plurality of anodes; A light-emitting layer disposed on a side of the anode layer away from the substrate; A cathode layer disposed on a side of the light-emitting layer away from the substrate; The encapsulation layer is arranged on a side of the cathode layer away from the substrate.

17. A display device, characterized in that: include: The display panel according to claim 15 or 16.

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