Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel comprises a normal display area and a fan-out display area, and the fan-out display area comprises a first area and a second area. The pixel driving circuit units of the display panel are located in the normal display area and the first area, and the fan-out wiring is located in the second area. The density of the pixel driving circuit units located in the first area is greater than the density of the pixel driving circuit units located in the normal display area, and the pixel driving circuit units are electrically connected to the corresponding anodes through the connecting wiring in the connecting wiring layer. By arranging a shielding layer on a side of the pixel definition layer away from the base substrate, the plurality of second openings of the shielding layer are arranged corresponding to the plurality of first openings of the pixel definition layer, so that the light reflected from the metal wiring can be shielded, which is beneficial to improving the visibility mura phenomenon in the off-screen and on-screen states.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of OLED panel technology, narrow border technology has become a differentiated technology to attract user groups. FIAA (Fanout in AA, fan-out routing is located in the display area) technology is a new layout method that can effectively reduce the bottom border of the panel. In FIAA technology, a multi-layer connection routing design is introduced to squeeze out wiring space for the fan-out routing. However, during the connection routing routing process, due to the limitation of the wiring space, it is easy to cause the metal routing density of the fan-out display area to be different from that of the normal display area. The different density can easily lead to uneven light reflection from the metal routing, resulting in visual display unevenness (mura) in the fan-out display area and the normal display area when the screen is off and on. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device to solve the technical problem that in existing display panels and display devices, there is a difference in metal wiring density in a fan-out display area and a metal wiring density in a normal display area, resulting in visible display mura phenomenon in the fan-out display area and the normal display area.

[0004] To solve the above problems, the technical solution provided by the present invention is as follows:

[0005] The present invention provides a display panel, comprising a normal display area and a fan-out display area, wherein the fan-out display area is located on one side of the normal display area, and the fan-out display area comprises a first area and a second area sequentially arranged in a direction from the normal display area to the fan-out display area; the display panel comprises:

[0006] substrate substrate;

[0007] A driving circuit layer, arranged on one side of the base substrate, the driving circuit layer comprising a plurality of pixel driving circuit units and a plurality of fan-out wirings, the pixel driving circuit units being located in the normal display area and the first area, the fan-out wirings being located in the second area, wherein the density of the pixel driving circuit units located in the first area is greater than the density of the pixel driving circuit units located in the normal display area;

[0008] At least one connection wiring layer is arranged on a side of the driving circuit layer away from the base substrate, and each of the connection wiring layers includes a plurality of connection wirings;

[0009] A plurality of anodes are arranged on a side of the connection wiring layer away from the base substrate, and the pixel driving circuit unit is electrically connected to the corresponding anodes through the connection wiring;

[0010] A pixel definition layer is disposed on a side of the connection wiring layer away from the base substrate, the pixel definition layer comprises a plurality of first openings, and the first openings expose at least a portion of the anode; and

[0011] A light-emitting layer is disposed in the first opening;

[0012] The display panel further includes a shielding layer, which is disposed on a side of the pixel definition layer away from the base substrate, and the shielding layer includes a plurality of second openings, which are disposed corresponding to the first openings.

[0013] According to the display panel provided by the present invention, the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0014] According to the display panel provided by the present invention, the ratio of the orthographic projection area of ​​the second opening on the base substrate to the orthographic projection area of ​​the first opening on the base substrate is in a range of 1 to 1.5.

[0015] According to the display panel provided by the present invention, the orthographic projection of the first opening on the base substrate covers the orthographic projection of the second opening on the base substrate.

[0016] According to the display panel provided by the present invention, the ratio of the orthographic projection area of ​​the second opening on the base substrate to the orthographic projection area of ​​the first opening on the base substrate is in the range of 0.8-1.

[0017] According to the display panel provided by the present invention, the light-emitting layer covers the sidewalls and the bottom of the second opening.

[0018] According to the display panel provided by the present invention, the thickness of the shielding layer along the direction perpendicular to the base substrate is 1 micrometer to 1.5 micrometers.

[0019] According to the display panel provided by the present invention, the material of the shielding layer includes a black matrix.

[0020] According to the display panel provided by the present invention, the display panel further includes a cathode, and the shielding layer is arranged between the cathode and the pixel definition layer.

[0021] According to the display panel provided by the present invention, at least one of the connection wiring layers includes a first connection wiring layer and a second connection wiring layer, and the display panel further includes a first flat layer, a second flat layer and a third flat layer stacked in sequence in a direction away from the base substrate;

[0022] The first flat layer covers a side of the driving circuit layer away from the base substrate, the first connecting wiring layer is arranged between the first flat layer and the second flat layer, and the second connecting wiring layer is arranged between the second flat layer and the third flat layer;

[0023] The driving circuit layer is electrically connected to the connecting wiring in the first connecting wiring layer through a via hole penetrating the first flat layer, the first connecting wiring layer is electrically connected to the connecting wiring in the second connecting wiring layer through a via hole penetrating the second flat layer, and the second connecting wiring layer is electrically connected to the anode through a via hole penetrating the third flat layer.

[0024] The present invention provides a display device, comprising the above-mentioned display panel.

[0025] The beneficial effects of the present invention are as follows: the display panel and the display device provided by the present invention, by setting a shielding layer on the side of the pixel definition layer away from the base substrate, the multiple second openings of the shielding layer are set corresponding to the first opening of the pixel definition layer, and the shielding layer can be used to block the light reflected by the metal wiring, so that the light reflected from the metal wiring in the fan-out display area and the normal display area is more uniform, which is beneficial to improving the visible mura phenomenon in the fan-out display area and the normal display area due to the difference in metal wiring density between the fan-out display area and the normal display area in the screen-off and screen-on states. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0028] Figure 2 yes Figure 1 A schematic diagram of a first cross-sectional structure of a display panel along AA;

[0029] Figure 3 yes Figure 2 A partial top view structural diagram of a first opening and a second opening in a display panel;

[0030] Figure 4 yes Figure 1 A schematic diagram of a second cross-sectional structure of a display panel along AA;

[0031] Figure 5 yes Figure 4 A partial top view structural diagram of a first opening and a second opening in a display panel;

[0032] Figure 6 yes Figure 1 A schematic diagram of a third cross-sectional structure of a display panel along AA;

[0033] Figure 7 yes Figure 6 A partial top view structural diagram of a first opening and a second opening in a display panel;

[0034] Figure 8 yes Figure 1 A schematic diagram of a fourth cross-sectional structure of a display panel along AA;

[0035] Fig. 9 yes Figure 8 A partial top view structural diagram of a first opening and a second opening in a display panel;

[0036] Fig.10 yes Figure 1 Schematic diagram of the fifth cross-sectional structure of the display panel along AA.

[0037] Description of reference numerals:

[0038] 100a, normal display area; 100b, fan-out display area; 1001b, first area; 1002b, second area;

[0039] 101, substrate; 102, barrier layer; 103, buffer layer; 104, drive circuit layer; 105, first flat layer; 106, first connection wiring layer; 107, second flat layer; 108, second connection wiring layer; 1081, connection wiring; 109, third flat layer; 110, anode; 111, pixel definition layer; 112, shielding layer; 113, light-emitting layer; 114, cathode; 115, pixel unit;

[0040] 104a, pixel driving circuit unit; 104b, fan-out wiring; 1041, active layer; 1042, first gate insulating layer; 1043, first gate layer; 1044, second gate insulating layer; 1045, second gate layer; 1046, first interlayer dielectric layer; 1047, second interlayer dielectric layer; 1048, first source and drain metal layer; 1049, fourth planar layer; 1050, second source and drain metal layer;

[0041] V1, first opening; V2, second opening. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0043] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention; Figure 2 1 is a schematic diagram of a first cross-sectional structure of a display panel provided by an embodiment of the present invention. The display panel provided by an embodiment of the present invention comprises a normal display area 100a and a fan-out display area 100b, wherein the fan-out display area 100b is arranged on one side of the normal display area 100a, and the fan-out display area 100b comprises a first area 1001b and a second area 1002b arranged in sequence along a direction from the normal display area 100a to the fan-out display area 100b; the display panel comprises a base substrate 101, a driving circuit layer 104, a connection wiring layer, a plurality of anodes 110, a pixel definition layer 111 and a light-emitting layer 113.

[0044] The fan-out display area 100b is disposed adjacent to the normal display area 100a. The fan-out display area 100b may be disposed at an edge of the display panel. Furthermore, in an embodiment of the present invention, the fan-out display area 100b is disposed at a lower edge of the display panel.

[0045] The driving circuit layer 104 is arranged on one side of the base substrate 101, and the driving circuit layer 104 includes a plurality of pixel driving circuit units 104a and a plurality of fan-out wirings 104b. The pixel driving circuit unit 104a is located in the normal display area 100a and the first area 1001b, and the fan-out wiring 104b is located in the second area 1002b. At least one layer of the connecting wiring layer is arranged on the side of the driving circuit layer 104 away from the base substrate 101, and each layer of the connecting wiring layer includes a plurality of connecting wirings 1081. A plurality of anodes 110 are arranged on the side of the connecting wiring layer located at the top layer away from the base substrate 101, and the pixel driving circuit unit 104a is electrically connected to the corresponding anode 110 through the connecting wiring 1081. The pixel definition layer 111 is arranged on the side of the connecting wiring layer away from the base substrate 101, and the pixel definition layer 111 includes a plurality of first openings V1, and the first openings V1 expose at least part of the anode 110. The light emitting layer 113 is disposed in the first opening V1 .

[0046] The display panel further includes a shielding layer 112 , which is disposed on a side of the pixel definition layer 111 away from the base substrate 101 . The shielding layer 112 includes a plurality of second openings V2 , which are disposed corresponding to the first openings V1 .

[0047] It can be understood that the distance between two adjacent light-emitting pixels in the display area of ​​the display panel in the prior art is equal, that is, the pixel density at each location in the display area is equal. Since each light-emitting pixel is electrically connected to the corresponding pixel driving circuit unit 104a, the density of the pixel driving circuit unit 104a at each location in the display area of ​​the display panel in the prior art is equal, and the distance between two adjacent pixel driving circuit units 104a is equal.

[0048] The display panel of the present application includes a normal display area 100a and a fan-out display area 100b. The position of each luminous pixel in the fan-out display area 100b and the distance between two adjacent luminous pixels are consistent with those in the normal display area 100a, that is, the pixel density of the fan-out display area 100b is the same as the pixel density of the normal display area 100a. The difference between the present invention and the prior art lies in that the pixel driving circuit unit 104a located in the fan-out display area 100b is electrically connected to the corresponding anode 110 through the connecting wiring 1081 to drive the corresponding light-emitting pixel located in the fan-out display area 100b to emit light. The setting of the connecting wiring layer can concentrate all the pixel driving circuit units 104a in the fan-out display area 100b in the first area 1001b of the fan-out display area 100b without changing the original position of the light-emitting pixel in the fan-out display area 100b, while the second area 1002b is not provided with any pixel driving circuit unit 104a. Therefore, the second area 1002b can be used to place the fan-out wiring 104b. Compared with the prior art in which the fan-out wiring 104b is set in the non-display area of ​​the display panel, since the fan-out wiring 104b in the present invention can be placed in the display area, the area of ​​the display area is increased and the area of ​​the non-display area is reduced, which is conducive to further realizing narrow frame and full-screen technology.

[0049] Specifically, the overall space occupied by all the pixel driving circuit units 104a in the fan-out display area 100b can be reduced by compressing the distance between two adjacent pixel driving circuit units 104a in the fan-out display area 100b, or by reducing the size of the pixel driving circuit unit 104a in the fan-out display area 100b, so that in the fan-out display area 100b, the driving circuit layer 104 can squeeze out part of the space for placing the fan-out wiring 104b. Of course, other methods can also be used, and the present invention is not limited to this.

[0050] It can be seen from the above that since the pixel driving circuit units 104a in the fan-out display area 100b in the present application are all concentrated in the first area 1001b of the fan-out display area 100b, the density of the pixel driving circuit units 104a located in the first area 1001b is greater than the density of the pixel driving circuit units 104a located in the normal display area 100a, and since the pixel driving circuit unit 104a includes multiple metal wirings, the metal wiring density of the first area 1001b is greater than the metal wiring density of the normal display area 100a.

[0051] Furthermore, first, since the fan-out wiring 104b is arranged in the second area 1002b of the fan-out display area 100b, the fan-out wiring 104b is a metal wiring and is a metal wiring newly introduced into the fan-out display area 100b; second, due to the limitation of the arrangement space, the density of the connecting wiring 1081 in the fan-out display area 100b is greater than the density of the connecting wiring 1081 in the normal display area 100a, and the connecting wiring 1081 is a transparent metal wiring. Therefore, the metal wiring density of the fan-out display area 100b in the present invention is greater than the metal wiring density of the normal display area 100a, and the difference in metal wiring density is likely to cause visible mura phenomenon in the fan-out display area 100b and the normal display area 100a.

[0052] In view of this, the present invention sets the shielding layer 112 on the side of the pixel definition layer 111 away from the base substrate 101, and the multiple second openings V2 of the shielding layer 112 are set corresponding to the first opening V1 of the pixel definition layer 111. The shielding layer 112 can be used to block the light reflected by the metal wiring, so that the light reflected from the metal wiring in the fan-out display area 100b and the normal display area 100a is more uniform, which is beneficial to improve the visible mura phenomenon in the fan-out display area 100b and the normal display area 100a due to the difference in metal wiring density between the fan-out display area 100b and the normal display area 100a in the screen-off and screen-on states.

[0053] In the embodiment of the present invention, the display area of ​​the display panel is composed of the normal display area 100a and the fan-out display area 100b, both of which have display functions, and the fan-out wiring 104b is arranged in the fan-out display area 100b. The display panel also includes a non-display area (not shown in the figure), and the fan-out display area 100b is arranged on one side of the normal display area 100a. Specifically, the fan-out display area 100b is arranged between the normal display area 100a and the non-display area.

[0054] Furthermore, the display panel also includes a driving chip, and the driving chip can also be arranged in the fan-out display area 100b. In this case, the non-display area can be omitted, so the display panel can achieve borderless and full-screen.

[0055] In the embodiment of the present invention, the substrate 101 is a flexible substrate, which is generally an organic polymer material such as polyimide and polyethylene terephthalate.

[0056] In the embodiment of the present invention, a barrier layer 102 and a buffer layer 103 are disposed between the base substrate 101 and the driving circuit layer 104, and are stacked in sequence in a direction away from the base substrate 101. The barrier layer 102 is used to block water and oxygen to prevent external water vapor or oxygen from corroding the display panel. The material used for the barrier layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and amorphous silicon. The buffer layer 103 mainly plays a role of buffering and protection. The material used for the buffer layer 103 includes one or both of silicon nitride and silicon oxide.

[0057] The pixel driving circuit unit 104a includes a plurality of thin film transistors. In the embodiment of the present invention, the thin film transistor may be a thin film transistor with a dual gate structure. Specifically, the thin film transistor includes an active layer 1041, a first gate insulating layer 1042, a first gate layer 1043, a second gate insulating layer 1044, a second gate layer 1045, a first interlayer dielectric layer 1046, a second interlayer dielectric layer 1047 and a first source-drain metal layer 1048, which are sequentially arranged in a direction away from the base substrate 101. The first source-drain metal layer 1048 is electrically connected to the active layer 1041 through vias penetrating the second interlayer dielectric layer 1047, the first interlayer dielectric layer 1046, the second gate insulating layer 1044 and the first gate insulating layer 1042. Of course, in some embodiments, the thin film transistor may also be a thin film transistor having only one gate layer. In addition, the thin film transistor may also be a top gate or bottom gate structure, which is not limited by the present invention.

[0058] In an embodiment of the present invention, the anode 110 may adopt a stacked structure of ITO (Indium tin oxide) / Ag (silver) / ITO, wherein ITO has good water-blocking properties, which can prevent water vapor or oxygen from diffusing through the anode 110 to the light-emitting layer 113, thereby preventing the light-emitting layer 113 from being corroded by water vapor or oxygen and causing black spots to appear on the display panel, thereby improving the display effect of the display panel.

[0059] It should be noted that the pixel definition layer 111 defines a plurality of first openings V1, and the first openings V1 are pixel openings. In an embodiment of the present invention, the first openings V1 refer to effective light-emitting pixel openings, and the orthographic projection area of ​​the first openings V1 on the base substrate 101 is the orthographic projection area of ​​the light-emitting layer 113 on the base substrate 101.

[0060] In the embodiment of the present invention, at least one layer of the connection wiring layer includes two layers of connection wiring layers, specifically including a first connection wiring layer 106 and a second connection wiring layer 108, and the display panel further includes a first flat layer 105, a second flat layer 107 and a third flat layer 109 which are sequentially stacked in a direction away from the base substrate 101. The first flat layer 105 covers a side of the driving circuit layer 104 away from the base substrate 101, the first connection wiring layer 106 is arranged between the first flat layer 105 and the second flat layer 107, and the second connection wiring layer 108 is arranged between the second flat layer 107 and the third flat layer 109. The driving circuit layer 104 is electrically connected to the connecting wiring 1081 in the first connecting wiring layer 106 through a via hole penetrating the first flat layer 105, the first connecting wiring layer 106 is electrically connected to the connecting wiring 1081 in the second connecting wiring layer 108 through a via hole penetrating the second flat layer 107, and the second connecting wiring layer 108 is electrically connected to the corresponding anode 110 through a via hole penetrating the third flat layer 109.

[0061] Specifically, the connection wiring layer is a transparent conductive layer, the connection wiring 1081 is a transparent wiring, and the material of the connection wiring 1081 is a transparent conductor material, and the transparent conductor material includes any one of indium tin oxide, indium oxide, indium zinc oxide and silver nanowires.

[0062] Of course, in other embodiments, the connection wiring layer can also be three layers, four layers, five layers... or even more layers, and the present invention is not limited to this. Accordingly, the display panel also needs to be provided with a corresponding number of flat layers, which are used to be arranged between two adjacent layers of the connection wiring layer; specifically, the material of the flat layer includes transparent organic material, and the transparent organic material includes polyimide and photoresist material.

[0063] Furthermore, the thin film transistor may also adopt a double-layer source and drain metal layer design to reduce impedance. Specifically, the thin film transistor also includes a second source and drain metal layer 1050 and a fourth flat layer 1049. The fourth flat layer 1049 covers the side of the first source and drain metal layer 1048 away from the base substrate 101, and the second source and drain metal layer 1050 is arranged on the side of the fourth flat layer 1049 away from the base substrate 101. The first flat layer 105 covers the side of the second source and drain metal layer 1050 away from the base substrate 101. The first source and drain metal layer 1048 is electrically connected to the second source and drain metal layer 1050 through a via penetrating the fourth flat layer 1049, and the second source and drain metal layer 1050 is electrically connected to the connecting wiring 1081 in the first connecting wiring layer 106 through a via penetrating the first flat layer 105.

[0064] In the embodiment of the present invention, the fan-out wiring 104 b is disposed in the same layer as the first gate layer 1043 or the second gate layer 1045 , and the fan-out wiring 104 b and the first gate layer 1043 or the second gate layer 1045 are manufactured through the same process.

[0065] In an embodiment of the present invention, the thickness of the shielding layer 112 along the direction perpendicular to the base substrate 101 is 1 micron to 1.5 microns. The thickness of the shielding layer 112 should not be too large or too small. If the thickness is too large, the overall thickness of the display panel will increase, which is contrary to the current trend of thinner and lighter displays. If the thickness is too small, the shading effect will be poor, which is not conducive to improving the visible mura phenomenon.

[0066] Optionally, the thickness of the blocking layer 112 along the direction perpendicular to the base substrate 101 can be 1 micron, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns and 1.5 microns. In an embodiment of the present invention, the thickness of the blocking layer 112 along the direction perpendicular to the base substrate 101 is 1.2 microns.

[0067] In an embodiment of the present invention, the material of the shielding layer 112 includes a black matrix. Of course, in some embodiments, the material of the shielding layer 112 may also be other light shielding materials, and the present invention does not limit this.

[0068] In the embodiment of the present invention, the shielding layer 112 may be formed by plasma enhanced chemical vapor deposition (PECVD). In some other embodiments, the shielding layer 112 may also be formed by chemical vapor deposition or atomic layer deposition.

[0069] In one embodiment, please continue to see Figure 2 to Figure 5 , Figure 3 yes Figure 2 A partial top view structural diagram of a first opening and a second opening in a display panel; Figure 4 is a schematic diagram of a second cross-sectional structure of a display panel provided by an embodiment of the present invention; Figure 5 yes Figure 4 A partial top view structural diagram of the first opening and the second opening in the display panel.

[0070] In the embodiment of the present invention, the orthographic projection of the second opening V2 on the base substrate 101 covers the orthographic projection of the first opening V1 on the base substrate 101. In this embodiment, the shielding layer 112 can shield part of the lower metal wiring, and since the orthographic projection of the shielding layer 112 on the base substrate 101 does not overlap with the orthographic projection of the light-emitting layer 113 on the base substrate 101, this embodiment significantly improves the visible mura phenomenon without affecting the light-emitting effect of the light-emitting layer 113.

[0071] In the embodiment of the present invention, the orthographic projection shape of the second opening V2 on the base substrate 101 is the same as the orthographic projection shape of the corresponding first opening V1 on the base substrate 101, that is, the orthographic projection shape of the second opening V2 on the base substrate 101 is the same as the orthographic projection shape of the corresponding light-emitting layer 113 on the base substrate 101. Taking the arrangement of each pixel unit 115 as a Peral (pearl) type arrangement as an example for explanation, each of the pixel units 115 includes two red light-emitting pixels, two blue light-emitting pixels and four green light-emitting pixels, the shapes of the red light-emitting pixels and the blue light-emitting pixels are octagons, and the shape of the green light-emitting pixels is an ellipse, then, in the embodiment of the present invention, the orthographic projection shape of the second opening V2 on the base substrate 101 is an octagon or an ellipse.

[0072] Of course, in other embodiments, the pixel unit 115 may also adopt other arrangements, the orthographic projection shape of the light-emitting layer 113 on the base substrate 101 may also be a rectangle, a circle, or other polygonal shapes, and the shape of the second opening V2 may also be different from the shape of the first opening V1. The present invention is not limited to this, and the second opening V2 may be designed according to the arrangement and shape of the first opening V1.

[0073] Specifically, the ratio of the orthographic projection area of ​​the second opening V2 on the base substrate 101 to the orthographic projection area of ​​the first opening V1 on the base substrate 101 is in a range of 1 to 1.5.

[0074] In detail, this embodiment includes two situations, wherein the first situation is, please refer to Figure 2 and Figure 3, there is a gap between the orthographic projection edge of the second opening V2 on the base substrate 101 and the orthographic projection edge of the first opening V1 on the base substrate 101, that is, the orthographic projection area of ​​the second opening V2 on the base substrate 101 is larger than the orthographic projection area of ​​the first opening V1 on the base substrate 101, that is, the ratio of the orthographic projection area of ​​the second opening V2 on the base substrate 101 to the orthographic projection area of ​​the first opening V1 on the base substrate 101 is greater than 1 and less than or equal to 1.5.

[0075] In the second case, see Figure 4 and Figure 5 , Figure 4 and Figure 2 The difference is that Figure 5 and Figure 3 The difference is that the orthographic projection edge of the second opening V2 on the base substrate 101 completely overlaps with the orthographic projection edge of the first opening V1 on the base substrate 101, that is, the orthographic projection area of ​​the second opening V2 on the base substrate 101 is equal to the orthographic projection area of ​​the first opening V1 on the base substrate 101, that is, the ratio of the orthographic projection area of ​​the second opening V2 on the base substrate 101 to the orthographic projection area of ​​the first opening V1 on the base substrate 101 is equal to 1. It can be understood that in the second case, compared with the first case, the area of ​​the lower metal wiring blocked by the shielding layer 112 is larger, and the improvement effect on the visibility mura is better.

[0076] In one embodiment, see Figure 6 and Figure 7 , Figure 6 is a schematic diagram of a third cross-sectional structure of a display panel provided by an embodiment of the present invention; Figure 7 yes Figure 6 A partial top view structural diagram of a first opening and a second opening in a display panel; Figure 6 and Figure 2 , Figure 7 and Figure 3 The difference is that the orthographic projection of the first opening V1 on the base substrate 101 covers the orthographic projection of the second opening V2 on the base substrate 101. In this embodiment, the shielding layer 112 can shield almost all the lower metal wirings. Since the orthographic projection of the shielding layer 112 on the base substrate 101 partially overlaps with the orthographic projection of the light-emitting layer 113 on the base substrate 101, the effective light-emitting area of ​​the light-emitting layer 113 is reduced. Therefore, compared with Figure 2 and Figure 4The improvement effect of visibility mura in this embodiment is further enhanced, but the luminous effect of the luminous layer 113 is sacrificed.

[0077] Specifically, the ratio of the orthographic projection area of ​​the second opening V2 on the base substrate 101 to the orthographic projection area of ​​the first opening V1 on the base substrate 101 is in the range of 0.8 to 1. The orthographic projection area of ​​the second opening V2 on the base substrate 101 cannot be too small, otherwise the luminous effect of the light-emitting layer 113 of the fan-out display area 100b will be greatly reduced, resulting in excessively large difference in display effect between the fan-out display area 100b and the normal display area 100a, resulting in reduced display uniformity.

[0078] Further, in one embodiment, see Figure 8 and Fig. 9 , Figure 8 is a schematic diagram of a fourth cross-sectional structure of a display panel provided by an embodiment of the present invention; Fig. 9 yes Figure 8 A partial top view structural diagram of a first opening and a second opening in a display panel; Figure 8 and Figure 6 , Fig. 9 and Figure 7 The difference is that, in order to improve the disadvantage of reduced luminous effect of the luminous layer 113 in the embodiment of the present invention, the luminous layer 113 covers the side wall and the bottom of the second opening V2, that is, the shielding layer 112 is equivalent to playing the role of the pixel definition layer 111, and the second opening V2 is equivalent to the pixel opening. Preferably, the luminous layer 113 completely covers the side wall and the bottom of the second opening V2. Since the height of the shielding layer 112 is greater than the height of the pixel definition layer 111, that is, the height of the second opening V2 is greater than the height of the first opening V1, therefore, in this embodiment, the luminous layer 113 is arranged in the second opening V2, which is equivalent to increasing the effective luminous area of ​​the luminous layer 113, which is beneficial to improving the luminous effect of the luminous layer 113, thereby achieving the purpose of improving visibility mura without affecting the luminous effect of the luminous layer 113.

[0079] In one embodiment, see Fig.10 , Fig.10 is a schematic diagram of a fifth cross-sectional structure of a display panel provided by an embodiment of the present invention; Fig.10 and Figure 2The difference is that the pixel definition layer 111 and the shielding layer 112 are made of the same shading material. Optionally, the material of the pixel definition layer 111 is also a black matrix. It can be understood that the pixel definition layer 111 not only defines the light-emitting layer 113, but also plays the same role as the shielding layer 112. Therefore, the pixel definition layer 111 can shield most of the pixel driving circuit unit 104a, the fan-out wiring 104b and the connecting wiring 1081, which can further improve the visibility mura; in addition, compared with Figure 2 In this embodiment, the thickness of the shielding layer 112 can be set to be smaller, or even the shielding layer 112 does not need to be set, which can solve the technical problem of the present invention and is conducive to realizing the thinness of the display panel.

[0080] In the embodiment of the present invention, the display panel further includes a cathode 114, and the shielding layer 112 is disposed between the cathode 114 and the pixel definition layer 111. Figure 2 and Fig.10 In the embodiment, the cathode 114 covers the pixel definition layer 111, the shielding layer 112 and the light emitting layer 113; Figure 4 , Figure 6 and Figure 8 In the embodiment, the cathode 114 covers the shielding layer 112 and the light-emitting layer 113 .

[0081] In an embodiment of the present invention, the display panel further includes an electron injection layer, an electron transport layer, a hole transport layer and a hole injection layer which are sequentially arranged in a direction away from the base substrate 101, the electron injection layer, the electron transport layer, the hole transport layer and the hole injection layer are arranged in the first opening V1, the electron injection layer and the electron transport layer are arranged between the light-emitting layer 113 and the anode 110, and the hole transport layer and the hole injection layer are arranged between the light-emitting layer 113 and the cathode 114.

[0082] In the embodiment of the present invention, the display panel further includes an encapsulation layer, which is coated on the side of the cathode 114 away from the base substrate 101 and is used to encapsulate the light-emitting layer 113 to prevent water vapor and oxygen in the external environment from invading and damaging the light-emitting layer 113. The encapsulation layer may be a thin film encapsulation, and the encapsulation layer may be a single-layer or multi-layer encapsulation stacking structure. Preferably, the encapsulation layer adopts an inorganic / organic / inorganic multi-layer encapsulation stacking structure, which is conducive to improving the encapsulation effect.

[0083] In an embodiment of the present invention, the display panel further comprises a touch layer, which is disposed on a side of the encapsulation layer away from the base substrate 101. The touch type of the touch layer may be self-capacitive or mutual-capacitive. The touch type of the touch layer may be selected according to actual conditions, and the present invention does not limit this.

[0084] In an embodiment of the present invention, the display panel further includes a polarizer and a cover plate, wherein the polarizer and the dry plate are sequentially stacked on a side of the touch layer away from the base substrate 101, the polarizer is bonded to a surface of the touch layer away from the base substrate 101 by optical adhesive, and the cover plate is bonded to a surface of the polarizer away from the base substrate 101 by optical adhesive.

[0085] An embodiment of the present invention also provides a display device, which includes the display panel in the above embodiment, and the display device includes fixed terminals such as televisions, desktop computers, mobile terminals such as mobile phones, laptops, and wearable devices such as bracelets, VR (virtual display) devices, and AR (augmented display) devices.

[0086] An embodiment of the present invention further provides a method for manufacturing a display panel, wherein the display panel comprises a normal display area 100a and a fan-out display area 100b, wherein the fan-out display area 100b is arranged on one side of the normal display area 100a, and the fan-out display area 100b comprises a first area 1001b and a second area 1002b arranged in sequence along a direction from the normal display area 100a to the fan-out display area 100b; the manufacturing method comprises the following steps:

[0087] Providing a substrate 101;

[0088] A driving circuit layer 104 is formed on one side of the base substrate 101, the driving circuit layer 104 includes a plurality of pixel driving circuit units 104a and a plurality of fan-out wirings 104b, the plurality of pixel driving circuit units 104a are arranged in the normal display area 100a and the first area 1001b, the plurality of fan-out wirings 104b are arranged in the second area 1002b, and the density of the pixel driving circuit units 104a located in the first area 1001b is greater than the density of the pixel driving circuit units 104a located in the normal display area 100a;

[0089] At least one connection wiring layer is formed on a side of the driving circuit layer 104 away from the base substrate 101, and each of the connection wiring layers includes a plurality of connection wirings;

[0090] An anode 110 is formed on a side of the connection wiring layer away from the base substrate 101;

[0091] A pixel definition layer 111 is formed on a side of the connection wiring layer away from the base substrate 101 , wherein the pixel definition layer 111 includes a plurality of first openings V1 , and the first openings V1 expose at least a portion of the anode 110 ;

[0092] The shielding layer 112 is formed on a side of the pixel definition layer 111 away from the base substrate 101 , and the shielding layer 112 includes a plurality of second openings V2 , and the second openings V2 are arranged corresponding to the first openings V1 ; and

[0093] A light emitting layer 113 is formed in the first opening V1 .

[0094] The beneficial effect is as follows: the display panel and the display device provided by the embodiments of the present invention, by setting a shielding layer on the side of the pixel definition layer away from the base substrate, the multiple second openings of the shielding layer are set corresponding to the first openings of the pixel definition layer, and the shielding layer can be used to block the light reflected by the metal wiring, so that the light reflected from the metal wiring in the fan-out display area and the normal display area is more uniform, which is beneficial to improving the visible mura phenomenon in the fan-out display area and the normal display area due to the difference in metal wiring density between the fan-out display area and the normal display area in the screen-off and screen-on states.

[0095] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A display panel, characterized in that: The display panel comprises a normal display area and a fan-out display area, wherein the fan-out display area is located on one side of the normal display area, and the fan-out display area comprises a first area and a second area arranged in sequence along a direction from the normal display area to the fan-out display area; the display panel comprises: substrate substrate; A driving circuit layer, arranged on one side of the base substrate, the driving circuit layer comprising a plurality of pixel driving circuit units and a plurality of fan-out wirings, the pixel driving circuit units being located in the normal display area and the first area, the fan-out wirings being located in the second area, wherein the density of the pixel driving circuit units located in the first area is greater than the density of the pixel driving circuit units located in the normal display area; At least one connection wiring layer is arranged on a side of the driving circuit layer away from the base substrate, and each of the connection wiring layers includes a plurality of connection wirings; A plurality of anodes are arranged on a side of the connection wiring layer away from the base substrate, and the pixel driving circuit unit is electrically connected to the corresponding anodes through the connection wiring; A pixel definition layer is disposed on a side of the connection wiring layer away from the base substrate, the pixel definition layer comprises a plurality of first openings, and the first openings expose at least a portion of the anode; and A light-emitting layer is disposed in the first opening; Among them, the display panel also includes a blocking layer, which is arranged on the side of the pixel definition layer away from the base substrate, and the blocking layer includes a plurality of second openings, and the second openings are arranged corresponding to the first openings; the blocking layer covers the side walls of the first openings and part of the anode, the light-emitting layer is located in the second opening and covers the side walls and bottom of the second opening, and the surface of the light-emitting layer away from the base substrate is located between the surface of the pixel definition layer away from the base substrate and the surface of the blocking layer away from the base substrate.

2. The display panel according to claim 1, characterized in that: The orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.

3. The display panel according to claim 2, characterized in that: The ratio of the orthographic projection area of ​​the second opening on the base substrate to the orthographic projection area of ​​the first opening on the base substrate is in a range of 1 to 1.

5.

4. The display panel according to claim 1, characterized in that: The orthographic projection of the first opening on the base substrate covers the orthographic projection of the second opening on the base substrate.

5. The display panel according to claim 4, characterized in that: The ratio of the orthographic projection area of ​​the second opening on the base substrate to the orthographic projection area of ​​the first opening on the base substrate is in a range of 0.8-1.

6. The display panel according to claim 1, characterized in that: The thickness of the shielding layer along a direction perpendicular to the substrate is 1 micron to 1.5 microns.

7. The display panel according to claim 1, characterized in that: The material of the shielding layer includes a black matrix.

8. The display panel according to claim 1, characterized in that: The display panel further includes a cathode, and the shielding layer is disposed between the cathode and the pixel definition layer.

9. The display panel according to claim 1, characterized in that: At least one of the connection wiring layers includes a first connection wiring layer and a second connection wiring layer, and the display panel also includes a first flat layer, a second flat layer and a third flat layer stacked in sequence in a direction away from the base substrate; The first flat layer covers a side of the driving circuit layer away from the base substrate, the first connecting wiring layer is arranged between the first flat layer and the second flat layer, and the second connecting wiring layer is arranged between the second flat layer and the third flat layer; The driving circuit layer is electrically connected to the connecting wiring in the first connecting wiring layer through a via hole penetrating the first flat layer, the first connecting wiring layer is electrically connected to the connecting wiring in the second connecting wiring layer through a via hole penetrating the second flat layer, and the second connecting wiring layer is electrically connected to the anode through a via hole penetrating the third flat layer.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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