A delay link and a delay control method

Abstract

This application discloses a delay link, comprising: a delay chain composed of n delay units connected in series, wherein the output signals of all delay units in the delay chain can be selected by a gating switch; interpolation modules are connected to the two output paths of the delay chain, and the interpolation modules include multiple parallel controllable delay buffer units, and the output terminals of each parallel controllable delay buffer unit are connected in parallel; wherein n > 1. Clearly, in this delay link, the two output paths of the delay chain are first set to have different delay times by the gating switch, and by adjusting the number of parallel controllable delay buffer units on the two output paths of the delay chain, the delayed output signals of the delay chain can be adjusted more finely using the delay buffer units, thereby enabling the delay link to have higher delay accuracy.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a delay link and a delay control method. Background Technology

[0002] Delay links are widely used in the circuit design of high-speed interfaces, and the delay accuracy of the delay link directly affects the data transmission performance of the high-speed interface. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a structural diagram of a delay link in existing technology. Figure 1 The delay link shown is composed of n delay units connected in series, where the delay time of each delay unit is t. d The output of each delay unit can be selected by a selector switch. If the output signal 'out' selects the m-th delay unit for output, then the delay time between the output signal 'out' and the input signal 'in' is m*t. d .exist Figure 1 In the delay link shown, the minimum delay time of the delay unit has been fixed at t. d In this case, the delay time of the output signal out can only be t. d The delay time is an integer multiple of the design value t. Furthermore, since the delay time of each delay unit is affected by factors such as manufacturing process and temperature, the actual delay time of each delay unit will differ from the design setting value t. d The significant difference in latency results in a substantial error in the actual delay accuracy of the delay link. Currently, there is no effective solution to this technical problem.

[0003] Therefore, how to further improve the delay accuracy of delay links is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a delay link and a delay control method to further improve the delay accuracy of the delay link. The specific solution is as follows:

[0005] A delay link includes: a delay chain composed of n delay units connected in series, wherein the output signals of all delay units in the delay chain can be selected and output by a gating switch, and an interpolation module is connected to each of the two output paths of the delay chain. The interpolation module includes multiple parallel controllable delay buffer units, and the output terminals of each parallel controllable delay buffer unit are connected in parallel; wherein n > 1.

[0006] Preferably, the delay unit is a logic gate circuit with a delay function.

[0007] Preferably, the gating switch is a signal selector or an AND gate.

[0008] Accordingly, the present invention also discloses a delay control method applied to the aforementioned delay link, comprising:

[0009] Receive target control signals;

[0010] The two output paths of the delay chain are controlled to output different delay signals according to the target control signal, and the number of conduction of delay buffer units in the interpolation module on each output path is adjusted according to the target control signal to regulate the delayed output signal of the delay chain.

[0011] Preferably, when the two output paths of the delay chain are a first output path and a second output path, and a first interpolation module and a second interpolation module are respectively connected to the first output path and the second output path, the process of controlling the two output paths of the delay chain to output different delay signals according to the target control signal, and adjusting the number of conduction points of delay buffer units in the interpolation modules on each output path according to the target control signal to regulate the delayed output signal of the delay chain includes:

[0012] Based on the target control signal, the delay time of the output signals of the first output path and the second output path relative to the input signal is set to i*t using the selection switch, respectively. d and (i+g)*t d ; where t d Let g be the delay time of the delay unit, where 0 < i < n, 1 < g < n-1;

[0013] According to the target control signal, the number of delayed buffer units in the first interpolation module is set to k, and the number of delayed buffer units in the second interpolation module is set to j; where 1 < k < m, 1 < j < m; m is the number of delayed buffer units in the first interpolation module or the second interpolation module;

[0014] If k = j, then the delay time of the delayed output signal of the delay chain relative to the input signal is determined to be g*t. d / 2.

[0015] Preferably, after the process of setting the number of delayed buffer units in the first interpolation module to k and the number of delayed buffer units in the second interpolation module to j according to the target control signal, the method further includes:

[0016] If k > j, then the delay of the delayed output signal of the delay chain relative to the input signal is determined to be less than g*t. d / 2, and the degree of delay of the delayed output signal of the delay chain relative to the input signal is determined by |kj|.

[0017] Preferably, after the process of setting the number of delayed buffer units in the first interpolation module to k and the number of delayed buffer units in the second interpolation module to j according to the target control signal, the method further includes:

[0018] If k < j, then the delay of the delayed output signal of the delay chain relative to the input signal is determined to be greater than g*t. d / 2, and the degree of delay of the delayed output signal of the delay chain relative to the input signal is determined by |kj|.

[0019] As can be seen, in the delay link provided by this invention, the delay chain is composed of n delay units connected in series. The output signal of each delay unit in the delay chain can be selected by a gating switch. Multiple parallel controllable delay buffer units are connected to the two output paths of the delay chain, and the output terminals of the two parallel controllable delay buffer units are connected in parallel. Clearly, in this delay link, by first setting the two output paths of the delay chain to have different delay times using the gating switch, and then adjusting the number of parallel controllable delay buffer units on the two output paths of the delay chain, the delayed output signal of the delay chain can be more finely adjusted using the delay buffer units, thereby enabling the delay link to have higher delay accuracy. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 This is a structural diagram of a delay link in existing technology;

[0022] Figure 2 This is a structural diagram of a delay link provided in an embodiment of the present invention;

[0023] Figure 3 This is another structural diagram of a delay link provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the delayed signals output by the two output paths in the delay chain. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figure 2 , Figure 2 The present invention provides a structural diagram of a delay link, which includes: a delay chain composed of n delay units connected in series, wherein the output signals of all delay units in the delay chain can be selected and output by a gating switch, and interpolation modules are respectively connected to the two output paths of the delay chain. The interpolation modules include multiple parallel controllable delay buffer units, and the output terminals of each parallel controllable delay buffer unit are connected in parallel; wherein n>1.

[0027] This delay link can significantly improve the delay accuracy. Please refer to [link / reference]. Figure 2 ,exist Figure 2 The delay link shown consists of a delay chain and two parallel controllable delay buffer units. It should be noted that since each delay unit in the delay chain can be selected by a gating switch, the delay chain includes multiple output paths. The two output paths in this embodiment are arbitrarily selected from all the output paths of the delay chain. Interpolation modules are connected to the two output paths of the delay chain. Each interpolation module includes multiple parallel controllable delay buffer units. The delay link adjusts the number of conducting delay buffer units in the interpolation modules connected to the two output paths of the delay chain according to the received target control signal, thereby achieving the purpose of regulating the delayed output signal of the delay chain.

[0028] Specifically, the delay unit in the delay chain can be set as any circuit module with delay function, such as a delayer, inverter, etc. As a preferred implementation, the delay unit can be set as a logic gate circuit with delay function. Because logic gate circuits are relatively inexpensive, using logic gate circuits to build the delay unit in the delay chain can relatively reduce the design cost of the delay unit. Furthermore, since logic gate circuits with delay function are functional modules well-known to those skilled in the art, their structure will not be described in detail.

[0029] Since the output signals of all delay units in the delay chain can be selected by a gating switch, the gating switch can be configured as a signal selector or an AND gate. When configuring the signal selector, it can have n input interfaces, so that each of the n input interfaces corresponds one-to-one with one of the n delay units in the delay chain, facilitating the gating output of the delayed signals. Alternatively, in practice, the signal selector can have two input interfaces, and multiple 2-to-1 multiplexers can be used to select the output signals of all delay units in the delay chain. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a structural diagram of another delay link provided in an embodiment of the present invention.

[0030] Furthermore, in practical applications, the delay buffer unit can be set as any circuit module with delay buffering function, as long as it can achieve the purpose of buffering and delaying the output signal of the delay chain. For example, the delay buffer unit can be set as a buffer or a transmission gate with delay function, etc.

[0031] Accordingly, embodiments of the present invention also provide a delay control method, applied to a delay link disclosed above, comprising:

[0032] Receive target control signals;

[0033] The two output paths of the delay chain are controlled to output different delay signals according to the target control signal. The number of conduction units in the interpolation module of each output path is adjusted according to the target control signal to regulate the delayed output signal of the delay chain.

[0034] This embodiment describes in detail the process of regulating the delayed signal output by the delay link. When the delay link receives a target control signal sent by the user or terminal, it combines and selects the gating switches set on the delay link according to the target control signal, thereby enabling the two output paths of the delay link to output different delayed signals. When the two output paths of the delay link can output different delayed signals, the delay link regulates the number of conduction units in the interpolation modules connected to the two output paths of the delay link according to the target control signal, thereby achieving the purpose of regulating the delayed output signal of the delay link.

[0035] In other words, by adjusting the number of delayed buffer units on the two output paths of the delay chain, the delayed output signals on the two output paths of the delay chain can be interpolated to allow for more refined adjustments to the delayed output signals of the delay chain, thereby enabling the delay chain to have higher delay accuracy.

[0036] Specifically, when the two output paths of the delay chain are the first output path and the second output path, and the first output path and the second output path are respectively connected to the first interpolation module and the second interpolation module, the above steps—controlling the two output paths of the delay chain to output different delay signals according to the target control signal, and adjusting the number of conduction points of the delay buffer units in the interpolation modules on each output path according to the target control signal to regulate the delayed output signal of the delay chain—include:

[0037] Based on the target control signal, the delay time of the output signals of the first and second output paths relative to the input signals is set to i*t using a gating switch. d and (i+g)*t d ; where t d Let g be the delay time of the delay unit, where 0 < i < n, 1 < g < n-1;

[0038] Based on the target control signal, the number of delayed buffer units in the first interpolation module is set to k, and the number of delayed buffer units in the second interpolation module is set to j; where 1 < k < m, 1 < j < m; m is the number of delayed buffer units in the first interpolation module or the second interpolation module;

[0039] If k = j, then the delay time of the delayed output signal relative to the input signal of the delay chain is determined to be g*t. d / 2.

[0040] Specifically, when the two output paths of the delay chain are the first output path OutK and the second output path OutJ, and the first output path OutK and the second output path OutJ are respectively connected to the first interpolation module and the second interpolation module, when the delay chain receives the target control signal, it can first use a gating switch to set the output signal of the first output path OutK of the delay chain to be delayed by i*t relative to the input signal. d The output signal of the second output path OutJ of the delay chain is set to be delayed by (i+g)*t relative to the input signal. d .

[0041] Please see Figure 3 ,exist Figure 3 In the delay link shown, the target control signal includes a KEN sequence signal that enables the delay buffer unit in the first interpolation module and a JEN sequence signal that enables the delay buffer unit in the second interpolation module. The number of delayed buffer units in the first and second interpolation modules is adjusted by the KEN sequence signal and the JEN sequence signal, respectively.

[0042] Please see Figure 4 , Figure 4 This diagram illustrates the delayed signals output by the two output paths in a delay chain. In this case, the delay time of the first output path OutK relative to the second output path OutJ is g*t. d Meanwhile, if the number of conduction units in the first interpolation module is set to k, and the number of conduction units in the second interpolation module is set to j, then the number of conduction units in the first and second interpolation modules can be used to interpolate and control the delay output of the entire delay link, thereby achieving flexible adjustment of the delay output of the delay link.

[0043] Specifically, if k = j, this is equivalent to not using the first and second interpolation modules to interpolate and delay the first output path OutK and the second output path OutJ of the delay chain. Instead, the delayed output signals of the two output paths OutK and OutJ of the delay chain are simply output in parallel. In this case, the delay time of the delayed output signal Out of the delay chain relative to the input signal is g*t. d / 2.

[0044] If k > j, it means that the delay of the delayed output signal Out relative to the input signal In of the delay chain will be less than g*t. d / 2. The delay of the delayed output signal Out relative to the input signal In of the delay chain is determined by |kj|. That is, the larger the difference between k and j, the closer the delay of the delayed output signal Out relative to the input signal In will be to 0; the smaller the difference between k and j, the closer the delay of the delayed output signal Out relative to the input signal In will be to g*t. d / 2.

[0045] If k < j, it means that the delay of the delayed output signal Out relative to the input signal In of the delay chain will be greater than g*t. d / 2. The delay of the delayed output signal Out relative to the input signal In of the delay chain is also determined by |kj|. That is, the larger the difference between j and k, the greater the delay of the delayed output signal Out relative to the input signal In will be, the more significant the delay will be compared to g*t. d / 2; The smaller the difference between j and k, the closer the delay of the delayed output signal Out relative to the input signal In will be to g*t. d / 2.

[0046] In practical applications, if the number of conducting units *k* in the first interpolation module and *j* in the second interpolation module is already determined, adjusting the delayed output signal *Out* of the delay chain can be achieved by dividing the delay time of *Out* relative to the input signal *In* into |kj| increments and adjusting them sequentially. This allows for more precise adjustment of the delayed output signal *Out*. Clearly, this setup not only enables a more accurate delayed output and improves the robustness of the delayed output, but also makes the adjustment of the delayed output more flexible.

[0047] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Finally, it should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] The above provides a detailed description of a delay link and a delay control method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A time-delay link, characterized in that, include: Depend on A delay chain consisting of multiple delay units connected in series, wherein the output signals of all delay units in the delay chain can be selected by a gating switch, and an interpolation module is connected to each of the two output paths of the delay chain. Each interpolation module includes multiple parallel controllable delay buffer units, and the outputs of each parallel controllable delay buffer unit are connected in parallel. ; The delay link is used to control the two output paths of the delay link to output different delay signals according to the target control signal, and to adjust the number of conduction of delay buffer units in the interpolation module on each output path according to the target control signal, so as to perform delay interpolation on the delayed output signals on the two output paths of the delay link, thereby adjusting the delayed output signals of the delay link. The delay chain has two output paths, namely a first output path and a second output path. A first interpolation module and a second interpolation module are connected to the first output path and the second output path, respectively. The delay chain is also used to set the number of conduction units in the first interpolation module to the target control signal. And set the number of conduction units in the delay buffer unit of the second interpolation module to 1. Wherein, the degree of delay of the delayed output signal of the delay chain relative to the input signal is determined by... and Decide.

2. A delay link according to claim 1, characterized in that, The delay unit is specifically a logic gate circuit with a delay function.

3. A delay link according to claim 1, characterized in that, The gating switch is specifically a signal selector or an AND gate.

4. A delay control method, characterized in that, Applied to a delay link according to any one of claims 1 to 3, comprising: Receive target control signals; The target control signal controls the two output paths of the delay chain to output different delay signals, and the target control signal adjusts the number of conduction of delay buffer units in the interpolation module of each output path to perform delay interpolation on the delayed output signals of the two output paths of the delay chain, thereby regulating the delayed output signals of the delay chain.

5. The delay control method according to claim 4, characterized in that, The process of controlling the two output paths of the delay chain to output different delay signals according to the target control signal, and adjusting the number of conduction points of delay buffer units in the interpolation modules of each output path according to the target control signal, so as to perform delay interpolation on the delayed output signals of the two output paths of the delay chain, and thereby adjust the delayed output signals of the delay chain, includes: Based on the target control signal, the delay time of the output signals of the first output path and the second output path relative to the input signal is set using the gating switch. and ;in, The delay time of the delay unit. , ; The number of delayed buffer units in the first interpolation module is set to the target control signal. And set the number of conduction units in the delay buffer unit of the second interpolation module to 1. ;in, , ; The number of delay buffer units in the first interpolation module or the second interpolation module; like Then the delay time of the delayed output signal of the delay chain relative to the input signal is determined to be... .

6. The delay control method according to claim 5, characterized in that, The number of conduction units in the delay buffer unit of the first interpolation module is set according to the target control signal. And set the number of conduction units in the delay buffer unit of the second interpolation module to 1. Following the process, it also includes: like Then it is determined that the delay of the delayed output signal of the delay chain relative to the input signal is less than 1 / 3. And the degree of delay of the delayed output signal of the delay chain relative to the input signal is determined by... The decision was made.

7. The delay control method according to claim 5, characterized in that, The number of conduction units in the delay buffer unit of the first interpolation module is set according to the target control signal. And set the number of conduction units in the delay buffer unit of the second interpolation module to 1. Following the process, it also includes: like If the delay of the delayed output signal of the delay chain relative to the input signal is greater than 1, then it is determined that the delay of the delayed output signal of the delay chain relative to the input signal is greater than 1. And the degree of delay of the delayed output signal of the delay chain relative to the input signal is determined by... The decision was made.

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