A dual-layer scheduling decoder, method and intelligent terminal based on 5G LDPC

Abstract

The present invention belongs to the technical field of decoders, and discloses a double-layer scheduling decoder, method and intelligent terminal based on 5G LDPC. The double-layer scheduling decoder based on 5G LDPC includes: LLR memory, control unit, shift network, calculation unit and check node storage unit; control unit, used to control the input order of two layers of variable nodes input from LLR memory to calculation unit and the output order of updated variable nodes written to LLR memory, and read related check nodes from check node storage unit at the same time; shift network, used for shifting two layers of variable nodes; calculation unit, used for updating variable nodes. The present invention utilizes the characteristics of 5G basic matrix divided into orthogonal matrix and non-orthogonal matrix, rearranges the input and output order of variable nodes of each layer, reduces the delay caused by conflicting variable nodes under the premise of ensuring performance, realizes double-layer scheduling of decoder, and then improves the throughput of decoder to meet the requirements of 5G high-speed communication.

Description

Technical Field

[0001] The present invention belongs to the technical field of decoders, and in particular to a double-layer scheduling decoder, method and intelligent terminal based on 5G LDPC. Background Art

[0002] At present, the fifth generation of mobile communications (5G) is divided into three major application scenarios: enhanced mobile broadband (eMBB), low latency and high reliability (URLLC), and massive machine type communications (mMTC). Data services are characterized by high speed and latency between 50 and 100 ms; interactive services have a latency of 5 to 10 ms; augmented reality and online games require high-definition video and a latency of tens of milliseconds.

[0003] Low-density parity check code (LDPC) was first proposed by Robert Gallager in his doctoral thesis in 1963. Classic LDPC has excellent performance and low decoding complexity for long code blocks, and has repeatedly refreshed the approximation record of Shannon's bound. After years of research, LDPC has made great breakthroughs in short code design, support for flexible code length and code rate, code rate compatibility, and adaptive retransmission. At the same time, the optimization of LDPC decoding algorithm has been ongoing. Finally, with its excellent performance, LDPC finally entered the strict 5G-NR standard in October 2016 (as the coding scheme for eMBB data channels).

[0004] 5G LDPC is a quasi-cyclic LDPC code. The basic check matrix is ​​divided into BG1 and BG2, supporting 51 boost values, with a minimum of 2 and a maximum of 384.

[0005] The decoding algorithm of LDPC is the belief propagation (BP) algorithm, which is in principle manifested as information interaction between variable nodes and check nodes, and multiple iterations are performed to obtain the decoding results. The scheduling methods between nodes are divided into flooding and layered. The characteristic of flooding is that in each decoding iteration, all soft information from variable nodes to check nodes is calculated first, and then the soft information from check nodes to variable nodes is calculated. It is mostly used for computer simulation. The characteristic of layered is that when calculating the soft information of each layer, the relevant node information in this iteration will be updated for the soft information calculation of the next layer, which is suitable for hardware implementation.

[0006] The architecture of the LDPC decoder is mainly divided into full parallel structure, row parallel structure and block parallel structure. The row parallel structure and block parallel structure adopt a hierarchical decoding scheduling method. The parallelism of the row parallel structure is affected by the number of rows of the basic check matrix, with a maximum of 46, and the parallelism of the block parallel structure is affected by the boost value of the 5G LDPC code, with a maximum of 384. At present, most 5G LDPC decoders adopt a hierarchical scheduling of row parallel or block parallel structure.

[0007] When designing traditional layered LDPC decoders, in order to avoid variable node conflicts between layers, decoding can only be done in sequence and on a single layer. LDPC codes have good throughput performance under high bit rates, but for low bit rates, the throughput is often low and cannot meet the basic requirements of 5G communications.

[0008] Through the above analysis, the problems and defects of the existing technology are as follows: the traditional layered 5G LDPC decoder decodes single-layer scheduling, and the throughput is low under low code conditions, which cannot meet the basic requirements of 5G communication. Summary of the invention

[0009] In view of the problems existing in the prior art, the present invention provides a double-layer scheduling decoder, method and intelligent terminal based on 5G LDPC. The variable node index of each layer of BG1 and BG2 is a fixed value, that is, the two matrices of BG1 and BG2 are fixed, and the index value of each layer is actually the position of the non-zero element of each row of the matrix. Since the matrix is ​​fixed, the orthogonal region and non-orthogonal region of BG1 and BG2 are fixed. The size of the basic matrix of BG1 is 46×68, and the size of the basic matrix of BG2 is 42×52, of which the orthogonal region of BG1 is the 21st to 46th rows, and the orthogonal region is 1 to 20 rows. The orthogonal region of BG2 is 21 to 42 rows, and the non-orthogonal region is 1 to 20 rows. The input and output order of the nodes is a solution designed in this paper to effectively solve the high delay of double-layer scheduling due to the large number of conflicting variable nodes.

[0010] The present invention is implemented as follows: a double-layer scheduling decoder based on 5G LDPC, the double-layer scheduling decoder based on 5G LDPC comprising:

[0011] LLR memory, global control unit, pre-calculation layer control unit, waiting layer control unit, two groups of shift networks, 768 calculation units and check node storage unit;

[0012] A global control unit controls the current decoding group and the number of decoding iterations;

[0013] The first calculation layer control unit and the waiting layer control unit are used to control the input sequence of the two-layer variable nodes from the LLR memory to the calculation unit, and the output sequence of the variable nodes updated by the calculation unit written to the LLR memory, and control the reading of related check nodes from the check node storage unit;

[0014] Two groups of shift networks, used for shifting two layers of variable nodes respectively;

[0015] The computing unit is used for the two-layer variable nodes to interact with the corresponding check nodes and obtain updated variable nodes.

[0016] Furthermore, the two layers of variable nodes include: a first-calculation layer variable node and a waiting layer variable node; the first-calculation layer variable node is an odd-numbered layer variable node; and the waiting layer variable node is an even-numbered layer variable node.

[0017] Another object of the present invention is to provide a double-layer scheduling method for a double-layer scheduling decoder based on 5G LDPC, and the double-layer scheduling method for a double-layer scheduling decoder based on 5G LDPC includes:

[0018] The control unit reads two layers of variable nodes from the LLR memory, respectively passes through the shift network and enters the calculation unit, interacts with the corresponding check nodes, and obtains updated variable nodes.

[0019] Further, the dual-layer scheduling method of the dual-layer scheduling decoder based on 5G LDPC includes the following steps:

[0020] Step 1: Divide each layer of the 5G basic check matrix into odd layers and even layers, decode each adjacent odd layer and even layer at the same time, and group the adjacent odd layers and even layers into one group;

[0021] Step 2: The calculation unit of the first calculation layer inputs the variable nodes required for the calculation of this layer, and immediately calculates and outputs the updated variable nodes. For non-orthogonal groups, the first calculation layer and the waiting layer are not calculated at the same time due to the existence of conflicting variable nodes. The conflicting variable nodes first enter the calculation unit of the first calculation layer for calculation, and the waiting layer first inputs the non-conflicting variable nodes. After the calculation of the first calculation layer is completed, the updated variable nodes are output, and the calculation unit of the waiting layer continues to input the conflicting variable nodes and starts calculation; for orthogonal groups, there are no conflicting variable nodes in the first calculation layer and the waiting layer, and they are calculated at the same time;

[0022] Step 3: When the waiting layer calculation is finished and the updated variable nodes are output, the decoding control unit controls the first calculation layer and the waiting layer calculation unit to input the next group of their respective variable nodes and start the calculation of the next group;

[0023] Step 4: After all groups are calculated, the number of decoding iterations is increased by 1. If the maximum number of decoding iterations is reached, the decoder ends the calculation and outputs the decoding result. Otherwise, steps 2 and 3 are repeated.

[0024] Furthermore, each layer of calculation of the double-layer scheduling decoder of the 5G LDPC adopts a block parallel structure.

[0025] Furthermore, the step of grouping adjacent odd-numbered layers and even-numbered layers into one group includes: the two layers of each group are divided into a first-calculated layer and a waiting layer; the odd-numbered layer is the first-calculated layer; and the even-numbered layer is the waiting layer.

[0026] Furthermore, the step 2 also includes: during decoding scheduling, the input and output order of the variable nodes of each layer is rearranged.

[0027] Further, the rearrangement of the input and output order of the variable nodes of each layer includes:

[0028] In the waiting layer of the non-orthogonal group, the conflicting variable nodes are input last, and wait for the results of updating the conflicting variable nodes in the first calculation layer.

[0029] Furthermore, the rearrangement of the input and output order of the variable nodes of each layer also includes: each layer of the current group first outputs the variable nodes that conflict with the next group.

[0030] The input order of the first calculation layer of all groups is adjusted to first input the variable nodes that do not conflict with the previous group, and then input other variable nodes.

[0031] The input order of the waiting layer of the non-orthogonal group is adjusted to first input the variable nodes that have no conflict with the first-calculated layer of the current group, then input the inter-group conflicting variable nodes that conflict with the previous group, wait for the first-calculated layer to update the conflicting variable nodes, and finally input the intra-group conflicting variable nodes.

[0032] The input order of the waiting layer of the orthogonal group is adjusted to first input the variable nodes that do not conflict with the previous group, and then input other variable nodes, without waiting in between.

[0033] The output order of the first calculation layer of the non-orthogonal group is adjusted to first output the conflicting variable nodes within the group that conflict with the waiting layer of the group, and then output other variable nodes.

[0034] The output order of the first calculation layer of the orthogonal group is adjusted to output the inter-group conflicting variable nodes that conflict with the next group first, and then output other variable nodes.

[0035] The output order of the waiting layer of all groups is adjusted to output the inter-group conflicting variable nodes that conflict with the next group first, and then output other variable nodes.

[0036] Another object of the present invention is to provide an information data processing terminal, which is used to execute the dual-layer scheduling method of the dual-layer scheduling decoder based on 5G LDPC.

[0037] In combination with the above technical solutions and the technical problems solved, please analyze the advantages and positive effects of the technical solutions to be protected by the present invention from the following aspects:

[0038] First, in view of the technical problems existing in the above-mentioned prior art and the difficulty of solving the problems, the technical solutions to be protected by the present invention and the results and data during the research and development process are closely combined to analyze in detail and deeply how the technical solutions of the present invention solve the technical problems, and some creative technical effects brought about after solving the problems. The specific description is as follows:

[0039] The present invention utilizes the double-layer scheduling of the rearranged decoder, which can greatly reduce the input and output delays of the intermediate variable nodes and has a higher throughput under low bit rate conditions.

[0040] The present invention proposes a 5G LDPC decoder with a block parallel structure and double-layer scheduling. According to the basic check matrix of 5G, every two layers are divided into a group, and each group includes a pre-calculation layer and a waiting layer, wherein the odd-numbered layers are the pre-calculation layers and the even-numbered layers are the waiting layers. During decoding scheduling, the input and output order of the variable nodes of each layer will be rearranged. The input order affecting the variable nodes of each layer comes from the conflicting variable nodes between and within the groups. In the waiting layer, the conflicting variable nodes are input last and wait for the result of the pre-calculation layer updating the conflicting variable nodes. The conflicting variable nodes between groups will affect the update order of the variable nodes of each layer. The current group will first output the variable nodes that conflict with the next group, thereby reducing the waiting of the next group. The double-layer scheduling of the rearranged decoder can greatly reduce the input and output delays of the intermediate variable nodes, and has a higher throughput under low bit rate conditions.

[0041] Second, considering the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by the present invention are described in detail as follows:

[0042] The present invention utilizes the characteristics of 5G basic matrix divided into orthogonal matrix and non-orthogonal matrix to rearrange the input and output order of variable nodes in each layer. Under the premise of ensuring performance, it reduces the delay caused by conflicting variable nodes, realizes double-layer scheduling of decoder, and thus improves the throughput of decoder to meet the requirements of 5G high-speed communication.

[0043] Third, as auxiliary evidence of the inventiveness of the claims of the present invention, it is also reflected in the following important aspects:

[0044] (1) The technical solution of the present invention fills the technical gap in the industry at home and abroad: The present invention fills the problem that the 5G LDPC decoder is difficult to implement in double-layer scheduling and has little significance. By rearranging the input and output order of the variable nodes of each layer, the decoder avoids the large delay caused by the conflicting variable nodes during calculation, while ensuring the performance of the decoder. The data input and output of the rearranged decoder are more pipelined and have a higher throughput.

[0045] (2) Whether the technical solution of the present invention solves the technical problem that people have been eager to solve but have never succeeded in solving: The present invention solves the problem of low throughput of the 5G LDPC decoder at low code rates. Under the lowest code rate of 1 / 3, the throughput can reach 9.6f, where f is the operating frequency. That is, when the frequency is 1 Gbps, the decoder throughput is 9.6 Gbps. Under single-layer scheduling conditions, the decoder throughput of 1 / 3 code rate is only 2.4f.

[0046] (3) Whether the technical solution of the present invention overcomes technical prejudice: The present invention overcomes the prejudice that the throughput of the double-layer scheduling scheme cannot reach twice the throughput of the single-layer scheduling scheme, although the resources are doubled due to the existence of conflicting variable nodes, and the efficiency improvement is too low. In the case of low bit rate, the throughput of the double-layer scheduling designed by the present invention can reach more than three times the throughput of the single-layer scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a schematic diagram of a double-layer scheduling decoder based on 5G LDPC provided in an embodiment of the present invention.

[0048] Figure 2 It is a flow chart of a double-layer scheduling method of a double-layer scheduling decoder based on 5G LDPC provided in an embodiment of the present invention.

[0049] Figure 3 This is a schematic diagram of conflicting variable nodes provided by an embodiment of the present invention.

[0050] Figure 4 It is a timing relationship diagram of the 8th and 9th groups provided in an embodiment of the present invention.

[0051] Figure 5 It is a schematic diagram of the input-output relationship between the 18th group and the 19th group provided in an embodiment of the present invention.

[0052] Figure 6 It is a diagram of the floating-point simulation performance of the LDPC code and the fixed-point hardware simulation performance of double-layer scheduling provided by the embodiment of the present invention.

[0053] Figure 7 It is a schematic diagram of the basic matrix structure of 5G LDPC provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0055] 1. Explanatory Examples In order to enable those skilled in the art to fully understand how to implement the present invention, this section provides an illustrative example that expands and describes the technical solution of the claims.

[0056] like Figure 1 As shown, the double-layer scheduling decoder based on 5G LDPC provided in an embodiment of the present invention includes:

[0057] LLR memory, global control control unit, first calculation layer control unit, waiting layer control unit, two groups of shift networks, 768 calculation units and check node storage unit;

[0058] A global control unit controls the current decoding group and the number of decoding iterations;

[0059] The first calculation layer control unit and the waiting layer control unit are used to control the input sequence of the two-layer variable nodes from the LLR memory to the calculation unit, and the output sequence of the variable nodes updated by the calculation unit written to the LLR memory, and control the reading of related check nodes from the check node storage unit;

[0060] Two groups of shift networks, used for shifting two layers of variable nodes respectively;

[0061] The computing unit is used to interact the two-layer variable nodes with the corresponding check nodes and obtain updated variable nodes.

[0062] The two-layer variable nodes provided in the embodiment of the present invention include: a first-calculation layer variable node and a waiting layer variable node; the first-calculation layer variable node is an odd-numbered layer variable node; the waiting layer variable node is an even-numbered layer variable node.

[0063] The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC provided in an embodiment of the present invention includes:

[0064] The control unit reads two layers of variable nodes from the LLR memory, respectively passes through the shift network and enters the calculation unit, interacts with the corresponding check nodes, and obtains updated variable nodes.

[0065] like Figure 2 As shown, the double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC provided in an embodiment of the present invention includes the following steps:

[0066] Divide each layer of the 5G basic check matrix into odd layers and even layers, decode each adjacent odd layer and even layer at the same time, and group the adjacent odd layers and even layers into one group;

[0067] The calculation unit of the first calculation layer inputs the variable nodes required for the calculation of this layer, and immediately calculates and outputs the updated variable nodes. The waiting layer of the non-orthogonal group first inputs the non-conflicting variable nodes and waits, and starts to output the updated variable nodes after the calculation unit of the first calculation layer finishes the calculation. The calculation unit of the waiting layer continues to input the remaining conflicting variable nodes and starts calculation. The waiting layer of the orthogonal group calculates at the same time as the first calculation layer and the waiting layer, and there is no need to input waiting in between.

[0068] Each layer of calculation of the 5G LDPC dual-layer scheduling decoder provided by the embodiment of the present invention adopts a block parallel structure.

[0069] The embodiment of the present invention provides that the adjacent odd-numbered layers and even-numbered layers are grouped into one group, including: the two layers of each group are divided into a first-calculated layer and a waiting layer; the odd-numbered layer is the first-calculated layer; and the even-numbered layer is the waiting layer.

[0070] The step S102 provided by the embodiment of the present invention also includes: during decoding scheduling, rearranging the input and output order of the variable nodes of each layer.

[0071] The embodiment of the present invention provides a method for rearranging the input and output order of the variable nodes of each layer, including:

[0072] The input order of the first calculation layer of all groups is adjusted to first input the variable nodes that do not conflict with the previous group, and then input other variable nodes.

[0073] The input order of the waiting layer of the non-orthogonal group is adjusted to first input the variable nodes that have no conflict with the first calculation layer of the current group, then input the inter-group conflicting variable nodes that conflict with the previous group, wait for the first calculation layer to update the conflicting variable nodes, and finally input the intra-group conflicting variable nodes.

[0074] The input order of the waiting layer of the orthogonal group is adjusted to first input the variable nodes that do not conflict with the previous group, and then input other variable nodes, without waiting in between.

[0075] The output order of the first calculation layer of the non-orthogonal group is adjusted to first output the conflicting variable nodes within the group that conflict with the waiting layer of the group, and then output other variable nodes.

[0076] The output order of the first calculation layer of the orthogonal group is adjusted to output the inter-group conflicting variable nodes that conflict with the next group first, and then output other variable nodes.

[0077] The output order of the waiting layer of all groups is adjusted to output the inter-group conflicting variable nodes that conflict with the next group first, and then output other variable nodes.

[0078] The rearrangement of the input and output order of the variable nodes of each layer provided by the embodiment of the present invention also includes: the current group first outputs the variable nodes that conflict with the next group.

[0079] The technical solution of the present invention is further described below in conjunction with specific embodiments.

[0080] 1. System model

[0081] The LPDC double-layer decoder structure is as follows: Figure 1 As shown, the control unit reads two layers of variable nodes from the LLR memory, respectively passes through two shift networks and enters the calculation unit, interacts with the corresponding check nodes, and finally obtains the updated variable nodes.

[0082] Each layer of the basic matrix is ​​divided into odd layers and even layers. Each adjacent odd layer and even layer are decoded at the same time, and the adjacent odd layers and even layers are divided into a group. For example, the first layer and the second layer of the first group can be decoded at the same time, and the third layer and the fourth layer of the second group can be decoded at the same time. Each layer calculation adopts a block parallel structure with a maximum parallelism of 384. At the same time, the two layers of each group are divided into a first calculation layer and a waiting layer for easy distinction.

[0083] The idea of ​​two-layer scheduling is that the calculation layer and the waiting layer input their own variable nodes at the same time. When encountering conflicting variable nodes, such as Figure 2 , the conflicting variable nodes first enter the first calculation layer for update, and the waiting layer stops inputting. After the waiting first calculation layer is finished, the updated conflicting variable nodes continue to be input into the waiting layer to update the variable nodes. Tables 1 and 2 are the variable node indexes of each layer of BG1 and BG2, and Tables 3 and 4 are the conflicting variable nodes between adjacent layers of each group of BG1 and BG2. Among them, groups 1 to 10 in BG1 are non-orthogonal groups, and groups 11 to 23 are orthogonal groups. Groups 1 to 10 in BG2 are non-orthogonal groups, and groups 11 to 21 are orthogonal groups. It can be seen from Tables 3 and 4 that in double-layer calculation, under normal input order, the groups in the non-orthogonal area (groups 1 to 10) will bring a large amount of input and output delays due to the influence of conflicting variable nodes. At the same time, it can be seen from Tables 5 and 6 that there are also a large number of conflicting variable nodes between groups. Under normal output order, each group will bring a large amount of input and output delays due to the influence of conflicting variable nodes between groups. Therefore, during the design, the input and output order of the variable nodes of each group will be rearranged, and there will be different arrangement strategies for groups in orthogonal areas and groups in non-orthogonal areas.

[0084] It is observed that only the row weight difference between the 5th and 6th layers of BG1 is large, where the row weight of the 5th layer is 3 and the row weight of the 6th layer is 8, and the first two variable nodes of the 5th layer are conflicting variable nodes. If the 6th layer is considered to be the first calculation layer, the 5th layer needs to wait for a lot of extra time to get the updated conflicting variable nodes of the 6th layer. If the 5th layer is used as the first calculation layer and the 6th layer is used as the waiting layer, when the 5th layer outputs the updated conflicting variable node, due to the large row weight of the 6th layer, only a small amount of waiting clock consumption will be generated, and the time utilization efficiency is maximized.

[0085] The difference in row weight between adjacent layers of other groups is not large, and the extra clock consumption of odd or even layers as the first-calculation layer is not much different. Therefore, considering the situation of all groups, all odd layers in BG1 and BG2 are used as the first-calculation layer, and all even layers are used as the waiting layer.

[0086] Table 1 Node index and row weight of variables at each layer of BG1

[0087]

[0088]

[0089] Table 2 Node index values ​​and row weights of variables at each layer of BG2

[0090]

[0091]

[0092] Table 3 Conflicting variable nodes between adjacent layers of BG1

[0093]

[0094]

[0095] Table 4 Conflict variable nodes between adjacent layers of BG2

[0096]

[0097]

[0098] Table 5 Variable nodes of intergroup conflict in BG1

[0099]

[0100] Table 6 Variable nodes of inter-group conflict in BG2

[0101]

[0102]

[0103] 2. Input and output order of non-orthogonal group variable nodes

[0104] The following takes the 8th and 9th groups in BG1 as an example to describe the input and output order arrangement strategy of the variable nodes of each layer of the non-orthogonal group. The original index order of the variable nodes of each layer of the 8th and 9th groups is as follows:

[0105] Group 8:

[0106] 15th floor: 1, 3, 16, 17, 18, 22, 37

[0107] 16th floor: 1, 2, 11, 14, 19, 26, 38

[0108] Group 9:

[0109] 17th floor: 2, 4, 12, 21, 23, 39

[0110] 18th floor: 1, 15, 17, 18, 22, 40

[0111] As for the input and output order within the group, it is observed that only the 15th and 16th layers of the 8th group have a conflict of variable nodes with index value 1, while the 9th group does not have it. Therefore, the input order of the variable nodes of the 15th and 16th layers is first rearranged as follows:

[0112] 15th floor: 1, 3, 16, 17, 18, 22, 37

[0113] 16th floor: 2, 11, 14, 19, 26, 38, 1

[0114] The rearrangement strategy is to put the conflicting nodes in the 16th layer at the last input, so there is no conflict in the first 6 clock inputs of the 8th group of double-layer calculations. At the 7th clock, only the 15th layer inputs the variable node value with an index value of 37, and the 16th layer waits. When the 15th layer calculation is completed and the updated variable nodes begin to be output, the rule of outputting the variable nodes that conflict with the waiting layer first is followed. Therefore, when outputting, the variable node with an index value of 1 will be output first. While this variable node is sent to the variable node storage module, it will also be sent to the waiting layer calculation unit to start the 16th layer variable node calculation. This input method can ensure that the delay caused by input is reduced without affecting the calculation results.

[0115] For the input and output order between groups, it is observed that the conflicting variable nodes of the 8th and 9th groups are 1, 2, 17, 18, and 22. Considering that when the decoder is calculating, the variable node input and output of each layer must pass through a shifter respectively, each shifter consumes 2 clocks, and the calculation waiting time between each layer of variable nodes is 3 clocks, that is, the updated variable node result of the waiting layer needs to wait for (the number of conflicting variable nodes + 6) clocks more than the normal situation. At the same time, since the first calculation layer of the non-orthogonal group can obtain the updated variable node result faster than the waiting layer, as long as the (number of conflicting variable nodes in the group + 6) of the current group is greater than the row weight value of the first calculation layer of this group, it can meet the requirement that when the calculation unit of the waiting layer outputs the updated variable node, the calculation unit of the first calculation layer has output all the updated variable nodes of this layer. Therefore, when designing, it is only necessary to count the conflicting variable nodes between the waiting layer of the current group and the first calculation layer and the waiting layer of the next group. From Tables 1 to 4, it can be seen that the non-orthogonal groups (groups 1 to 10) in BG1 and BG2 all meet this condition. The conflicting variable nodes between the waiting layer in the 8th group and the next group are 1 and 2. To ensure the highest system throughput and the highest working efficiency of the computing unit, when the computing unit completes the calculation of the current group, it starts to receive the variable nodes of the next group at the same time. Therefore, the waiting layer of the 8th group will first update variable nodes 1 and 2 and then update other variable nodes. The 9th group will first input variable nodes that do not conflict with the 8th group, and finally input variable nodes 1 and 2. This can satisfy the fact that the waiting layer of the 8th group outputs the updated variable nodes while starting to input the variable nodes of the 9th group without any conflicts. That is, the variable nodes input by the 9th group are the updated variable nodes. Finally, the variable nodes of the 8th and 9th groups are input in the same order.

[0116] 15th floor: 1, 3, 16, 17, 18, 22, 37

[0117] 16th floor: 2, 11, 14, 19, 26, 38, 1

[0118] 17th floor: 4, 12, 21, 23, 29, 2

[0119] 18th floor: 15, 17, 18, 22, 40, 1

[0120] Output order of variable nodes in groups 8 and 9

[0121] 15th floor: 1, 3, 16, 17, 18, 22, 37

[0122] 16th floor: 1, 2, 11, 14, 19, 26, 38

[0123] 17th floor: 2, 4, 12, 21, 23, 29

[0124] 18th floor: 1, 15, 17, 18, 22, 40

[0125] From this, we can deduce the order of variable node input and output in non-orthogonal groups in BG1 and BG2

[0126] Table 7 BG1 rearranges the order of input and output of non-orthogonal group variable nodes

[0127]

[0128]

[0129] Table 8 Input and output order of non-orthogonal group variable nodes after BG2 rearrangement

[0130]

[0131] 3. Orthogonal group variable node input and output order

[0132] Take groups 18 and 19 in BG1 as an example to explain the input-output relationship of orthogonal groups. Since there are no conflicting variable nodes in the orthogonal groups, the waiting layer and the pre-calculation layer are calculated at the same time, and there is no additional clock delay. When considering the input-output waiting relationship between groups, it is necessary to consider the conflict relationship between the pre-calculation layer and the waiting layer of the current group and the next group. The variable node indexes of groups 18 and 19 are as follows: group 18

[0133] 35th floor: 1, 8, 16, 18, 57

[0134] 36th floor: 2, 7, 13, 23, 58

[0135] Group 19:

[0136] 37th floor: 1, 15, 16, 19, 59

[0137] 38th floor: 2, 14, 26, 60

[0138] The variable nodes 1 and 16 in the first calculation layer of group 18 conflict with the first calculation layer of the next group, and the variable node 2 in the waiting layer conflicts with the waiting layer of the next group. At the same time, since the variable node 1 in the first calculation layer and the variable node 2 in the waiting layer can be updated at the same time, in order to reduce clock consumption, each group will input the variable nodes that conflict with the previous group last when inputting, and will give priority to outputting the variable nodes that conflict with the next group when outputting. Therefore, the input and output order of the output variable nodes of groups 18 and 19 after rearrangement is as follows:

[0139] 18 groups, 35 floors,

[0140] Input order: 1, 8, 16, 18, 57, Output order: 1, 16, 8, 18, 57

[0141] 18 groups, 36 floors

[0142] Input order: 2, 7, 13, 23, 58, Output order: 2, 7, 13, 23, 58

[0143] 19 groups, 37 floors

[0144] Input order: 15, 19, 59, 1, 16, Output order: 1, 15, 16, 19, 59

[0145] 19 groups, 38 floors

[0146] Input order: 14, 24, 60, 2, Output order: 2, 14, 24, 60

[0147] The specific timing relationship between Group 18 and Group 19 is as follows Figure 3 shown.

[0148] Thus, the input and output order of the variable nodes of each layer of the orthogonal region after the rearrangement of BG1 and BG2 in Table 9 and Table 10 can be obtained. After the rearrangement, there is no need to wait for the clock between the groups in the orthogonal region. As long as the current group obtains the calculation result, the variable nodes of the next group can be input, so that the variable nodes of the current group output and the variable nodes of the next group input are carried out at the same time, which is more in line with the pipeline design of the hardware, thereby improving the throughput of the decoder.

[0149] Table 9 BG1 rearranges the order of input and output of group variable nodes in orthogonal regions

[0150]

[0151] Table 10 BG2 rearranges the order of input and output of group variable nodes in orthogonal regions

[0152]

[0153]

[0154] 2. Application Examples: In order to prove the creativity and technical value of the technical solution of the present invention, this section provides application examples of the technical solution of the claims on specific products or related technologies.

[0155] The present invention provides an information data processing terminal, which is used to execute the double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC.

[0156] The present invention provides a double-layer scheduling decoder based on 5G LDPC that implements a double-layer scheduling method of a double-layer scheduling decoder based on 5G LDPC, and can be applied to 5G high-speed communication.

[0157] The present invention provides a 5G LDPC decoder that is compatible with multiple code rates, such as 1 / 3, 1 / 2, 2 / 3, 3 / 4, 5 / 6, 8 / 9, and can be flexibly switched.

[0158] The present invention provides a 5G LDPC decoder supporting multiple code lengths, with the shortest supported code length being 40 and the longest supported code length being 25344.

[0159] The present invention provides a 5G LDPC decoder that supports all matrices of BG1 and BG2 at the same time, and supports all boost value sizes, with the minimum boost value being 2 and the maximum being 384.

[0160] The present invention provides a double-layer scheduling scheme based on 5G LDPC decoding, which effectively reduces the probability of conflict between double-layer decoding variable nodes while ensuring performance.

[0161] The present invention provides a system structure of a double-layer scheduling decoder based on 5G LDPC, which realizes double-layer decoding without occupying too much storage resources.

[0162] The present invention provides a decoder pipeline solution based on 5G LDPC, that is, changing the order of input and output variable nodes to pipeline node input, calculation and output, reduce intermediate delays, and further improve the decoder throughput.

[0163] The present invention provides a double-layer scheduling decoding scheme based on LDPC, which is applicable to all LDPC codes including 5G LDPC codes.

[0164] The present invention provides a sustainable 5G LDPC decoder, which is not only applicable to the basic matrices BG1 and BG2 in the current 5G standard, but also applicable to the future BG3 and BG4.

[0165] 3. Evidence of the effects of the embodiments. The embodiments of the present invention have achieved some positive effects during the development or use process, and indeed have great advantages over the prior art. The following content is described in conjunction with the data, charts, etc. of the test process.

[0166] 1. Decoder performance analysis

[0167] 1.1 Throughput

[0168] The calculation formula for throughput is as follows

[0169]

[0170] Where N LDPC represents the length of the encoded LDPC code, cycle represents the number of clocks required for each iteration, and n iterrepresents the number of iterations, and f represents the clock frequency.

[0171] Under the same conditions, the throughput performance comparison between the double-layer scheduling LDPC decoder designed by the present invention and the single-layer scheduling LDPC decoder is as follows.

[0172] Table 11 Comparison of 8 / 9 bitrate throughput

[0173] Performance Indicators Traditional single-layer scheduling The present invention Code length 9000 9000 Bitrate 8 / 9 8 / 9 Operating frequency 200MHZ 200MHZ Iterations 8 8 Throughput 2.44Gbps 4.89Gbps

[0174] Table 12 1 / 3 bitrate throughput comparison

[0175] Performance Indicators Traditional single-layer scheduling The present invention Code length 25344 25344 Bitrate 1 / 3 1 / 3 Operating frequency 200MHZ 200MHZ Iterations 8 8 Throughput 480Mbps 1.92Gps

[0176] It can be seen from the table that, regardless of high or low bit rates, the throughput of the double-layer scheduling LDPC decoder designed by the present invention is significantly improved compared to the single-layer scheduling decoder, especially at low bit rates. At 1 / 3 bit rate, the throughput of the double-layer scheduling decoder designed by the present invention is more than 3 times that of the single-layer scheduling decoder. At the same time, the double-layer scheduling decoder designed by the present invention is compatible with multiple bit rates, and can be manually switched between 1 / 3 and 8 / 9 bit rates. It also supports all 51 boost values ​​under the basic matrix BG1 and the basic matrix BG2, with a minimum boost value of 2 and a maximum of 384. Therefore, the double-layer scheduling decoder designed by the present invention has good versatility and configurability.

[0177] 1.2 Resource Occupancy

[0178] The decoder resource usage is as follows

[0179] Table 13 Resource occupancy of dual-layer scheduling decoder

[0180] resource Single-layer scheduling decoding The present invention LUT 136640 273280 LUTRAM 1560 4149 FF 46608 73748 BRAM 177 201 DSP 1 2 IO 2 2 BUFG 5 8 PLL 1 1

[0181] Since the double-layer scheduling decoder designed in the present invention needs to read double-layer variable nodes and calculate simultaneously, it will consume more BRAM resources and LUT resources in terms of resource occupation. However, since the access addresses of the variable nodes are reasonably allocated in the design, the total resources do not increase exponentially.

[0182] 1.3 Simulation Results

[0183] The following is a comparison between the floating-point simulation performance of the LDPC code and the fixed-point hardware simulation performance of the double-layer scheduling. It can be observed that the LDPC decoder designed under the present invention hardly loses the performance of the LDPC code under the double-layer scheduling.

[0184] It can be seen from the simulation results and throughput results that the decoder of the present invention can have a higher throughput for high and low code rate LDPC codes while ensuring performance, meeting the basic requirements of 5G communications.

[0185] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0186] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A dual-layer scheduling decoder based on 5G LDPC, characterized in that: The dual-layer scheduling decoder based on 5G LDPC includes: LLR memory, global control unit, pre-calculation layer control unit, waiting layer control unit, two groups of shift networks, 768 calculation units and check node storage unit; A global control unit controls the current decoding group and the number of decoding iterations; The first calculation layer control unit and the waiting layer control unit are used to control the input sequence of the two-layer variable nodes input from the LLR memory to the calculation unit and the output sequence of the updated variable nodes written to the LLR memory, and read the relevant check nodes from the check node storage unit; Two groups of shift networks, used for shifting two layers of variable nodes respectively; The computing unit is used for the two-layer variable nodes to interact with the corresponding verification and obtain the updated variable nodes; The two layers of variable nodes include: a first calculation layer variable node and a waiting layer variable node; the first calculation layer variable node is an odd-numbered layer variable node; the waiting layer variable node is an even-numbered layer variable node.

2. A double-layer scheduling method for a double-layer scheduling decoder based on 5G LDPC applied to the double-layer scheduling decoder based on 5G LDPC as claimed in claim 1, characterized in that: The dual-layer scheduling decoder dual-layer scheduling method based on 5G LDPC includes: The control unit reads two layers of variable nodes from the LLR memory, respectively passes through the shift network and enters the calculation unit, interacts with the corresponding check nodes, and obtains updated variable nodes.

3. The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as claimed in claim 2, characterized in that: The dual-layer scheduling method of the dual-layer scheduling decoder based on 5G LDPC includes the following steps: Step 1: Divide each layer of the 5G basic check matrix into odd layers and even layers, decode each adjacent odd layer and even layer at the same time, and group the adjacent odd layers and even layers into one group; Step 2: The calculation unit of the first calculation layer inputs the variable nodes required for the calculation of this layer, and immediately calculates and outputs the updated variable nodes; for non-orthogonal groups, the first calculation layer and the waiting layer are not calculated at the same time due to the existence of conflicting variable nodes; the conflicting variable nodes first enter the calculation unit of the first calculation layer for calculation, and the waiting layer first inputs the variable nodes without conflict, and outputs the updated variable nodes after the calculation of the first calculation layer is completed, and the calculation unit of the waiting layer continues to input the conflicting variable nodes and starts calculation; for orthogonal groups, there are no conflicting variable nodes in the first calculation layer and the waiting layer, and they are calculated at the same time; Step 3: After the calculation of the waiting layer is completed, when the conflicting variable nodes and other variable nodes are output and updated, the decoding control unit controls the first calculation layer and the waiting layer to input the next group of their respective variable nodes and start the calculation of the next group; Step 4: After all groups are calculated, the number of decoding iterations is increased by 1. If the maximum number of decoding iterations is reached, the decoder ends the calculation and outputs the decoding result. Otherwise, steps 2 and 3 are repeated.

4. The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as claimed in claim 3, characterized in that: Each layer of the 5G basic check matrix adopts a block parallel structure.

5. The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as claimed in claim 3, characterized in that: The step of grouping adjacent odd-numbered layers and even-numbered layers into one group includes: the two layers of each group are divided into a first-calculated layer and a waiting layer; the odd-numbered layer is the first-calculated layer; and the even-numbered layer is the waiting layer.

6. The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as claimed in claim 3, characterized in that: The step 2 also includes: during decoding scheduling, rearranging the input and output order of the variable nodes of each layer.

7. The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as claimed in claim 6, characterized in that: The rearrangement of the input and output order of the variable nodes of each layer includes: The input order of all groups' first calculation layers is adjusted to first input the variable nodes that do not conflict with the previous group, and then input other variable nodes; The input order of the waiting layer of the non-orthogonal group is adjusted to first input the variable nodes that have no conflict with the first calculation layer of the group, then input the inter-group conflicting variable nodes that conflict with the previous group, wait for the first calculation layer to update the conflicting variable nodes, and finally input the intra-group conflicting variable nodes; The input order of the waiting layer of the orthogonal group is adjusted to first input the variable nodes that do not conflict with the previous group, and then input other variable nodes, without waiting in between; The output order of the first calculation layer of the non-orthogonal group is adjusted to output the conflicting variable nodes in the group that conflict with the waiting layer of the group first, and then output other variable nodes; The output order of the first calculation layer of the orthogonal group is adjusted to output the inter-group conflicting variable nodes that conflict with the next group first, and then output other variable nodes; The output order of the waiting layer of all groups is adjusted to output the inter-group conflicting variable nodes that conflict with the next group first, and then output other variable nodes.

8. The double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as claimed in claim 6, characterized in that: The rearrangement of the input and output order of the variable nodes of each layer also includes: the current group first outputs the variable nodes that conflict with the next group.

9. An information data processing terminal, characterized in that: The information data processing terminal is used to execute the double-layer scheduling method of the double-layer scheduling decoder based on 5G LDPC as described in any one of claims 1-6.

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