A semiconductor structure and a method of fabricating the same
By using a multilayer heterojunction structure and p-type semiconductor design, the problems of low 2DEG concentration and low threshold voltage in semiconductor devices were solved, resulting in reduced resistance and increased threshold voltage, thus improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ENKRIS SEMICON
- Filing Date
- 2019-12-31
- Publication Date
- 2026-06-05
AI Technical Summary
Existing semiconductor devices suffer from problems such as high resistance and low threshold voltage due to low 2DEG concentration.
A multilayer heterojunction structure is adopted, including a channel layer and a barrier layer stacked together, combined with first and second p-type semiconductor materials. The first p-type semiconductor is set in the gate region of the heterojunction to deplete the 2DEG, and the gate leakage current is reduced and the threshold voltage is increased through an in-situ insulating layer and a transition layer.
The increased 2DEG concentration reduced resistance, enhanced device reliability and operating current, and improved threshold voltage and gate control over the channel.
Smart Images
Figure CN114830351B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more specifically to a semiconductor structure and its fabrication method. Background Technology
[0002] Currently, normally-off devices typically have a layer of gallium nitride doped with p-type impurities formed under the gate to deplete the two-dimensional electron gas (2DEG) under the gate. When no forward voltage is applied to the gate, the concentration of 2DEG under the gate is 0, thus achieving normally-off operation.
[0003] However, the above structure has the following two problems:
[0004] 1. The low concentration of 2DEG results in a higher resistance of the device when it is turned on.
[0005] 2. The threshold voltage is low. Summary of the Invention
[0006] In view of this, embodiments of the present invention aim to provide a semiconductor structure that solves the problems of high resistance and low threshold voltage of the above-mentioned devices when turned on.
[0007] One embodiment of this application discloses a semiconductor structure comprising: a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially; a first p-type semiconductor located in the gate region of the heterojunction and extending to the bottom of the heterojunction; and a second p-type semiconductor located above the gate region of the heterojunction.
[0008] In another embodiment, the semiconductor structure further includes: a source disposed above the heterojunction source region, a drain disposed above the heterojunction drain region, and a gate disposed above the heterojunction gate region.
[0009] In another embodiment, the materials of the first p-type semiconductor, the second p-type semiconductor, and the heterojunction include gallium nitride-based materials.
[0010] In another embodiment, the semiconductor structure further includes a substrate located below the heterojunction.
[0011] In another embodiment, a nucleation layer and a buffer layer are sequentially disposed between the substrate and the heterojunction.
[0012] In another embodiment, a regrowth layer is provided between the first p-type semiconductor and the heterojunction.
[0013] In another embodiment, the semiconductor structure further includes an in-situ insulating layer and a transition layer, the in-situ insulating layer being disposed on the heterojunction, the transition layer being disposed on the in-situ insulating layer, and the second p-type semiconductor penetrating the in-situ insulating layer and the transition layer, and directly contacting the heterojunction.
[0014] In another embodiment, the semiconductor structure further includes an in-situ insulating layer and a transition layer, the in-situ insulating layer being disposed on the heterojunction, the transition layer being disposed on the in-situ insulating layer, and the second p-type semiconductor covering the transition layer and penetrating a portion of the in-situ insulating layer and a portion of the transition layer to directly contact the heterojunction.
[0015] In another embodiment, the semiconductor structure further includes an in-situ insulating layer and a transition layer, the in-situ insulating layer being disposed on the heterojunction, the transition layer covering the in-situ insulating layer and penetrating a portion of the in-situ insulating layer to contact the heterojunction, and the second p-type semiconductor being disposed on the transition layer.
[0016] In another embodiment, the semiconductor structure further includes an insulating dielectric layer located above the second p-type semiconductor and the heterojunction, and below the gate.
[0017] One embodiment of this application also discloses a method for fabricating a semiconductor structure, comprising: fabricating a heterojunction, the heterojunction comprising at least two sets of channel layers and barrier layers stacked sequentially; fabricating a groove in the gate region of the heterojunction, the groove extending to the bottom of the heterojunction, and filling the groove with a first p-type semiconductor; and fabricating a second p-type semiconductor and a gate sequentially above the gate region of the heterojunction.
[0018] In another embodiment, the method for fabricating the above-mentioned semiconductor structure further includes fabricating a source and a drain in the source region and drain region of the heterojunction, respectively.
[0019] In another embodiment, the method for fabricating the above-described semiconductor structure further includes fabricating a regrowth layer above the heterojunction before filling the groove with the first p-type semiconductor.
[0020] In another embodiment, the method for fabricating the above-mentioned semiconductor structure further includes, before fabricating a groove in the gate region of the heterojunction, first fabricating an in-situ insulating layer and a transition layer above the heterojunction; and then removing the in-situ insulating layer and the transition layer above the gate region of the heterojunction.
[0021] In another embodiment, the method for fabricating the above-described semiconductor structure further includes: before fabricating a groove in the gate region of the heterojunction, first fabricating an in-situ insulating layer above the heterojunction; removing the in-situ insulating layer above the gate region of the heterojunction; and fabricating a transition layer to cover the in-situ insulating layer and the exposed heterojunction.
[0022] The semiconductor structure provided in this invention, by setting at least two heterojunctions including stacked channel layers and barrier layers, utilizes multiple channel layers and barrier layers to realize multiple 2DEGs to increase the 2DEG concentration, thereby reducing resistance; wherein the gate region of the heterojunction is provided with a first p-type semiconductor, the 2DEG can be depleted by the p-type semiconductor material in the first p-type semiconductor to achieve normally off state and increase the threshold voltage; the design of the regenerated layer can improve the reliability of the device; the in-situ insulating layer and transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device, so the thickness of the barrier layer in the heterojunction can be smaller, thereby increasing the threshold voltage; in addition, due to the setting of the in-situ insulating layer, the sheet resistance can be reduced, the concentration of two-dimensional electron gas can be increased, the gate's control capability over the channel can be improved, and the operating current can be increased. Attached Figure Description
[0023] Figure 1 The image shown is a perspective view of a semiconductor structure provided in an embodiment of the present invention.
[0024] Figure 2 The following is an embodiment. Figure 1 A schematic diagram of the cross-sectional structure along A1-A2.
[0025] Figure 3 The following is an embodiment. Figure 1 A schematic diagram of the cross-sectional structure along B1-B2.
[0026] Figure 4 The following is another embodiment. Figure 1 A schematic diagram of the cross-sectional structure along B1-B2.
[0027] Figure 5 The diagram shows a cross-sectional view of a semiconductor structure along B1-B2, as provided in another embodiment of this application.
[0028] Figure 6 The diagram shown is a cross-sectional view of a semiconductor structure along B1-B2 provided in another embodiment of this application.
[0029] Figure 7 The diagram shown is a cross-sectional view of a semiconductor structure along B1-B2 provided in another embodiment of this application.
[0030] Figure 8 The image shown is a perspective view of a semiconductor structure provided in another embodiment of this application.
[0031] Figures 9a-9c The diagram shown is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention.
[0032] Figure 10 The image shown is a perspective view of a semiconductor structure provided in another embodiment of the present invention.
[0033] Figure 11 The image shown is a perspective view of a semiconductor structure provided in another embodiment of the present invention.
[0034] Figures 12a-12c The diagram shown is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention.
[0035] Figure 13 The diagram shown is a three-dimensional schematic diagram of a semiconductor structure provided in another embodiment of this application. Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] Furthermore, in exemplary embodiments, since the same reference numerals denote the same components having the same structure or the same steps of the same method, if one embodiment has been described by way of example, then in other exemplary embodiments only structures or methods different from those described in the embodiment will be described.
[0038] Throughout the specification and claims, when a component is described as being “connected” to another component, that component may be “directly connected” to the other component or “electrically connected” to the other component via a third component. Furthermore, unless explicitly stated otherwise, the term “comprising” and its corresponding terms should be understood only to include the stated component and not to exclude any other component.
[0039] Figure 1 The image shown is a perspective view of a semiconductor structure provided in an embodiment of the present invention. Figure 2 As shown Figure 1 A schematic diagram of the cross-sectional structure along A1-A2. Figure 3 As shown Figure 1 A schematic diagram of the cross-sectional structure along B1-B2. (See attached diagram.) Figure 1 , Figure 2 , Figure 3As shown, the semiconductor structure includes: a heterojunction 1, which includes at least two sets of stacked channel layers 11 and barrier layers 12, and a two-dimensional electron gas can be formed between the channel layers 11 and the barrier layers 12; wherein a first p-type semiconductor 2 is disposed in the gate region of the heterojunction 1, and the first p-type semiconductor 2 extends to the bottom of the heterojunction 1; a gate 5 and a second p-type semiconductor 6 are disposed above the gate region of the heterojunction 1, wherein the second p-type semiconductor 6 is located between the gate 5 and the heterojunction 1. The semiconductor structure of this embodiment may further include a source 3 disposed in the source region of the heterojunction 1, and a drain 4 disposed in the drain region of the heterojunction 1.
[0040] The arrangement of multiple channel layers and barrier layers can realize multilayer 2DEG to increase the concentration of 2DEG. The arrangement of the first p-type semiconductor and the second p-type semiconductor can deplete the two-dimensional electron gas in the gate region of heterojunction 1 to achieve a normally off state.
[0041] In this embodiment, three first p-type semiconductors 2 are provided. It should be understood that the number of first p-type semiconductors in this application embodiment can be selected according to the needs of the actual application scenario, and this application does not impose any special restrictions on this.
[0042] like Figure 2 and Figure 3 In the illustrated embodiment, the first p-type semiconductor 2 completely penetrates the heterojunction 1, thereby realizing the extension of the first p-type semiconductor 2 to the bottom of the heterojunction 1 as described in this application. It should be understood that in other embodiments, the first p-type semiconductor 2 does not necessarily completely penetrate the heterojunction 1; it can be very close to the bottom of the heterojunction 1, as long as it can achieve the normally off state required by the enhancement-mode device when the semiconductor structure of this application is applied.
[0043] The aforementioned heterojunction 1, the first p-type semiconductor 2, and the second p-type semiconductor 6 all include gallium nitride-based materials.
[0044] In the above embodiments, the cross-section of the first p-type semiconductor 2 is rectangular; however, this application does not impose any particular limitation on this. In other embodiments, such as... Figure 4 As shown, Figure 4 The diagram shown is a cross-sectional view of a semiconductor structure along B1-B2 provided in another embodiment of the present invention. The cross-sectional shape of the first p-type semiconductor 2 may also be, for example, trapezoidal. This application does not impose any particular limitation on the specific cross-sectional shape of the first p-type semiconductor 2.
[0045] Figure 5 The diagram shows a cross-sectional view of a semiconductor structure along B1-B2, according to another embodiment of this application. The semiconductor structure may further include a substrate 8 located below the heterojunction 1 for supporting the heterojunction 1. Figure 6The diagram shown is a cross-sectional view of a semiconductor structure along B1-B2 according to another embodiment of this application. Figure 6 As shown, a nucleation layer 9 and a buffer layer 10 are disposed between the substrate 8 and the heterojunction 1. Compared with directly fabricating the heterojunction 1 on the substrate, this improves the production quality of the heterojunction 1. In one embodiment, the buffer layer 10 includes one or more of the following materials: aluminum nitride, gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride. In one embodiment, the nucleation layer 9 may include one or more of the following materials: aluminum nitride, gallium nitride, and aluminum gallium nitride. It should be understood that the materials of the buffer layer in this application embodiment can be selected according to the needs of the actual application scenario. This application embodiment does not limit the specific materials of the buffer layer.
[0046] Figure 7 The diagram shown is a cross-sectional view of a semiconductor structure along B1-B2 according to another embodiment of this application. Figure 7 As shown, a regeneration layer 7 can be disposed between the first p-type semiconductor 2 and the heterojunction 1. The regeneration layer 7 is also a gallium nitride-based material, and can further be the same as the material composition of the barrier layer 12 (for example, it can be an aluminum gallium nitride material). By disposing of the regeneration layer 7, the reliability of the device can be improved.
[0047] Figure 8 The image shown is a perspective view of a semiconductor structure provided in another embodiment of this application. Figure 8 As shown, the semiconductor structure may further include an insulating dielectric layer 20, which is located above the second p-type semiconductor 6 and the heterojunction 1, and below the gate 5. The insulating dielectric layer 20 may be, for example, SiO2, SiN, etc.
[0048] Figures 9a-9c The diagram shown is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention. Figure 9a The image shown is a perspective view of a semiconductor structure according to another embodiment of this application. Figure 9b As shown Figure 9a The diagram shows a cross-sectional view of the semiconductor structure along line A1-A2. Figure 9c As shown Figure 9a The diagram shows a cross-sectional view of the semiconductor structure along B1-B2. Figures 9a-9cAs shown, the semiconductor structure may further include an in-situ insulating layer 13 and a transition layer 14. The in-situ insulating layer 13 is disposed on the heterojunction 1, and the transition layer 14 is disposed on the in-situ insulating layer 13. The second p-type semiconductor 6 penetrates the in-situ insulating layer 13 and the transition layer 14 and is in direct contact with the heterojunction 1. The material of the in-situ insulating layer 13 includes at least one of SiN and SiAlN. The material of the transition layer 14 includes at least one of AlN, SiAlN, and AlGaN. P-type semiconductors cannot be directly fabricated with high quality on the in-situ insulating layer. The provision of the transition layer can improve the high-quality fabrication of p-type semiconductors. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device. Therefore, the thickness of the barrier layer in the heterojunction can be designed to be smaller, thereby increasing the threshold voltage. In addition, due to the provision of the in-situ insulating layer, the sheet resistance can be reduced, the concentration of two-dimensional electron gas can be increased, the gate's control capability over the channel can be improved, and the operating current can be increased. Figure 10 As shown, Figure 10 This is a perspective view of the semiconductor structure in another embodiment. Due to the provision of the in-situ insulating layer 13 and the transition layer 14, the second p-type semiconductor 6 can be located on the transition layer 14 in the gate region, or in the transition layer 14 in the region between the source and the gate, and in the region between the drain and the gate. That is, the second p-type semiconductor 6 covers the transition layer 14 and penetrates part of the in-situ insulating layer 13 and part of the transition layer 14 to directly contact the heterojunction 1. In this way, when the second p-type semiconductor 6 is fabricated on the transition layer 14, it is not necessary to remove the second p-type semiconductor 6 in the region other than the gate region, which reduces the process difficulty.
[0049] Figure 11 This is a perspective view of another embodiment of the semiconductor structure, and... Figures 9a to 9c The difference in the embodiment shown is that an insulating dielectric layer 20 is disposed above the transition layer 14 and the second p-type semiconductor 6, and the insulating dielectric layer 20 is located below the gate 5.
[0050] Figures 12a-12c The diagram shown is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention. Figure 12a The image shown is a perspective view of a semiconductor structure according to another embodiment of this application. Figure 12b As shown Figure 12a The diagram shows a cross-sectional view of the semiconductor structure along line A1-A2. Figure 12c As shown Figure 12a The diagram shows a cross-sectional view of the semiconductor structure along line B1-B2. Figures 9a-9c The difference in the embodiment is that the transition layer 14 covers the in-situ insulating layer 13 and penetrates a portion of the in-situ insulating layer 13 to contact the heterojunction 1, and the second p-type semiconductor 6 is disposed on the transition layer 14.
[0051] Figure 13 The diagram shown is a three-dimensional schematic diagram of a semiconductor structure provided in another embodiment of this application. Figure 13 and Figure 12a The difference in the illustrated embodiment is that an insulating dielectric layer 20 is also provided, located above the second p-type semiconductor 6 and the transition layer 14, and below the gate 5.
[0052] This application also discloses a method for fabricating a semiconductor structure, referring to... Figures 1-3 The preparation method includes:
[0053] Step S1: Prepare heterojunction 1, wherein heterojunction 1 includes at least two sets of channel layers 11 and barrier layers 12 stacked sequentially;
[0054] Step S2: A groove is prepared in the gate region of the heterojunction 1, the groove extending to the bottom of the heterojunction, and a first p-type semiconductor 2 is filled in the groove;
[0055] Step S3: A second p-type semiconductor 6 is fabricated above the gate region of heterojunction 1;
[0056] Step S4: Source 3, drain 4 and gate 5 are fabricated in the source region, drain region and gate region of heterojunction 1, respectively.
[0057] It should be understood that the groove extends to the bottom of the heterojunction, for example... Figures 1-3 As shown, it can penetrate the heterojunction, or it can be infinitely close to the bottom of the heterojunction, but not penetrate it.
[0058] like Figure 7 As shown, in step S2 above, after the groove is fabricated, before filling the groove with a p-type semiconductor, a regenerated layer 7 is first fabricated above the heterojunction. The material of the regenerated layer can be the same as the material of the barrier layer. By setting the regenerated layer 7, the surface loss caused by etching and other processes during the preparation of the groove can be reduced, thereby reducing the impact on the subsequent p-type semiconductor and improving device reliability.
[0059] like Figure 8 As shown, after step S3 and before step S4, step S31 can be added: preparing an insulating dielectric layer 20, located above the second p-type semiconductor 6 and the heterojunction 1.
[0060] Between steps S1 and S2, a step can be added: preparing the in-situ insulating layer 13 and the transition layer 14. Specifically, there are two methods.
[0061] The first type is as follows Figures 9a-9c As shown, a step can be added between steps S1 and S2:
[0062] S210, first prepare an in-situ insulating layer 13 and a transition layer 14 on the heterojunction 1;
[0063] S211, remove the in-situ insulating layer 13 and transition layer 14 above the gate region of heterojunction 1.
[0064] The second type is as follows Figures 12a-12c As shown, a step can be added between steps S1 and S2:
[0065] S220, first prepare an in-situ insulating layer 13 on the heterojunction 1:
[0066] S221, Remove the in-situ insulating layer 13 above the gate region of heterojunction 1;
[0067] S222, a transition layer 14 is prepared above the heterojunction 1 and the in-situ insulating layer 13.
[0068] Furthermore, when the method for fabricating the semiconductor structure of this application includes the above-described steps S210 and S211, or includes steps S220, S221, and S222, such as Figure 11 As shown, in step S31 above, an insulating dielectric layer 20 is prepared, which is located on the transition layer 14 and the second p-type semiconductor 6.
[0069] The in-situ insulating layer 13 is made of at least one of SiN and SiAlN. The transition layer 14 is made of at least one of AlN, SiAlN, and AlGaN. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device, thus the thickness of the barrier layer in the heterojunction can be smaller, thereby increasing the threshold voltage. In addition, due to the setting of the in-situ insulating layer, the sheet resistance can be reduced, the concentration of two-dimensional electron gas can be increased, the gate's control capability over the channel can be improved, and the operating current can be increased. Due to the setting of the in-situ insulating layer 13 and the transition layer 14, the second p-type semiconductor 6 can be located on the transition layer 14 in the gate region, or in the transition layer 14 in the region between the source and the gate, and in the region between the drain and the gate. Thus, when fabricating the second p-type semiconductor 6 on the transition layer 14, the second p-type semiconductor 6 in the region other than the gate region is removed, reducing the process difficulty.
[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications or equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention. It should be understood that the above embodiments can be combined in any way, as long as they meet the inventive purpose of this application.
Claims
1. A semiconductor structure, characterized in that, include: A heterojunction, wherein the heterojunction comprises at least two sets of channel layers and barrier layers stacked sequentially; A first p-type semiconductor located in the gate region of the heterojunction and extending to the bottom of the heterojunction; as well as A second p-type semiconductor located above the gate region of the heterojunction; The semiconductor structure further includes an in-situ insulating layer and a transition layer. The in-situ insulating layer is disposed on the heterojunction, and the transition layer covers the in-situ insulating layer and penetrates a portion of the in-situ insulating layer to contact the heterojunction. The second p-type semiconductor is disposed on the transition layer. The material of the in-situ insulating layer includes at least one of SiN and SiAlN, and the material of the transition layer includes at least one of AlN, SiAlN, and AlGaN.
2. The semiconductor structure according to claim 1, characterized in that, Also includes: The source electrode is disposed above the heterojunction source region, the drain electrode is disposed above the heterojunction drain region, and the gate electrode is disposed above the heterojunction gate region.
3. The semiconductor structure according to claim 1, characterized in that, The materials of the first p-type semiconductor, the second p-type semiconductor, and the heterojunction include gallium nitride-based materials.
4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes a substrate located below the heterojunction.
5. The semiconductor structure according to claim 4, characterized in that, A nucleation layer and a buffer layer are sequentially disposed between the substrate and the heterojunction.
6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, A regeneration layer is provided between the first p-type semiconductor and the heterojunction.
7. The semiconductor structure according to claim 2, characterized in that, It also includes an insulating dielectric layer disposed above the second p-type semiconductor and the heterojunction, and below the gate.
8. A method for fabricating a semiconductor structure, characterized in that, include: A heterojunction is prepared, wherein the heterojunction comprises at least two sets of channel layers and barrier layers stacked sequentially; A groove is formed in the gate region of the heterojunction, the groove extending to the bottom of the heterojunction, and a first p-type semiconductor is filled in the groove; A second p-type semiconductor is sequentially fabricated above the gate region of the heterojunction; The method for fabricating the semiconductor structure, prior to fabricating the groove in the gate region of the heterojunction, further includes: An in-situ insulating layer is prepared on the heterojunction: Remove the in-situ insulating layer above the gate region of the heterojunction; A transition layer is prepared to cover the in-situ insulating layer and the exposed heterojunction, wherein the material of the in-situ insulating layer includes at least one of SiN and SiAlN, and the material of the transition layer includes at least one of AlN, SiAlN, and AlGaN.
9. The preparation method according to claim 8, characterized in that, Also includes: The source, drain, and gate electrodes are fabricated in the source region, drain region, and gate region of the heterojunction, respectively.
10. The preparation method according to claim 8, characterized in that, A regrowth layer is prepared on top of the heterojunction before the first p-type semiconductor is filled into the groove.
11. The preparation method according to any one of claims 8 to 10, characterized in that, After the second p-type semiconductor is fabricated, an insulating dielectric layer is fabricated, such that the insulating dielectric layer is located above the second p-type semiconductor and the heterojunction.