Memory system

Abstract

The present disclosure relates to a memory system including a memory device and a controller. The controller is coupled to the memory device by input / output (I / O) lines. The controller includes an interface component and a virtual power component. The interface component performs a signal training operation for adjusting timing of a clock signal synchronized with test data. The virtual power component performs a virtual power operation while the signal training operation is performed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0014795, filed on February 2, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to a memory system, and more particularly, to a memory system including a non-volatile memory device. Background Technology

[0004] The memory system can be configured to store data provided by the host device in response to a write request from the host device. Furthermore, the memory system can be configured to provide the stored data to the host device in response to a read request from the host device. The host device is an electronic device capable of processing data and may include computers, digital cameras, mobile phones, etc. For operation, the memory system can be installed in the host device or can be manufactured to be connected to and separate from the host device. Summary of the Invention

[0005] In embodiments of this disclosure, a memory system may include a memory device and a controller. The controller may be coupled to the memory device via input / output (I / O) lines. The controller may include an interface component and a dummy power consumption component. The interface component may be configured to perform a signal training operation for adjusting the timing of a clock signal synchronized with test data. The dummy power consumption component may be configured to perform a dummy power consumption operation during the signal training operation.

[0006] In embodiments of this disclosure, a memory system may include a memory device and a controller. The memory device may be coupled to one or more input / output (I / O) lines and one or more virtual I / O lines. The controller may be configured to transmit virtual data via the virtual I / O lines during signal training operations, while test data is transmitted via the I / O lines.

[0007] In embodiments of this disclosure, a memory system may include a memory device and a controller. The controller may be coupled to the memory device via input / output (I / O) lines and may include an error correction code (ECC) component. The ECC component may be configured to perform error correction operations on data transmitted from the memory device via the I / O lines. The ECC component may be configured to perform virtual ECC operations during signal training operations when restricted test data is transmitted via the I / O lines.

[0008] In an embodiment of the disclosure, a system can include a memory device, a plurality of normal input / output (I / O) lines, one or more virtual I / O lines, and a controller. The plurality of normal input / output (I / O) lines can include a particular normal I / O line and remaining normal I / O lines. The controller can be coupled to the memory device through the plurality of normal I / O lines and the virtual I / O line, and configured to transmit test data to the memory device through the plurality of normal I / O lines and simultaneously transmit virtual data to the memory device through the virtual I / O line. The virtual data can be all-flipped data and the test data is flipped less than the all-flipped data. A bit of the test data on the particular normal I / O line at a first point in time can have a different value than a bit of the test data on the particular normal I / O line at a second point in time, while a bit of the test data on the remaining normal I / O lines at the first point in time can be the same as a bit of the test data on the remaining normal I / O lines at the second point in time. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the disclosure.

[0010] Figures 2 to 4 is a diagram illustrating a signal training operation according to an embodiment of the disclosure.

[0011] Figure 5 is a block diagram illustrating a signal training operation according to an embodiment of the disclosure.

[0012] Figure 6 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the disclosure.

[0013] Figure 7 is a diagram illustrating a data processing system including a memory system according to an embodiment of the disclosure.

[0014] Figure 8 is a diagram illustrating a data processing system including a memory system according to an embodiment of the disclosure.

[0015] Figure 9 is a diagram illustrating a network system including a memory system according to an embodiment of the disclosure.

[0016] Figure 10 is a block diagram illustrating a non-volatile memory device included in a memory system according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0017] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms, and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0018] The accompanying drawings are not necessarily drawn to scale, and in some instances, the dimensions can have been exaggerated for the sake of illustration only. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0019] As used herein, the term "and / or" includes at least one of the related listed items. It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on, directly connected, or directly coupled to the other element, or one or more intervening elements can exist. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and "including," when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements.

[0020] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0021] According to an embodiment of the present disclosure, a memory system capable of performing a signal training operation with improved accuracy can be provided.

[0022] Figure 1 is a block diagram illustrating a memory system 100 according to an embodiment of the present disclosure.

[0023] The memory system 100 can be configured to store data provided by an external host device in response to a write request from a host device. In addition, the memory system 100 can be configured to provide the stored data to the host device in response to a read request from the host device.

[0024] The memory system 100 can be configured as a Personal Computer Memory Card International Association (PCMCIA) card, a CompactFlash (CF) card, a smart media card, a memory stick, various multimedia cards (e.g., MMC, eMMC, RS-MMC, and micro-SD), a Secure Digital (SD) card (e.g., SD, mini-SD, and micro-SD), a Universal Flash Storage (UFS), or a Solid State Drive (SSD).

[0025] The memory system 100 can include a controller 110 and a memory device 120.

[0026] The controller 110 can control all operations of the memory system 100. The controller 110 can control the memory device 120 to perform foreground operations in response to instructions from the host device. The foreground operations can include operations of writing data to and reading data from the memory device 120 in response to write requests and read requests from the host device.

[0027] In addition, the controller 110 can control the memory device 120 to perform internal necessary background operations independently of the host device. The background operations can include at least one of a wear leveling operation, a garbage collection operation, an erase operation, a read recycling operation, and a refresh operation of the memory device 120. As with the foreground operations, the background operations can also include operations of writing data to and reading data from the memory device 120.

[0028] The controller 110 can include an interface component 111 and a virtual power component 112. The interface component 111 and the virtual power component 112 include all circuits, systems, software, firmware, and devices necessary for their respective operations and functions.

[0029] The interface component 111 can be coupled to the memory device 120 through input / output (I / O) lines DQ. The interface component 111 can provide data to the memory device 120 through the I / O lines DQ and can receive data from the memory device 120 through the I / O lines DQ.

[0030] The interface component 111 can perform a signal training operation on the memory device 120. The signal training operation can be performed between the interface component 111 and the memory device 120 to improve accuracy of sampling data transferred through the I / O lines DQ. Specifically, the interface component 111 can provide test data to the memory device 120 through the I / O lines DQ while adjusting timing of a clock signal synchronized with the test data to perform the signal training operation. Also, the interface component 111 can receive test data from the memory device 120 through the I / O lines DQ while adjusting timing of a clock signal synchronized with the test data to perform the signal training operation. The interface component 111 can adjust timing of the clock signal such that the test data transferred to the memory device 120 or the interface component 111 is correctly sampled by the timing-adjusted clock signal. For example, the interface component 111 can adjust timing of the clock signal such that an edge of the timing-adjusted clock signal is located at a center of the test data. The interface component 111 can include a delay-locked loop circuit (not shown) to adjust timing of the clock signal. The clock signal can be a data strobe signal.

[0031] To reduce the interference effects that can occur on the I / O lines DQ during the signal training operation, the interface component 111 and the memory device 120 can utilize a predetermined pattern of limited test data, where the test data includes the limited test data. To reduce the interference effects, the limited test data can toggle less than full toggle data that constantly toggles between "0" and "1". In an embodiment, the limited test data can be configured by a Gray code. In an embodiment, the limited test data can be configured by a one hot code. In an embodiment, the limited test data can toggle on selected ones of the I / O lines DQ for a predetermined time.

[0032] Accordingly, in an embodiment, the interference effects that can occur on the I / O lines DQ can be reduced with the limited test data, which can improve the accuracy of the signal training operation.

[0033] When the limited test data is utilized during the signal training operation, the virtual power consumption component 112 can perform a virtual power consumption operation that induces the memory system 100 to consume a similar amount of power as consumed in an actual operation with full toggle data.

[0034] In an embodiment, the virtual power consumption component 112 can transmit virtual data to the memory device 120 through one or more virtual I / O lines (not shown) coupled to the memory device 120 to perform the virtual power consumption operation.

[0035] In an embodiment, the virtual power consumption component 112 can control an ECC component (not shown) included in the controller 110 to perform the virtual power consumption operation. The ECC component includes all circuits, systems, software, firmware, and devices necessary for their respective operations and functions.

[0036] Although the power consumption due to the limited test data during the signal training operation is lower than the actual data due to the number of toggles of the limited test data being less than the actual data, the virtual power consumption component 112 can control the memory system 100 to consume an additional amount of power as much as the difference between the amount of power consumed during the actual operation and the signal training operation. Accordingly, a power dependency that is substantially the same as the power dependency of the actual operation can be correctly reflected on the I / O lines DQ, which can improve the accuracy of the signal training operation.

[0037] Under the control of the controller 110, the memory device 120 can store data provided from the controller 110 and can read out the stored data to the controller 110. During the signal training operation, the memory device 120 can exchange the predetermined pattern of limited test data with the interface component 111 through the I / O lines DQ.

[0038] The memory device 120 can include a volatile memory device or a non-volatile memory device. The volatile memory device can include a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like. The non-volatile memory device can include a flash memory device (e.g., NAND flash or NOR flash), a ferroelectric random access memory (FeRAM), a phase change random access memory (PCRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), and the like.

[0039] Although Figure 1 The memory system 100 is shown to include a single memory device 120, but the number of memory devices included in the memory system 100 will not be limited thereto.

[0040] Figures 2 to 4 is a diagram illustrating a signal training operation according to an embodiment of the disclosure. As an example, Figures 2 to 4 A virtual power consumption operation performed by the virtual power consumption component 112 by driving the virtual I / O line DM1 is shown.

[0041] Referring to Figure 2 During the signal training operation, the interface component 111 can exchange limited test data TD1 with the memory device 120 through the I / O lines DQ0 to DQ7. The limited test data TD1 can be configured by a Gray code. That is, when comparing the pattern of the limited test data TD1 at, for example, a first time point t1 and a second time point t2, only a single signal on the second I / O line DQ1 changes from a value "0" to a value "1", the limited test data TD1 can be a Gray code.

[0042] While the limited test data TD1 is being transmitted through the I / O lines DQ0 to DQ7, the virtual power consumption component 112 can provide virtual data DD to the memory device 120 through the virtual I / O line DM1. As Figure 2 shown, the virtual data DD can be all-flip data, but this will not limit the present disclosure. Despite receiving the virtual data DD, the memory device 120 can ignore the virtual data DD without sampling the virtual data DD, unlike the case of the limited test data TD1.

[0043] In summary, although the power consumption caused by the limited test data TD1 during the signal training operation is lower than that of the actual data due to the number of flips of the limited test data TD1 being less than that of the actual data, additional power as much as the difference between the amount of power consumed during the actual operation and the signal training operation can be consumed on the virtual I / O line DM1. Accordingly, a power dependency substantially the same as that of the actual operation can be correctly reflected on the I / O lines DQ.

[0044] Referring to Figure 3 , the limited test data TD2 can be configured by one-hot code. That is, since only a single signal on one of the I / O lines DQ0 to DQ7 becomes a value "1" at each of the first to eighth time points t1 to t8, the limited test data TD2 is configured by one-hot code.

[0045] While the limited test data TD2 is being transmitted through the I / O lines DQ0 to DQ7, the virtual power consumption component 112 can provide the virtual data DD to the memory device 120 through the virtual I / O line DM1, similar to the embodiment of Figure 2 .

[0046] Referring to Figure 4 , the limited test data TD3 can be flipped on selected ones of the I / O lines DQ0 to DQ7 for a predetermined period of time. For example, only the signal on the first I / O line DQ0 can be flipped during the first to fourth time points t1 to t4, while only the signal on the second I / O line DQ1 can be flipped during the fifth to eighth time points t5 to t8. Although not shown, after the eighth time point t8, the respective signals can be sequentially flipped on the corresponding third to eighth I / O lines DQ3 to DQ7.

[0047] While the limited test data TD3 is being transmitted through the I / O lines DQ0 to DQ7, the virtual power consumption component 112 can provide the virtual data DD to the memory device 120 through the virtual I / O line DM1, similar to the embodiment of Figure 2 .

[0048] In an embodiment, the virtual I / O line DM1 can be physically spaced apart from the I / O lines DQ0 to DQ7, thereby not causing a disturbance effect on the I / O lines DQ0 to DQ7.

[0049] Figures 2 to 4 Eight I / O lines DQ0 to DQ7 are shown, which will not limit the present disclosure.

[0050] Although Figures 2 to 4A single virtual I / O line DM1 is shown, but according to embodiments, the memory system 100 can include a plurality of virtual I / O lines, and the virtual power consumption component 112 can drive the plurality of virtual I / O lines.

[0051] In embodiments, the virtual power consumption component 112 can drive the virtual I / O line, and the number of virtual I / O lines can be determined by Equations 1 to 6 below. The number of virtual I / O lines can be determined such that the switching power consumption amount P dummy is the difference between the switching power consumption amount P full and the switching power consumption amount P gray . The switching power consumption amount P dummy may represent the amount of power consumed when the virtual data DD is transmitted through the virtual I / O line. The switching power consumption amount P full may represent the amount of power consumed during actual operation. The switching power consumption amount P gray may represent the amount of power consumed when the restricted test data (for example, the restricted test data configured by the Gray code) is transmitted through the I / O line DQ. Accordingly, Equation 1 below can be established. The switching power consumption amount P full in the actual operation can be the switching power consumption amount when the fully flipped data is transmitted through the I / O line DQ.

[0052] Equation 1:

[0053] P dummy = P full – P gray

[0054] Equation 2 can represent the switching power consumption amount P switch consumed when a signal on a general signal line changes from "0" to "1" or from "1" to "0". Equations 3 to 5 can be derived based on Equation 2.

[0055] Equation 2:

[0056] P switch = ∑ i a i *f*C eff *V dd 2 ,

[0057] where "a i " represents an operation of signal switching, "f" represents a frequency, "C eff " represents a coefficient factor, and "V dd " represents an operating voltage.

[0058] Equation 3:

[0059] P full = (N DQ )*fHS *C eff-HS *V dd-HS 2 ,

[0060] where "N DQ " represents the number of I / O lines DQ, and "f HS " represents the coefficient of I / O lines DQ.

[0061] Equation 4:

[0062] P gray = f HS *C eff-HS *V dd-HS 2

[0063] Equation 5:

[0064] P dummy = (N dummy )*f LS *C eff-LS *V dd-LS 2 ,

[0065] where "N dummy " represents the number of virtual I / O lines, and "f LS " represents the coefficient of virtual I / O lines.

[0066] When Equations 3 to 5 are applied to Equation 1, Equation 6 can be established to represent the number N dummy of virtual I / O lines.

[0067] Equation 6:

[0068] N dummy = {(N DQ -1)*f HS *C eff-HS *V dd-HS 2} / (f LS *C eff-LS *V dd-LS 2 )

[0069] In an embodiment, the frequency f LS of virtual data can be lower than the frequency f HS of limited test data.

[0070] Even when the limited test data is configured by another code different from the Gray code, the number N dummy of virtual I / O lines can be determined in a similar manner to the above-described scheme.That is, when the amount of switching power consumed while the limited test data is transferred through the I / O line DQ is derived according to Equation 2 and the result of Equation 2 is applied to Equation 1 instead of the amount of switching power P gray . dummy .

[0071] Figure 5 is a block diagram illustrating a signal training operation according to an embodiment of the disclosure. Figure 5 The virtual power consumption component 112 performs a virtual power consumption operation by controlling the ECC component 113.

[0072] Referring to Figure 5 , the controller 110 can further include an ECC component 113. The ECC component 113 can perform an error correction operation by encoding data to be stored into the memory device 120 and decoding data read from the memory device 120.

[0073] When the limited test data is transferred through the I / O line DQ during the signal training operation, the virtual power consumption component 112 can control the ECC component 113 to perform a virtual ECC operation. The virtual ECC operation can include a virtual encoding operation and a virtual decoding operation, and not include an operation of error correction on data read from the memory device 120.

[0074] Specifically, when the limited test data is transferred from the interface component 111 to the memory device 120, the virtual power consumption component 112 can control the ECC component 113 to perform a virtual encoding operation. During the virtual encoding operation, the ECC component 113 can encode the limited test data. In an embodiment, the ECC component 113 can encode predetermined random data different from the limited test data during the virtual encoding operation. The interface component 111 can provide at least one of the limited test data TD1 to TD3 described with reference to Figures 2 to 4 to the memory device 120, without considering the data encoded by the ECC component 113.

[0075] When the limited test data is transferred from the memory device 120 to the interface component 111, the virtual power consumption component 112 can control the ECC component 113 to perform a virtual decoding operation. During the virtual decoding operation, the ECC component 113 can decode the limited test data provided from the interface component 111. In an embodiment, the ECC component 113 can decode predetermined random data different from the limited test data provided from the interface component 111 during the virtual decoding operation.

[0076] Accordingly, although the power consumption due to the limited test data during the signal training operation is lower than the actual data during the actual operation because the number of flips is less than the actual data due to the limited test data, the ECC component 113 can consume as much additional power as the difference between the amount of power consumed during the actual operation and the signal training operation. Accordingly, the power dependency substantially the same as that of the actual operation can be correctly reflected on the I / O line DQ.

[0077] Figure 6 is a diagram illustrating a data processing system 1000 including a solid state drive (SSD) 1200 according to an embodiment of the disclosure. The SSD 1200 can be Figure 1 the memory system 100 shown. Referring to Figure 6 , the data processing system 1000 can include a host device 1100 and the SSD 1200.

[0078] The SSD 1200 can include a controller 1210, a buffer memory device 1220, a plurality of nonvolatile memory devices 1231 through 123n, a power supply 1240, a signal connector 1250, and a power supply connector 1260.

[0079] The controller 1210 can control general operations of the SSD 1200. The controller 1210 can include a host interface component 1211, a control component 1212, a random access memory 1213, an error correction code (ECC) component 1214, and a memory interface component 1215.

[0080] The host interface component 1211 can exchange a signal SGL with the host device 1100 through the signal connector 1250. The signal SGL can include a command, an address, data, etc. The host interface component 1211 can interface the host device 1100 with the SSD 1200 according to a protocol of the host device 1100. For example, the host interface component 1211 can communicate with the host device 1100 through a communication standard or interface such as secure digital, universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial SCSI (SAS), peripheral component interconnect (PCI), high-speed PCI (PCI-e or PCIe), and universal flash storage (UFS).

[0081] The control component 1212 can analyze and process a signal SGL received from the host device 1100. According to firmware or software for driving the SSD 1200, the control component 1212 can control operations of internal functional blocks. A random access memory 1213 can be used as a working memory for driving such firmware or software. The control component 1212 can include Figure 1 a virtual power consumption component 112 shown.

[0082] The ECC component 1214 can generate parity data of data to be transmitted to at least one of the nonvolatile memory devices 1231 through 123n. The generated parity data can be stored in the nonvolatile memory devices 1231 through 123n together with the data. The ECC component 1214 can detect an error of data read from at least one of the nonvolatile memory devices 1231 through 123n based on the parity data. If the detected error is within a correctable range, the ECC component 1214 can correct the detected error.

[0083] According to control of the control component 1212, the memory interface component 1215 can provide a control signal such as a command and an address to at least one of the nonvolatile memory devices 1231 through 123n. Further, according to control of the control component 1212, the memory interface component 1215 can exchange data with at least one of the nonvolatile memory devices 1231 through 123n. For example, the memory interface component 1215 can provide data stored in the buffer memory device 1220 to at least one of the nonvolatile memory devices 1231 through 123n, or provide data read from at least one of the nonvolatile memory devices 1231 through 123n to the buffer memory device 1220. The memory interface component 1215 can include Figure 1 an interface component 111 shown.

[0084] The buffer memory device 1220 can temporarily store data to be stored in at least one of the nonvolatile memory devices 1231 through 123n. Further, the buffer memory device 1220 can temporarily store data read from at least one of the nonvolatile memory devices 1231 through 123n. According to control of the controller 1210, data temporarily stored in the buffer memory device 1220 can be transmitted to the host device 1100 or at least one of the nonvolatile memory devices 1231 through 123n.

[0085] The nonvolatile memory devices 1231 through 123n can be used as storage media of the SSD 1200. The nonvolatile memory devices 1231 through 123n can be coupled with the controller 1210 through a plurality of channels CH1 through CHn, respectively. One or more nonvolatile memory devices can be coupled to one channel. The nonvolatile memory devices coupled to each channel can be coupled to the same signal bus and data bus.

[0086] The power supply 1240 can supply power PWR input through the power supply connector 1260 to the inside of the SSD 1200. The power supply 1240 can include an auxiliary power supply 1241. The auxiliary power supply 1241 can supply power to allow the SSD 1200 to terminate normally when a sudden power outage occurs. The auxiliary power supply 1241 can include a large-capacity capacitor.

[0087] The signal connector 1250 can be configured by various types of connectors according to an interface scheme between the host device 1100 and the SSD 1200.

[0088] The power supply connector 1260 can be configured by various types of connectors according to a power supply scheme of the host device 1100.

[0089] Figure 7 is a diagram illustrating a data processing system 2000 including a memory system 2200 according to an embodiment of the disclosure. Referring to Figure 7 , the data processing system 2000 can include a host device 2100 and the memory system 2200.

[0090] The host device 2100 can be configured in the form of a board such as a printed circuit board. Although not illustrated, the host device 2100 can include internal function blocks for performing functions of the host device.

[0091] The host device 2100 can include a connection terminal 2110 such as a socket, a slot, or a connector. The memory system 2200 can be mounted to the connection terminal 2110.

[0092] The memory system 2200 can be configured in the form of a board such as a printed circuit board. The memory system 2200 can be referred to as a memory module or a memory card. The memory system 2200 can include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 and 2232, a power management integrated circuit (PMIC) 2240, and a connection terminal 2250.

[0093] The controller 2210 can control general operations of the memory system 2200. The controller 2210 can be configured in the same manner as the controller 1210 illustrated in Figure 6 .

[0094] The buffer memory device 2220 can temporarily store data to be stored in the nonvolatile memory devices 2231 and 2232. Further, the buffer memory device 2220 can temporarily store data read from the nonvolatile memory devices 2231 and 2232. The data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the nonvolatile memory devices 2231 and 2232 according to the control of the controller 2210.

[0095] The nonvolatile memory devices 2231 and 2232 can serve as storage media of the memory system 2200.

[0096] The PMIC 2240 can supply power input through the connection terminal 2250 to the inside of the memory system 2200. The PMIC 2240 can manage power of the memory system 2200 according to the control of the controller 2210.

[0097] The connection terminal 2250 can be coupled to the connection terminal 2110 of the host device 2100. Through the connection terminal 2250, signals such as commands, addresses, data, and the like, and power can be transmitted between the host device 2100 and the memory system 2200. The connection terminal 2250 can be configured in various types according to an interface scheme between the host device 2100 and the memory system 2200. The connection terminal 2250 can be disposed at any side of the memory system 2200.

[0098] Figure 8 is a diagram illustrating a data processing system 3000 including a memory system 3200 according to an embodiment of the present disclosure. Referring to Figure 8 , the data processing system 3000 can include a host device 3100 and the memory system 3200.

[0099] The host device 3100 can be configured in the form of a board such as a printed circuit board. Although not shown, the host device 3100 can include internal functional blocks for performing functions of the host device.

[0100] The memory system 3200 can be configured in the form of a surface mount type package. The memory system 3200 can be mounted to the host device 3100 through solder balls 3250. The memory system 3200 can include a controller 3210, a buffer memory device 3220, and nonvolatile memory devices 3230.

[0101] The controller 3210 can control general operations of the memory system 3200. The controller 3210 can be configured in the same manner as the controller 1210 shown in Figure 6 .

[0102] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memory device 3230. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memory device 3230. Under the control of the controller 3210, data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memory device 3230.

[0103] The non-volatile memory device 3230 can be used as the storage medium of the memory system 3200.

[0104] Figure 9 This is a diagram illustrating a network system 4000 including a memory system 4200 according to an embodiment of the present disclosure. (Refer to...) Figure 9 The network system 4000 may include a server system 4300 and multiple client systems 4410 to 4430 connected via a network 4500.

[0105] Server system 4300 can serve data in response to requests from multiple client systems 4410 to 4430. For example, server system 4300 can store data provided by multiple client systems 4410 to 4430. As another example, server system 4300 can provide data to multiple client systems 4410 to 4430.

[0106] Server system 4300 may include host device 4100 and memory system 4200. Memory system 4200 may be composed of… Figure 1 The memory system 100 shown Figure 6 The SSD 1200 shown Figure 7 The memory system 2200 shown or Figure 8 The memory system 3200 configuration shown is illustrated.

[0107] Figure 10 This is a block diagram illustrating a non-volatile memory device 300 included in a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 10 The non-volatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read / write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

[0108] The memory cell array 310 may include memory cells MC arranged in the region where word lines WL1 to WLm and bit lines BL1 to BLn intersect.

[0109] The row decoder 320 can be coupled with the memory cell array 310 through the word lines WL1 to WLm. The row decoder 320 can operate according to the control of the control logic 360. The row decoder 320 can decode an address provided from an external device (not shown). The row decoder 320 can select and drive the word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 can provide a word line voltage provided from the voltage generator 350 to the word lines WL1 to WLm.

[0110] The data read / write block 330 can be coupled with the memory cell array 310 through the bit lines BL1 to BLn. The data read / write block 330 can include read / write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn, respectively. The data read / write block 330 can operate according to the control of the control logic 360. The data read / write block 330 can operate as a write driver or a sense amplifier according to an operation mode. For example, the data read / write block 330 can operate as a write driver that stores data provided from an external device in the memory cell array 310 in a write operation. For another example, the data read / write block 330 can operate as a sense amplifier that senses data from the memory cell array 310 in a read operation.

[0111] The column decoder 340 can operate according to the control of the control logic 360. The column decoder 340 can decode an address provided from an external device. The column decoder 340 can couple the read / write circuits RW1 to RWn of the data read / write block 330 corresponding to the bit lines BL1 to BLn, respectively, with a data input / output line or a data input / output buffer based on the decoding result.

[0112] The voltage generator 350 can generate a voltage to be used in an internal operation of the non-volatile memory device 300. The voltage generated by the voltage generator 350 can be applied to a memory cell of the memory cell array 310. For example, a program voltage generated in a program operation can be applied to a word line of a memory cell on which the program operation is to be performed. For another example, an erase voltage generated in an erase operation can be applied to a well region of a memory cell on which the erase operation is to be performed. For another example, a read voltage generated in a read operation can be applied to a word line of a memory cell on which the read operation is to be performed.

[0113] The control logic 360 can control general operations of the non-volatile memory device 300 based on a control signal provided from an external device (e.g., a memory controller). For example, the control logic 360 can control operations of the non-volatile memory device 300, such as a read operation, a write operation, and an erase operation of the non-volatile memory device 300.

[0114] According to embodiments, the memory system is capable of performing a signal training operation with improved accuracy.

[0115] While specific embodiments have been described above, one skilled in the art will appreciate that the described embodiments are only examples. Accordingly, no limitation is placed on the memory system based on the described embodiments. Rather, the memory system described herein should only be limited as described in the claims, based on the above description, and the accompanying drawings. In addition, embodiments can be combined to form additional embodiments.

Claims

1. A memory system comprising: a memory device; and a controller coupled to the memory device by input / output (I / O) lines, wherein the controller comprises: an interface component that performs a signal training operation that adjusts timing of a clock signal that is synchronized with test data; and a virtual power component coupled to the memory device by one or more virtual I / O lines and that performs a virtual power operation by transferring virtual data to the memory device through the virtual I / O lines while the test data is transferred from the interface component to the memory device through the I / O lines.

2. The memory system of claim 1, wherein a number of the virtual I / O lines is determined such that an amount of switching power consumed while transferring the virtual data through the virtual I / O lines is a difference between an amount of switching power consumed during actual operation and an amount of switching power consumed while transferring the test data through the I / O lines.

3. The memory system of claim 1, wherein a frequency of the virtual data is lower than a frequency of the test data.

4. The memory system of claim 1, wherein the virtual I / O lines are physically spaced apart from the I / O lines to not cause interference effects to the I / O lines.

5. The memory system of claim 1, wherein the controller further comprises an error correction code (ECC) component, and wherein the virtual power component performs the virtual power operation by controlling the ECC component to perform a virtual ECC operation.

6. The memory system of claim 5, wherein the ECC component performs the virtual ECC operation on predetermined random data that is different from the test data.

7. The memory system of claim 1, wherein the test data comprises limited test data that is flipped less than full flip data.

8. A memory system comprising: a memory device coupled to one or more input / output (I / O) lines and one or more virtual I / O lines; and a controller that transfers virtual data to the memory device through the virtual I / O lines while test data is transferred to the memory device through the I / O lines during a signal training operation.

9. The memory system of claim 8, wherein a number of the virtual I / O lines is determined such that an amount of switching power consumed while transferring the virtual data through the virtual I / O lines is a difference between an amount of switching power consumed during actual operation and an amount of switching power consumed while transferring the test data through the I / O lines.

10. The memory system of claim 8, wherein a frequency of the virtual data is lower than a frequency of the test data.

11. The memory system of claim 8, wherein the virtual I / O lines are physically spaced apart from the I / O lines to not cause interference effects to the I / O lines.

12. The memory system of claim 8, wherein the dummy data is all-flip data, and the test data is less flipped than the all-flip data.

13. The memory system of claim 8, wherein the test data comprises limited test data, the limited test data being less flipped than all-flip data.

14. The memory system of claim 8, wherein the memory device receives dummy data transmitted over the dummy I / O lines, and ignores the received dummy data.

15. The memory system of claim 8, wherein the controller performs a signal training operation that adjusts timing of a clock signal that is synchronized with the test data.

16. A memory system comprising: a memory device; and a controller coupled to the memory device by input / output (I / O) lines, and including an error correction code (ECC) component that performs an error correction operation on data transmitted from the memory device over the I / O lines, wherein the ECC component performs a dummy ECC operation during a signal training operation when limited test data is transmitted from the controller to the memory device over the I / O lines.

17. The memory system of claim 16, wherein the ECC component performs the dummy ECC operation on the test data or predetermined random data different from the test data.

18. The memory system of claim 16, wherein the limited test data is less flipped than all-flip data.

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