Receiver circuit and data receiver

Abstract

The present invention provides a receiver circuit having: a first-stage circuit having a first-stage input and a first-stage output, the first-stage output setting a first-stage common-mode voltage; a second-stage circuit having a second-stage input connected to the first-stage output and a second-stage output setting a second-stage common-mode voltage; and a buffer circuit having a trip-point voltage, the buffer circuit being connected to the second-stage output. The first-stage circuit may include circuit elements configured to establish the first-stage common-mode voltage such that the second-stage common-mode voltage matches the trip-point voltage. The second-stage circuit may include a self-biased amplifier.

Description

Technical Field

[0001] The present invention relates to a high-speed, low-distortion receiver for use in an integrated circuit, such as in an input buffer for receiving data from an external source. Background Art

[0002] Integrated circuits are typically configured to receive high-speed data signals, such as double data rate (DDR) signals of more than one billion bits per second. For example, a high-speed receiver may be connected to an input / output pin on an integrated circuit, which is coupled to a transmission line for data transfer between chips.

[0003] As the data rate increases, the pulse width of the input signal becomes smaller. The pulse width is a critical characteristic of some data signals, such as DDR signals in which both rising and falling edges are sensed. Figure 1 A basic receiver circuit is shown. In Figure 1 the example, receiver 11 is essentially configured as a comparator. Receiver 11 receives an input pulse having a pulse width of, for example, 400 ps, and compares the input pulse with a reference voltage Vref. Ideally, the output of receiver 11 would also have a pulse width of 400 ps. However, due to distortion in the receiver, the pulse width of the output signal may be different, for example, 300 ps in this instance. Additionally, the pulse amplitude, represented by the low input voltage VIL and the high input voltage VIH, becomes smaller as the data rate increases, making the operation of the receiver more complex.

[0004] There is a need to provide a receiver circuit suitable for an integrated circuit that can operate at high speeds and has low distortion.

[0005] Disclosure

[0006] The present disclosure provides a receiver circuit comprising: a first-stage circuit having a first-stage input and a first-stage output, the first-stage output setting a first-stage common-mode voltage; a second-stage circuit having a second-stage input connected to the first-stage output and a second-stage output setting a second-stage common-mode voltage; and a buffer circuit having a trip-point voltage, the buffer circuit being connected to the second-stage output. The first-stage circuit may include circuit elements configured to establish the first-stage common-mode voltage such that the second-stage common-mode voltage matches the trip-point voltage.

[0007] The circuit may receive a single-ended signal at the first-stage input and provide the first-stage output as a differential signal pair.

[0008] The first-stage circuit may be configured in a first power domain, and the second-stage circuit may be configured in a second power domain different from the first power domain.

[0009] The second-stage circuit may include a self-biased amplifier.

[0010] A receiver circuit is described, which includes a first differential transistor pair, a reference current circuit, a second differential transistor pair, and a buffer circuit. In this example, the first differential transistor pair has a drain connected to a first drain-side supply voltage via a first matching resistor and a second matching resistor, and a source connected to a current source transistor. The first transistor in the first differential pair has a gate connected to a reference voltage, and the second transistor in the first differential pair has a gate connected to a first-stage input. The drain of the first differential transistor pair provides a differential signal pair as a first-stage output.

[0011] In this example, the reference current circuit includes a reference resistor connected in series between a drain-side supply voltage and a source-side supply voltage. The first transistor of the reference current circuit has a gate connected to a reference voltage; and the second transistor of the reference current circuit has a gate connected to a node between the reference resistor and the first transistor of the reference current circuit and to the gate of the current source transistor, which is connected to the first differential transistor pair.

[0012] In this example, the second differential transistor pair has a drain connected to a second drain-side supply voltage via a first current mirror transistor and a second current mirror transistor, gates connected to respective ones of the differential signal pair, and a source connected to a second current source transistor.

[0013] In this example, the buffer circuit is connected to the drain of the first one of the second differential transistor pair.

[0014] The second current source transistor may have a gate connected to the drain of the second one of the second differential transistor pair.

[0015] A voltage regulator can be used to generate the second drain-side supply voltage.

[0016] A data receiver is described, which includes a first amplifier circuit (first stage), the first amplifier circuit being configured to receive a reference voltage and a first-stage input signal and output a control voltage based on the reference voltage and the first-stage input signal. In this example, a self-biased amplifier circuit is configured to receive the control voltage from the first amplifier circuit and provide a self-biased voltage and an output signal, where the self-biased voltage is connected to a current mirror of the self-biased amplifier circuit.

[0017] Other aspects and advantages of the present invention will become apparent upon review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram showing distortion in a conventional receiver.

[0019] Figure 2Circuit diagram of an example of a conventional receiver circuit.

[0020] Figure 3 Shows the pulse width distortion process boundary angle chart of a circuit similar to the Figure 2 circuit with respect to process, voltage, and temperature (PVT) variations.

[0021] Figure 4 For comparing the common mode voltage of a receiver circuit similar to the Figure 2 receiver circuit and the process boundary angle chart of the inverter trigger point with respect to PVT variations.

[0022] Figure 5A And Figure 5B Combined to provide a circuit diagram of a two - stage receiver according to the technology of the present invention.

[0023] Figures 6A to 6C Shows a model of the common mode voltage of a self - biasing amplifier similar to the second - stage self - biasing amplifier of the Figure 5A and Figure 5B circuit.

[0024] Figures 7A to 7D Shows alternative resistor technologies that can be used in the receivers described herein.

[0025] Figure 8A And Figure 8B Combined to provide a circuit diagram of a two - stage receiver according to the technology of the present invention using p - channel MOS transistors of a differential pair.

[0026] Figure 9 For a receiver circuit similar to Figure 5A Combined with Figure 5B the process boundary angle chart of the common mode voltage and the inverter trigger point with respect to PVT variations.

[0027] Figure 10 For comparing the pulse width distortion of a circuit similar to Figure 5A Combined with Figure 5B and the pulse width distortion of a circuit similar to Figure 2 with respect to PVT variations in the process boundary angle chart.

[0028] Figure 11 Circuit diagram of an alternative second - stage circuit that can be used in some embodiments of the receivers described herein.

[0029] Figure 12 For comparing a circuit similar to Figure 5A Combined with Figure 5B a circuit similar to Figure 5A Combined with Figure 11 a circuit, and a circuit similar to Figure 2Process corner chart of pulse width distortion of the circuit with respect to PVT variations.

[0030] Description of Reference Numerals

[0031] 11: Receiver

[0032] 201: VSS Node

[0033] 205: LDO Voltage Regulator

[0034] 207, 209, 530, 630, 631, 800, 801, 830, 901, 902, 930, 931, OUT, OUTA, OUTB: Nodes

[0035] 210, 211, 610, 611, 911, 912: Inverters

[0036] 221, 222, 502, 503, 623, 624: n-channel MOS Transistors

[0037] 223, 224, 621, 622, 822, 823: p-channel MOS Transistors

[0038] 225: Current Source Transistor

[0039] 500, 607: Drain-Side Supply Nodes

[0040] 501, 601: Source-Side Supply Nodes

[0041] 504, 625: n-channel MOS Current Source Transistors

[0042] 510, 511: n-channel Transistors

[0043] 512, 513, 531: Resistors

[0044] 605, 910: Voltage Regulators

[0045] 621 / 622: Equivalent p-channel Transistors

[0046] 623 / 624 / 625: Equivalent n-channel Transistors

[0047] 824, 924: p-channel MOS Current Source Transistors

[0048] 831, 832, 922, 923: p-channel Transistors

[0049] 926, 927: n-channel MOS Current Mirror Transistors

[0050] BIAS: Bias Voltage

[0051] IN: Input node

[0052] R1, R2: Resistors

[0053] REF: Reference voltage

[0054] VCCQ: Drain - side supply voltage

[0055] VCOM: Common - mode voltage

[0056] VDDIO: Drain - side supply voltage

[0057] VDD_EXT: External drain - side supply voltage

[0058] VIH: High input voltage

[0059] VIL: Low input voltage

[0060] VIN: First - stage input node

[0061] Vref: Reference voltage Detailed implementation

[0062] Figure 2 Is a circuit diagram of an example receiver circuit including a first - stage operational amplifier. The circuit is deployed in a power domain that includes a drain - side supply voltage VDDIO of approximately 1.3V provided by a low - dropout (LDO) voltage regulator 205 at node 207, and a source - side reference voltage provided by the VSS node 201. The power for the LDO voltage regulator 205 is provided by an external drain - side supply voltage VDD_EXT, which in this example can vary between approximately 2.35V and approximately 3.6V at node 200.

[0063] A power domain includes circuits configured to be powered by a voltage source having: a first supply voltage at a drain - side reference node (or equivalently a collector - side), traditionally called VDD or VCC; and a second supply voltage at a source - side reference node (or equivalently an emitter - side), traditionally called VSS or VEE. Typically, the VSS voltage or VEE voltage is a DC ground voltage. For some voltage domains, the source - side reference node may be connected to an AC ground or to another voltage reference. Some integrated circuits have multiple power domains.

[0064] Figure 2The circuit therein includes a first differential pair of an n-channel MOS transistor 221 and an n-channel MOS transistor 222, which has drains that are connected to node 207 through a current mirror configured by a first p-channel MOS transistor 223 and a second p-channel MOS transistor 224. The gates of the first p-channel MOS transistor 223 and the second p-channel MOS transistor 224 are connected together and connected to the drain of the transistor 221 in the first differential pair.

[0065] The gate of the transistor 221 is connected to a reference voltage REF. The gate of the transistor 222 is connected to an input node IN, where a high-speed data signal can be received.

[0066] The sources of the transistor 221 and the transistor 222 are connected together and connected to the drain of a current source transistor 225. In this example, the current source transistor 225 is an n-channel MOS transistor and has a gate connected to a bias voltage BIAS and a source connected to the VSS node 201.

[0067] In Figure 2 representative transistor widths are provided. Generally, in this example, the sizes (e.g., 3µ) of the differential pair of the transistor 221 and the transistor 222 are the same, and the sizes (e.g., 3µ) of the current mirror transistor 223 and the current mirror transistor 224 are the same. The size (e.g., 6µ) of the current source transistor 225 is equal to the sum of the widths of the differential pair of the transistor 221 and the transistor 222.

[0068] A signal is generated at node 209, which has a common-mode voltage VCOM. The common-mode voltage VCOM varies with changes in the input data signal and other circuit factors. Generally, when the input data signal at node IN is greater than the reference voltage REF, the signal at node 209 is lower, and when the input data signal at node IN is less than the reference voltage REF, the signal at node 209 is higher. Node 209 is connected to the input of an inverter 210, and the output of the inverter 210 is connected to a second inverter 211, which provides an output signal on node OUT. The inverter 210 and the inverter 211 are labeled with representative transistor sizes (2µ / 1µ), which represent the widths of the p-channel MOS transistor and the n-channel MOS transistor used to implement the inverter.

[0069] As mentioned above, the output signal on node OUT represents the input signal on node IN. However, the output signal may be distorted.

[0070] Figure 3 A process boundary angle chart showing the pulse-width distortion of the circuit, the circuit is related to Figure 2is similar to the circuit, with a temperature range of approximately -50°C to approximately 105°C and a supply voltage range of approximately 1.15V to approximately 1.6V. As shown, in this example, for a first-stage input signal with a pulse width of 400ps, the maximum distortion is approximately 219ps.

[0071] Figure 4 is a process corner plot of the common-mode voltage VCOM relative to the trigger point for comparing Figure 2 the inverter 210 in the circuit, with a temperature range of approximately -50°C to approximately 105°C and a supply voltage range of approximately 1.15V to approximately 1.6V. As shown, the differences vary significantly and are up to 0.4V in some process corners.

[0072] Figure 5A and Figure 5B illustrates a two-stage data receiver for high-speed input signals with low distortion. The first stage is illustrated in Figure 5A in.

[0073] Figure 5A The circuit in is a preamplifier that can shift the voltage level of its output relative to the first-stage input signal. The preamplifier includes a differential pair of an n-channel MOS transistor 502 and an n-channel MOS transistor 503. The drain of transistor 502 is connected to the drain-side supply voltage VCCQ at node 500 via a resistor 512 with a resistor R2. The drain of transistor 503 is connected to the drain-side supply voltage VCCQ at node 500 via a resistor 513 with a resistor R2. The sources of transistor 502 and transistor 503 are connected to the drain of an n-channel MOS current source transistor 504 (M2). The gate of the current source transistor 504 is connected to generate a bias voltage at node 530.

[0074] The gate of transistor 502 is connected to the reference voltage Vref. The gate of transistor 503 is connected to the first-stage input node VIN, where a single-ended input signal is received.

[0075] The preamplifier also includes a reference current circuit that includes a resistor 531 with a resistor R1, an n-channel transistor 510, and an n-channel transistor 511 (M1) connected in series between the drain-side supply node 500 and the source-side supply node 501. The gate of transistor 510 is connected to the reference voltage Vref. Additionally, transistor 510 can have the same width as transistor 502 and transistor 503 (e.g., 10 microns). The gate of transistor 511 is connected to node 530 and is configured in a current mirror with transistor 504. In this example, transistor 511 has a first width and transistor 504 has a second width, which is twice the first width such that it carries twice the current of transistor 511.

[0076] The preamplifier provides a first-stage output at nodes OUTA and OUTB. In this example, the output is a differential signal pair having a common-mode voltage that varies with the ratio of resistor R1 to resistor R2. Since the resistors 512 and 513 have the same value R2, and since transistors 502 and 503 are of the same size, the common-mode voltages of the signals at nodes OUTA and OUTB are approximately the same. The value R1 of resistor 531 controls the voltage at node 530, thus controlling the magnitude of the current through transistor 511, whereby the current mirror configuration controls the current in current source transistor 504. The common-mode voltage of the preamplifier stage at nodes OUTA and OUTB varies with the current through current source transistor 504. Accordingly, the common-mode voltage of the preamplifier stage can be adjusted by adjusting the ratio of resistor R1 to resistor R2. In another embodiment, the common-mode voltage can be adjusted by adjusting the relative sizes of transistors 511 and 504. In another embodiment, the common-mode voltage can be adjusted by a combination of adjustments to the sizes of transistors 511 and 504 and resistors R1 and R2. In other circuits, different circuit elements can be used to adjust the common-mode voltage.

[0077] Figure 5A The preamplifier circuit is deployed in a first voltage domain, which in this example has a drain-side supply voltage VCCQ that can be set based on the voltage swing of the first-stage input signal on node VIN.

[0078] Figure 5A The preamplifier illustrated in is an example of an amplifier or level shifter that can offset the DC level relative to the first-stage input signal, which may affect the common-mode voltage of the second stage and, in some embodiments, raise the DC level of the second-stage input signal.

[0079] Figure 5B is a circuit diagram of the second stage of a high-speed receiver, where Figure 5A the outputs on nodes OUTA and OUTB of the first stage illustrated in are connected to the second-stage inputs of the second stage.

[0080] The second-stage circuit includes a second differential pair of n-channel MOS transistors 623 and n-channel MOS transistors 624 having drains that are connected to a drain-side supply node 607 via a first p-channel MOS current mirror transistor 621 and a second p-channel MOS current mirror transistor 622. The gates of transistors 623 and 624 are connected respectively from Figure 5AEach of the differential signal pairs of nodes OUTA and OUTB in the first-stage circuit. The sources of transistors 623 and 624 are commonly connected to the drain of n-channel MOS current source transistor 625, and the source of the n-channel MOS current source transistor 625 is connected to the source-side supply node 601. The gates of current mirror transistors 621 and 622 are connected together at node 630, and in this example, are also connected to the drain of current mirror transistor 623. The circuit sets a self-biased voltage at node 630. Additionally, node 630 is connected to the gate of current source transistor 625.

[0081] In this example, the drain-side supply voltage VDDIO at node 607 is approximately 1.3V, which is provided by voltage regulator 605, which can be, for example, a low dropout voltage (LDO) regulator that sets the voltage difference between drain-side node 607 and source-side node 601. The low dropout voltage regulator 605 receives an external drain-side supply voltage VDD_EXT, which in this example can be in the range of approximately 2.35V to approximately 3.6V.

[0082] Therefore, Figure 5B the second-stage circuit in is deployed in a different voltage domain from Figure 5A the first-stage circuit of.

[0083] Node 631 on the drain of transistor 624 is connected to the input of inverter 610. The output of inverter 610 is applied to the input of inverter 611, which provides an output voltage OUT that corresponds to Figure 5A the voltage applied at node VIN in the amplification stage of. Additionally, node 631 is connected to the drain of p-channel transistor 622 of the current mirror including transistors 621 and 622, which facilitates self-biasing of the second-stage circuit.

[0084] Inverters 610 and 611 provide buffering to avoid output load effects on node 631. The buffer can be implemented using other types of circuits (such as NOR gates, NAND gates, latches, etc.).

[0085] As can be seen in the figure, the typical transistor widths of the differential pair of transistors 623 and 624 (e.g., 3 microns), the typical transistor widths of current mirror transistors 621 and 622 (e.g., 3 microns), and the typical transistor width of current source transistor 625 (e.g., 6 microns). Additionally, inverters 610 and 611 are marked with typical transistor sizes (2µ / 1µ), which represent the widths of the p-channel MOS transistor and n-channel MOS transistor used to implement the inverter.

[0086] Figure 5B The second-stage circuit therein is a self-biased amplifier, by which the gate of the current source transistor 625 is connected to node 630. Due to the self-bias, the common-mode voltage VCOM at node 631 naturally tracks the trigger point (or other buffer input) of the inverter with respect to variations in PVT. By tracking the trigger point of the inverter, the distortion associated with the mismatch of the rise-time delay and the fall-time delay can be reduced. That is, when the trigger point changes, the signal on node 631 increases in the case of the rising edge or decreases in the case of the falling edge, and the amount of time it takes to reach the trigger point also changes. These changes in triggering thus result in distortion in the form of a change in the pulse width at the output of the inverter.

[0087] In this example circuit, the first-stage circuit includes circuit elements that can be used to adjust the common-mode voltage VCOM at node 631 in the second-stage circuit. Figure 5A The components in the example of include resistor 512 and resistor 513 having values of R2 and resistor 531 having a value of R1. The values of R2 and R1 can be set such that VCOM at node 631 matches the trigger point of inverter 610. Analog or other techniques known in electronic design automation for integrated circuit design can be used to determine the values of R2 and R1.

[0088] Reference is made to explain Figure 5B how the self-biased amplifier has a common-mode voltage that tracks the trigger point of inverter 610 with respect to variations in PVT Figures 6A to 6C . In Figure 6A are labeled with the same reference numerals as the circuit elements in the circuit shown in Figure 5B , where the common-mode voltage VCOM is labeled at node 631 at the drain of transistor 624. When the DC level of signal OUTA is equal to the DC level of signal OUTB, for the purpose of explanation, the circuit is reduced to the circuit shown in Figure 6B , where transistor 623 and transistor 624 are combined into a single transistor with twice the width, and transistor 621 and transistor 622 are combined into a single transistor with twice the width. If, as discussed above, the components of the preamplifier circuit of Figure 5A are set to adjust the common-mode voltage VCOM in the second-stage circuit of Figure 5B , and thus the common-mode at OUTA matches VCOM, for the purpose of explanation, the circuit is reduced to Figure 6CThe circuit shown therein includes an equivalent p-channel transistor 621 / 622 that combines transistor 621 and transistor 622, and an equivalent n-channel transistor 623 / 624 / 625 that combines transistor 623, transistor 624, and transistor 625. The equivalent p-channel transistor 621 / 622 has a width of 6 microns, and the equivalent n-channel transistor 623 / 624 / 625 has a width of 3 microns. The resulting circuit is an inverter, and the input and output of the inverter are connected, and the ratio of the p-channel width to the n-channel width of the inverter is equal to 2:1, so as to match the ratio of inverter 610, and thereby match the trigger point of the inverter. In this way, Figure 5B the common-mode voltage VCOM in the self-biased amplifier stage should track the trigger point of inverter 610 that varies with respect to PVT.

[0089] Figure 5A The resistors R1 and R2 in can be implemented using diffusion resistors, polysilicon resistors, or other passive resistor components. Figures 7A to 7D shows an embodiment of an alternative resistor. As Figure 7A shown in, the resistor can be implemented using an n-channel MOS transistor having a gate connected to a high-voltage (HV) bias. As Figure 7B shown in, the resistor can be implemented using a p-channel transistor having a gate connected to VSS. As Figure 7C shown in, the resistor can be implemented using a p-channel transistor in a diode configuration (with its gate and drain connected). As Figure 7D shown in, the resistor can be implemented using an n-channel transistor in a diode configuration (with its gate and drain connected).

[0090] Figure 8A and Figure 8B shows a two-stage data receiver for high-speed input signals with low distortion using a p-channel differential pair. The first stage is shown in Figure 8A .

[0091] Figure 8AThe circuit therein is a preamplifier. The preamplifier includes a differential pair of a p-channel MOS transistor 822 and a p-channel MOS transistor 823. The drain of transistor 822 is connected to a drain-side reference voltage (ground in this example) at node 801 via a resistor having a resistance R2. The drain of transistor 823 is connected to a drain-side reference voltage (ground in this example) at node 801 via a resistor having a resistance R2. The sources of transistor 822 and transistor 823 are connected to the drain of a p-channel MOS current source transistor 824. The gate of the current source transistor 824 is connected to a bias voltage generated at node 830.

[0092] The gate of transistor 822 is connected to a reference voltage Vref. The gate of transistor 823 is connected to a first-stage input node VIN, at which a single-ended input signal is received.

[0093] The preamplifier also includes a reference current circuit, which includes a resistor having a resistance R1, a p-channel transistor 832, and a p-channel transistor 831 connected in series between a first drain-side supply voltage (ground in this example) at node 801 and a first source-side supply voltage (VCCQ in this example) at node 800. The gate of transistor 831 is connected to the reference voltage Vref. Additionally, transistor 832 may have the same width as transistor 822 and transistor 823. The gate of transistor 832 is connected to node 830 and is configured in a current mirror relationship with transistor 824. In this example, transistor 832 and transistor 824 have the same transistor width.

[0094] The preamplifier provides a first-stage output at node OUTA and node OUTB. In this example, the output is a differential signal pair, the common-mode voltage of which varies with the ratio of resistance R1 to resistance R2. Since the resistances on the drains of transistor 822 and transistor 823 are the same value R2, and since transistor 822 and transistor 823 are of the same size, the common-mode voltages of the signals at node OUTA and node OUTB are approximately the same. The value R1 controls the voltage at node 830, and thus controls the magnitude of the current passing through transistor 832. From this current mirror relationship, the magnitude of the current passing through current source transistor 824 is controlled. The common-mode voltage of the preamplifier stage at node OUTA and node OUTB varies with the current passing through current source transistor 824. Therefore, the common-mode voltage of the preamplifier stage can be adjusted by adjusting the ratio of resistance R1 to resistance R2. In another embodiment, the common-mode voltage can be adjusted by adjusting the relative sizes of transistor 832 and transistor 824. In another embodiment, the common-mode voltage can be adjusted by a combination of adjustments to the sizes of transistor 832 and transistor 824 and to resistances R1 and R2. In other circuits, different circuit elements may be used to adjust the common-mode voltage.

[0095] Figure 8A The preamplifier circuit is deployed in the first voltage domain. In this example, the first voltage domain has a first source-side supply voltage (VCCQ in this example), which can be set according to the voltage swing of the first-stage input signal on node VIN.

[0096] Figure 8B Circuit diagram of the second stage of a high-speed receiver, where Figure 8A The outputs on nodes OUTA and OUTB of the first stage shown in are connected to the second-stage inputs of the second stage.

[0097] The second-stage circuit includes a second differential pair of p-channel MOS transistors 922 and p-channel MOS transistors 923, which are connected to the drain-side supply voltage (ground in this example) at node 901 via a first n-channel MOS current mirror transistor 926 and a second n-channel MOS current mirror transistor 927. The gates of transistors 922 and 923 are respectively connected to each of the differential signal pairs from Figure 8A nodes OUTA and OUTB in the first-stage circuit of. The sources of transistors 922 and 923 are commonly connected to a p-channel MOS current source transistor 924, and the source of the p-channel MOS current source transistor 924 is connected to the second source-side supply voltage at node 902. In this example, the gates of the n-channel current mirror transistor 926 and the n-channel current mirror transistor 927 are connected together at node 930 and are also connected to the drain of transistor 922. The self-biased voltage set by the circuit at node 930. Additionally, node 930 is connected to the gate of the current source transistor 924.

[0098] In this example, the source-side supply voltage (VDDIO in this example) at node 902 is approximately 1.3V, which is provided by a voltage regulator 910. The voltage regulator 910 can be, for example, a low-dropout voltage regulator that sets the voltage difference between the source-side node 902 and the drain-side node 901. The low-dropout voltage regulator 910 receives an external drain-side supply voltage VDD_EXT. In this example, the external drain-side supply voltage VDD_EXT can be in the range of approximately 2.35V to approximately 3.6V.

[0099] Therefore, Figure 8B the second-stage circuit in is deployed in a voltage domain different from the Figure 8A first-stage circuit of.

[0100] The node 931 on the drain of transistor 923 is connected to the input of inverter 911. The output of inverter 911 is applied to the input of inverter 912, and the inverter 912 provides an output voltage OUT, and the output voltage OUT correspondsFigure 8A The voltage applied at node VIN in the amplification stage. Additionally, node 931 is connected to the drain of the n-channel transistor 927 of a current mirror including transistor 926 and transistor 927, which facilitates the self-biasing of the second-stage circuit.

[0101] Inverters 911 and 912 provide buffering to avoid output load effects on node 931. The buffer can be implemented using other types of circuits (such as NOR gates, NAND gates, latches, etc.).

[0102] Figure 5A Combined Figure 5B wherein a data receiver circuit is shown and Figure 8A Combined Figure 8B an alternative is shown, which includes: a first amplifier circuit and a self-biasing amplifier circuit. The first amplifier circuit is configured to receive a reference voltage and a first-stage input signal, and output control voltages (OUTA, OUTB) based on the reference voltage and the first-stage input signal. The self-biasing amplifier circuit is configured to receive the control voltages from the first amplifier circuit, and provide self-biasing voltages for output as output signals (node 631, node 931) to inverters (610, 611 or 911, 912), wherein the self-biasing voltages are connected to the current mirrors (transistor 622, transistor 621 or transistor 926, transistor 927) of the self-biasing amplifier circuit.

[0103] Figure 9 is a process corner plot of the common-mode voltage VCOM with respect to the trigger point, for comparing Figure 5A Combined Figure 5B the inverter 610 in the circuit of, with a temperature range of approximately -50°C to approximately 105°C, and a supply voltage range of approximately 1.15V to approximately 1.6V. As shown, the difference is quite small, with the maximum difference being approximately 0.1V. This is unexpectedly better than the variation of approximately 0.4V as shown in Figure 4 .

[0104] Figure 10 is for comparing Figure 5A Combined Figure 5B the pulse-width distortion of a circuit similar to Figure 2 with the pulse-width distortion of a circuit similar to Figure 5A Combined Figure 5B as a process corner plot with respect to PVT variations. As shown, Figure 2 the pulse-width distortion of the circuit combined with Figure 2 is much smaller than that of the circuit of Figure 5A Combined Figure 5B . Compared to the maximum value of approximately 219ps for the circuit of

[0105] Figure 11 For a similar Figure 5A Combined Figure 5B Alternative implementation of the second stage in the circuit (i.e., using Figure 11 Instead of Figure 5B , combined with Figure 5A ), where the second stage is not self-biased. In the Figure 11 diagram, the same reference numerals as in Figure 5B are also used and will not be elaborated further. However, in the Figure 11 circuit, the gate of the current source transistor 625 is connected to Figure 5A the node 530 in the preamplifier stage of

[0106] Figure 12 Process boundary angle chart of pulse width distortion versus PVT variations for comparing similar Figure 5A Combined Figure 11 circuits, similar Figure 5A Combined Figure 5B circuits, and similar Figure 2 circuits. As shown, Figure 5A Combined Figure 11 the circuit has much less pulse width distortion than Figure 2 the circuit.

[0107] The high-speed data receivers described herein can be used in many types of memory integrated circuits, including DRAM, SRAM, flash memory, RRAM, MRAM, PCRAM, etc.

[0108] Describe a sensitive input receiver with extremely low input signal distortion suitable for high-speed circuits operating at over one billion bits per second. A two-stage amplifier is described herein that enables the amplifier in the receiver output to have a common-mode voltage that tracks the trigger point of the output buffer (such as an inverter). This can reduce the rise and fall delay mismatches to avoid input signal distortion.

[0109] Although the present invention is disclosed with reference to the preferred embodiments and examples detailed above, it should be understood that these examples are intended in an illustrative rather than a limiting sense. Various modifications and combinations are expected to occur readily to those skilled in the art, which will fall within the spirit of the present invention and the scope of the appended claims.

Claims

1. A receiver circuit, characterized in that, comprising: A first-stage circuit having a first-stage input and a first-stage output, the first-stage output setting a first-stage common-mode voltage; A second-stage circuit having a second-stage input connected to the first-stage output and a second-stage output setting a second-stage common-mode voltage; and A buffer circuit having a trip point voltage, the buffer circuit being connected to the second-stage output; wherein the first-stage circuit includes circuit elements configured to set the first-stage common-mode voltage such that the second-stage common-mode voltage matches the trip point voltage; The first-stage circuit further includes: A differential transistor pair having drains connected to a drain-side supply voltage node via a first matching resistor and a second matching resistor and a source connected to a current source transistor, a first transistor in the differential transistor pair having a gate connected to a reference voltage, and a second transistor in the differential transistor pair having a gate connected to the first-stage input; and A reference current circuit including a reference resistor connected in series between the drain-side supply voltage node and the source-side supply voltage node, a first transistor of the reference current circuit having a gate connected to the reference voltage, a second transistor of the reference current circuit having a gate connected to a node between the reference resistor and the first transistor of the reference current circuit and connected to the gate of the current source transistor, wherein: The circuit elements configured to set the first-stage common-mode voltage include the reference resistor and the first and second matching resistors.

2. The receiver circuit according to claim 1, characterized in that, The first-stage input receives a single-ended signal, and the first-stage output is a differential signal pair.

3. The receiver circuit according to claim 1, characterized in that, The first-stage circuit is configured in a first power domain, and the second-stage circuit is configured in a second power domain different from the first power domain.

4. The receiver circuit according to claim 1, characterized in that, The second-stage circuit includes a self-biased amplifier.

5. The receiver circuit according to claim 1, characterized in that, The buffer circuit includes an inverter having the trip point voltage, which is connected to the second-stage output.

6. The receiver circuit according to claim 1, characterized in that, The second-stage circuit includes a self-biased amplifier.

7. The receiver circuit according to claim 1, characterized in that, The first-stage output is a differential signal pair, and the second-stage circuit includes: A second differential transistor pair having drains, gates, and sources, the drains being connected to a second drain-side supply voltage node via a first current mirror transistor and a second current mirror transistor, the gates being respectively connected to each of the differential signal pair of the first-stage output, and the sources being connected to a second current source transistor.

8. The receiver circuit according to claim 7, characterized in that, The second current source transistor has a gate, and the gate is connected to the drain of one of the transistors in the second differential transistor pair.

9. The receiver circuit according to claim 7, wherein, it includes a voltage regulator for setting the voltage difference between the second drain side supply voltage node and the second source side supply voltage node.

10. The receiver circuit according to claim 1, wherein, the first stage output is a differential signal pair, and the second stage circuit includes: a differential transistor pair having a drain, a gate, and a source, the drain is connected to the drain side supply voltage via a first current mirror transistor and a second current mirror transistor, the gates are respectively connected to each of the differential signal pair of the first stage output, and the source is connected to a current source transistor.

11. The receiver circuit according to claim 10, wherein, the current source transistor has a gate, and the gate is connected to the drain of one of the transistors in the differential transistor pair.

12. The receiver circuit according to claim 10, wherein, it includes a voltage regulator for generating the drain side supply voltage.

13. A receiver circuit, wherein, it includes: a first differential transistor pair having a drain connected to a first drain side supply voltage node via a first matching resistor and a second matching resistor and a source connected to a current source transistor, the first transistor in the first differential pair has a gate connected to a reference voltage, and the second transistor in the first differential pair has a gate connected to a first stage input, the drain of the first differential transistor pair provides a differential signal pair as a first stage output; a reference current circuit connected to the first drain side supply voltage node, including a reference resistor, a first transistor, and a second transistor, the reference resistor, the first transistor, and the second transistor are connected in series, the first transistor has a gate connected to the reference voltage, the second transistor has a gate, the gate is connected to a node and connected to the gate of the current source transistor, the node is located between the reference resistor and the first transistor of the reference current circuit, and the current source transistor is connected to the first differential transistor pair; a second differential transistor pair having a drain, a gate, and a source, the drain is connected to a second drain side supply voltage node via a first current mirror transistor and a second current mirror transistor, the gates are connected to the respective ones of the differential signal pair, and the source is connected to a second current source transistor; and a buffer circuit connected to the drain of one of the second differential transistor pair.

14. The receiver circuit according to claim 13, wherein, the second current source transistor has a gate connected to the drain of the second one of the second differential transistor pair.

15. The receiver circuit according to claim 13, wherein, it includes a voltage regulator for setting the voltage difference between the second drain side supply voltage node and the second source side supply voltage node.

16. The receiver circuit according to claim 13, wherein, the first differential transistor pair is disposed in a first power domain, and the second differential transistor pair is disposed in a second power domain different from the first power domain.

17. The receiver circuit according to claim 13, wherein, the buffer circuit has a trip point voltage, and the second differential transistor pair has a common-mode voltage matching the trip point voltage.

18. The receiver circuit according to claim 17, wherein, the reference current circuit includes circuit elements configured to establish a first-stage common-mode voltage of the differential signal pair such that a signal on the drain of one of the second differential transistor pair has the common-mode voltage matching the trip point voltage.

19. A data receiver, wherein, comprising: a first amplifier circuit configured to receive a reference voltage and a first-stage input signal and output a control voltage based on the reference voltage and the first-stage input signal; and a self-biased amplifier circuit configured to receive the control voltage from the first amplifier circuit, set a self-bias voltage, and provide an output signal, wherein the self-bias voltage is connected to a current mirror of the self-biased amplifier circuit; and a buffer circuit having a trip point voltage, the buffer circuit being connected to the output of the self-biased amplifier circuit, wherein the buffer circuit includes an inverter having the trip point voltage, which is connected to the output of the self-biased amplifier circuit; wherein, the control voltage output by the first amplifier circuit is a differential signal pair, the self-biased amplifier circuit includes a differential transistor pair and a voltage regulator, the differential transistor pair has a drain, a gate, and a source, the drain is connected to a drain-side supply voltage via a first current mirror transistor and a second current mirror transistor, the gates are respectively connected to each of the differential signal pair of the first-stage output, and the source is connected to a current source transistor; the current source transistor has a gate connected to the drain of one of the transistors in the differential transistor pair; the voltage regulator is used to generate a source-side supply voltage, and the source-side supply voltage is connected to the source of the current source transistor.

Images