Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel comprises a perforated area and a display area disposed adjacent to each other. The display panel includes a drive array substrate located in the display area and a light-emitting device layer located on the drive array substrate. The drive array substrate includes a substrate, and a drive circuit layer and a fan-out wiring layer located in sequence on the substrate. The drive circuit layer includes a plurality of first data lines and a plurality of second data lines extending along a first direction. The second data lines are divided into first sub-data lines and second sub-data lines by the perforated area in the first direction. The fan-out wiring layer includes a plurality of fan-out wirings electrically connected to the plurality of first data lines and the plurality of second data lines in a one-to-one correspondence, and a plurality of data line connection lines electrically connected to the plurality of second data lines in a corresponding manner. The two ends of the data line connection lines are electrically connected to the corresponding first sub-data lines and the second sub-data lines, respectively. The present application facilitates reducing the bezel around the display area and the bezel around the perforated area, thereby achieving an extremely narrow bezel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) display panels have gradually replaced LCD (Liquid Crystal Display) as the next-generation display technology due to their advantages in display performance, such as high contrast, wide color gamut, and low power consumption. Compared to traditional LCD panels, OLED display panels are easier to make flexible and are a key technology for wearable and foldable products.

[0003] With the advancement of OLED panel technology, OLED displays are no longer limited to the development of wearable and foldable products. To achieve better display effects and provide users with a better visual experience, narrow-bezel technology has gradually become a major attraction for users. However, due to limitations in panel resolution, vapor deposition accuracy, and packaging, panel bezels are still relatively large. Summary of the Invention

[0004] The present application provides a display panel and a display device. On the basis of setting the fan-out wiring in the display area, the data line connection line is also set in the display area, which is beneficial to reducing the border around the display area and reducing the border of the hole area, thereby achieving an extremely narrow border.

[0005] The present application provides a display panel having a hole-punch area and a display area adjacent to each other; the display panel comprises a drive array substrate located in the display area and a light-emitting device layer located on the drive array substrate; the drive array substrate comprises a substrate and a drive circuit layer and a fan-out wiring layer sequentially located on the substrate;

[0006] The driving circuit layer includes a plurality of first data lines and a plurality of second data lines extending along a first direction; the second data lines are divided into first sub-data lines and second sub-data lines by the hole area in the first direction; the fan-out routing layer includes a plurality of fan-out routing lines electrically connected to the plurality of first data lines and the plurality of second data lines in a one-to-one correspondence, and a plurality of data line connecting lines electrically connected to the plurality of second data lines in correspondence; the two ends of the data line connecting line are respectively electrically connected to the corresponding first sub-data lines and the second sub-data lines.

[0007] Optionally, the data line connection line and at least part of the fan-out lines are arranged on the same layer.

[0008] Optionally, the fan-out routing layer includes a first routing layer and a second routing layer sequentially located on the driving circuit layer;

[0009] The fan-out wiring is located at least in one of the first wiring layer and the second wiring layer; and the data line connection line is located at least in one of the first wiring layer and the second wiring layer.

[0010] Optionally, the driving circuit layer further includes a plurality of scan lines extending along a second direction perpendicular to the first direction; the plurality of scan lines are insulated from the plurality of first data lines and the plurality of second data lines and cross to form a plurality of pixel areas arranged in multiple rows and columns;

[0011] The data line connecting line includes a first data line connecting portion extending along the first direction, a second data line connecting portion extending along the second direction, and a third data line connecting portion; one end of the second data line connecting portion is electrically connected to the corresponding first sub-data line, and the other end is electrically connected to one end of the first data line connecting portion; the other end of the first data line connecting portion is electrically connected to one end of the third data line connecting portion; and the other end of the third data line connecting portion is electrically connected to the corresponding second sub-data line;

[0012] The first data line connection portion is disposed corresponding to the plurality of pixel regions in the column direction, and the second data line connection portion and the third data line connection portion are disposed corresponding to the plurality of pixel regions in two different row directions.

[0013] Optionally, each of the pixel areas includes at least one line-changing hole extending in a direction perpendicular to the display panel and used to connect different metal layers; the first data line connection portion includes a bending portion arranged corresponding to the line-changing hole in the corresponding pixel area; the bending portion bends in a direction away from the corresponding line-changing hole.

[0014] Optionally, the shape of the bending portion includes any one of a rectangle, a triangle and an arc.

[0015] Optionally, an orthographic projection of at least one first data line on the substrate is located between orthographic projections of two adjacent first data line connecting portions on the substrate.

[0016] Optionally, at least a portion of the first data line connecting portion is overlapped with a middle position of the corresponding plurality of pixel regions.

[0017] Optionally, the display area is arranged around the hole area, and the hole area is symmetrical about a symmetry axis extending along the first direction; and the plurality of data line connection lines are symmetrically arranged about the symmetry axis.

[0018] The present application also provides a display device, comprising the display panel and driver integrated circuit described above; the display panel also includes a binding area located on one side of the display area; the driver integrated circuit is bound and connected to the binding area; the fan-out line extends from the display area to the binding area and is electrically connected to the driver integrated circuit.

[0019] The display panel and display device provided by the present application arrange both the fan-out routing and the data line connection line in the display area, specifically in the fan-out routing layer located on the driving circuit layer, so that the fan-out routing and the data line connection line are arranged in a different layer from the first data line and the second data line in the driving circuit layer; on the one hand, it is possible to avoid arranging the fan-out routing in the non-display area to reduce the width of the border around the display area; on the other hand, it is possible to avoid arranging the data line connection line at the edge of the hole area, which is conducive to reducing the width of the border of the hole area; on the other hand, it is possible to avoid arranging the fan-out routing and the data line connection line in the driving circuit layer, thereby avoiding unstable signal transmission caused by too dense wiring; therefore, the present application achieves an extremely narrow border of the display panel on the basis of ensuring a stable display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0021] Figure 1 A top view of a display panel provided in an embodiment of the present application.

[0022] Figure 2 A schematic diagram of a partial cross-sectional structure of a pixel area of ​​a display panel provided in an embodiment of the present application.

[0023] Figure 3 for Figure 1 A partial enlarged view of area A in the middle.

[0024] Figure 4 for Figure 1 A partial enlarged view of area B in the middle.

[0025] Figure 5 A top view of a partial structure of a display area of ​​a display panel provided in an embodiment of the present application.

[0026] Figure 6 A top view of a partial structure of a display area of ​​another display panel provided in an embodiment of the present application.

[0027] Figure 7 A top view of a data line connection line provided in an embodiment of the present application.

[0028] Figure 8 A top view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0030] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0032] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0033] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0034] Combine Figures 1 to 4 As shown, the embodiment of the present application provides a display panel 1; the display panel 1 has a hole-punch area 2 and a display area 3 adjacent to the hole-punch area 2; Figure 2 As shown, the display panel 1 includes a driving array substrate 4 located in a display area 3 and a light-emitting device layer 5 located on the driving array substrate 4; the driving array substrate 4 includes a substrate 6 and a driving circuit layer 7 and a fan-out wiring layer 8 located in sequence on the substrate 6; the driving circuit layer 7 includes a plurality of first data lines 9 and a plurality of second data lines 10 extending along a first direction (e.g., a vertical direction, i.e., a column direction hereinafter); the second data lines 10 are divided into first sub-data lines 11 and second sub-data lines 12 in the first direction by the hole area 2; as shown Figure 3 and Figure 4 As shown, the fan-out routing layer 8 includes a plurality of fan-out routing lines 13 electrically connected to a plurality of first data lines 9 and a plurality of second data lines 10 in a one-to-one correspondence, and a plurality of data line connecting lines 14 electrically connected to a plurality of second data lines 10; both ends of the data line connecting line 14 are electrically connected to the corresponding first sub-data lines 11 and second sub-data lines 12, respectively.

[0035] It can be understood that the embodiment of the present application will bypass the data line connection line 14 used to connect the first sub-data line 11 and the second sub-data line 12 to the display area 3, avoiding setting the data line connection line 14 at the edge of the hole area 2, which can effectively reduce the border width of the hole area 2; and, the embodiment of the present application will set the fan-out line 13 used to transmit data signals to the first data line 9 and the second data line 10 in the display area 3, avoiding setting the fan-out line 13 in the non-display area, which can effectively reduce the width of the outer border (non-display area) of the display area 3, that is, reduce the outer border width of the display panel 1.

[0036] Specifically, the display panel 1 includes a through hole located in the hole area 2 and extending perpendicularly to the display panel 1 through at least the drive array substrate 4 and the light-emitting device layer 5 of the display panel 1, for arranging an under-screen camera or other optical device. The display area 3 can be arranged around the entire hole area 2 or along a portion of the edge of the hole area 2, without limitation. For ease of description, the embodiment of the present application is described as an example in which the display area 3 is arranged around the hole area 2.

[0037] Specifically, the substrate 6 of the driving array substrate 4 may be a flexible substrate. Figure 2 As shown, the substrate 6 includes a first flexible layer 15 and a first buffer layer 16 and a second flexible layer 17 sequentially arranged on the first flexible layer 15; wherein the materials of the first flexible layer 15 and the second flexible layer 17 are organic materials, such as polyimide (PI), and the material of the first buffer layer 16 is inorganic material, such as at least one of silicon oxide and silicon nitride.

[0038] In one embodiment, Figure 2 As shown, a second buffer layer 18 is further provided on the side of the driving circuit layer 7 close to the substrate 6; of course, in other embodiments, a barrier layer may also be provided on the side of the driving circuit layer 7 close to the substrate 6, and the order of the second buffer layer 18 and the barrier layer is not limited.

[0039] Specifically, the driving circuit layer 7 of the driving array substrate 4 includes a plurality of pixel driving circuit units 19 distributed in an array, a plurality of data lines (e.g., a plurality of first data lines 9 and a plurality of second data lines 10) electrically connected to the plurality of pixel driving circuit units 19, and a plurality of scan lines 20. Of course, the driving circuit layer 7 also includes power signal lines (e.g., a VDD signal line) arranged in parallel with the data lines and other signal lines (e.g., an EM signal line) arranged in parallel with the scan lines 20.

[0040] Specifically, the scan lines 20 extend in a second direction perpendicular to the first direction (e.g., a horizontal direction, hereinafter referred to as a row direction). The scan lines 20 are insulated from and intersect with the first data lines 9 and the second data lines 10 to form a plurality of pixel regions 21 arranged in multiple rows and columns. Each pixel region 21 corresponds to a pixel driving circuit unit 19.

[0041] Specifically, the pixel driving circuit unit 19 includes at least one thin film transistor. In a specific embodiment, the pixel driving circuit unit 19 includes a 7T1C pixel driving circuit, but is not limited thereto.

[0042] In one specific embodiment, the driving thin film transistor in the pixel driving circuit unit 19 includes an active layer 22 (e.g., polysilicon), a first gate insulating layer 23, a first gate layer 24, a second gate insulating layer 25, an interlayer insulating layer 27, and a source-drain electrode layer, sequentially located on the substrate 6. The source and drain electrodes in the source-drain electrode layer are electrically connected to both ends of the active layer 22 via through-holes penetrating the first gate insulating layer 23, the second gate insulating layer 25, and the interlayer insulating layer 27. The first gate, the second gate, and the active layer 22 are disposed correspondingly. Specifically, the source-drain electrode layer may have a double-layer electrode structure, for example, including a first source-drain electrode layer 28 and a second source-drain electrode layer 29 sequentially located on the interlayer insulating layer 27. A first planarizing layer 30 located between the first source-drain electrode layer 28 and the second source-drain electrode layer 29, and a second planarizing layer 31 located on the side of the second source-drain electrode layer 29 away from the first source-drain electrode layer 28 are further provided on the side of the pixel driving circuit unit 19 away from the substrate 6.

[0043] It is understood that the scan line 20 is provided in the same layer as the gate layer (the first gate layer 24 or the second gate layer 26), and the first data line 9 and the second data line 10 are provided in the same layer as the source-drain electrode layer (the first source-drain electrode layer 28 or the second source-drain electrode layer 29). It should be noted that the present application does not limit the number and type of thin-film transistors in the pixel driving circuit unit 19, and the structure of the driving thin-film transistor described above is merely an exemplary description.

[0044] Specifically, the light emitting device layer 5 includes a plurality of organic light emitting devices (eg, OLED devices) electrically connected to the plurality of pixel driving circuit units 19 in a one-to-one correspondence. In one embodiment, the plurality of organic light emitting devices are disposed in a one-to-one correspondence with the plurality of pixel regions 21 .

[0045] Specifically, the first data line 9 does not intersect the hole-punch area 2, that is, the first data line 9 is not affected by the hole-punch area 2 and extends normally and continuously in the first direction. The second data line 10 is arranged corresponding to the hole-punch area 2 and is divided into two parts by the hole-punch area 2 in the first direction, namely, a first sub-data line 11 and a second sub-data line 12. It can be understood that the data signals on the first sub-data line 11 and the second sub-data line 12 are the same.

[0046] In one embodiment, Figure 3 As shown, each first data line 9 is electrically connected to a column of pixel driving circuit units 19 (or pixel areas 21), and each second data line 10 is electrically connected to a column of pixel driving circuit units 19 (or pixel areas 21); the first data line 9 and the second data line 10 respectively provide data signals to the corresponding pixel driving circuit units 19.

[0047] Specifically, such as Figure 3As shown, the scan line 20 includes multiple first scan lines 32 and multiple second scan lines 33; the second scan line 33 is divided into two parts by the hole area 2, for example, a first sub-scan line and a second sub-scan line located on either side of the hole area 2 in the second direction. In one specific embodiment, the display panel 1 includes a GOA circuit located on either side of the display area 3 in the second direction, respectively providing scan signals to the scan line 20 from both sides. Specifically, the first sub-scan line and the second sub-scan line are respectively connected to two GOA circuits, and the two GOA circuits provide scan signals to the first sub-scan line and the second sub-scan line from both sides, avoiding the need to provide a scan line connection line for connecting the first sub-scan line and the second sub-scan line in the display area 3. In another embodiment, the display panel 1 also includes a scan line connection line located in the display area 3 and on the fan-out routing layer 8, for connecting the first sub-scan line and the second sub-scan line. Even with only one GOA circuit, scan signals can still be normally provided to the first sub-scan line and the second sub-scan line. This embodiment of the present application does not provide a detailed description of the scan line connection line; its specific configuration can refer to the configuration of the data line connection line 14.

[0048] Specifically, such as Figure 1 As shown, the display panel 1 also includes a binding area 36 located at least on one side of the display area 3 for arranging a driver integrated circuit (IC). One end of the fan-out trace 13 in the fan-out trace layer 8 extends to the binding area 36 and is electrically connected to the driver integrated circuit, and the other end is electrically connected to the corresponding data line or scan line in the display area 3. In the embodiment of the present application, the electrical connection between the fan-out trace and the data line is used as an example for description, but the invention is not limited to this.

[0049] It can be understood that, usually, the hole area 2 is set in the upper half of the display panel 1, and the binding area 36 is set at the lower frame of the display panel 1, so the wiring areas of the data line connection line 14 and the fan-out line 13 may not overlap, which is beneficial to reduce the wiring density and increase the line spacing, thereby improving the stability of the signal.

[0050] Specifically, the data line connection line 14 and at least part of the fan-out wiring 13 are arranged on the same layer.

[0051] Specifically, the fan-out routing layer 8 includes at least one routing layer; when multiple fan-out routing lines 13 are located in the same routing layer, the data line connection line 14 is set on the same layer as the fan-out routing lines 13; when multiple fan-out routing lines 13 are distributed in multiple routing layers, the data line connection line 14 can be set on the same layer as only one of the routing layers, or can be distributed in multiple routing layers like the fan-out routing lines 13.

[0052] In one embodiment, Figure 2As shown, the fan-out routing layer 8 includes a first routing layer 37 and a second routing layer 38, which are sequentially located on the driver circuit layer 7. The fan-out routing lines 13 are located on at least one of the first routing layer 37 and the second routing layer 38. Furthermore, the data line connection lines 14 are located on at least one of the first routing layer 37 and the second routing layer 38. For example, some fan-out routing lines 13 are located on the first routing layer 37, while others are located on the second routing layer 38. This avoids multiple fan-out routing lines 13 being distributed on the same layer, which would result in overly dense wiring. Alternatively, each fan-out routing line 13 includes two electrically connected routing sections, one of which is located on the first routing layer 37 and the other on the second routing layer 38. This also avoids overly dense wiring.

[0053] In one embodiment, the data connection line 14 is located in the first wiring layer 37 .

[0054] In another specific embodiment, the data connection line 14 is located in the second routing layer 38 .

[0055] In another specific embodiment, some of the data line connection lines 14 are located in the first routing layer 37 , and another part of the data line connection lines 14 are located in the second routing layer 38 .

[0056] In another specific embodiment, part of each data line connection line 14 is located in the first routing layer 37 , and another part of each data line connection line is located in the second routing layer 38 , and the two parts of each data line connection line are connected through a via.

[0057] Specifically, such as Figure 2 As shown, a third flat layer 39 is provided between the first wiring layer 37 and the second wiring layer 38, and a fourth flat layer 40 is provided on the side of the second wiring layer 38 away from the first wiring layer 37; the light-emitting device layer 5 includes an anode layer 41, a pixel definition layer 42, a support layer 43, a light-emitting layer 44 and a cathode layer 45 sequentially located on the fourth flat layer 40; the anode layer 41, the light-emitting layer 44 and the cathode layer 45 constitute an organic light-emitting device.

[0058] In one embodiment, Figure 2 As shown, the anode layer 41 and the source / drain electrode layer are electrically connected via a first connecting electrode 46 located on the second source / drain electrode layer 29 and extending through the first planar layer 30, a second connecting electrode 47 located on the first wiring layer 37 and extending through the second planar layer 31, a third connecting electrode 48 located on the second wiring layer 38 and extending through the third planar layer 39, and a fourth connecting electrode 49 located on the fourth planar layer 40 and extending through the fourth planar layer 40. The materials of the first connecting electrode 46, the second connecting electrode 47, and the third connecting electrode 48 include, but are not limited to, indium tin oxide (ITO); and the material of the fourth connecting electrode 49 includes, but is not limited to, indium zinc oxide (IZO).

[0059] Specifically, such as Figure 3 As shown, the data line connection line 14 includes a first data line connection portion 50 extending along the first direction and a second data line connection portion 51 and a third data line connection portion 52 extending along the second direction; one end of the second data line connection portion 51 is electrically connected to the corresponding first sub-data line 11, and the other end is electrically connected to one end of the first data line connection portion 50; the other end of the first data line connection portion 50 is electrically connected to one end of the third data line connection portion 52; the other end of the third data line connection portion 52 is electrically connected to the corresponding second sub-data line 12; the first data line connection portion 50 is arranged corresponding to a plurality of pixel areas 21 in the column direction, and the second data line connection portion 51 and the third data line connection portion 52 are arranged corresponding to a plurality of pixel areas 21 in two different row directions.

[0060] It can be understood that the first data line connection portion 50, the second data line connection portion 51 and the third data line connection portion 52 can be located in the same routing layer, for example, in the first routing layer 37 or the second routing layer 38; of course, they can also be located in different routing layers, for example, the first data line connection portion 50 is located in the second routing layer 38, and the second data line connection portion 51 and the third data line connection portion 52 are located in the first routing layer 37.

[0061] Specifically, such as Figure 5 and Figure 6 As shown, each pixel region 21 includes at least one wiring hole 53 extending perpendicular to the display panel 1 and used to connect different metal layers; the first data line connection portion 50 includes a bending portion 54 corresponding to the wiring hole 53 in the corresponding pixel region 21; the bending portion 54 bends away from the corresponding wiring hole 53 to avoid the wiring hole 53. It can be understood that the wiring hole 53 is filled with a conductive material (such as ITO) to connect the wiring or electrodes of the upper and lower layers.

[0062] Understandably, Figure 7 As shown, the first data line connection portion 50 extends in a bent shape in the first direction; specifically, the shape of the bent portion 54 includes any one of a rectangle, a triangle and an arc. This application only takes the rectangular bent portion 54 as an example for explanation, and the specific shape is not limited to the ones listed above.

[0063] Specifically, such as Figure 5 and Figure 6 As shown, the orthographic projection of at least one first data line 9 on the substrate 6 is located between the orthographic projections of two adjacent first data line connecting portions 50 on the substrate 6. It is understandable that multiple first data line connecting portions 50 can be provided corresponding to multiple sequentially adjacent columns of pixel areas 21, or one first data line connecting portion 50 can be provided corresponding to at least two columns of pixel areas 21.

[0064] In one embodiment, at least a portion of the first data line connecting portion 50 is overlapped with the middle position of the corresponding plurality of pixel regions 21 to achieve an optimal light shielding effect;

[0065] In one embodiment, Figure 3 As shown, the display area 3 is arranged around the hole area 2 and the hole area 2 is symmetrical about the symmetry axis L extending along the first direction; the plurality of data line connection lines 14 are symmetrically arranged about the symmetry axis L. Specifically, the plurality of second data lines 10 are also symmetrically arranged about the symmetry axis L.

[0066] Specifically, the material of the fan-out trace 13 and the data line connection line 14 includes ITO, but is not limited thereto.

[0067] In an embodiment of the present application, the fan-out routing 13 and the data line connection line 14 are both arranged in the display area 3, specifically in the fan-out routing layer 8 located on the driving circuit layer 7, so that the fan-out routing 13 and the data line connection line 14 are arranged in different layers from the first data line 9 and the second data line 10 in the driving circuit layer 7; on the one hand, it is possible to avoid setting the fan-out routing 13 in the non-display area to reduce the border width outside the display area 3; on the other hand, it is possible to avoid setting the data line connection line 14 at the edge of the hole area 2, which is beneficial to reducing the border width of the hole area 2; on the other hand, it is possible to avoid setting the fan-out routing 13 and the data line connection line 14 in the driving circuit layer 7, thereby avoiding unstable signal transmission caused by too dense wiring of the driving circuit layer 7; therefore, the present application achieves an extremely narrow border of the display panel 1 on the basis of ensuring a stable display effect.

[0068] Combine Figures 1 to 8 As shown, the embodiment of the present application further provides a display device 55, which includes the aforementioned display panel 1 and a driver integrated circuit 56. The display panel 1 also includes a binding area 36 located on one side of the display area 3. The driver integrated circuit 56 is bound and connected to the binding area 36. The fan-out trace 13 extends from the display area 3 to the binding area 36 and is electrically connected to the driver integrated circuit 56. The driver integrated circuit 56 provides signals to the data lines and scan lines 20 in the display area 3 through the fan-out trace 13.

[0069] In an embodiment of the present application, the fan-out routing 13 and the data line connection line 14 are both arranged in the display area 3, specifically in the fan-out routing layer 8 located on the driving circuit layer 7, so that the fan-out routing 13 and the data line connection line 14 are arranged in different layers from the first data line 9 and the second data line 10 in the driving circuit layer 7; on the one hand, it is possible to avoid setting the fan-out routing 13 in the non-display area to reduce the border width outside the display area 3; on the other hand, it is possible to avoid setting the data line connection line 14 at the edge of the hole area 2, which is beneficial to reducing the border width of the hole area 2; on the other hand, it is possible to avoid setting the fan-out routing 13 and the data line connection line 14 in the driving circuit layer 7, thereby avoiding unstable signal transmission caused by too dense wiring of the driving circuit layer 7; therefore, the present application achieves an extremely narrow border of the display device 55 on the basis of ensuring a stable display effect.

[0070] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0071] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a hole-punch area and a display area arranged adjacent to each other; the display panel comprises a drive array substrate located in the display area and a light-emitting device layer located on the drive array substrate; the drive array substrate comprises a substrate and a drive circuit layer and a fan-out wiring layer sequentially located on the substrate; The driving circuit layer includes a plurality of first data lines and a plurality of second data lines extending along a first direction; the second data lines are divided into first sub-data lines and second sub-data lines by the hole area in the first direction; the fan-out routing layer includes a plurality of fan-out routings and a plurality of data line connecting lines, the two ends of the data line connecting lines are respectively electrically connected to the corresponding first sub-data lines and the second sub-data lines, and the plurality of fan-out routings are electrically connected to the plurality of first data lines and the plurality of second data lines in a one-to-one correspondence.

2. The display panel according to claim 1, wherein: The data line connection line is arranged on the same layer as at least part of the fan-out wiring.

3. The display panel according to claim 2, wherein: The fan-out routing layer includes a first routing layer and a second routing layer sequentially located on the driving circuit layer; The fan-out wiring is located at least in one of the first wiring layer and the second wiring layer; and the data line connection line is located at least in one of the first wiring layer and the second wiring layer.

4. The display panel according to claim 1, wherein: The driving circuit layer further includes a plurality of scanning lines extending along a second direction perpendicular to the first direction; the plurality of scanning lines are insulated from the plurality of first data lines and the plurality of second data lines and cross to form a plurality of pixel areas arranged in multiple rows and columns; The data line connecting line includes a first data line connecting portion extending along the first direction, a second data line connecting portion extending along the second direction, and a third data line connecting portion; one end of the second data line connecting portion is electrically connected to the corresponding first sub-data line, and the other end is electrically connected to one end of the first data line connecting portion; the other end of the first data line connecting portion is electrically connected to one end of the third data line connecting portion; and the other end of the third data line connecting portion is electrically connected to the corresponding second sub-data line; The first data line connection portion is disposed corresponding to the plurality of pixel regions in a column direction, and the second data line connection portion and the third data line connection portion are disposed corresponding to the plurality of pixel regions in two different row directions.

5. The display panel according to claim 4, wherein: Each of the pixel areas includes at least one line-changing hole extending in a direction perpendicular to the display panel and used to connect different metal layers; the first data line connection portion includes a bending portion arranged corresponding to the line-changing hole in the corresponding pixel area; the bending portion bends in a direction away from the corresponding line-changing hole.

6. The display panel according to claim 5, wherein: The shape of the bending portion includes any one of a rectangle, a triangle and an arc.

7. The display panel according to claim 4, wherein: An orthographic projection of at least one first data line on the substrate is located between orthographic projections of two adjacent first data line connecting portions on the substrate.

8. The display panel according to claim 4, wherein: At least a portion of the first data line connecting portion is overlapped with a middle position of the corresponding plurality of pixel regions.

9. The display panel according to claim 1, wherein: The display area is arranged around the hole-punching area, and the hole-punching area is symmetrical about a symmetry axis extending along the first direction; the plurality of data line connection lines are symmetrically arranged about the symmetry axis.

10. A display device, characterized in that: It comprises a display panel and a driver integrated circuit as described in any one of claims 1 to 9; the display panel also includes a binding area located on one side of the display area; the driver integrated circuit is bound and connected to the binding area; the fan-out line extends from the display area to the binding area and is electrically connected to the driver integrated circuit.

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