Array substrate, display panel

Abstract

The present application discloses an array substrate and a display panel, comprising: a base substrate, and a routing layer and a light-emitting layer stacked in sequence on the base substrate, wherein the routing layer comprises a signal routing 2, a first routing and a second routing; the projection of the first routing on the base substrate and the projection of the second routing on the base substrate are separated from each other, and the first routing and the second routing are respectively arranged on both sides below the light-emitting layer; the signal routing 2 is located between the first routing and the second routing, and the projection of the first routing on the base substrate and the projection of the second routing on the base substrate overlap with the projections of the two edges of the light-emitting layer on the base substrate respectively; in the extension direction of the signal routing 2, the length of the second routing is less than the length of the signal routing 2. The technical solution of the embodiment of the present invention can improve the color deviation phenomenon.

Description

[0001] This divisional application is a divisional application with application date of March 28, 2019, application number 2019102449018, and name “Array substrate, preparation method thereof, display panel, device and pixel driving circuit”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0003] In recent years, with the advancement of display technology, organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research. More and more active matrix organic light emitting diode (AMOLED) display panels have entered the market. Compared with traditional thin film transistor liquid crystal display panels (TFTLCD), AMOLED has faster response speed, higher contrast and wider viewing angle. And with the development of display technology, more and more electronic devices have begun to use thin and light and good impact resistance bendable flexible OLED display screens.

[0004] Traditional display technologies all use a single display method. When viewing, for example, when the user's viewing direction changes from the left side of the screen to the right side of the screen, the brightness, contrast, color gamut and visual color bias (color difference at different viewing angles) of the LCD display device will change, resulting in a reduction in visual effects. This is especially true for some high-end displays or special display venues, such as medical and graphic design fields, which have high requirements for visual color bias and need to improve the visual color bias of ordinary display panels.

[0005] OLED displays mainly display images by driving electroluminescent devices to emit light through current. When the user's viewing angle changes, the brightness and contrast of the display will also change, resulting in color shift. Therefore, how to improve the color shift problem of the OLED display area and improve the display effect of the display panel is a problem that needs to be solved urgently. Summary of the invention

[0006] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a display substrate that can improve the utilization rate of the mask plate to reduce the production and development costs.

[0007] In a first aspect, an embodiment of the present invention provides an array substrate, including:

[0008] A base substrate, and a wiring layer and a light-emitting layer sequentially stacked on the base substrate, wherein the wiring layer includes a signal wiring 2, a first wiring, and a second wiring;

[0009] The projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate are separated from each other, and the first wiring and the second wiring are respectively arranged on two sides below the light-emitting layer;

[0010] The signal wiring 2 is located between the first wiring and the second wiring, and the projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate respectively overlap with the projections of two edges of the light-emitting layer on the base substrate;

[0011] In the extending direction of the signal line 2 , the length of the second line is smaller than the length of the signal line 2 .

[0012] Optionally, the first wiring and the second wiring are arranged on both sides of a center line of the light-emitting layer.

[0013] Optionally, an extension direction of the signal wiring 2 , an extension direction of the first wiring, and an extension direction of the second wiring are parallel to a center line of the light-emitting layer.

[0014] Optionally, an overlapping projection area of ​​a projection of the second wiring on the base substrate and the light-emitting layer on the base substrate is smaller than an overlapping projection area of ​​a projection of the signal wiring 2 on the base substrate and the light-emitting layer on the base substrate.

[0015] Optionally, the length of the projection of the second routing line on the substrate and the overlapping projection of the light-emitting layer on the substrate in the extension direction of the signal routing line 2 is less than the length of the projection of the signal routing line 2 on the substrate and the overlapping projection of the light-emitting layer on the substrate in the extension direction of the signal routing line 2.

[0016] Optionally, an overlapping pattern of a projection of the second wiring on the base substrate and a projection of the light-emitting layer on the base substrate is a trapezoid.

[0017] Optionally, the length of an overlapping pattern of the projection of the second routing line on the substrate and the projection of the light-emitting layer on the substrate is closer to the signal routing line 2 in the extension direction of the signal routing line 2 than the length of an overlapping pattern of the projection of the second routing line on the substrate and the projection of the light-emitting layer on the substrate is farther from the signal routing line 2 in the extension direction of the signal routing line 2.

[0018] Optionally, a surface of the first wiring facing away from the substrate is flush with a surface of the second wiring facing away from the substrate.

[0019] Optionally, the first routing line and the second routing line are located in the same routing layer.

[0020] Optionally, the second routing line is an SD metal routing line.

[0021] Optionally, the second routing line and the first routing line access different signals.

[0022] Optionally, the signal routing line 2 , the first routing line and the second routing line are located in the same routing layer.

[0023] Optionally, a distance from an area A of the light-emitting layer corresponding to the first wiring to the substrate is equal to a distance from an area B of the light-emitting layer corresponding to the second wiring to the substrate.

[0024] In a second aspect, an embodiment of the present invention provides a display panel, comprising any of the above array substrates.

[0025] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0026] An array substrate provided by an embodiment of the present invention comprises a base substrate, and a wiring layer and a light-emitting layer stacked in sequence on the base substrate, wherein the wiring layer comprises a first wiring and a second wiring, the projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate are separated from each other, and the first wiring and the second wiring are respectively arranged on both sides below the light-emitting layer. Compared with the prior art, the first wiring and the second wiring are respectively arranged on both sides below the light-emitting layer of the array substrate, so that the film thickness of the light-emitting layer is equal, the brightness decays uniformly on both sides, and the purpose of improving color deviation is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0028] Figure 1 A top view of an arrangement of the wiring layer of the array substrate;

[0029] Figure 2 for Figure 1 A cross-sectional view of the array substrate;

[0030] Figure 3 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0031] Figure 4 A top view of the arrangement of the routing layer provided in an embodiment of the present application;

[0032] Figure 5 A flowchart of a method for preparing an array substrate provided in an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of a pixel driving circuit provided by an embodiment of the present invention.

[0034] Wherein, the reference numerals are:

[0035] 10 - substrate; 20 - routing layer; 30 - flat layer; 40 - light-emitting layer; 21 - signal routing 1; 22 - signal routing 2; 23 - first routing; 24 - second routing. DETAILED DESCRIPTION

[0036] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0037] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0038] First, if Figure 1 and Figure 2 The figures show a top view and a cross-sectional view of an arrangement of the wiring layer of the array substrate.

[0039] Reference Figure 1 and Figure 2 In the pixel structure arranged in GGRB, signal line 1 is located below region A of the light-emitting layer 40, signal line 2 is located below the center line of the light-emitting layer 40, and there is no signal line below region B of the light-emitting layer 40. This distribution biased to one side of the pixel will cause the flat layer 30 to tilt, so that the heights of region A and region B of the light-emitting layer 40 are inconsistent, that is, the light-emitting layer 40 is higher in region A and lower in region B, which causes the pixel to tilt, causing the brightness to decay too slowly on one side, resulting in redness on one side, and ultimately leading to RGB color differences on both sides. When the user's viewing angle changes, the brightness and contrast of the display will change, resulting in color shift.

[0040] In view of the above defects, an embodiment of the present invention provides an array substrate that can improve the color shift phenomenon.

[0041] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0042] like Figure 3 , which is a schematic structural diagram of an array substrate provided by an embodiment of the present invention.

[0043] The array substrate comprises:

[0044] A base substrate 10, and a wiring layer 20 and a light-emitting layer 40 stacked in sequence on the base substrate 10, the wiring layer 20 includes a first wiring 23 and a second wiring 24, wherein a projection of the first wiring 23 on the base substrate 10 and a projection of the second wiring 24 on the base substrate 10 are separated from each other, and the first wiring 23 and the second wiring 24 are respectively located on both sides below the light-emitting layer 40.

[0045] A planarization layer 30 may be formed between the wiring layer 20 and the light emitting layer 40 .

[0046] In the embodiment of the present application, the first wiring 23 may correspond to Figure 1 The second routing line 24 is a newly added virtual routing line. The second routing line 24 is similar to the first routing line 23 only in appearance, and it does not have the function of the first routing line 23. Its main function is to make the film thickness of the A area and the B area the same.

[0047] Optionally, a surface of the first wiring 23 facing away from the base substrate 1 may be flush with a surface of the second wiring 24 facing away from the base substrate 1 .

[0048] Optionally, a projection of the first wiring 23 on the base substrate 10 and a projection of the second wiring 24 on the base substrate 10 respectively overlap with projections of two edges of the light emitting layer 40 on the base substrate 10 .

[0049] In addition, the first wiring 23 and the second wiring 24 may also be symmetrically arranged relative to the center line of the light emitting layer 40 .

[0050] Optionally, the first wiring 23 may be a source drain (SD) wiring, and the second wiring 24 may be referred to as a virtual SD wiring.

[0051] The above arrangement can further ensure that the film thickness of area A and area B is the same, and the brightness decays uniformly on both sides, thereby achieving the purpose of improving color deviation.

[0052] like Figure 4 , which is a top view of the arrangement of the routing layer provided in the embodiment of the present application. Among them, the Dummy SD routing in the B area is a virtual SD routing newly added in the embodiment of the present application.

[0053] Further, the substrate 10 may include a flexible backplane and an interlayer dielectric (ILD) layer formed on the flexible backplane, wherein:

[0054] The first wiring 23 and the second wiring 24 are formed on the surface of the interlayer dielectric layer facing away from the flexible backplane.

[0055] An array substrate provided by an embodiment of the present invention comprises a base substrate, and a wiring layer and a light-emitting layer stacked in sequence on the base substrate, wherein the wiring layer comprises a first wiring and a second wiring, the projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate are separated from each other, and the first wiring and the second wiring are respectively arranged on both sides below the light-emitting layer. Compared with the prior art, the first wiring and the second wiring are respectively arranged on both sides below the light-emitting layer of the array substrate, so that the film thickness of the light-emitting layer is equal, the brightness decays uniformly on both sides, and the purpose of improving color deviation is achieved.

[0056] refer to Figure 5 , is a flow chart of a method for preparing an array substrate provided in an embodiment of the present invention. The exemplary process is described below in conjunction with the accompanying drawings:

[0057] Step 51, providing a base substrate, forming a routing layer on the surface of the base substrate, the routing layer including a first routing and a second routing, the projection of the first routing on the base substrate and the projection of the second routing on the base substrate are separated from each other, and the first routing and the second routing are respectively located on both sides below the light-emitting layer.

[0058] Specifically, a metal layer is first deposited on the surface of the substrate, and then a photoresist is coated on the surface of the metal layer facing away from the substrate, the photoresist is exposed and developed through a pre-set mask, and then the metal layer is etched to obtain a first routing line, such as an SD routing line, and a second routing line, such as a virtual SD routing line.

[0059] In addition, in order to prevent the array substrate prepared in the embodiment of the present invention from being easily damaged, optionally, after the metal layer is formed, a protective layer for protecting the metal layer may be formed on the metal layer.

[0060] Step 52, forming a light-emitting layer on the surface of the wiring layer.

[0061] Wherein, a flat layer and an electrode layer are first formed in sequence on the surface of the wiring layer, and then a light-emitting layer is formed.

[0062] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, comprising the above array substrate, which is prepared according to the above array substrate preparation method. Other essential components of the display panel are well understood by those skilled in the art and are not described in detail here.

[0063] Based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0064] Other essential components of the display panel should be understood by those skilled in the art and will not be described in detail here.

[0065] like Figure 6 FIG. 1 is a schematic diagram of a pixel driving circuit based on the above array substrate, wherein the pixel driving circuit includes:

[0066] A first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), a capacitor (C1), an organic light emitting diode (D1), and a second wiring, wherein:

[0067] The source of the first thin film transistor (T1) is electrically connected to the virtual SD wiring, the gate is electrically connected to the reset signal, and the drain is electrically connected to the first node A;

[0068] The source of the second thin film transistor (T2) is electrically connected to the second node B, and the drain is electrically connected to the first node A;

[0069] The source of the third thin film transistor (T3) is electrically connected to the second node B, the gate is electrically connected to the first node A, and the drain is electrically connected to the third node C;

[0070] The source of the fourth thin film transistor (T4) is electrically connected to the data signal (Data), and the drain is electrically connected to the third node C;

[0071] The source of the fifth thin film transistor (T5) is connected to the power supply high voltage (VDD), the gate is connected to the light emitting control signal (EM), and the drain is electrically connected to the third node C;

[0072] The source of the sixth thin film transistor (T6) is electrically connected to the second node B, the gate is connected to the light emitting control signal (EM), and the drain is electrically connected to the fourth node D;

[0073] The source of the seventh thin film transistor (T7) is electrically connected to the virtual SD wiring, and the drain is electrically connected to the fourth node D;

[0074] The anode of the organic light emitting diode (D1) is connected to the fourth node, and the cathode is connected to a power low voltage (VSS);

[0075] Two ends of the capacitor (C1) are electrically connected to a first node and a power supply high voltage (VDD) respectively;

[0076] The second wiring is connected to an initialization signal, namely, a Vinit signal.

[0077] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. An array substrate, characterized in that: include: A base substrate, and a wiring layer and a light-emitting layer sequentially stacked on the base substrate, wherein the wiring layer includes a signal wiring 2, a first wiring, and a second wiring; The projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate are separated from each other, and the first wiring and the second wiring are respectively arranged on two sides below the light-emitting layer; The signal wiring 2 is located between the first wiring and the second wiring, and the projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate respectively overlap with the projections of two edges of the light-emitting layer on the base substrate; In the extension direction of the signal line 2, the length of the second line is less than the length of the signal line 2; A surface of the first wiring facing away from the substrate is flush with a surface of the second wiring facing away from the substrate.

2. The array substrate according to claim 1, characterized in that: The first wiring and the second wiring are arranged at two sides of a center line of the light emitting layer.

3. The array substrate according to claim 2, characterized in that: An extension direction of the signal wiring 2 , an extension direction of the first wiring, and an extension direction of the second wiring are parallel to a center line of the light emitting layer.

4. The array substrate according to claim 1, characterized in that: The overlapping projection area of ​​the projection of the second wiring on the base substrate and the light emitting layer on the base substrate is smaller than the overlapping projection area of ​​the projection of the signal wiring 2 on the base substrate and the light emitting layer on the base substrate.

5. The array substrate according to claim 1, characterized in that: The length of the projection of the second routing line on the base substrate and the overlapping projection of the light-emitting layer on the base substrate in the extension direction of the signal routing line 2 is smaller than the length of the projection of the signal routing line 2 on the base substrate and the overlapping projection of the light-emitting layer on the base substrate in the extension direction of the signal routing line 2.

6. The array substrate according to claim 1, characterized in that: The overlapping pattern of the projection of the second wiring on the base substrate and the projection of the light-emitting layer on the base substrate is a trapezoid.

7. The array substrate according to claim 6, characterized in that: The length of the overlapping pattern of the projection of the second routing line on the substrate and the projection of the light-emitting layer on the substrate close to the signal routing line 2 in the extension direction of the signal routing line 2 is longer than the length of the overlapping pattern of the projection of the second routing line on the substrate and the projection of the light-emitting layer on the substrate away from the signal routing line 2 in the extension direction of the signal routing line 2.

8. The array substrate according to claim 1, characterized in that: The first routing line and the second routing line are located in the same routing layer.

9. The array substrate according to claim 1, characterized in that: The second routing line is an SD metal routing line.

10. The array substrate according to claim 1, characterized in that: The second routing line and the first routing line access different signals.

11. The array substrate according to claim 1, characterized in that: The signal routing line 2 , the first routing line and the second routing line are located in the same routing layer.

12. The array substrate according to claim 1, characterized in that: The distance from the light emitting layer in region A corresponding to the first wiring to the substrate is equal to the distance from the light emitting layer in region B corresponding to the second wiring to the substrate.

13. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 12.

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