Method and apparatus for programming operation of memory

Abstract

The application relates to a programming operation method and device of a memory, the memory comprising a first storage string and a first input end and a second input end located at two ends of the first storage string, the first storage string comprising a plurality of first storage units in series, the programming operation method comprising: performing pre-charging of a first programming operation, comprising providing a first preset voltage to the second input end and providing a second preset voltage to a gate layer of a first storage unit in a programmed state, so that the first storage unit in the programmed state is turned on to pre-charge a channel in the first storage string; and performing the first programming operation, the first programming operation programming a plurality of first storage units to be programmed from the first storage unit close to the second input end to the direction away from the second input end, so that when the programming operation is performed on the storage string, the charge density of the channel can be effectively reduced in the pre-charging stage of the programming operation, and the programming interference is reduced.

Description

[0001] This application is a divisional application of the patent filed on January 19, 2021, with application number 202110071215.2, entitled "Programming Operation Method and Apparatus for Memory". Technical Field

[0002] This invention relates to the field of memory technology, and more specifically to a method and apparatus for programming a memory. Background Technology

[0003] With technological advancements, the semiconductor industry is constantly seeking new production methods to enable each memory die in a memory device to have a greater number of memory cells. Among these, 3D NAND memory, due to its advantages such as high storage density and low cost, has become a cutting-edge and highly promising three-dimensional memory technology.

[0004] Currently, in the erasure process of 3D NAND memory, in order to improve erasure efficiency and reduce repeated read and write operations on memory cells, a half-block erasure scheme is adopted. That is, for a memory block that has been written with data, only the data in the upper or lower stack of the memory block is erased, without erasing the data in the other stack.

[0005] In the programming process of 3D NAND memory, pre-charging is required to increase the potential of the entire channel. However, after a partial erase, the channel cannot conduct due to the possibility of the upper or lower stack not being erased. Therefore, pre-charging needs to be performed in different ways. Specifically, when programming the upper stack without erasing the lower stack, a large positive bias voltage is usually provided to the drain terminal during the pre-charging phase of the programming operation to pre-charge the channel, and programming is performed in a top-to-bottom order. However, this programming scheme for the upper stack suffers from the problem that pre-charging cannot effectively increase the channel potential, resulting in severe programming interference. Summary of the Invention

[0006] The purpose of this invention is to provide a method and apparatus for programming a memory, so as to reduce programming interference.

[0007] To address the aforementioned problems, this invention provides a method for programming a memory. The memory includes a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string. The first memory string includes a plurality of first memory cells connected in series. Each first memory cell includes a gate layer, a memory layer storing data states, and a channel. The data states include a programmed state and an unprogrammed state. The programming method includes:

[0008] The pre-charge for performing the first programming operation includes providing a first preset voltage to the second input terminal and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, thereby turning on the first memory cell in the programmed state to pre-charge the channels in the first memory string; and,

[0009] A first programming operation is performed, in which multiple first memory cells to be programmed are programmed from the first memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0010] The duration for which a first preset voltage is provided to the second input terminal is longer than the duration for which a second preset voltage is provided to the gate layer of the first memory cell in the programmed state.

[0011] The first programming operation specifically includes:

[0012] Program the first memory unit currently being programmed;

[0013] When programming of the currently programmed first storage cell is completed, the next first storage cell is updated to the currently programmed first storage cell, and the process returns to the pre-charge step of performing the first programming operation, wherein the next first storage cell is the first storage cell adjacent to the currently programmed first storage cell and located on the side of the currently programmed first storage cell away from the second input terminal.

[0014] The first programming operation specifically includes:

[0015] A programming voltage is provided to the gate layer of the currently programmed first memory cell, and a channel turn-on voltage is provided to the remaining first memory cells.

[0016] The memory further includes a first redundant memory string located between the first memory string and the second input terminal. The first redundant memory string includes at least one first redundant memory cell connected in series. Each first redundant memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data state of at least one first redundant memory cell is a programmed state. The pre-charge for the first programming operation also includes:

[0017] A third preset voltage is provided to the gate layer of the first redundant memory cell in the programmed state to turn on the first redundant memory cell in the programmed state.

[0018] The memory further includes a second memory string located between the first input terminal and the first memory string, and a second redundant memory string located between the first memory string and the second memory string. The second memory string includes a plurality of second memory cells connected in series, and the second redundant memory string includes at least one second redundant memory cell connected in series. Each second memory cell and the second redundant memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data state of at least one second redundant memory cell is a programmed state. The pre-charge for the first programming operation further includes:

[0019] A fourth preset voltage is provided to the gate layer of the second redundant memory cell that is in the programmed state, so that the second redundant memory cell in the programmed state is not turned on.

[0020] The programming operation methods also include:

[0021] After programming multiple first memory cells is completed, a second programming operation is triggered, which includes:

[0022] The pre-charging for the second programming operation includes providing a fifth preset voltage to the second input terminal and a sixth preset voltage to the gate layers of the programmed second memory cell, first memory cell, and second redundant memory cell, thereby turning on the programmed second memory cell, first memory cell, and second redundant memory cell to pre-charge the channels in the first and second memory strings; and,

[0023] A second programming operation is performed, in which multiple second memory cells to be programmed are programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0024] The memory further includes a third redundant memory string located between the second memory string and the first input terminal. The third redundant memory string includes at least one third redundant memory cell connected in series. Each third redundant memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data state of at least one third redundant memory cell is a programmed state. The programming operation method further includes:

[0025] After programming multiple first memory cells is completed, a third programming operation is triggered, which includes:

[0026] The pre-charging for the third programming operation includes providing a seventh preset voltage to the first input terminal and providing an eighth preset voltage to the gate layer of the third redundant memory cell in the programmed state to turn on the third redundant memory cell, and providing a ninth preset voltage to the remaining memory cells located between the second input terminal and the third redundant memory cell to turn off the remaining memory cells, so as to pre-charge the channel in the second memory string.

[0027] A third programming operation is performed, in which multiple second memory cells to be programmed are programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0028] The ninth preset voltage is 0V.

[0029] The first input terminal is electrically connected to the source side of the first memory string, and the second input terminal is electrically connected to the drain side of the first memory string.

[0030] The memory is a three-dimensional memory, with the first input terminal and the second input terminal located at the two ends of the first storage string in the vertical direction, and multiple first storage units stacked in the vertical direction.

[0031] To address the aforementioned problems, the present invention also provides a programming operation device for a memory, the memory including a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string, the first memory string including a plurality of first memory cells connected in series, each first memory cell including a gate layer, a memory layer storing data states, and a channel, the data states including a programmed state and an unprogrammed state, the programming operation device including:

[0032] A first pre-charge module is used for pre-charging during a first programming operation. Specifically, the pre-charging includes: providing a first preset voltage to a second input terminal and providing a second preset voltage to the gate layer of a first memory cell in a programmed state, thereby turning on the first memory cell in the programmed state to pre-charge the channels in the first memory string; and...

[0033] The first programming module is used to perform a first programming operation, which programs multiple first storage cells to be programmed from the first storage cell near the second input terminal to the direction away from the second input terminal.

[0034] The duration for which a first preset voltage is provided to the second input terminal is longer than the duration for which a second preset voltage is provided to the gate layer of the first memory cell in the programmed state.

[0035] Specifically, the first programming module is used for:

[0036] Program the first memory unit currently being programmed;

[0037] When programming of the first memory cell to be programmed is completed, the next first memory cell is updated to the first memory cell to be programmed, and the first pre-charge module is triggered to perform pre-charge of the first programming operation again. The next first memory cell is the first memory cell that is adjacent to the first memory cell to be programmed and located on the side of the first memory cell to be programmed away from the second input terminal.

[0038] Specifically, the first programming module is used for:

[0039] A programming voltage is provided to the gate layer of the currently programmed first memory cell, and a channel turn-on voltage is provided to the remaining first memory cells.

[0040] The memory further includes a first redundant memory string located between the first memory string and the second input terminal. The first redundant memory string includes at least one first redundant memory cell connected in series. Each first redundant memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data state of at least one first redundant memory cell is a programmed state. The pre-charge for the first programming operation also includes:

[0041] A third preset voltage is provided to the gate layer of the first redundant memory cell in the programmed state to turn on the first redundant memory cell in the programmed state.

[0042] The memory further includes a second memory string located between the first input terminal and the first memory string, and a second redundant memory string located between the first memory string and the second memory string. The second memory string includes a plurality of second memory cells connected in series, and the second redundant memory string includes at least one second redundant memory cell connected in series. Each second memory cell and the second redundant memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data state of at least one second redundant memory cell is a programmed state. The pre-charge for the first programming operation further includes:

[0043] A fourth preset voltage is provided to the gate layer of the second redundant memory cell that is in the programmed state, so that the second redundant memory cell in the programmed state is not turned on.

[0044] The programming operation device also includes:

[0045] A first triggering module is used to trigger a second programming operation after programming of multiple first memory units is completed. The second programming operation includes:

[0046] The pre-charging for the second programming operation includes providing a fifth preset voltage to the second input terminal and a sixth preset voltage to the gate layers of the programmed second memory cell, first memory cell, and second redundant memory cell, thereby turning on the programmed second memory cell, first memory cell, and second redundant memory cell to pre-charge the channels in the first and second memory strings; and,

[0047] A second programming operation is performed, in which multiple second memory cells to be programmed are programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0048] The memory further includes a third redundant memory string located between the second memory string and the first input terminal. The third redundant memory string includes at least one third redundant memory cell connected in series. Each third redundant memory cell includes a gate layer, a memory layer storing data states, and a channel. The data state of at least one third redundant memory cell is a programmed state. The programming operation device further includes:

[0049] The second triggering module is used to trigger a third programming operation after programming of multiple first memory units is completed. The third programming operation includes:

[0050] The pre-charging for the third programming operation includes providing a seventh preset voltage to the first input terminal and providing an eighth preset voltage to the gate layer of the third redundant memory cell in the programmed state to turn on the third redundant memory cell, and providing a ninth preset voltage to the remaining memory cells located between the second input terminal and the third redundant memory cell to turn off the remaining memory cells, so as to pre-charge the channel in the second memory string.

[0051] A third programming operation is performed, in which multiple second memory cells to be programmed are programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0052] The ninth preset voltage is 0V.

[0053] The first input terminal is electrically connected to the source side of the first memory string, and the second input terminal is electrically connected to the drain side of the first memory string.

[0054] The memory is a three-dimensional memory, with the first input terminal and the second input terminal located at the two ends of the first storage string in the vertical direction, and multiple first storage units stacked in the vertical direction.

[0055] The beneficial effects of this invention are as follows: Unlike the prior art, the memory programming operation method provided by this invention is applied to a memory, which includes a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string. The first memory string includes a plurality of first memory cells connected in series. Each first memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data states include a programmed state and an unprogrammed state. This programming operation method performs a pre-charge for the first programming operation, including providing a first preset voltage to the second input terminal and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, so as to turn on the first memory cell in the programmed state to pre-charge the channel in the first memory string. Then, the first programming operation is performed. The first programming operation programs the plurality of first memory cells to be programmed from the first memory cell near the second input terminal to the direction away from the second input terminal. Therefore, when performing the first programming operation on the first memory string, the problem of not being able to effectively increase the channel potential due to the channel being turned off by the programmed first memory cell can be avoided during the pre-charge stage of the first programming operation, thus reducing programming interference. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a flowchart illustrating the memory programming method provided in an embodiment of the present invention;

[0058] Figure 2 This is a simplified structural diagram of the three-dimensional memory provided in an embodiment of the present invention;

[0059] Figure 3 This is a schematic diagram of the specific structure of the three-dimensional memory provided in an embodiment of the present invention;

[0060] Figure 4 yes Figure 3 A schematic diagram of the enlarged structure of the first memory cell;

[0061] Figure 5 This is a timing diagram of the first programming operation provided in an embodiment of the present invention;

[0062] Figure 6 This is another simplified structural diagram of the three-dimensional memory provided in an embodiment of the present invention;

[0063] Figure 7 This is another specific structural schematic diagram of the three-dimensional memory provided in an embodiment of the present invention;

[0064] Figure 8 This is another timing diagram of the first programming operation provided in the embodiments of the present invention;

[0065] Figure 9 This is a timing diagram of the second programming operation provided in an embodiment of the present invention;

[0066] Figure 10 This is a timing diagram of the third programming operation provided in an embodiment of the present invention;

[0067] Figure 11 This is a schematic diagram of the structure of the memory programming operation device provided in an embodiment of the present invention. Detailed Implementation

[0068] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] Furthermore, the directional terms used in this invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], and [side], are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. In the various figures, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the figures are not drawn to scale. Additionally, some well-known parts may not be shown in the figures.

[0070] This invention can be presented in various forms, some of which will be described below.

[0071] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for programming a memory according to an embodiment of the present invention. The specific process of this method is as follows:

[0072] Step S11: Pre-charging for the first programming operation includes providing a first preset voltage to the second input terminal and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, so as to turn on the first memory cell in the programmed state to pre-charge the channel in the first memory string.

[0073] In this embodiment, the memory includes a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string. The first memory string includes a plurality of first memory cells connected in series. Each first memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data states include a programmed state and an unprogrammed state. The memory can be specifically a two-dimensional memory or a three-dimensional memory.

[0074] For ease of description and understanding, the embodiments of the present invention will be illustrated using a three-dimensional memory as an example. Figure 2 As shown, the three-dimensional memory may include a first storage string 12, and a first input terminal 11 and a second input terminal 14 located at both ends of the first storage string 12 along the vertical direction Z. The first storage string 12 includes a plurality of first storage cells 121 stacked along the vertical direction Z. The first storage cells 121 in the first storage string 12 are connected in series, and one end of the first storage string 12 along the vertical direction Z is connected in series with the first input terminal 11, and the other end is connected in series with the second input terminal 14.

[0075] Specifically, such as Figure 3 and Figure 4As shown, the first memory string 12 can be arranged as a vertical string in a stacked structure 15, wherein the stacked structure 15 may include multiple alternating layers of conductive layers 151 and dielectric layers 152 stacked in the vertical direction Z. Each of the first memory cells 121 may include a gate layer A, a memory layer B, and a channel C, and the channels C of each of the first memory cells 121 are connected in the vertical direction Z to form a channel layer 16 that runs through the stacked structure 15. Similarly, the memory layers B of each of the first memory cells 121 may also be connected in the vertical direction Z to form a charge storage layer 17 that runs through the stacked structure 15 and surrounds the channel layer 16. Furthermore, each conductive layer 151 in the stacked structure 15 can provide the gate layer A of each of the first memory cells 121 and a word line WL connected to the gate layer A of each of the first memory cells 121. The aforementioned three-dimensional memory may further include a first oxide layer 18 (e.g., a silicon oxide layer) located between the channel layer 16 and the charge storage layer 17, and a second oxide layer 19 (e.g., a silicon oxide layer) located between the charge storage layer 17 and the stacked structure 15. The first oxide layer 18 and the second oxide layer 19 may respectively provide a tunneling layer D and a barrier layer E for each of the first memory cells 121. That is, each first memory cell 121 has one tunneling layer D and one barrier layer E, wherein the tunneling layer D is located between the memory layer B and the channel C, and the barrier layer E is located between the gate layer A and the memory layer B. The channel layer 16 may be a semiconductor layer (e.g., a polysilicon layer), the charge storage layer 17 may be a silicon nitride layer, the conductive layer 151 may be made of tungsten, and the dielectric layer 152 may be made of silicon oxide.

[0076] In this embodiment, the storage layer B of the first storage unit 121 is used to store data states, which may include a programmed state and an unprogrammed state. Specifically, the data state stored in the storage layer B of the selected first storage unit 121 can be programmed by performing a programming operation on the selected first storage unit 121, and the data state stored in the storage layer B of the selected first storage unit 121 can be restored to the unprogrammed state by performing an erase operation on the selected first storage unit 121.

[0077] In one specific embodiment, the first input terminal 11 can be electrically connected to the source side of the first memory string 12, for electrically connecting the source side of the first memory string 12 to the common source of the three-dimensional memory (not shown in the figure), so that the common source driver can provide a drive signal to the first input terminal 11 via the common source. The second input terminal 14 can be electrically connected to the drain side of the first memory string 12, for electrically connecting the drain side of the first memory string 12 to the bit line BL, so that the bit line driver can provide a drive signal to the second input terminal 14 via the bit line BL. Accordingly, before the above step S11, it may also include: performing an erase operation, including providing an erase voltage Ve to the first input terminal 11 and providing a ground voltage (i.e., 0V) to the gate layer A of each first memory cell 121 to erase the data of each first memory cell 121, so that the data state of each first memory cell 121 is unprogrammed.

[0078] It is understood that the erase voltage Ve should be large enough to create a sufficiently large negative voltage difference between the gate layer A and the source of each first memory cell 121. This allows electrons in the storage layer B of each first memory cell 121 to leave the storage layer B through tunneling and return to the corresponding channel C. As a result, the data stored in the storage layer B of each first memory cell 121 is either erased or unprogrammed, which means that the data state of each first memory cell 121 is switched from programmed to unprogrammed.

[0079] Among them, such as Figure 5 As shown, when performing a first programming operation on the first storage string 12, the first programming operation can be divided into at least two stages: a pre-charging stage and a programming stage. In this embodiment, by providing a first preset voltage V1 to the second input terminal 14 during the pre-charging stage, the purpose is to make the potential of the second input terminal 14 higher than the potential of the first input terminal 11, thereby applying an electric field force pointing towards the second input terminal 14 to the free electrons in the channel layer 16, and causing the free electrons to leave the channel layer 16 under the action of the electric field force and be absorbed by the second input terminal 14.

[0080] In this embodiment, when performing a first programming operation on the first storage string 12, the first programming operation programs multiple first storage units 121 to be programmed from the first storage unit 121 near the second input terminal 14 toward the direction away from the second input terminal 14. That is, the programmed first storage unit 121 or the first storage unit 121 in a programmed state is located on the side of the currently programmed first storage unit 121 away from the first input terminal 11, while the unprogrammed first storage unit 121 or the first storage unit 121 in an unprogrammed state is located on the side of the currently programmed first storage unit 121 near the first input terminal 11.

[0081] Furthermore, given that when the data state of the first storage cell 121 changes from an unprogrammed state to a programmed state, the threshold voltage of the first storage cell 121 increases, which in turn leads to a significant decrease in the conductivity of the channel C of the first storage cell 121, a significant voltage drop will occur between the two ends of the channel C of the programmed first storage cell 121 when the first preset voltage V1 on the second input terminal 14 is transmitted to the first input terminal 11 through the channel C of the programmed first storage cell 121. As a result, the potential of the channel layer 16 cannot be effectively increased, nor can the density of free electrons in the channel layer 16 be effectively reduced. To address this issue, in this embodiment, during the pre-charging phase of the first programming operation on the first storage string 12, in addition to providing a first preset voltage V1 to the second input terminal 14, a second preset voltage V2 is also provided to the programmed first storage cell 121 in the first storage string 12. This turns on the programmed first storage cell 121, reducing the voltage drop between the two ends of the longitudinal direction of the channel C of the programmed first storage cell 121 when the first preset voltage V1 on the second input terminal 14 is transmitted to the first input terminal 11 via the channel C of the programmed first storage cell 121. This increases the potential of the channel layer 16, making the electrons in the channel layer 16 experience a stronger electric field force, making it easier for them to migrate and diffuse to the second input terminal 14. This is more conducive to reducing the electron density in the channel layer 16 and reducing programming interference.

[0082] Wherein, the aforementioned second preset voltage V2 is greater than the threshold voltage of the corresponding programmed first memory cell 121. For example, the threshold voltage of the programmed first memory cell 121 can range from -2 to 5V, and correspondingly, the range of the aforementioned second preset voltage V2 can be from 5 to 7V. Specifically, as... Figure 5 As shown, during the pre-charging phase of the first programming operation, a ground voltage of 0V can be provided to the first input terminal 11. Correspondingly, the first preset voltage V1 is a positive voltage, and its value range can be 0 to 4V, for example, 2.2V.

[0083] Furthermore, in specific implementation, during the pre-charging phase of the first programming operation, the duration for which the first preset voltage V1 is provided to the second input terminal 14 can be greater than the duration for which the second preset voltage V2 is provided to the gate layer A of the programmed first memory cell 121. This ensures that the voltage applied to the gate layer A of the programmed first memory cell 121 drops to 0V. That is, when the channel C of the programmed first memory cell 121 is not conductive or has very poor conductivity, electrons located at the channel C of the programmed first memory cell 121 can still continue to migrate and diffuse toward the second input terminal 14 under the electric field force of the first preset voltage V1, thereby further reducing the electron density in the channel layer 16.

[0084] In some embodiments, such as Figure 6 and Figure 7 As shown, the aforementioned stacking structure 15 may include a first stacking structure 15A and a first redundant stacking structure 15B stacked in the vertical direction Z. Correspondingly, the first storage string 12 may be disposed in the first stacking structure 15A. The three-dimensional memory may also include a first redundant storage string 20 located between the first storage string 12 and the second input terminal 14. This first redundant storage string 20 may be located in the first redundant stacking structure 15B and may include at least one first redundant storage cell 201 stacked in the vertical direction Z. Each first redundant storage cell 201 has a similar structure to the first storage cell 121, such as... Figure 4 As shown, it may also include a gate layer A, a storage layer B for storing data states, and a channel C. The first redundant storage cell 201 is a non-data memory cell that does not meet the conditions for storing user data, while the first storage cell 121 is a data memory cell that meets the conditions for storing user data. Furthermore, before the pre-charge of the first programming operation, the data state of at least one first redundant storage cell 201 in the first redundant storage string 20 has been set to a programmed state. In one embodiment, before the pre-charge of the first programming operation, the data state of all first redundant storage cells 201 in the first redundant storage string 20 may have been set to a programmed state.

[0085] Specifically, in the pre-charging phase of the first programming operation described above, such as Figure 8As shown, a third preset voltage V3 also needs to be provided to the gate layer A of the programmed first redundant memory cell 201 to turn on the programmed first redundant memory cell 201, thereby ensuring that electrons in the channel C of the first memory string 12 below the first redundant memory string 20 can enter the upper second input terminal 14 through the channel C of the first redundant memory string 20. The third preset voltage V3 is not less than the threshold voltage of the corresponding programmed first redundant memory cell 201. In one embodiment, the third preset voltage V3 can be 2.2V.

[0086] In other embodiments, such as Figure 6 and Figure 7 As shown, the aforementioned stacking structure 15 may include a second stacking structure 15C located on the side of the first stacking structure 15A opposite to the second input terminal 14, and a second redundant stacking structure 15D located between the first stacking structure 15A and the second stacking structure 15C. Correspondingly, the aforementioned three-dimensional memory may also include a second storage string 13 located between the first input terminal 11 and the first storage string 12, and a second redundant storage string 21 located between the first storage string 12 and the second storage string 13. The second storage string 13 may be located in the second stacking structure 15C, and the second redundant storage string 21 may be located in the second redundant stacking structure 15D. The second storage string 13 includes a plurality of second storage cells 131 stacked in the vertical direction Z, and the second redundant storage string 21 includes at least one second redundant storage cell 211 stacked in the vertical direction Z. Each second storage cell 131 and the second redundant storage cell 211 has a similar structure to the first storage cell 121, such as... Figure 4 As shown, it may also include a gate layer A, a storage layer B for storing data states, and a channel C. The second redundant storage cell 211 is a non-data memory cell that does not meet the conditions for storing user data, while the second storage cell 131 is a data memory cell that meets the conditions for storing user data. Furthermore, before the pre-charge of the first programming operation, the data state of at least one second redundant storage cell 211 in the second redundant storage string 21 has been set to a programmed state. In one embodiment, before the pre-charge of the first programming operation, the data state of all second redundant storage cells 211 in the second redundant storage string 21 may have been set to a programmed state.

[0087] Specifically, in the pre-charging phase of the first programming operation described above, such as Figure 8As shown, a fourth preset voltage V4 can also be provided to the gate layer A of the programmed second redundant memory cell 211 to prevent the programmed second redundant memory cell 211 from conducting, thereby ensuring that electrons in the channel C of the second memory string 13 below the second redundant memory string 21 will not enter the channel C of the first memory string 12 above via the channel C of the second redundant memory string 21. The fourth preset voltage V4 is less than the threshold voltage of the corresponding programmed second redundant memory cell 211. In one embodiment, the fourth preset voltage V4 can be the ground voltage (0V).

[0088] In the above embodiments, the data state of all second storage cells 131 in the second storage string 13 can be either programmed or unprogrammed. In one embodiment, the data state of all second storage cells 131 in the second storage string 13 can be programmed. Accordingly, before step S11, a partial erase operation may be performed, wherein for the first storage string 12 and the second storage string 13 that have been written with data, only the data of the first storage string 12 is erased, and the data of the second storage string 13 is not erased, so that before the pre-charge of the first programming operation, the data state of all first storage cells 121 in the first storage string 12 is adjusted to an unprogrammed state, and the data state of all second storage cells 131 in the second storage string 13 can be programmed. In another embodiment, the data state of all second storage cells 131 in the second storage string 13 can be unprogrammed. Accordingly, before step S11, the process may further include: performing an erasure operation, which erases not only the data in the first storage string 12 and the second storage string 13 that have been written with data, but also the data in the second storage string 13, so that before the pre-charging of the first programming operation, the data state of all first storage cells 121 in the first storage string 12 is adjusted to an unprogrammed state, and at the same time, the data state of all second storage cells 131 in the second storage string 13 is also adjusted to an unprogrammed state.

[0089] Furthermore, in specific implementation, such as Figure 8 As shown, during the pre-charge phase of the first programming operation, a ground voltage of 0V can also be provided to the gate layer A of the second memory cell 131.

[0090] Step S12: Perform a first programming operation, in which the first programming operation programs multiple first memory cells to be programmed from the first memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0091] Specifically, such as Figure 8As shown, after the pre-charge phase of the first programming operation ends, the programming phase of the first programming operation will then begin. During the programming phase of the first programming operation, a programming voltage Vpgm (e.g., 22V) can be provided to the gate layer A of the currently programmed first memory cell 121 to enable data writing; and a channel turn-on voltage Vpass (e.g., 7.2V) can be provided to the remaining first memory cell 121, second memory cell 131, first redundant memory cell 201 and second redundant memory cell 211 to ensure the conduction of the aforementioned channel layer 16.

[0092] It is understood that the programming voltage Vpgm should be large enough to ensure a sufficiently high positive voltage difference between the gate layer A and the source of each currently programmed first memory cell 121. This allows electrons in the channel C of the currently programmed first memory cell 121 to tunnel into the corresponding memory layer B, thereby enabling the data stored in the memory layer B of the currently programmed first memory cell 121 to be in a programmed state. In other words, the data state of the currently programmed first memory cell 121 is switched from an unprogrammed state to a programmed state.

[0093] Furthermore, in specific implementation, the aforementioned first programming operation can sequentially program the unprogrammed first storage cells 121 in the first storage string 12 from the first storage cell 121 closest to the second input terminal 14 away from the second input terminal 14. Moreover, after programming the currently programmed first storage cell 121, before programming the next first storage cell 121 to be programmed, step S11 is re-executed to recharge the channel C in the first storage string 12, thereby removing electrons generated in the channel C due to the previous programming steps. For example, step S12 above may specifically include: programming the currently programmed first storage unit 121; when the programming of the currently programmed first storage unit 121 is completed, updating the next first storage unit to the currently programmed first storage unit 121, and returning to execute step S11 above, wherein the next first storage unit is the first storage unit 121 adjacent to the currently programmed first storage unit 121 and located on the side of the currently programmed first storage unit 121 away from the second input terminal 14, thereby forming a loop, and each time the loop is completed, the programming of one first storage unit 121 to be programmed can be completed, until all the first storage units 121 to be programmed are programmed and the loop ends.

[0094] In one specific embodiment, when the data state of all second storage cells 131 in the second storage string 13 is unprogrammed, after step S12, the programming operation method may further include:

[0095] Step S13: After programming the multiple first memory cells is completed, a second programming operation is triggered.

[0096] The second programming operation mentioned above includes:

[0097] Sub-step S131: Pre-charging for the second programming operation includes providing a fifth preset voltage to the second input terminal and providing a sixth preset voltage to the gate layers of the second memory cell, the first memory cell, and the second redundant memory cell in the programmed state, so as to turn on the second memory cell, the first memory cell, and the second redundant memory cell in the programmed state to pre-charge the channels in the first memory string and the second memory string.

[0098] Specifically, after programming the plurality of first storage units 121, the data state of all first storage units 121 in the first storage string 12 can be in a programmed state, and the programming operation device will then perform a second programming operation to program the second storage units 131 in the second storage string 13. In this embodiment, when performing the second programming operation on the second storage string 13, the second programming operation will program the plurality of second storage units 131 to be programmed from the second storage unit 131 near the second input terminal 14 in a direction away from the second input terminal 14. That is, the programmed second storage unit 131 or the second storage unit 131 in a programmed state is located on the side of the currently programmed second storage unit 131 away from the first input terminal 11, while the unprogrammed second storage unit 131 or the second storage unit 131 in an unprogrammed state is located on the side of the currently programmed second storage unit 131 near the first input terminal 11.

[0099] Among them, such as Figure 9 As shown, when performing a second programming operation on the second memory string 13, the second programming operation can be divided into at least two stages: a pre-charging stage and a programming stage. In this embodiment, by providing a fifth preset voltage V5 to the second input terminal 14 during the pre-charging stage of the second programming operation, the purpose is to make the potential of the second input terminal 14 higher than the potential of the first input terminal 11, thereby applying an electric field force pointing towards the second input terminal 14 to the free electrons in the channel layer 16, and causing the free electrons to leave the channel layer 16 under the action of the electric field force and be absorbed by the second input terminal 14.

[0100] Furthermore, given that the programmed first storage cell 121, the programmed first redundant storage cell 201, and the programmed second redundant storage cell 211 are located in the vertical Z direction between the second input terminal 14 and the second storage string 13, in order to enable the fifth preset voltage V5 on the second input terminal 14 to be transmitted to the first input terminal 11 via the channel C of the programmed first storage cell 121, the programmed first redundant storage cell 201, the programmed second redundant storage cell 211, and the programmed second storage cell 131, and to effectively increase the potential of the channel layer 16, in this embodiment, during the pre-charging phase of the second programming operation, in addition to providing the fifth preset voltage V5 to the second input terminal 14, a sixth preset voltage V6 is also provided to the programmed second storage cell 131, the first storage cell 121, the first redundant storage cell 201, and the second redundant storage cell 211 to ensure the conduction of the storage cell located between the currently programmed second storage cell 131 and the second input terminal 14.

[0101] The sixth preset voltage V6 is greater than the threshold voltage of the corresponding programmed second storage unit 131, first storage unit 121, first redundant storage unit 201, and second redundant storage unit 211. For example, the threshold voltage of the programmed first storage unit 121 can range from -2 to 5V, and correspondingly, the sixth preset voltage V6 can range from 5 to 7V. The fifth preset voltage V5 can be the same as the first preset voltage V1, for example, it can be a positive voltage, and its range can be from 0 to 4V, for example, 2.2V.

[0102] Sub-step S132: Perform a second programming operation, in which the second programming operation programs multiple second memory cells to be programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0103] Specifically, such as Figure 9 As shown, after the pre-charge phase of the second programming operation ends, the programming phase of the second programming operation will then begin. During the programming phase of the second programming operation, a programming voltage Vpgm (e.g., 22V) can be provided to the gate layer A of the currently programmed second memory cell 131 to enable data writing; and a channel turn-on voltage Vpass (e.g., 7.2V) is provided to the remaining second memory cell 131, first memory cell 121, first redundant memory cell 201 and second redundant memory cell 211 to ensure the conduction of the channel layer 16.

[0104] Furthermore, in specific implementation, the aforementioned second programming operation can sequentially program the unprogrammed second storage cells 131 in the second storage string 13 from the second storage cell 131 closest to the second input terminal 14 away from the second input terminal 14. Moreover, after programming the currently programmed second storage cell 131, before programming the next second storage cell 131 to be programmed, the aforementioned sub-step S131 is re-executed to recharge the channel C in the first storage string 12 and the second storage string 13, thereby removing electrons generated in the channel C due to the previous programming steps.

[0105] In another specific embodiment, such as Figure 6 and Figure 7 As shown, the aforementioned stacked structure 15 may include a fifth stacked structure 15E located between the first input terminal 11 and the second stacked structure 15C. Correspondingly, the aforementioned three-dimensional memory may also include a third redundant memory string 22 located between the second memory string 13 and the first input terminal 11. This third redundant memory string includes at least one third redundant memory cell 221 stacked in the vertical Z direction, and each third redundant memory cell 221 has a similar structure to the aforementioned first memory cell 121, such as... Figure 4 As shown, it may also include a gate layer A, a storage layer B for storing data states, and a channel C. The aforementioned third redundant storage cell 221 is a non-data memory cell that does not meet the conditions for storing user data, and before the pre-charge of the aforementioned first programming operation, the data state of at least one third redundant storage cell 221 in the aforementioned third redundant storage string 22 has been set to a programmed state. In one embodiment, before the pre-charge of the aforementioned first programming operation, the data state of all third redundant storage cells 221 in the aforementioned third redundant storage string 22 may have been set to a programmed state. Further, the aforementioned step S13 can be replaced by the following steps:

[0106] Step S14: After programming the multiple first memory cells is completed, a third programming operation is triggered.

[0107] The third programming operation mentioned above includes:

[0108] Sub-step S141: Pre-charging for the third programming operation includes providing a seventh preset voltage to the first input terminal and providing an eighth preset voltage to the gate layer of the third redundant memory cell in the programmed state to turn on the third redundant memory cell, and providing a ninth preset voltage to the remaining memory cells located between the second input terminal and the third redundant memory cell to turn off the remaining memory cells, so as to pre-charge the channel in the second memory string.

[0109] Specifically, after programming the plurality of first storage units 121, the data state of all first storage units 121 in the first storage string 12 can be in a programmed state, and the programming operation device will then perform a third programming operation to program the second storage units 131 in the second storage string 13. In this embodiment, when performing the third programming operation on the second storage string 13, the third programming operation will program the plurality of second storage units 131 to be programmed from the second storage unit 131 near the second input terminal 14 in a direction away from the second input terminal 14. That is, the programmed second storage unit 131 or the second storage unit 131 in a programmed state is located on the side of the currently programmed second storage unit 131 away from the first input terminal 11, while the unprogrammed second storage unit 131 or the second storage unit 131 in an unprogrammed state is located on the side of the currently programmed second storage unit 131 near the first input terminal 11.

[0110] Among them, such as Figure 10 As shown, when the third programming operation is performed on the second memory string 13, the third programming operation can be divided into at least two stages: a pre-charging stage and a programming stage. In this embodiment, by providing a seventh preset voltage V7 to the first input terminal 11 during the pre-charging stage of the third programming operation, the purpose is to make the potential of the first input terminal 11 higher than the potential of the second input terminal 14, thereby applying an electric field force pointing towards the first input terminal 11 to the free electrons in the channel layer 16, and causing the free electrons to leave the channel layer 16 under the action of the electric field force and be absorbed by the first input terminal 11.

[0111] Furthermore, given that the programmed third redundant memory cell 221 is located in the vertical Z direction between the first input terminal 11 and the second memory string 13, in order to enable the seventh preset voltage V7 on the first input terminal 11 to be transmitted to the second input terminal 14 via the channel C of the programmed third redundant memory cell 221 and to effectively increase the potential of the channel layer 16, in this embodiment, during the pre-charge phase of the third programming operation, in addition to providing the seventh preset voltage V7 to the first input terminal 11, an eighth preset voltage V8 is also provided to the programmed third redundant memory cell 221 to turn on the programmed third redundant memory cell 221. Simultaneously, during the pre-charge phase of the third programming operation, the remaining memory cells (including the first memory cell, the first redundant memory cell, and the second redundant memory cell) located between the second input terminal and the third redundant memory cell do not need to be turned on. Specifically, the ninth preset voltage can be 0V to prevent the remaining memory cells from turning on.

[0112] Wherein, the aforementioned eighth preset voltage V8 is greater than the threshold voltage of the corresponding programmed third redundant memory cell 221. Specifically, as shown... Figure 10 As shown, during the pre-charging phase of the third programming operation, a ground voltage of 0V can be provided to the second input terminal 14. Correspondingly, the seventh preset voltage V7 is a positive voltage, and its value range can be 0 to 4V, for example, 2.2V.

[0113] Sub-step S142: Perform a third programming operation, in which the third programming operation programs multiple second memory cells to be programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0114] The specific implementation of sub-step S142 can be found in the specific implementation of sub-step S132, so it will not be repeated here.

[0115] Unlike existing technologies, the programming method for a three-dimensional memory provided in this embodiment is applied to a memory, which includes a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string. The first memory string includes multiple first memory cells connected in series. Each first memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data states include a programmed state and an unprogrammed state. This programming method performs a pre-charge for the first programming operation, including providing a first preset voltage to the second input terminal and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, so as to turn on the first memory cell in the programmed state to pre-charge the channel in the first memory string. Then, the first programming operation is performed. The first programming operation programs multiple first memory cells to be programmed from the first memory cell near the second input terminal to the direction away from the second input terminal. Therefore, when performing the first programming operation on the first memory string, the problem of not being able to effectively increase the channel potential due to the channel being turned off by the programmed first memory cell can be avoided during the pre-charge stage of the first programming operation, thereby reducing programming interference.

[0116] Please see Figure 11 , Figure 11 The present invention provides a specific description of a memory programming operation device 90, which includes a first pre-charge module 901 and a first programming module 902, wherein:

[0117] (1) First pre-charging module 901

[0118] The first pre-charge module 901 is used for pre-charging the first programming operation. Specifically, the pre-charging for the first programming operation includes: providing a first preset voltage to the second input terminal and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, so as to turn on the first memory cell in the programmed state and pre-charge the channel in the first memory string.

[0119] In this embodiment, the memory includes a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string. The first memory string includes a plurality of first memory cells connected in series. Each first memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data states include a programmed state and an unprogrammed state. The memory can be specifically a two-dimensional memory or a three-dimensional memory.

[0120] For ease of description and understanding, the embodiments of the present invention are described using the above-mentioned memory as a three-dimensional memory as an example. The three-dimensional memory may include a first memory string and a first input terminal and a second input terminal located at both ends of the first memory string in the vertical direction. The first memory string includes a plurality of first memory cells stacked in the vertical direction. Each first memory cell includes a gate layer, a memory layer for storing data states, and a channel. The data states include a programmed state and an unprogrammed state.

[0121] The duration for which a first preset voltage is provided to the second input terminal is longer than the duration for which a second preset voltage is provided to the gate layer of the first memory cell in the programmed state.

[0122] In one specific embodiment, the three-dimensional memory may further include a first redundant memory string located between the first memory string and the second input terminal. The first redundant memory string includes at least one first redundant memory cell stacked vertically. Each first redundant memory cell includes a gate layer, a memory layer storing data states, and a channel. The data state of at least one first redundant memory cell is a programmed state. The pre-charging for performing the first programming operation may further include:

[0123] A third preset voltage is provided to the gate layer of the first redundant memory cell in the programmed state to turn on the first redundant memory cell in the programmed state.

[0124] In some embodiments, the three-dimensional memory may further include a second memory string located between the first input terminal and the first memory string, and a second redundant memory string located between the first memory string and the second memory string. The second memory string includes a plurality of second memory cells stacked vertically, and the second redundant memory string includes at least one second redundant memory cell stacked vertically. Each second memory cell and the second redundant memory cell includes a gate layer, a memory layer storing data states, and a channel. The data state of at least one second redundant memory cell is a programmed state. The pre-charging for performing the first programming operation may further include:

[0125] A fourth preset voltage is provided to the gate layer of the second redundant memory cell that is in the programmed state, so that the second redundant memory cell in the programmed state is not turned on.

[0126] (2) First programming module 902

[0127] The first programming module 902 is used to perform a first programming operation, which programs multiple first storage cells to be programmed from the first storage cell near the second input terminal to the direction away from the second input terminal.

[0128] Specifically, the first programming module 902 is used for:

[0129] A programming voltage is provided to the gate layer of the currently programmed first memory cell, and a channel turn-on voltage is provided to the remaining first memory cells.

[0130] In specific implementation, the first programming module 902 mentioned above can be used for:

[0131] Program the first memory unit currently being programmed;

[0132] When programming of the first memory cell to be programmed is completed, the next first memory cell is updated to the first memory cell to be programmed, and the first pre-charge module is triggered to perform pre-charge of the first programming operation again. The next first memory cell is the first memory cell that is adjacent to the first memory cell to be programmed and located on the side of the first memory cell to be programmed away from the second input terminal.

[0133] In one specific embodiment, the programming operation device 90 may further include:

[0134] (3) First trigger module

[0135] The first triggering module is used to trigger the second programming operation after the programming of multiple first storage units is completed.

[0136] The second programming operation mentioned above may include:

[0137] The pre-charging for the second programming operation includes providing a fifth preset voltage to the second input terminal and a sixth preset voltage to the gate layers of the programmed second memory cell, first memory cell, and second redundant memory cell, thereby turning on the programmed second memory cell, first memory cell, and second redundant memory cell to pre-charge the channels in the first and second memory strings; and,

[0138] A second programming operation is performed, in which multiple second memory cells to be programmed are programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0139] In another specific embodiment, the above-mentioned three-dimensional memory may further include a third redundant memory string located between the second memory string and the first input terminal. The third redundant memory string includes at least one third redundant memory cell stacked vertically. Each third redundant memory cell includes a gate layer, a memory layer storing data states, and a channel. The data state of at least one third redundant memory cell is a programmed state. The above-mentioned first trigger module can be replaced with:

[0140] (4) Second trigger module

[0141] The second trigger module is used to trigger a third programming operation after programming of multiple first storage units is completed.

[0142] The third programming operation mentioned above may include:

[0143] The pre-charging for the third programming operation includes providing a seventh preset voltage to the first input terminal and providing an eighth preset voltage to the gate layer of the third redundant memory cell in the programmed state to turn on the third redundant memory cell, and providing a ninth preset voltage to the remaining memory cells located between the second input terminal and the third redundant memory cell to turn off the remaining memory cells, so as to pre-charge the channel in the second memory string.

[0144] A third programming operation is performed, in which multiple second memory cells to be programmed are programmed from the second memory cell closest to the second input terminal toward the direction away from the second input terminal.

[0145] Among them, the aforementioned ninth preset voltage can be the ground voltage, that is, 0V.

[0146] In the above embodiments, the first input terminal can be electrically connected to the source side of the first memory string, and the second input terminal can be electrically connected to the drain side of the first memory string.

[0147] For specific implementation details of each of the above modules, please refer to the preceding method implementation examples, which will not be repeated here.

[0148] Unlike existing technologies, the memory programming device provided in this embodiment can avoid the problem of not being able to effectively increase the channel potential due to the channel turn-off of the programmed first memory cell during the pre-charging stage of the first programming operation when performing the first programming operation on the first memory string, thereby reducing programming interference.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for programming a memory, characterized in that, The memory includes a first memory string, a second redundant memory string, and a second memory string connected in series. The first memory string is connected to a bit line; the second memory string is connected to a source line. The first memory string includes a plurality of first memory cells connected in series and a plurality of first word lines coupled to the plurality of first memory cells. The second redundant memory string includes at least one second redundant memory cell connected in series and a second redundant word line coupled to the at least one second redundant memory cell. The programming operation method includes: A pre-charge for performing a first programming operation on the plurality of first memory cells included in the first memory string, wherein the pre-charge includes: providing a first preset voltage to the bit line; providing a second preset voltage to a first word line coupled to a first memory cell in the programmed state, so that the first memory cell in the programmed state is turned on; and providing a fourth preset voltage to a second redundant word line coupled to a second redundant memory cell in the programmed state, so that the second redundant memory cell in the programmed state is not turned on. The first programming operation is performed, wherein the first programming operation is performed sequentially from the first storage cell adjacent to the bit line to the first storage cell adjacent to the second redundant storage string; The memory further includes a first redundant memory string located between the first memory string and the bit line. The first redundant memory string includes at least one first redundant memory cell connected in series and a first redundant word line coupled to the at least one first redundant memory cell. The pre-charging for performing the first programming operation further includes providing a third preset voltage to the first redundant word line coupled to the first redundant memory cell in the programmed state, so as to turn on the first redundant memory cell in the programmed state.

2. The memory programming operation method according to claim 1, characterized in that, The duration of the first preset voltage is longer than the duration of the second preset voltage.

3. The method for programming a memory according to claim 1, characterized in that, Performing the first programming operation includes: Program the currently selected first memory cell; When programming of the currently selected first storage cell is completed, the first programming operation is pre-charged and the first programming operation is performed on the next selected first storage cell, wherein the next selected first storage cell is located between the currently selected first storage cell and the second redundant storage string and is adjacent to the currently selected first storage cell.

4. The memory programming operation method according to claim 1, characterized in that, Performing the first programming operation includes: Provide a programming voltage to the first word line coupled to the currently selected first memory cell; Channel on-voltage is provided to the first word line coupled to the remaining first memory cell, the second redundant word line, and the second word line coupled to the second memory cell contained in the second memory string.

5. The method for programming a memory according to claim 1, characterized in that, The second storage string includes a plurality of second storage cells and a plurality of second word lines coupled to the plurality of second storage cells, and the programming operation method further includes: A pre-charge for performing a second programming operation on the plurality of second memory cells included in the second memory string; wherein the pre-charge includes: providing a fifth preset voltage to the bit line; and providing a sixth preset voltage to the second word line coupled to the second memory cell in the programmed state, the plurality of first word lines and the second redundant word line, so as to turn on the second memory cell in the programmed state, the plurality of first memory cells and the at least one second redundant memory cell; The second programming operation is performed sequentially from the second memory cell adjacent to the second redundant memory string to the second memory cell adjacent to the source line.

6. The method for programming a memory according to claim 1, characterized in that, The memory further includes a third redundant memory string located between the second memory string and the source line, the third redundant memory string including at least one third redundant memory cell connected in series and a third redundant word line coupled to the at least one third redundant memory cell, and the programming operation method further includes: A pre-charge for performing a third programming operation on a plurality of second memory cells included in the second memory string, wherein the pre-charge includes: providing a seventh preset voltage to the source line; providing an eighth preset voltage to a third redundant word line coupled to the at least one third redundant memory cell in the programmed state, so that the at least one third redundant memory cell in the programmed state is turned on; and providing a ninth preset voltage to a word line coupled to a memory cell located between the bit line and the third redundant memory string, so that the memory cell located between the bit line and the third redundant memory string is not turned on. The third programming operation is performed sequentially from the second storage cell adjacent to the second redundant storage string to the second storage cell adjacent to the third redundant storage string.

7. The method for programming a memory according to claim 6, characterized in that, The ninth preset voltage is 0V.

8. The method for programming a memory according to any one of claims 1 to 7, characterized in that, Before pre-charging the plurality of first storage cells included in the first storage string during the first programming operation, the programming operation method further includes: A partial erase operation is performed on the memory, wherein the partial erase operation includes: for the first memory string and the second memory string that have been written with data, only the first memory string is erased, and the second memory string is not erased.

9. The method for programming a memory according to any one of claims 1 to 7, characterized in that, The memory is a three-dimensional memory.

10. A memory, characterized in that, The memory includes: a first memory string, a second redundant memory string, and a second memory string connected in series; and a control circuit for controlling the first memory string, the second redundant memory string, and the second memory string; wherein the first memory string is connected to a bit line; the second memory string is connected to a source line; the first memory string includes a plurality of first memory cells connected in series and a plurality of first word lines coupled to the plurality of first memory cells; the second redundant memory string includes at least one second redundant memory cell connected in series and a second redundant word line coupled to the at least one second redundant memory cell; The control circuit is configured as follows: A pre-charge for performing a first programming operation on the plurality of first memory cells included in the first memory string, wherein the pre-charge includes: providing a first preset voltage to the bit line; providing a second preset voltage to a first word line coupled to a first memory cell in the programmed state, so that the first memory cell in the programmed state is turned on; and providing a fourth preset voltage to a second redundant word line coupled to a second redundant memory cell in the programmed state, so that the second redundant memory cell in the programmed state is not turned on. The first programming operation is performed, wherein the first programming operation is performed sequentially from the first storage cell adjacent to the bit line to the first storage cell adjacent to the second redundant storage string; The memory further includes a first redundant memory string located between the first memory string and the bit line. The first redundant memory string includes at least one first redundant memory cell connected in series and a first redundant word line coupled to the at least one first redundant memory cell. The control circuit is further configured to provide a third preset voltage to the first redundant word line coupled to the first redundant memory cell in the programmed state, thereby turning on the first redundant memory cell in the programmed state.

11. The memory according to claim 10, characterized in that, The duration of the first preset voltage is longer than the duration of the second preset voltage.

12. The memory according to claim 10, characterized in that, The control circuit is also configured to: Program the currently selected first memory cell; When programming of the currently selected first storage cell is completed, the first programming operation is pre-charged and the first programming operation is performed on the next selected first storage cell, wherein the next selected first storage cell is located between the currently selected first storage cell and the second redundant storage string and is adjacent to the currently selected first storage cell.

13. The memory according to claim 10, characterized in that, The control circuit is also configured to: Provide a programming voltage to the first word line coupled to the currently selected first memory cell; Channel on-voltage is provided to the first word line coupled to the remaining first memory cell, the second redundant word line, and the second word line coupled to the second memory cell contained in the second memory string.

14. The memory according to claim 10, characterized in that, The second memory string includes a plurality of second memory cells and a second word line coupled to the plurality of second memory cells. The control circuit is further controlled to precharge the plurality of second memory cells included in the second memory string for a second programming operation. The precharging includes providing a fifth preset voltage to the bit line; and providing a sixth preset voltage to the second word line coupled to the second memory cell in the programmed state, the plurality of first word lines, and the second redundant word line, so that the second memory cell in the programmed state, the plurality of first memory cells, and the at least one second redundant memory cell are turned on. The second programming operation is performed sequentially from the second memory cell adjacent to the second redundant memory string to the second memory cell adjacent to the source line.

15. The memory according to claim 10, characterized in that, The memory further includes a third redundant memory string located between the second memory string and the source line, the third redundant memory string including at least one third redundant memory cell connected in series and a third redundant word line coupled to the at least one third redundant memory cell, and the controlled circuit is further configured to: A pre-charge for performing a third programming operation on a plurality of second memory cells included in the second memory string, wherein the pre-charge includes: providing a seventh preset voltage to the source line; providing an eighth preset voltage to a third redundant word line coupled to the at least one third redundant memory cell in the programmed state, so that the at least one third redundant memory cell in the programmed state is turned on; and providing a ninth preset voltage to a word line coupled to a memory cell located between the bit line and the third redundant memory string, so that the memory cell located between the bit line and the third redundant memory string is not turned on. The third programming operation is performed sequentially from the second storage cell adjacent to the second redundant storage string to the second storage cell adjacent to the third redundant storage string.

16. The memory according to claim 15, characterized in that, The ninth preset voltage is 0V.

17. The memory according to any one of claims 10 to 16, characterized in that, Prior to the pre-charging of the plurality of first memory cells included in the first memory string during the first programming operation, the control circuit is further configured to: A partial erase operation is performed on the memory, wherein the partial erase operation includes: for the first memory string and the second memory string that have been written with data, only the first memory string is erased, and the second memory string is not erased.

18. The memory according to any one of claims 10 to 16, characterized in that, The memory is a three-dimensional memory.

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