Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure, a forming method thereof and a memory. The forming method comprises: providing a substrate, the substrate comprising a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, the first gate region comprising a first channel region, and the second gate region comprising a second channel region; forming a gate material layer on a surface of the substrate, the gate material layer comprising a middle region and an edge region, a projection of the middle region on the substrate covering at least a region between the first channel region and the second channel region, and a projection of the edge region on the substrate covering at least the first channel region and the second channel region; removing the gate material layer in the middle region and retaining the gate material layer in the edge region to form a first gate structure in the first gate region and a second gate structure in the second gate region. The forming method of the present disclosure can reduce the instability of the gate line width and improve the size uniformity of the gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and high transfer speed. The gate structure, as the core component of DRAM, plays a crucial role in the electrical performance of the device.

[0003] With the continuous advancement of semiconductor technology, the miniaturization of gate structure dimensions greatly helps to save costs and generate revenue. However, the size of the gate structure is positively correlated with its accuracy and stability. How to achieve gate structure miniaturization while ensuring that its performance is not affected or even improved has become a research hotspot. However, with the miniaturization of size, the etching difficulty of the gate structure increases, and the etching stability of different gate structures is poor.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce the instability of the gate linewidth and improve the dimensional uniformity of the gate structure.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] A substrate is provided, the substrate including a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, the first gate region including a first channel region and the second gate region including a second channel region;

[0008] A gate material layer is formed on the surface of the substrate. The gate material layer includes an adjacently distributed intermediate region and an edge region. The orthographic projection of the intermediate region on the substrate at least covers the region between the first channel region and the second channel region. The orthographic projection of the edge region on the substrate at least covers the first channel region and the second channel region.

[0009] The gate material layer located in the middle region is removed, while the gate material layer in the edge region is retained, to form a first gate structure in the first gate region and a second gate structure in the second gate region.

[0010] In one exemplary embodiment of this disclosure, the forming method further includes:

[0011] A first insulating layer is formed on the top of the first gate structure, on the sidewall of the first gate structure away from the second gate structure, on the top of the second gate structure, and on the sidewall of the second gate structure away from the first gate structure.

[0012] A second insulating layer is formed on the surface of the first insulating layer located on top of the first gate structure, on the sidewall of the first gate structure near the second gate structure, on the surface of the first insulating layer located on top of the second gate structure, and on the sidewall of the second gate structure near the first gate structure.

[0013] In one exemplary embodiment of this disclosure, a first insulating layer is formed on the top of the first gate structure, the sidewall of the first gate structure away from the second gate structure, the top of the second gate structure, and the sidewall of the second gate structure away from the first gate structure, including:

[0014] After forming a gate material layer on the surface of the substrate, a first insulating material layer is formed on the surface and sidewalls of the gate material layer.

[0015] Before removing the gate material layer located in the intermediate region and retaining the gate material layer in the edge region, the method further includes:

[0016] Remove the first insulating material layer in the middle region and retain the first insulating material layer in the edge region.

[0017] In one exemplary embodiment of this disclosure, removing the first insulating material layer in the intermediate region and removing the gate material layer in the intermediate region includes:

[0018] A support layer is formed on the surface of the substrate, and the support layer is in contact with the first insulating material layer located on the sidewall of the gate material layer;

[0019] A mask layer is formed on the surface of the structure jointly formed by the support layer and the first insulating material layer;

[0020] A photoresist layer is formed on the surface of the mask layer;

[0021] The photoresist layer is exposed and developed to form a developed area, which exposes the mask layer.

[0022] The mask layer is etched in the developing area to form a mask pattern that covers the first insulating material layer in the edge region and exposes the first insulating material layer in the middle region.

[0023] Using the substrate as an etch stop layer and the mask layer as a mask, the first insulating material layer and the gate material layer are etched.

[0024] In one exemplary embodiment of this disclosure, forming a second insulating layer on the surface of the first insulating layer located on top of the first gate structure, the sidewall of the first gate structure near the second gate structure, the surface of the first insulating layer located on top of the second gate structure, and the sidewall of the second gate structure near the first gate structure includes:

[0025] A second insulating material layer is formed on the surface of the structure jointly formed by the first gate structure, the second gate structure, the first insulating layer and the substrate;

[0026] The second insulating material layer covering the surface of the substrate is removed, and the second insulating material layer located on the sidewall of the first gate structure and the sidewall of the second gate structure is in contact with the surface of the substrate.

[0027] In one exemplary embodiment of this disclosure, at least one of the first insulating layer and the second insulating layer includes a first isolation layer, a second isolation layer and a third isolation layer stacked sequentially, wherein the first isolation layer and the third isolation layer are made of the same material.

[0028] In one exemplary embodiment of this disclosure, the orthographic projection of the gate material layer on the substrate is rectangular; the edge region includes a first edge region whose orthographic projection on the substrate coincides with the first channel region, and a second edge region whose orthographic projection on the substrate coincides with the second channel region.

[0029] In one exemplary embodiment of this disclosure, the edge region further includes a third edge region and a fourth edge region that are orthographically projected onto the substrate and cover the shallow trench isolation structure, and are respectively connected between the first edge region and the second edge region, wherein the third edge region and the fourth edge region are spaced apart.

[0030] In one exemplary embodiment of this disclosure, the width of the first gate structure in a direction parallel to the substrate is equal to the width of the second gate structure.

[0031] In one exemplary embodiment of this disclosure, the widths of both the first gate structure and the second gate structure are 20 nm to 80 nm.

[0032] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0033] The substrate includes a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, wherein the first gate region includes a first channel region and the second gate region includes a second channel region.

[0034] A first gate structure is formed on the surface of the first channel region;

[0035] A second gate structure is formed on the surface of the second channel region;

[0036] A first insulating layer is formed on the top of the first gate structure, the sidewall of the first gate structure away from the second gate structure, the top of the second gate structure, and the sidewall of the second gate structure away from the first gate structure.

[0037] The second insulating layer is formed on the surface of the first insulating layer at the top of the first gate structure, on the sidewall of the first gate structure near the second gate structure, on the surface of the first insulating layer at the top of the second gate structure, and on the sidewall of the second gate structure near the first gate structure.

[0038] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0039] A support layer is formed on the surface of the substrate and is in contact with the first insulating layer located on the sidewalls of the first gate structure and the second gate structure.

[0040] In one exemplary embodiment of this disclosure, at least one of the first insulating layer and the second insulating layer includes a first isolation layer, a second isolation layer and a third isolation layer stacked sequentially, wherein the first isolation layer and the third isolation layer are made of the same material.

[0041] In one exemplary embodiment of this disclosure, the orthographic projection of the gate material layer on the substrate is rectangular; the edge region includes a first edge region whose orthographic projection on the substrate coincides with the first channel region, and a second edge region whose orthographic projection on the substrate coincides with the second channel region.

[0042] In one exemplary embodiment of this disclosure, the edge region further includes a third edge region and a fourth edge region that are orthographically projected onto the substrate and cover the shallow trench isolation structure, and are respectively connected between the first edge region and the second edge region, wherein the third edge region and the fourth edge region are spaced apart.

[0043] In one exemplary embodiment of this disclosure, the width of the first gate structure in a direction parallel to the substrate is equal to the width of the second gate structure.

[0044] In one exemplary embodiment of this disclosure, the widths of both the first gate structure and the second gate structure are 20 nm to 80 nm.

[0045] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0046] The semiconductor structure and its formation method disclosed herein, as well as the memory, can simultaneously form a first gate structure and a second gate structure through a single thin film removal process. This reduces the instability of gate linewidth caused by the loading effect, improves the dimensional uniformity of the gate structure, and thus improves product yield. Furthermore, in the direction parallel to the substrate, the two ends of the gate material layer can respectively serve as the ends of the first gate structure and the second gate structure that are far from the first gate structure. Since the size of the gate material layer is much larger than the linewidth of the first and second gate structures, compared to gate structures with low linewidths, the larger width of the gate material layer makes it easier to align its ends with the pre-set positions during the formation process. This reduces process difficulty, minimizes positional deviations, and improves product stability.

[0047] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0049] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0050] Figure 2 This is a schematic diagram of the structure after step S120 is completed in the embodiment of this disclosure;

[0051] Figure 3 This is a schematic diagram of the first conductive material layer, the second conductive material layer, and the passivation material layer in the embodiments of this disclosure;

[0052] Figure 4 This is a schematic diagram of the structure after step S130 is completed in the embodiment of this disclosure;

[0053] Figure 5 This is a schematic diagram of the first insulating material layer in an embodiment of this disclosure;

[0054] Figure 6 This is a schematic diagram of the structure after step S210 is completed in the embodiment of this disclosure;

[0055] Figure 7 This is a schematic diagram of the structure after step S250 is completed in the embodiment of this disclosure;

[0056] Figure 8 This is a schematic diagram of the structure after step S150 is completed in the embodiment of this disclosure;

[0057] Figure 9 This is a schematic diagram of the structure after step S310 is completed in the embodiment of this disclosure;

[0058] Figure 10 This is a schematic diagram of the fourth isolation material layer in the embodiments of this disclosure;

[0059] Figure 11 This is a schematic diagram of the fifth isolation material layer in the embodiments of this disclosure;

[0060] Figure 12 This is a schematic diagram of the photoresist layer in an embodiment of this disclosure.

[0061] Explanation of reference numerals in the attached figures:

[0062] 1. Substrate; 11. Shallow trench isolation structure; 12. First gate region; 13. Second gate region; 2. Gate material layer; 21. First gate structure; 22. Second gate structure; 210. First conductive layer; 220. Second conductive layer; 230. Passivation layer; 3. First insulating layer; 31. First isolation layer; 32. Second isolation layer; 33. Third isolation layer; 4. Second insulating layer; 41. Fourth isolation layer; 42. Fifth isolation layer; 43. Sixth isolation layer; 5. 6. Support layer; 7. Mask layer; 8. Photoresist layer; 201. First conductive material layer; 202. Second conductive material layer; 203. Passivation material layer; 204. Mask material layer; 300. First insulating material layer; 301. First isolation material layer; 302. Second isolation material layer; 303. Third isolation material layer; 400. Second insulating material layer; 401. Fourth isolation material layer; 402. Fifth isolation material layer; 403. Sixth isolation material layer; 8. Photoresist layer. Detailed Implementation

[0063] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0064] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0065] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0066] This disclosure provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the forming method may include steps S110-S130, wherein:

[0067] Step S110: Provide a substrate, the substrate including a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, the first gate region including a first channel region and the second gate region including a second channel region.

[0068] Step S120: A gate material layer is formed on the surface of the substrate. The gate material layer includes an adjacently distributed intermediate region and an edge region. The orthographic projection of the intermediate region on the substrate at least covers the region between the first channel region and the second channel region. The orthographic projection of the edge region on the substrate at least covers the first channel region and the second channel region.

[0069] Step S130: Remove the gate material layer located in the middle region and retain the gate material layer in the edge region to form a first gate structure in the first gate region and a second gate structure in the second gate region.

[0070] The semiconductor structure formation method disclosed herein can simultaneously form a first gate structure and a second gate structure through a single thin film removal process. This reduces the instability of gate linewidth caused by the loading effect, improves the dimensional uniformity of the gate structure, and thus improves product yield. Furthermore, in the direction parallel to the substrate, the two ends of the gate material layer can respectively serve as the ends of the first gate structure and the second gate structure that are far from the first gate structure. Since the size of the gate material layer is much larger than the linewidth of the first and second gate structures, compared to gate structures with low linewidths, the larger width of the gate material layer makes it easier to align its ends with the pre-set positions during the formation process. This reduces process difficulty, minimizes positional deviations, and further improves product stability.

[0071] like Figure 1 As shown, in step S110, a substrate is provided, the substrate including a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, the first gate region including a first channel region and the second gate region including a second channel region.

[0072] like Figure 2 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0073] In one embodiment, the substrate 1 may be a silicon substrate, with a shallow trench isolation structure 11 formed therein. The shallow trench isolation structure 11 is formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structure 11 may include silicon nitride or silicon oxide, etc., and is not specifically limited thereto. The cross-sectional shape of the shallow trench isolation structure 11 can be set according to actual needs. The shallow trench isolation structure 11 can separate a plurality of gate regions on the substrate 1, and each gate region may include a first doped region and a second doped region arranged at intervals.

[0074] Substrate 1 can be an n-type substrate, and the first and second doped regions can be doped to form the source and drain, respectively. For example, both the first and second doped regions can be p-type doped to form p-type doped regions, which can form a pn junction with the n-type substrate. For example, p-type doping material can be doped into the first and second doped regions to form p-type semiconductors. The p-type doping material can be an element located in Group III of the periodic table, for example, boron, but it can also be materials of other elements, which will not be listed here.

[0075] The first doped region can be used as the source and the second doped region can be used as the drain; or, the first doped region can be used as the drain and the second doped region can be used as the source.

[0076] In one embodiment, boron ions can be implanted into the first doped region and the second doped region by ion implantation. Of course, other processes can also be used to dope the first doped region and / or the second doped region, and no special limitation is made here.

[0077] The area between the first doped region and the second doped region can be a channel region, which allows current to flow. The current in the channel region can be controlled by the voltage of the gate structure above it to achieve gate control function.

[0078] In one embodiment of this disclosure, a shallow doped region can be formed on the side of the first doped region and the second doped region near the channel region, thereby reducing the short-channel effect of the semiconductor structure.

[0079] In one exemplary embodiment of this disclosure, the gate regions on both sides of a shallow trench isolation structure 11 can be defined as a first gate region 12 and a second gate region 13, respectively, and the channel region in the first gate region 12 can be defined as a first channel region; meanwhile, the channel region in the second gate region 13 can be defined as a second channel region. In one embodiment, the first doped region, the first channel region, the second doped region of the first gate region 12, the shallow trench isolation structure 11, the first doped region, the second channel region of the second gate region 13, and the second doped region of the second gate region 13 are sequentially adjacent to each other.

[0080] like Figure 1 As shown, in step S120, a gate material layer is formed on the surface of the substrate. The gate material layer includes an adjacently distributed intermediate region and an edge region. The orthographic projection of the intermediate region on the substrate at least covers the region between the first channel region and the second channel region. The orthographic projection of the edge region on the substrate at least covers the first channel region and the second channel region.

[0081] The gate material layer 2 may be formed on the substrate surface and may span the first gate region 12, the shallow trench isolation structure 11, and the second gate region 13. For example, the gate material layer 2 may simultaneously cover the surface of the first channel region, the second doped region of the first gate region 12, the shallow trench isolation structure 11, the first doped region of the second gate region 13, and the second channel region.

[0082] In one exemplary embodiment of this disclosure, the gate material layer 2 may include an adjacently distributed intermediate region and an edge region. The orthographic projection of the intermediate region onto the substrate 1 may at least cover the region between the first channel region and the second channel region, and the orthographic projection of the edge region onto the substrate 1 may at least cover the first channel region and the second channel region.

[0083] In some embodiments of this disclosure, the orthographic projection of the gate material layer 2 onto the substrate 1 may be rectangular, and the central region may also be rectangular. The edge regions may include a first edge region and a second edge region spaced apart. Both the first and second edge regions may be strip-shaped, and the first edge region contacts one side of the rectangle of the central region. The second edge region contacts the side of the central region that is directly opposite the side connected to the first edge region. For example, the first and second edge regions may respectively contact the short side of the rectangle of the central region, or the first and second edge regions may respectively contact the long side of the rectangle of the central region.

[0084] In one embodiment of this disclosure, the orthographic projection of the first edge region on the substrate 1 coincides with the first channel region, and the orthographic projection of the second edge region on the substrate 1 coincides with the second channel region. At this time, the orthographic projection of the middle region on the substrate 1 covers the shallow trench isolation structure 11, the second doped region of the first gate region 12, and the first doped region of the second gate region 13.

[0085] In one embodiment of this disclosure, the edge region may further include a third edge region and a fourth edge region. The orthogonal projections of the third edge region and the fourth edge region onto the substrate 1 can both cover the shallow trench isolation structure 11. The third edge region and the fourth edge region can be spaced apart and can both be connected between the first edge region and the second edge region. That is, the first edge region, the second edge region, the third edge region, and the fourth edge region can form an annular region to facilitate the subsequent formation of a common-gate structure for two transistors.

[0086] In one exemplary embodiment of this disclosure, the gate material layer 2 may include a first conductive layer 210, a second conductive layer 220, and a passivation layer 230 stacked along a direction perpendicular to the substrate 1, wherein:

[0087] For example, the first conductive layer 210 may be a thin film formed on the surface of the substrate 1 or a coating formed on the surface of the substrate 1. The form of the first conductive layer 210 is not specifically limited here. The first conductive layer 210 may cover the surface of the first channel region, the second doped region of the first gate region 12, the shallow trench isolation structure 11, the first doped region of the second gate region 13, and the second channel region.

[0088] The second conductive layer 220 can be a thin film formed on the side of the first conductive layer 210 away from the substrate 1, or it can be a coating formed on the surface of the first conductive layer 210. No particular limitation is made to the form of the second conductive layer 220. The second conductive layer 220 can be in contact with the first conductive layer 210, and its orthographic projection on the substrate 1 can coincide with the orthographic projection of the first conductive layer 210 on the substrate 1; that is, the second conductive layer 220 can be flush with the end of the first conductive layer 210.

[0089] The passivation layer 230 can be a thin film formed on the side of the second conductive layer 220 opposite to the first conductive layer 210, or it can be a coating formed on the side of the second conductive layer 220 opposite to the first conductive layer 210. No particular limitation is made to the form of the passivation layer 230. The passivation layer 230 can cover the entire surface of the second conductive layer 220, that is, the orthogonal projection of the passivation layer 230 on the substrate 1 can coincide with the orthogonal projection of the second conductive layer 220 on the substrate 1, or the orthogonal projection of the second conductive layer 220 on the substrate 1 is within the orthogonal projection of the passivation layer 230 on the substrate 1. The passivation layer 230 can protect the surface of the second conductive layer 220 to prevent damage to the surface of the second conductive layer 220; at the same time, the passivation layer 230 can also serve as an insulating layer, isolating the second conductive layer 220 from other structures, preventing coupling or short circuits between the second conductive layer 220 and other structures, and improving product yield.

[0090] In one exemplary embodiment of this disclosure, such as Figure 3 As shown, a first conductive material layer 201, a second conductive material layer 202, and a passivation material layer 203 can be sequentially formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. The material of the first conductive material layer 201 can be polycrystalline silicon, the material of the second conductive material layer 202 can be tungsten, and the material of the passivation material layer 203 can be silicon nitride.

[0091] The orthographic projections of the first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 on the substrate 1 can completely overlap, and each of the first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 at least covers the first gate region 12, the second gate region 13, and the shallow trench isolation structure 11 between the first gate region 12 and the second gate region 13. The first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 can be etched using an etching process to form the gate material layer 2.

[0092] For example, a mask material layer 204 can be formed on the surface of the passivation material layer 203 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods. The material of the mask material layer 204 can be at least one of silicon oxide, silicon oxynitride, or carbon; of course, other materials are also possible, which will not be listed here. The mask material layer 204 can be a single-layer structure or a multi-layer structure, without special limitation. A photoresist layer 8 can be formed on the mask material layer 204 by spin coating or other methods. The material of the photoresist layer 8 can be a positive photoresist or a negative photoresist, without special limitation.

[0093] A photoresist layer 8 can be exposed using a photomask. The photomask pattern can match the required pattern of the gate material layer 2. The orthogonal projection of the photomask pattern onto the substrate 1 can cover the first channel region, the second doped region of the first gate region 12, the shallow trench isolation structure 11, the first doped region of the second gate region 13, and the second channel region. Subsequently, the exposed photoresist layer 8 can be developed to form a developing region, which exposes the photomask material layer 204. The photomask material layer 204, the first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 are etched in the developing region to form the gate material layer 2.

[0094] After the gate material layer 2 is formed, the photoresist layer 8 can be ashed to remove the photoresist layer 8, and the mask material layer 204 can be removed by dry etching process so that the mask material layer 204 no longer covers the surface of the gate material layer 2.

[0095] like Figure 1 As shown, in step S130, the gate material layer located in the middle region is removed, while the gate material layer in the edge region is retained, so as to form a first gate structure in the first gate region and a second gate structure in the second gate region.

[0096] In one exemplary embodiment of this disclosure, the gate material layer 2 may be etched to form a first gate structure 21 in the first gate region 12, and simultaneously, a second gate structure 22 in the second gate region 13. In this embodiment, the structure after step S130 is as follows: Figure 4 As shown. In this process, the first gate structure 21 and the second gate structure 22 can be formed simultaneously through a single etching process, which can reduce the instability of gate linewidth caused by the load effect, improve the dimensional uniformity of the gate structure, and thus improve the product yield. In the direction parallel to the substrate 1, the two ends of the gate material layer 2 can be respectively used as the ends of the first gate structure 21 away from the second gate structure 22 and the ends of the second gate structure 22 away from the first gate structure 21. Since the size of the gate material layer 2 is much larger than the linewidth of the first gate structure 21 and the second gate structure 22, compared with directly etching to form a low linewidth gate structure, the accuracy of aligning its ends with the pre-set position is higher during the formation of the gate material layer 2 due to the larger width of the gate material layer 2. This results in higher end alignment accuracy of the final first gate structure 21 and the second gate structure 22, which can improve product stability.

[0097] In some embodiments of this disclosure, the end positions of the first gate structure 21 near the second gate structure 22 and the end positions of the second gate structure 22 near the first gate structure 21 can be accurately located using a mask, thereby accurately defining the linewidths of the first gate structure 21 and the second gate structure 22. In one embodiment, the width of the first gate structure 21 can be equal to the width of the second gate structure 22 in a direction parallel to the substrate 1, which can improve product stability.

[0098] For example, the width of both the first gate structure 21 and the second gate structure 22 can be 20nm to 80nm. For example, its width can be 20nm, 40nm, 60nm or 80nm, and of course, it can also be other linewidths, which will not be listed here.

[0099] Preferably, the widths of the first gate structure 21 and the second gate structure 22 can both be 40nm to 60nm.

[0100] In some embodiments, when the central region is a rectangular region and the edge regions only include the first edge region and the second edge region, the first gate structure 21 and the second gate structure 22 are independent gate structures. The first gate structure 21 may be located at the top of the first channel region, and the first doped region and the second doped region adjacent to each other on both sides of the first channel region may serve as the source or drain, respectively, and together with the first gate structure 21, form a transistor structure. It should be noted that, in this process, the first doped region adjacent to the first channel region may serve as the source, and the second doped region adjacent to the first channel region may serve as the drain; or, the second doped region adjacent to the first channel region may serve as the source, and the first doped region adjacent to the first channel region may serve as the drain, without any special limitation. The second gate structure 22 may be located at the top of the second channel region, and the first doped region and the second doped region adjacent to each other on both sides of the second channel region may serve as the source or drain, respectively, and together with the second gate structure 22, form a transistor structure. It should be noted that, in this process, the first doped region adjacent to the second channel region can be used as the source, and the second doped region adjacent to the second channel region can be used as the drain; or, the second doped region adjacent to the second channel region can be used as the source, and the first doped region adjacent to the second channel region can be used as the drain, without any special limitation.

[0101] In one embodiment, the gate material layer 2 on the surface of the shallow trench isolation structure 11 and a portion of the gate material layer 2 on the surfaces of the first gate region 12 and the second gate region 13 adjacent to the shallow trench isolation structure 11 can be removed by an etching process, with the substrate 1 as the etching stop layer. That is, the gate material layer 2 on the surface of the shallow trench isolation structure 11, the gate material layer 2 on the surface of the second doped region of the first gate region 12, and the gate material layer 2 on the surface of the first doped region of the second gate region 13 can be removed by an etching process, leaving only the gate material layer 2 on the surface of the first channel region and the gate material layer 2 on the surface of the second channel region. The gate material layer 2 retained on the surface of the first channel region can be defined as the first gate structure 21, and the gate material layer 2 retained on the surface of the second channel region can be defined as the second gate structure 22.

[0102] It should be noted that when the middle region is a rectangular region and the edge region is an annular region, the first gate structure 21 and the second gate structure 22 are connected together to form two common gate transistors.

[0103] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include steps S140 and S150, wherein:

[0104] Step S140: A first insulating layer is formed on the top of the first gate structure, the sidewall of the first gate structure away from the second gate structure, the top of the second gate structure, and the sidewall of the second gate structure away from the first gate structure.

[0105] The first insulating layer 3 can be located on the top of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21. The first insulating layer 3 can provide insulation protection for the surfaces and sidewalls of the first gate structure 21 and the second gate structure 22, preventing coupling or short circuits between the first gate structure 21 and the second gate structure 22 and other surrounding structures, thereby improving product yield. At the same time, the first insulating layer 3 can also isolate the source and / or drain from the sides of the first gate structure 21 and / or the second gate structure 22 by a non-zero distance, thereby reducing the GIDL effect and reducing standby power consumption.

[0106] The first insulating layer 3 can be a single-layer film or a multi-layer film, without any particular limitation. Preferably, the first insulating layer 3 is a multi-layer structure, which may include a first isolation layer 31, a second isolation layer 32 and a third isolation layer 33 stacked sequentially. The first isolation layer 31, the second isolation layer 32 and the third isolation layer 33 can form triple protection, enhance the insulation effect, reduce the possibility of coupling between the first gate structure 21 and the second gate structure 22 and other structures, and improve product yield.

[0107] For example, a first isolation layer 31 is formed on the top surface of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top surface of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21; a second isolation layer 32 may cover the surface of the first isolation layer 31, and a third isolation layer 33 may cover the surface of the second isolation layer 32.

[0108] In one embodiment of this disclosure, the first isolation layer 31 and the third isolation layer 33 are made of the same material, while the second isolation layer 32 is made of a different material than the first isolation layer 31 and the third isolation layer 33. This different material arrangement can balance the internal stress of the device, thereby maintaining stress balance within the device. For example, the second isolation layer 32 can balance the compressive stress within the first isolation layer 31 and the third isolation layer 33; simultaneously, the first isolation layer 31 and the third isolation layer 33 can balance the tensile stress within the second isolation layer 32. For instance, the first isolation layer 31 and the third isolation layer 33 can be made of silicon nitride, and the second isolation layer 32 can be made of silicon oxide. Of course, the materials of the first isolation layer 31, the second isolation layer 32, and the third isolation layer 33 can also be other materials, which will not be listed here.

[0109] In one exemplary embodiment of this disclosure, forming a first insulating layer 3 on the top of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21 (i.e., step S140) may include forming a first insulating material layer on the surface and sidewall of the gate material layer 2 after forming a gate material layer 2 on the surface of the substrate.

[0110] In some embodiments, such as Figure 5 As shown, the first insulating material layer 300 can cover the surface and sidewalls of the gate material layer 2, and can provide insulation protection for the surface and sidewalls of the gate material layer 2, so as to prevent the gate material layer 2 from coupling or short-circuiting with other structures.

[0111] The first insulating material layer 300 can be a single-layer film or a multi-layer film, without any particular limitation. Preferably, the first insulating material layer 300 has a multi-layer structure, which may include a first isolation material layer 301, a second isolation material layer 302, and a third isolation material layer 303 stacked sequentially, wherein the first isolation material layer 301 is formed on the surface and sidewalls of the gate material layer 2; the second isolation material layer 302 may cover the surface of the first isolation material layer 301, and the third isolation material layer 303 may cover the surface of the second isolation material layer 302.

[0112] In one embodiment of this disclosure, the first insulating material layer 301 and the third insulating material layer 303 are made of the same material, while the second insulating material layer 302 is made of a different material than the first insulating material layer 301 and the third insulating material layer 303. The use of different materials can balance the stress within the first insulating material layer 300. For example, the first insulating material layer 301 and the third insulating material layer 303 can be made of silicon nitride, and the second insulating material layer 302 can be made of silicon oxide. Of course, the materials of the first insulating material layer 301, the second insulating material layer 302, and the third insulating material layer 303 can also be other materials, which will not be listed here.

[0113] For example, a first isolation material layer 301, a second isolation material layer 302, and a third isolation material layer 303 may be sequentially formed on the surface and sidewalls of the gate material layer 2 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods. Of course, the first isolation material layer 301, the second isolation material layer 302, and the third isolation material layer 303 may also be sequentially formed on the surface and sidewalls of the gate material layer 2 by other methods. No special limitation is made here on the formation method of the first isolation material layer 301, the second isolation material layer 302, and the third isolation material layer 303.

[0114] In one embodiment of this disclosure, before removing the gate material layer 2 located in the middle region and retaining the gate material layer 2 in the edge region, the method further includes: removing the first insulating material layer 300 in the middle region and retaining the first insulating material layer 300 in the edge region.

[0115] For example, substrate 1 can be an etch stop layer. The gate material layer 2 and the first insulating material layer 300 located in the middle region can be removed simultaneously by the same etch process, leaving only the gate material layer 2 and the first insulating material layer 300 located in the edge region. The first insulating material layer 300 retained at the top of the first channel region and the top of the second channel region can be defined as the first insulating layer 3. The first insulating layer 3 covers the top of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21.

[0116] In one exemplary embodiment of this disclosure, removing the first insulating material layer in the intermediate region and removing the gate material layer 2 in the intermediate region may include steps S210-S260, wherein:

[0117] Step S210: A support layer is formed on the surface of the substrate, the support layer being in contact with the first insulating material layer located on the sidewall of the gate material layer.

[0118] A support layer 5 can be formed on the surface of the substrate 1 and can contact the first insulating material layer 300 on the sidewall of the gate material layer 2. During the subsequent etching of the gate material layer 2 to form the first gate structure 21 and the second gate structure 22, the support layer 5 can support the periphery of the first gate structure 21 and the second gate structure 22, preventing the remaining gate material layer 2 from collapsing during the etching process, thus improving product yield. Furthermore, in subsequent processes, the support layer 5 can also support the first gate structure 21 and the second gate structure 22, reducing the possibility of collapse during subsequent processes and further improving product yield. In this embodiment, the structure after step S210 is as follows: Figure 6 As shown.

[0119] Step S220: A mask layer is formed on the surface of the structure formed by the support layer and the first insulating material layer.

[0120] The mask layer 6 can be formed on the surface of the structure jointly formed by the support layer 5 and the first insulating material layer 300 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or other methods. Of course, other methods can also be used to form the mask layer 6; no specific limitation is made here. The material of the mask layer 6 can be at least one of silicon oxide, oxide nitride, or carbon; other materials are also possible, but will not be listed here. The mask layer 6 can be a single-layer structure or a multi-layer structure; no specific limitation is made here.

[0121] Step S230: A photoresist layer is formed on the surface of the mask layer.

[0122] A photoresist layer 7 can be formed on the mask layer 6 by spin coating or other methods. The material of the photoresist layer 7 can be positive photoresist or negative photoresist, and no special limitation is made here.

[0123] Step S240: Expose and develop the photoresist layer to form a developing area, which exposes the mask layer.

[0124] A photomask can be used to expose the photoresist layer 7. The pattern of the photomask can be matched with the pattern required for the first gate structure 21 and the second gate structure 22. The orthogonal projection of the pattern of the photomask onto the substrate 1 can cover the second doped region of the first gate region 12, the shallow trench isolation structure 11, and the first doped region of the second gate region 13.

[0125] In step S250, the mask layer is etched in the developing area to form a mask pattern that covers the first insulating material layer in the edge region and exposes the first insulating material layer in the middle region.

[0126] Subsequently, the exposed photoresist layer 7 can be developed to form a developing area, which exposes the mask layer 6. The mask layer 6 is then etched in the developing area to form a mask pattern. In this embodiment, the structure after step S250 is as follows: Figure 7 As shown.

[0127] Step S260: Using the substrate as an etch stop layer and the mask layer as a mask, the first insulating material layer and the gate material layer are etched.

[0128] Using substrate 1 as an etch stop layer and mask layer 6 with mask pattern as a mask, anisotropic etching is performed on gate material layer 2 and first insulating material layer 300 at the mask pattern, thereby removing gate material layer 2 and first insulating material layer 300 located in the middle region.

[0129] After the first insulating material layer 300 and the gate material layer 2 are etched, the photoresist layer 7 can be ashed to remove the photoresist layer 7, and the mask layer 6 can be removed by a dry etching process so that the mask layer 6 no longer covers the surface of the support layer 5 and the first insulating layer 3.

[0130] Step S150: A second insulating layer is formed on the surface of the first insulating layer located at the top of the first gate structure, on the sidewall of the first gate structure near the second gate structure, on the surface of the first insulating layer located at the top of the second gate structure, and on the sidewall of the second gate structure near the first gate structure.

[0131] The second insulating layer 4 can cover the surface of the first insulating layer 3 on top of the first gate structure 21, the sidewall of the first gate structure 21 near the second gate structure 22, the surface of the first insulating layer 3 on top of the second gate structure 22, and the sidewall of the second gate structure 22 near the first gate structure 21. The second insulating layer 4 can provide insulation protection for the sidewall of the first gate structure 21 near the second gate structure 22 and the sidewall of the second gate structure 22 near the first gate structure 21, avoiding coupling or short circuits between the first gate structure 21 and the second gate structure 22 and other surrounding structures, thus improving product yield. At the same time, the second insulating layer 4 can also isolate the source and / or drain from the sides of the first gate structure 21 and / or the second gate structure 22 by a non-zero distance, thereby reducing the GIDL effect and further reducing standby power consumption.

[0132] The structure of the second insulating layer 4 can be the same as or different from that of the first insulating layer 3, and no special limitation is made here. For example, the second insulating layer 4 can be a single-layer film or a multi-layer film, and no special limitation is made here. Preferably, the second insulating layer 4 is a multi-layer structure, which may include a first isolation layer, a second isolation layer and a third isolation layer stacked sequentially. In order to distinguish the second insulating layer 4 from the first insulating layer 3, the first isolation layer, the second isolation layer and the third isolation layer of the second insulating layer 4 can be defined as the fourth isolation layer 41, the fifth isolation layer 42 and the sixth isolation layer 43, respectively. The fourth isolation layer 41, the fifth isolation layer 42 and the sixth isolation layer 43 can form triple protection, enhance the insulation effect, further reduce the possibility of coupling between the first gate structure 21 and the second gate structure 22 and other structures, and improve the product yield.

[0133] For example, a fourth isolation layer 41 is formed on the surface of the first insulating layer 3 on top of the first gate structure 21, on the sidewall of the first gate structure 21 near the second gate structure 22, on the surface of the first insulating layer 3 on top of the second gate structure 22, and on the sidewall of the second gate structure 22 near the first gate structure 21; a fifth isolation layer 42 may cover the surface of the fourth isolation layer 41, and a sixth isolation layer 43 may cover the surface of the fifth isolation layer 42.

[0134] In one embodiment of this disclosure, the fourth isolation layer 41 and the sixth isolation layer 43 are made of the same material, while the fifth isolation layer 42 is made of a different material than the fourth isolation layer 41 and the sixth isolation layer 43. This different material arrangement can balance the internal stress of the device, thus maintaining stress balance within the device. For example, the fifth isolation layer 42 can balance the compressive stress within the fourth isolation layer 41 and the sixth isolation layer 43; simultaneously, the fourth isolation layer 41 and the sixth isolation layer 43 can balance the tensile stress within the fifth isolation layer 42. For instance, the fourth isolation layer 41 and the sixth isolation layer 43 can be made of silicon nitride, and the fifth isolation layer 42 can be made of silicon oxide. Of course, the materials of the fourth isolation layer 41, the fifth isolation layer 42, and the sixth isolation layer 43 can also be other materials, which will not be listed here. In this embodiment of the disclosure, the structure after step S150 is as follows: Figure 8 As shown.

[0135] In one exemplary embodiment of this disclosure, forming a second insulating layer 4 on the surface of the first insulating layer 3 located on top of the first gate structure 21, the sidewall of the first gate structure 21 near the second gate structure 22, the surface of the first insulating layer 3 located on top of the second gate structure 22, and the sidewall of the second gate structure 22 near the first gate structure 21 (i.e., step S150) may include steps S310 and S320, wherein:

[0136] Step S310: A second insulating material layer is formed on the surface of the structure jointly formed by the first gate structure, the second gate structure, the first insulating layer and the substrate.

[0137] In some embodiments, such as Figure 9 As shown, the second insulating material layer 400 can cover the sidewall of the first gate structure 21 near the second gate structure 22, the sidewall of the second gate structure 22 near the first gate structure 21, the surface of the first insulating layer 3 on top of the first gate structure 21, the surface of the first insulating layer 3 on top of the second gate structure 22, and the surface of the substrate 1 between the first gate structure 21 and the second gate structure 22.

[0138] It should be noted that when the support layer 5 has been formed on the surface of the substrate 1, for the convenience of the process, the second insulating material layer 400 can also be simultaneously covered on the surface of the support layer 5.

[0139] The second insulating material layer 400 can be a single-layer film or a multi-layer film, without special limitation. Preferably, the second insulating material layer 400 has a multi-layer structure, which may include a fourth insulating material layer 401, a fifth insulating material layer 402, and a sixth insulating material layer 403 stacked sequentially, such as... Figure 10 As shown, the fourth isolation material layer 401 can be formed on the sidewall of the first gate structure 21 near the second gate structure 22, the sidewall of the second gate structure 22 near the first gate structure 21, the surface of the first insulating layer 3 on top of the first gate structure 21, the surface of the first insulating layer 3 on top of the second gate structure 22, the surface of the substrate 1 between the first gate structure 21 and the second gate structure 22, and the surface of the support layer 5; as shown Figure 11 As shown, the fifth isolation material layer 402 can cover the surface of the fourth isolation material layer 401, and the sixth isolation material layer 403 can cover the surface of the fifth isolation material layer 402.

[0140] In one embodiment of this disclosure, the fourth insulating material layer 401 and the sixth insulating material layer 403 are made of the same material, while the fifth insulating material layer 402 is made of a different material than the fourth insulating material layer 401 and the sixth insulating material layer 403. This arrangement of different materials can balance the stress within the second insulating material layer 400. For example, the fourth insulating material layer 401 and the sixth insulating material layer 403 can be made of silicon nitride, and the fifth insulating material layer 402 can be made of silicon oxide. Of course, the materials of the fourth insulating material layer 401, the fifth insulating material layer 402, and the sixth insulating material layer 403 can also be other materials, which will not be listed here.

[0141] For example, a fourth isolation material layer 401, a fifth isolation material layer 402, and a sixth isolation material layer 403 can be sequentially formed on the sidewall of the first gate structure 21 near the second gate structure 22, the sidewall of the second gate structure 22 near the first gate structure 21, the surface of the first insulating layer 3 at the top of the first gate structure 21, the surface of the first insulating layer 3 at the top of the second gate structure 22, the surface of the substrate 1 between the first gate structure 21 and the second gate structure 22, and the surface of the support layer 5 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods. Of course, the fourth isolation material layer 401, the fifth isolation material layer 402, and the sixth isolation material layer 403 can also be formed by other methods. No special limitation is made here regarding the formation method of the fourth isolation material layer 401, the fifth isolation material layer 402, and the sixth isolation material layer 403. In this embodiment, the structure after step S310 is as follows: Figure 9 As shown.

[0142] Step S320: Remove the second insulating material layer covering the surface of the substrate, and the second insulating material layer located on the sidewall of the first gate structure and the sidewall of the second gate structure is in contact with the surface of the substrate.

[0143] The substrate 1 can be used as an etch stop layer. The second insulating material layer 400 located on the surface of the substrate 1 can be removed by an etching process, while the second insulating material layer 400 located on the sidewall of the first gate structure 21 near the second gate structure 22, the sidewall of the second gate structure 22 near the first gate structure 21, the surface of the first insulating layer 3 at the top of the first gate structure 21, the surface of the first insulating layer 3 at the top of the second gate structure 22, and the surface of the support layer 5 can be retained. The retained second insulating material layer 400 can be defined as the second insulating layer 4, that is: the second insulating layer 4 covers the sidewall of the first gate structure 21 near the second gate structure 22, the sidewall of the second gate structure 22 near the first gate structure 21, the surface of the first insulating layer 3 at the top of the first gate structure 21, the surface of the first insulating layer 3 at the top of the second gate structure 22, and the surface of the support layer 5.

[0144] It should be noted that when etching away the second insulating material layer 400 on the surface of the substrate 1, the ends of the second insulating material layer 400 that are in contact with the substrate 1 on the sidewalls of the first gate structure 21 and the second gate structure 22 can be retained. The substrate 1 can support the second insulating material layer 400 formed on the sidewalls of the first gate structure 21 and the second gate structure 22, reducing the possibility of peeling off the second insulating material layer 400 formed on the sidewalls of the first gate structure 21 and the second gate structure 22, which helps to improve product yield.

[0145] like Figure 12As shown, a photoresist layer 8 can be formed on the surface of the second insulating material layer 400. The orthogonal projection of the photoresist layer 8 onto the substrate 1 can cover the support layer 5, the first gate structure 21, the second gate structure 22, and the orthogonal projection of the second insulating material layer 400 on the sidewalls of the first gate structure 21 and the second gate structure 22 onto the substrate 1. Anisotropic etching can be performed on the areas not covered by the photoresist layer 8 to remove the second insulating material layer 400 covering the surface of the substrate 1.

[0146] After the second insulating layer 4 is formed, the photoresist layer 8 can be ashed to remove the photoresist layer 8, thereby exposing the second insulating layer 4.

[0147] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0148] This disclosure also provides a semiconductor structure, which can be formed by the semiconductor structure formation method of any of the above embodiments, such as... Figure 8 As shown, the semiconductor structure may include a substrate 1, a first gate structure 21, a second gate structure 22, a first insulating layer 3, and a second insulating layer 4, wherein:

[0149] The substrate 1 may include a shallow trench isolation structure 11 and a first gate region 12 and a second gate region 13 separated by the shallow trench isolation structure 11. The first gate region 12 includes a first channel region and the second gate region 13 includes a second channel region.

[0150] The first gate structure 21 may be formed on the surface of the first channel region;

[0151] The second gate structure 22 may be formed on the surface of the second channel region;

[0152] The first insulating layer 3 may be formed on the top of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21.

[0153] The second insulating layer 4 may be formed on the surface of the first insulating layer 3 at the top of the first gate structure 21, the sidewall of the first gate structure 21 near the second gate structure 22, the surface of the first insulating layer 3 at the top of the second gate structure 22, and the sidewall of the second gate structure 22 near the first gate structure 21.

[0154] The semiconductor structure disclosed herein can simultaneously form the first gate structure 21 and the second gate structure 22 through a single thin film removal process. This reduces the instability of gate linewidth caused by the load effect, improves the dimensional uniformity of the gate structure, and thus improves product yield. Furthermore, in the direction parallel to the substrate 1, the two ends of the gate material layer 2 can respectively serve as the ends of the first gate structure 21 away from the second gate structure 22 and the ends of the second gate structure 22 away from the first gate structure 21. Since the size of the gate material layer 2 is much larger than the linewidth of the first gate structure 21 and the second gate structure 22, compared to gate structures with low linewidths, the larger width of the gate material layer 2 makes it easier to align its ends with the pre-set positions during the formation of the gate material layer 2. This reduces process difficulty, minimizes positional deviation, and improves product stability.

[0155] The substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1.

[0156] In one embodiment, the substrate 1 may be a silicon substrate, with a shallow trench isolation structure 11 formed therein. The shallow trench isolation structure 11 is formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structure 11 may include silicon nitride or silicon oxide, etc., and is not specifically limited thereto. The cross-sectional shape of the shallow trench isolation structure 11 can be set according to actual needs. The shallow trench isolation structure 11 can separate a plurality of gate regions on the substrate 1, and each gate region may include a first doped region and a second doped region arranged at intervals.

[0157] Substrate 1 can be an n-type substrate, and the first and second doped regions can be doped to form the source and drain, respectively. For example, both the first and second doped regions can be p-type doped to form p-type doped regions, which can form a pn junction with the n-type substrate. For example, p-type doping material can be doped into the first and second doped regions to form p-type semiconductors. The p-type doping material can be an element located in Group III of the periodic table, for example, boron, but it can also be materials of other elements, which will not be listed here.

[0158] The first doped region can be used as the source and the second doped region can be used as the drain; or, the first doped region can be used as the drain and the second doped region can be used as the source.

[0159] In one embodiment, boron ions can be implanted into the first doped region and the second doped region by ion implantation. Of course, other processes can also be used to dope the first doped region and / or the second doped region, and no special limitation is made here.

[0160] The area between the first doped region and the second doped region can be a channel region, which allows current to flow. The current in the channel region can be controlled by the voltage of the gate structure above it to achieve gate control function.

[0161] In one embodiment of this disclosure, a shallow doped region can be formed on the side of the first doped region and the second doped region near the channel region, thereby reducing the short-channel effect of the semiconductor structure.

[0162] In one exemplary embodiment of this disclosure, the gate regions on both sides of a shallow trench isolation structure 11 can be defined as a first gate region 12 and a second gate region 13, respectively, and the channel region in the first gate region 12 can be defined as a first channel region; meanwhile, the channel region in the second gate region 13 can be defined as a second channel region. In one embodiment, the first doped region, the first channel region, the second doped region of the first gate region 12, the shallow trench isolation structure 11, the first doped region, the second channel region of the second gate region 13, and the second doped region of the second gate region 13 are sequentially adjacent to each other.

[0163] The first gate structure 21 can be formed on the surface of the first gate region 12. For example, the first gate structure 21 can be located at the top of the first channel region. The first doped region and the second doped region adjacent to each other on both sides of the first channel region can serve as the source or the drain, respectively, and together with the first gate structure 21, they form a transistor structure. It should be noted that, in this process, the first doped region adjacent to the first channel region can serve as the source, and the second doped region adjacent to the first channel region can serve as the drain; or, the second doped region adjacent to the first channel region can serve as the source, and the first doped region adjacent to the first channel region can serve as the drain. No special limitation is made here.

[0164] In some embodiments, the first gate structure 21 may include a first conductive layer 210, a second conductive layer 220, and a passivation layer 230 stacked along a direction perpendicular to the substrate 1, wherein:

[0165] For example, the first conductive layer 210 may be a thin film formed on the surface of the first channel region, or it may be a coating formed on the surface of the first channel region. The form of the first conductive layer 210 is not specifically limited here. The material of the first conductive layer 210 may be polycrystalline silicon or other conductive materials, and is not specifically limited here.

[0166] The second conductive layer 220 can be a thin film formed on the side of the first conductive layer 210 facing away from the substrate 1, or it can be a coating formed on the surface of the first conductive layer 210. No particular limitation is made to the form of the second conductive layer 220. The second conductive layer 220 can be in contact with the first conductive layer 210, and its orthographic projection on the substrate 1 can coincide with the orthographic projection of the first conductive layer 210 on the substrate 1; that is, the second conductive layer 220 can be flush with the end of the first conductive layer 210. The material of the second conductive layer 220 can be tungsten or other conductive materials, which will not be listed here.

[0167] The passivation layer 230 can be a thin film formed on the side of the second conductive layer 220 opposite to the first conductive layer 210, or it can be a coating formed on the side of the second conductive layer 220 opposite to the first conductive layer 210. No particular limitation is made to the form of the passivation layer 230. The passivation layer 230 can cover the entire surface of the second conductive layer 220, that is, the orthogonal projection of the passivation layer 230 on the substrate 1 can coincide with the orthogonal projection of the second conductive layer 220 on the substrate 1, or the orthogonal projection of the second conductive layer 220 on the substrate 1 is within the orthogonal projection of the passivation layer 230 on the substrate 1. The passivation layer 230 can protect the surface of the second conductive layer 220 to prevent damage to the surface of the second conductive layer 220; at the same time, the passivation layer 230 can also serve as an insulating layer, isolating the second conductive layer 220 from other structures, preventing coupling or short circuits between the second conductive layer 220 and other structures, and improving product yield. The material of the passivation layer 230 can be an insulating material, for example, silicon nitride or other insulating materials, which will not be listed here.

[0168] The second gate structure 22 can be formed on the surface of the second gate region 13. For example, the second gate structure 22 can be located at the top of the second channel region. The first doped region and the second doped region adjacent to each other on both sides of the second channel region can serve as the source or the drain, respectively, and together with the second gate structure 22, they form a transistor structure. It should be noted that, in this process, the first doped region adjacent to the second channel region can serve as the source, and the second doped region adjacent to the second channel region can serve as the drain; or, the second doped region adjacent to the second channel region can serve as the source, and the first doped region adjacent to the second channel region can serve as the drain. No special limitation is made here.

[0169] The specific structure of the second gate structure 22 is similar to that of the first gate structure 21. For example, the second gate structure 22 may also include a first conductive layer 210, a second conductive layer 220 and a passivation layer 230 stacked and distributed along a direction perpendicular to the substrate 1. For specific details, please refer to the first gate structure 21, which will not be repeated here.

[0170] In some embodiments of this disclosure, the end positions of the first gate structure 21 near the second gate structure 22 and the end positions of the second gate structure 22 near the first gate structure 21 can be accurately located using a mask, thereby accurately defining the linewidths of the first gate structure 21 and the second gate structure 22. In one embodiment, the width of the first gate structure 21 can be equal to the width of the second gate structure 22 in a direction parallel to the substrate 1, which can improve product stability.

[0171] For example, the width of both the first gate structure 21 and the second gate structure 22 can be 20nm to 80nm. For example, its width can be 20nm, 40nm, 60nm or 80nm, and of course, it can also be other linewidths, which will not be listed here.

[0172] Preferably, the widths of the first gate structure 21 and the second gate structure 22 can both be 40nm to 60nm.

[0173] The first insulating layer 3 can be located on the top of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21. The first insulating layer 3 can provide insulation protection for the surfaces and sidewalls of the first gate structure 21 and the second gate structure 22, preventing coupling or short circuits between the first gate structure 21 and the second gate structure 22 and other surrounding structures, thereby improving product yield. At the same time, the first insulating layer 3 can also isolate the source and / or drain from the sides of the first gate structure 21 and / or the second gate structure 22 by a non-zero distance, thereby reducing the GIDL effect and reducing standby power consumption.

[0174] The first insulating layer 3 can be a single-layer film or a multi-layer film, without any particular limitation. Preferably, the first insulating layer 3 is a multi-layer structure, which may include a first isolation layer 31, a second isolation layer 32 and a third isolation layer 33 stacked sequentially. The first isolation layer 31, the second isolation layer 32 and the third isolation layer 33 can form triple protection, enhance the insulation effect, reduce the possibility of coupling between the first gate structure 21 and the second gate structure 22 and other structures, and improve product yield.

[0175] For example, a first isolation layer 31 is formed on the top surface of the first gate structure 21, the sidewall of the first gate structure 21 away from the second gate structure 22, the top surface of the second gate structure 22, and the sidewall of the second gate structure 22 away from the first gate structure 21; a second isolation layer 32 may cover the surface of the first isolation layer 31, and a third isolation layer 33 may cover the surface of the second isolation layer 32.

[0176] In one embodiment of this disclosure, the first isolation layer 31 and the third isolation layer 33 are made of the same material, while the second isolation layer 32 is made of a different material than the first isolation layer 31 and the third isolation layer 33. This different material arrangement can balance the internal stress of the device, thereby maintaining stress balance within the device. For example, the second isolation layer 32 can balance the compressive stress within the first isolation layer 31 and the third isolation layer 33; simultaneously, the first isolation layer 31 and the third isolation layer 33 can balance the tensile stress within the second isolation layer 32. For instance, the first isolation layer 31 and the third isolation layer 33 can be made of silicon nitride, and the second isolation layer 32 can be made of silicon oxide. Of course, the materials of the first isolation layer 31, the second isolation layer 32, and the third isolation layer 33 can also be other materials, which will not be listed here.

[0177] The second insulating layer 4 can cover the surface of the first insulating layer 3 on top of the first gate structure 21, the sidewall of the first gate structure 21 near the second gate structure 22, the surface of the first insulating layer 3 on top of the second gate structure 22, and the sidewall of the second gate structure 22 near the first gate structure 21. The second insulating layer 4 can provide insulation protection for the sidewall of the first gate structure 21 near the second gate structure 22 and the sidewall of the second gate structure 22 near the first gate structure 21, avoiding coupling or short circuits between the first gate structure 21 and the second gate structure 22 and other surrounding structures, thus improving product yield. At the same time, the second insulating layer 4 can also isolate the source and / or drain from the sides of the first gate structure 21 and / or the second gate structure 22 by a non-zero distance, thereby reducing the GIDL effect and further reducing standby power consumption.

[0178] The structure of the second insulating layer 4 can be the same as or different from that of the first insulating layer 3, and no special limitation is made here. For example, the second insulating layer 4 can be a single-layer film or a multi-layer film, and no special limitation is made here. Preferably, the second insulating layer 4 is a multi-layer structure, which may include a first isolation layer, a second isolation layer and a third isolation layer stacked sequentially. In order to distinguish the second insulating layer 4 from the first insulating layer 3, the first isolation layer, the second isolation layer and the third isolation layer of the second insulating layer 4 can be defined as the fourth isolation layer 41, the fifth isolation layer 42 and the sixth isolation layer 43, respectively. The fourth isolation layer 41, the fifth isolation layer 42 and the sixth isolation layer 43 can form triple protection, enhance the insulation effect, further reduce the possibility of coupling between the first gate structure 21 and the second gate structure 22 and other structures, and improve the product yield.

[0179] For example, a fourth isolation layer 41 is formed on the surface of the first insulating layer 3 on top of the first gate structure 21, on the sidewall of the first gate structure 21 near the second gate structure 22, on the surface of the first insulating layer 3 on top of the second gate structure 22, and on the sidewall of the second gate structure 22 near the first gate structure 21; a fifth isolation layer 42 may cover the surface of the fourth isolation layer 41, and a sixth isolation layer 43 may cover the surface of the fifth isolation layer 42.

[0180] In one embodiment of this disclosure, the fourth isolation layer 41 and the sixth isolation layer 43 are made of the same material, while the fifth isolation layer 42 is made of a different material than the fourth isolation layer 41 and the sixth isolation layer 43. This different material arrangement can balance the internal stress of the device, thereby maintaining stress balance within the device. For example, the fifth isolation layer 42 can balance the compressive stress within the fourth isolation layer 41 and the sixth isolation layer 43; simultaneously, the fourth isolation layer 41 and the sixth isolation layer 43 can balance the tensile stress within the fifth isolation layer 42. For instance, the fourth isolation layer 41 and the sixth isolation layer 43 can be made of silicon nitride, and the fifth isolation layer 42 can be made of silicon oxide. Of course, the materials of the fourth isolation layer 41, the fifth isolation layer 42, and the sixth isolation layer 43 can also be other materials, which will not be listed here.

[0181] A support layer 5 can be formed on the surface of the substrate 1 and can contact the first insulating layer 3 of the sidewalls of the first gate structure 21 and the second gate structure 22. During the subsequent etching of the gate material layer 2 to form the first gate structure 21 and the second gate structure 22, the support layer 5 can support the periphery of the first gate structure 21 and the second gate structure 22, preventing the gate material layer 2 from collapsing during the etching process, thus improving product yield. Furthermore, in subsequent processes, the support layer 5 can also support the first gate structure 21 and the second gate structure 22, reducing the possibility of collapse during subsequent processes, further improving product yield.

[0182] This disclosure also provides a memory, which may include the semiconductor structure described in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and the method for forming the semiconductor structure, and will not be repeated here.

[0183] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0184] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, the first gate region including a first channel region and the second gate region including a second channel region; A gate material layer is formed on the surface of the substrate. The gate material layer includes an adjacently distributed intermediate region and an edge region. The orthographic projection of the intermediate region on the substrate at least covers the region between the first channel region and the second channel region. The orthographic projection of the edge region on the substrate at least covers the first channel region and the second channel region. The orthographic projection of the gate material layer on the substrate is rectangular. The edge region includes a first edge region whose orthographic projection on the substrate coincides with the first channel region, and a second edge region whose orthographic projection on the substrate coincides with the second channel region. The gate material layer located in the middle region is removed, while the gate material layer in the edge region is retained, to form a first gate structure in the first gate region and a second gate structure in the second gate region.

2. The forming method according to claim 1, characterized in that, The forming method further includes: A first insulating layer is formed on the top of the first gate structure, on the sidewall of the first gate structure away from the second gate structure, on the top of the second gate structure, and on the sidewall of the second gate structure away from the first gate structure. A second insulating layer is formed on the surface of the first insulating layer located on top of the first gate structure, on the sidewall of the first gate structure near the second gate structure, on the surface of the first insulating layer located on top of the second gate structure, and on the sidewall of the second gate structure near the first gate structure.

3. The forming method according to claim 2, characterized in that, A first insulating layer is formed on the top of the first gate structure, the sidewall of the first gate structure away from the second gate structure, the top of the second gate structure, and the sidewall of the second gate structure away from the first gate structure, including: After forming a gate material layer on the surface of the substrate, a first insulating material layer is formed on the surface and sidewalls of the gate material layer. Before removing the gate material layer located in the intermediate region and retaining the gate material layer in the edge region, the method further includes: Remove the first insulating material layer in the middle region and retain the first insulating material layer in the edge region.

4. The forming method according to claim 3, characterized in that, Removing the first insulating material layer in the intermediate region and removing the gate material layer in the intermediate region includes: A support layer is formed on the surface of the substrate, and the support layer is in contact with the first insulating material layer located on the sidewall of the gate material layer; A mask layer is formed on the surface of the structure jointly formed by the support layer and the first insulating material layer; A photoresist layer is formed on the surface of the mask layer; The photoresist layer is exposed and developed to form a developed area, which exposes the mask layer. The mask layer is etched in the developing area to form a mask pattern that covers the first insulating material layer in the edge region and exposes the first insulating material layer in the middle region. Using the substrate as an etch stop layer and the mask layer as a mask, the first insulating material layer and the gate material layer are etched.

5. The forming method according to claim 2, characterized in that, The formation of a second insulating layer on the surface of the first insulating layer located at the top of the first gate structure, the sidewall of the first gate structure near the second gate structure, the surface of the first insulating layer located at the top of the second gate structure, and the sidewall of the second gate structure near the first gate structure includes: A second insulating material layer is formed on the surface of the structure jointly formed by the first gate structure, the second gate structure, the first insulating layer and the substrate; The second insulating material layer covering the surface of the substrate is removed, and the second insulating material layer located on the sidewall of the first gate structure and the sidewall of the second gate structure is in contact with the surface of the substrate.

6. The forming method according to claim 2, characterized in that, At least one of the first insulating layer and the second insulating layer includes a first isolation layer, a second isolation layer and a third isolation layer stacked in sequence, wherein the first isolation layer and the third isolation layer are made of the same material.

7. The forming method according to claim 1, characterized in that, The edge region also includes a third edge region and a fourth edge region that are orthographically projected onto the substrate and cover the shallow trench isolation structure, and are respectively connected between the first edge region and the second edge region, with the third edge region and the fourth edge region being spaced apart.

8. The forming method according to any one of claims 1-7, characterized in that, In a direction parallel to the substrate, the width of the first gate structure is equal to the width of the second gate structure.

9. The forming method according to any one of claims 1-7, characterized in that, The widths of both the first gate structure and the second gate structure are 20nm to 80nm.

10. A semiconductor structure, characterized in that, include: The substrate includes a shallow trench isolation structure and a first gate region and a second gate region separated by the shallow trench isolation structure, wherein the first gate region includes a first channel region and the second gate region includes a second channel region. A first gate structure is formed on the surface of the first channel region; A second gate structure is formed on the surface of the second channel region; A first insulating layer is formed on the top of the first gate structure, the sidewall of the first gate structure away from the second gate structure, the top of the second gate structure, and the sidewall of the second gate structure away from the first gate structure. The second insulating layer is formed on the surface of the first insulating layer at the top of the first gate structure, on the sidewall of the first gate structure near the second gate structure, on the surface of the first insulating layer at the top of the second gate structure, and on the sidewall of the second gate structure near the first gate structure.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A support layer is formed on the surface of the substrate and is in contact with the first insulating layer located on the sidewalls of the first gate structure and the second gate structure.

12. The semiconductor structure according to claim 10, characterized in that, At least one of the first insulating layer and the second insulating layer includes a first isolation layer, a second isolation layer and a third isolation layer stacked in sequence, wherein the first isolation layer and the third isolation layer are made of the same material.

13. The semiconductor structure according to any one of claims 10-12, characterized in that, In a direction parallel to the substrate, the width of the first gate structure is equal to the width of the second gate structure.

14. The semiconductor structure according to any one of claims 10-12, characterized in that, The widths of both the first gate structure and the second gate structure are 20nm to 80nm.

15. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 10-12.

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