Method for manufacturing sgt with low on-resistance, semiconductor device, and apparatus

Abstract

The application provides a preparation method of SGT with low on-resistance, which comprises the following steps: forming a stack layer of an interlayer dielectric layer, a first epitaxial layer and a second epitaxial layer on a substrate in sequence; forming a well region and a source region in the first epitaxial layer; forming a plurality of gate trenches, growing a first oxide layer, and the first oxide layer covers the sidewalls of all the gate trenches and the top of the second epitaxial layer; forming a gate in the gate trench; etching off all the gates in part of the gate trench, growing an inter-gate oxide layer, and the inter-gate oxide layer covers the top of the gate; forming a shielding gate in the gate trench; forming a patterned second oxide layer, which covers the top of the shielding gate; forming a third epitaxial layer, which covers the second epitaxial layer; thinning the substrate; and forming a plurality of conductive plugs in the substrate. It can be seen that the preparation method provided by the application eliminates the substrate resistance, solves the problem that the substrate resistance is difficult to eliminate, and realizes the reduction of the main on-resistance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a method for fabricating a low on-resistance SGT, a semiconductor device, and an apparatus. Background Technology

[0002] The on-resistance of SGT (split gate trench MOSFET) products is currently defined as: Rdson = Rcontact + Rsource + Rch + RA + Rmesa + Rd + Rsub, where Rdson is the on-resistance, Rcontact is the contact resistance, Rsource is the source resistance, Rch is the channel resistance, RA is the accumulation region resistance, Rmesa is the drift region resistance between trenches, Rd is the drift region resistance, and Rsub is the substrate resistance. In SGT products, the main components of the on-resistance Rdson are Rch, Rd, and Rsub.

[0003] In the existing SGT fabrication process, there are certain limitations to thinning the substrate. If the substrate is thinned too much, the wafer is prone to fragmentation. Therefore, the current mass production process is to thin it to 100um. However, when the substrate is thinned to this extent, the substrate resistance Rsub cannot be eliminated when the device is working.

[0004] Therefore, how to reduce the increase in the on-resistance Rdson of SGT caused by the substrate resistance Rsub has become a key technical issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0005] This invention provides a method for fabricating a low on-resistance SGT, a semiconductor device, and an apparatus to solve the problem of difficult-to-eliminate substrate resistance.

[0006] According to a first aspect of the present invention, a method for fabricating a low on-resistance SGT is provided, comprising:

[0007] A substrate is provided on which a stacked layer of an interlayer dielectric layer, a first epitaxial layer and a second epitaxial layer are sequentially formed; wherein a well region and a source region are formed in the first epitaxial layer;

[0008] A plurality of gate trenches are formed, each gate trench penetrating the first epitaxial layer and the second epitaxial layer, and resting on the surface of the interlayer dielectric layer;

[0009] A first oxide layer is grown, which covers all the sidewalls of the gate trenches and the top of the second epitaxial layer;

[0010] The first polysilicon layer is deposited in all the gate trenches and etched to form the gate;

[0011] Under the protection of the first photoblocking layer, all the first polysilicon layer in part of the gate trench is etched away to remove the first photoblocking layer;

[0012] An inter-gate oxide layer is grown, the inter-gate oxide layer covering the top of the gate;

[0013] A shielding gate is formed in all gate trenches;

[0014] A patterned second oxide layer is formed, which covers the top of the shielding gate;

[0015] A third epitaxial layer is formed, which covers the second epitaxial layer and surrounds the patterned second oxide layer;

[0016] The substrate is thinned on the back side;

[0017] A plurality of conductive plugs are formed in the substrate; the conductive plugs penetrate the interlayer dielectric layer.

[0018] Optionally, forming a plurality of gate trenches specifically includes:

[0019] A patterned hard mask is formed on the second epitaxial layer, and the second epitaxial layer and the first epitaxial layer are etched using the patterned hard mask as a mask.

[0020] Remove the patterned hard mask to form the plurality of gate trenches.

[0021] Optionally, a shielding gate is formed in all the gate trenches, specifically including:

[0022] A second polysilicon layer is filled in all gate trenches;

[0023] The second polysilicon layer is CMP polished to form the shielding gate.

[0024] Optionally, forming the patterned second oxide layer specifically includes:

[0025] The second oxide layer is grown on top of the second epitaxial layer and the shielding gate;

[0026] Photoresist is coated onto the surface of the second oxide layer and patterned.

[0027] Using the patterned photoresist as a mask, the second oxide layer is etched to form the patterned second oxide layer; and the photoresist is removed.

[0028] Optionally, a plurality of conductive plugs are formed in the substrate, specifically including:

[0029] Contact holes are formed on the back side of the substrate, and the contact holes are filled with a conductive metallic material to form a plurality of the conductive plugs.

[0030] Optionally, after forming a plurality of conductive plugs in the substrate, the method further includes:

[0031] A source metal layer and a gate metal layer are formed on the back side of the substrate.

[0032] According to a second aspect of the present invention, a semiconductor device is provided, comprising:

[0033] A substrate is provided on which an interlayer dielectric layer, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer are stacked sequentially; wherein a well region and a source region are formed in the first epitaxial layer;

[0034] A plurality of gate trenches are formed in the first epitaxial layer and the second epitaxial layer. Each gate trench penetrates the first epitaxial layer and the second epitaxial layer and stops at the surface of the interlayer dielectric layer. A gate, an inter-gate oxide layer and a shielding gate are sequentially formed on the surface of the interlayer dielectric layer in all the gate trenches.

[0035] The gate trench sidewalls and top are further provided with a first oxide layer and a patterned second oxide layer, wherein the first oxide layer covers all the sidewalls of the gate trenches; the patterned second oxide layer covers the top of the shielding gate; and the third epitaxial layer covers the second epitaxial layer and surrounds the patterned second oxide layer.

[0036] A plurality of conductive plugs are formed in the substrate; the conductive plugs penetrate the interlayer dielectric layer.

[0037] According to a third aspect of the present invention, an electronic device is provided, comprising the semiconductor device described in the second aspect of the present invention.

[0038] The present invention provides a method for fabricating a low on-resistance SGT, wherein an interlayer dielectric layer, a first epitaxial layer and a second epitaxial layer are sequentially formed on a substrate; then a plurality of gate trenches are formed, each gate trench penetrating the first epitaxial layer and the second epitaxial layer and stopping at the surface of the interlayer dielectric layer; then a gate and a shielding gate are sequentially formed in the gate trenches; the substrate is back-side thinned to form a plurality of conductive plugs in the substrate.

[0039] As can be seen, in the device fabricated using the method of the present invention, the substrate is isolated from the first epitaxial layer and the second epitaxial layer by the interlayer dielectric layer, which is used to form a conductive plug without increasing the on-resistance of the device. Therefore, the technical solution provided by the present invention eliminates the substrate resistance, solves the problem of the difficulty in eliminating the substrate resistance, and achieves a reduction in the main on-resistance of the device. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic flowchart of a method for fabricating a low on-resistance SGT according to an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 1 ;

[0043] Figure 3 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 2 ;

[0044] Figure 4 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 3 ;

[0045] Figure 5 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 4 ;

[0046] Figure 6 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 5 ;

[0047] Figure 7 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 6 ;

[0048] Figure 8 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 7 ;

[0049] Figure 9 This is a schematic diagram of a device at different etching stages in one embodiment of the present invention. Figure 8 ;

[0050] Explanation of reference numerals in the attached figures:

[0051] 101-Substrate;

[0052] 102 - Interlayer dielectric layer;

[0053] 103 - Source region and sink region;

[0054] 104 - Epitaxial layer;

[0055] 105 - First oxide layer;

[0056] 106-gate;

[0057] 107 - Intergate oxide layer;

[0058] 108 - Shielding fence;

[0059] 109 - Second oxide layer;

[0060] 110 - Conductive plug. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0063] In SGT products, the main components of the on-resistance Rdson are the channel resistance Rch, the drift region resistance Rd, and the substrate resistance Rsub.

[0064] The existing manufacturing process for SGT products is as follows:

[0065] An epitaxial layer is grown on the substrate;

[0066] A hard mask layer and photoresist are sequentially deposited on a substrate. The photoresist is patterned, and the hard mask layer is etched using the patterned photoresist as a mask to form a patterned hard mask layer. The epitaxial layer is etched using the patterned hard mask layer as a mask to remove the photoresist and form a gate trench.

[0067] An oxide layer is grown on the substrate surface and in the gate trench, and then a shielding gate, an inter-gate oxide layer and a gate are sequentially formed in the gate trench.

[0068] P-type and N-type ions are implanted in the epitaxial layer around the gate to form the source and well regions;

[0069] An interlayer dielectric layer is deposited on the surface of the epitaxial layer and the top of the gate. Photoresist is coated on the surface of the interlayer dielectric layer, and the photoresist is patterned. The device is etched using the patterned photoresist as a mask to form a contact hole. After filling the contact hole with metal material, a contact hole plug is formed.

[0070] Then, the substrate is thinned on the back side. However, thinning has certain limitations. If the thinning is too excessive, the substrate wafer is prone to fragmentation. Therefore, the current mass production process is to thin it to 100um. Even if it is thinned to 100um, the substrate current cannot be eliminated when the device is working.

[0071] Based on this technical challenge, in order to reduce the increase in Rdson caused by Rsub, the inventors of this patent conducted experiments and found that: by forming the gate, the shielding gate, and the source and well regions in the epitaxial layer, while the substrate is isolated from the epitaxial layer by the interlayer dielectric layer, the top of the formed device is not provided with a substrate; while the substrate on the back side forms a conductive plug, wherein the substrate on the back side does not generate the resistance of the device.

[0072] Therefore, the device manufactured by the process of the present invention will not calculate the resistance of Sub in Rdson, thereby greatly reducing the on-resistance of the device.

[0073] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0074] Please refer to Figures 1-9 According to an embodiment of the present invention, a method for fabricating a low on-resistance SGT is provided, and the flowchart of the low on-resistance SGT fabrication method is as follows. Figure 1 As shown, the method includes:

[0075] S11: A substrate 101 is provided, on which a stacked layer of an interlayer dielectric layer 102, a first epitaxial layer and a second epitaxial layer are sequentially formed; wherein, a well region and a source region are formed in the first epitaxial layer;

[0076] S12: Form a plurality of gate trenches, each gate trench penetrating the first epitaxial layer and the second epitaxial layer, and resting on the surface of the interlayer dielectric layer 102;

[0077] S13: Grow a first oxide layer 105, which covers all the sidewalls of the gate trenches and the top of the second epitaxial layer; the first oxide layer 105 includes a gate oxide layer and a field oxide layer; the gate oxide layer is formed by the first oxide layer 105 covered by the sidewalls of the gate trenches; the field oxide layer is formed by the first oxide layer 105 covered by the top of the second epitaxial layer.

[0078] S14: A first polysilicon layer is deposited in all gate trenches and etched to form gate 106; wherein gate 106 is formed in a portion of the gate trenches, and the first polysilicon layer of the shielded gate connection region is etched away in step 15; the shielded gate connection region refers to a portion of the gate trenches, and the device after forming gate 106 is as follows: Figure 4 As shown;

[0079] S15: Under the protection of the first photoblocking layer, etch away all the first polysilicon layers in a portion of the gate trench to remove the first photoblocking layer; wherein, the gate trench from which all the first polysilicon layers have been etched away is the shielding gate connection region in step 14 above, and the device after etching away all the first polysilicon layers in a portion of the gate trench is as follows: Figure 5 As shown;

[0080] S16: Grow an inter-gate oxide layer 107, which covers the top of the gate 106; perform thermal oxidation on the device after step 15, and form an oxide layer 107 on the top of the gate 106; at the same time, further oxidize the epitaxial layer 104 covered by the first oxide layer 105.

[0081] S17: Form a shielding gate 108 in all gate trenches;

[0082] S18: Form a patterned second oxide layer that covers the top of the shielding gate 108;

[0083] S19: Form a third epitaxial layer, which covers the second epitaxial layer and surrounds the patterned second oxide layer; Step 19 specifically includes: depositing a third epitaxial layer on the second epitaxial layer, and polishing the third epitaxial layer by CMP, so that the third epitaxial layer surrounds the patterned second oxide layer;

[0084] S20: The substrate 101 is thinned on the back side to form a device as shown in the figure. Figure 8 As shown;

[0085] S21: A plurality of conductive plugs 110 are formed in the substrate 101; the conductive plugs 110 penetrate the interlayer dielectric layer 102, and the device after forming the plurality of conductive plugs 110 is as follows: Figure 9 As shown.

[0086] The device fabricated using the process of the present invention has a gate 106, a shielding gate 108, and a source and well region 103 formed in an epitaxial layer 104. The substrate 101 is separated from the epitaxial layer 104 by an interlayer dielectric layer 102. It can be seen that the top of the device formed after S21 does not have a substrate 101; while the substrate 101 on the back side forms a conductive plug 110. The substrate 101 on the back side does not generate resistance in the device. Therefore, the device fabricated using the process of the present invention eliminates the resistance caused by the substrate 101, solving the problem that substrate resistance is not easy to eliminate. As a result, the main components of the device's Rdson (on-resistance) are changed from Rch (channel resistance), Rd (drift region resistance), and Rsub (substrate resistance) to only Rch (channel resistance) and Rd (drift region resistance), thereby achieving a further reduction in the overall main on-resistance of the device.

[0087] In one embodiment, step S11 specifically includes:

[0088] S111: An interlayer dielectric layer 102 is deposited on the substrate 101; in one specific embodiment, the interlayer dielectric layer 102 is composed of oxides; of course, it should be understood that the interlayer dielectric layer 102 can also be composed of other components commonly used in the art, and the present invention is not limited thereto. Regardless of the composition, it is within the protection scope of the present invention.

[0089] S112: A first epitaxial layer is grown on the interlayer dielectric layer 102; S113: P-type and N-type ions are implanted into the first epitaxial layer to form a well region and a source region; S114: A second epitaxial layer is deposited on the first epitaxial layer to form the aforementioned stacked structure, and the device after forming the aforementioned stacked structure is as follows: Figure 2 As shown.

[0090] In one embodiment, step S12: forming a plurality of gate trenches specifically includes:

[0091] S121: A patterned hard mask is formed on the second epitaxial layer; in a specific embodiment, it can be described as: depositing a hard mask layer on the second epitaxial layer, coating a layer of photoresist on the hard mask layer, patterning the photoresist, and etching the hard mask layer with the patterned photoresist as a mask to form a patterned hard mask.

[0092] S122: Using the graphical hard mask as a mask, etch the second epitaxial layer and the first epitaxial layer;

[0093] S123: Remove the patterned hard mask to form the plurality of gate trenches. The device after forming the plurality of gate trenches is as follows: Figure 3 As shown.

[0094] In one embodiment, step S17: forming a shielding gate 108 in all gate trenches specifically includes:

[0095] S171: Fill all gate trenches with a second polysilicon layer;

[0096] S172: The second polysilicon layer is CMP polished to form the shielding gate 108;

[0097] The top of the second polysilicon layer after CMP polishing is flush with the second epitaxial layer to expose the field oxide layer;

[0098] Part of the shielding gate 108 is formed in the gate trench at the top of the inter-gate oxide layer 107, and another part of the shielding gate 108 is formed in the shielding gate connection region after step 15. The device after forming the shielding gate 108 is as follows: Figure 6 As shown;

[0099] In one embodiment, step S18: forming the patterned second oxide layer specifically includes:

[0100] S181: A second oxide layer 109 is grown on top of the second epitaxial layer and the shielding gate 108; in a specific embodiment, step 181 specifically includes: thermally oxidizing the top of the second epitaxial layer to form a new oxide layer, depositing an oxide layer on the top of the gate 106, wherein the second oxide layer 109 includes the oxide layer deposited on the top of the gate 106, the new oxide layer formed on the top of the second epitaxial layer, and the aforementioned field oxide layer;

[0101] In one specific embodiment, when the oxide layer is deposited at the top of the gate 106, an oxide layer is also deposited on the surface of the field oxide layer, so that the second oxide layer 109 includes: the oxide layer deposited at the top of the gate 106, the new oxide layer formed at the top of the second epitaxial layer, the aforementioned field oxide layer, and the oxide layer deposited on the field oxide layer.

[0102] S182: Coat the surface of the second oxide layer 109 with photoresist and pattern the photoresist;

[0103] S183: Using the patterned photoresist as a mask, etch the second oxide layer 109 to form the patterned second oxide layer; and S184: Remove the photoresist to form the device after the patterned second oxide layer is formed. Figure 7 As shown.

[0104] In one embodiment, step S21: forming a plurality of conductive plugs 110 in the substrate 101 specifically includes:

[0105] S211: A contact hole is formed in the substrate 101;

[0106] S212: and fill the contact hole with a conductive metal material to form a plurality of the conductive plugs 110;

[0107] The conductive plug 110 penetrates the interlayer dielectric layer 102 and the substrate 101. The conductive plug 110 that contacts the source region and the well region 103 does not contact the epitaxial layer 104. The conductive plug 110 that contacts the gate 106 does not contact the intergate oxide layer 107. In addition, other conductive plugs 110 are inserted into the shielding gate 108.

[0108] In one embodiment, after forming a plurality of conductive plugs 110 in the substrate 101, the method further includes:

[0109] S22: A source metal layer and a gate metal layer are formed on the back side of the substrate 101.

[0110] According to another embodiment of the present invention, a semiconductor device is provided, such as... Figure 9 As shown, the device includes:

[0111] Substrate 101, on which an interlayer dielectric layer 102, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer are stacked sequentially; wherein, a well region and a source region are formed in the first epitaxial layer;

[0112] A plurality of gate trenches are formed in the first epitaxial layer and the second epitaxial layer, each gate trench penetrating the first epitaxial layer and the second epitaxial layer and resting on the surface of the interlayer dielectric layer 102;

[0113] A gate 106, an inter-gate oxide layer 107, and a shielding gate 108 are sequentially formed on the surface of the interlayer dielectric layer 102 in all the gate trenches;

[0114] A first oxide layer 105 and a patterned second oxide layer are formed on the sidewalls and top of several gate trenches. The first oxide layer 105 covers all the sidewalls of the gate trenches. The patterned second oxide layer covers the top of the shielding gate 108. The third epitaxial layer covers the second epitaxial layer and surrounds the patterned second oxide layer.

[0115] A plurality of conductive plugs 110 are formed in the substrate 101; the conductive plugs 110 penetrate the interlayer dielectric layer 102.

[0116] According to other embodiments of the present invention, an electronic device is provided, including the semiconductor device described in the foregoing embodiments of the present invention.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a low on-resistance SGT, characterized in that, include: A substrate is provided, on which a stacked layer of an interlayer dielectric layer, a first epitaxial layer and a second epitaxial layer are sequentially formed; wherein a well region and a source region are formed in the first epitaxial layer; A plurality of gate trenches are formed, each gate trench penetrating the first epitaxial layer and the second epitaxial layer, and stopping at the surface of the interlayer dielectric layer; A first oxide layer is grown, which covers all the sidewalls of the gate trenches and the top of the second epitaxial layer; The first polysilicon layer is deposited in all the gate trenches and then etched to form the gate. Under the protection of the first photoblocking layer, all the first polysilicon layers in part of the gate trench are etched away to remove the first photoblocking layer; An inter-gate oxide layer is grown, the inter-gate oxide layer covering the top of the gate; A shielding gate is formed in all gate trenches; A patterned second oxide layer is formed, which covers the top of the shielding gate; A third epitaxial layer is formed, which covers the second epitaxial layer and surrounds the patterned second oxide layer; The substrate is thinned on the back side; A plurality of conductive plugs are formed from the back side of the substrate; the conductive plugs penetrate the substrate and the interlayer dielectric layer.

2. The method for fabricating a low on-resistance SGT according to claim 1, characterized in that, The formation of several gate trenches specifically includes: A patterned hard mask is formed on the second epitaxial layer, and the second epitaxial layer and the first epitaxial layer are etched using the patterned hard mask as a mask. Remove the patterned hard mask to form the plurality of gate trenches.

3. The method for fabricating a low on-resistance SGT according to claim 2, characterized in that, A shielding gate is formed in all the gate trenches, specifically including: A second polysilicon layer is filled in all gate trenches; The second polysilicon layer is CMP polished to form the shielding gate.

4. The method for fabricating a low on-resistance SGT according to claim 3, characterized in that, The formation of the patterned second oxide layer specifically includes: The second oxide layer is grown on top of the second epitaxial layer and the shielding gate; Photoresist is coated onto the surface of the second oxide layer and patterned. Using the patterned photoresist as a mask, the second oxide layer is etched to form the patterned second oxide layer; and the photoresist is removed.

5. The method for fabricating a low on-resistance SGT according to claim 4, characterized in that, A plurality of conductive plugs are formed in the substrate, specifically including: Contact holes are formed on the back side of the substrate, and the contact holes are filled with a conductive metallic material to form a plurality of the conductive plugs.

6. The method for fabricating a low on-resistance SGT according to claim 5, characterized in that, After forming a plurality of conductive plugs in the substrate, the method further includes: A source metal layer and a gate metal layer are formed on the back side of the substrate.

7. A semiconductor device, characterized in that, include: A substrate on which an interlayer dielectric layer, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer are stacked sequentially; wherein a well region and a source region are formed in the first epitaxial layer; A plurality of gate trenches are formed in the first epitaxial layer and the second epitaxial layer, each gate trench penetrating the first epitaxial layer and the second epitaxial layer and stopping at the surface of the interlayer dielectric layer; A portion of the gate trenches in a plurality of gate trenches are shielded gate connection regions. On the surface of the interlayer dielectric layer in all the gate trenches of the non-shielded gate connection regions, a gate, an inter-gate oxide layer and a shielded gate are sequentially formed. A shielded gate is also formed in the shielded gate connection region. The gate trench sidewalls and top are further provided with a first oxide layer and a patterned second oxide layer, wherein the first oxide layer covers all the sidewalls of the gate trenches; the patterned second oxide layer covers the top of the shielding gate; and the third epitaxial layer covers the second epitaxial layer and surrounds the patterned second oxide layer. A plurality of conductive plugs are formed from the back side of the substrate; the conductive plugs penetrate the substrate and the interlayer dielectric layer.

8. An electronic device, characterized in that, Includes the semiconductor device as described in claim 7.

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