Semiconductor device, integrated chip and method for providing electrostatic discharge protection thereof

Abstract

The ESD protection device protects a circuit from the effects of a TLP (Transient Voltage Pulse) between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP trigger device. The first terminal is connected to the p-type doped emitter and n-type doped base of the PNP trigger device, and also to the n-type doped emitter of the NPN discharge structure. The second terminal is connected to the n-type doped collector of the NPN discharge structure. The p-type doped collector of the PNP trigger device is connected to the p-type doped base of the NPN discharge structure. The TLP pulse causes base-collector junction breakdown in the PNP trigger device, resulting in current flowing through the PNP trigger device. This current is injected into the base of the NPN discharge structure, resulting in a larger discharge current flowing through the NPN discharge structure. This device provides a high holding voltage ESD protection device with a quick revving. Embodiments of this application provide semiconductor devices, integrated chips, and methods for providing electrostatic discharge protection thereto.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices, integrated chips, and methods for providing electrostatic discharge protection for them. Background Technology

[0002] Electrostatic discharge (ESD) protection devices are needed to protect integrated circuits. The protection challenges are particularly pronounced for BCD (Bipolar-CMOS-DMOS) technology. BCD technology combines multiple process technologies to provide multiple functions on a single integrated chip. These technologies include bipolar technology for analog functions, complementary metal-oxide-semiconductor (CMOS) technology for digital functions, and double-diffused metal-oxide-semiconductor (DMOS) technology for power and high-voltage devices. The resulting integrated chip has both high-voltage and low-voltage regions. Coupled with continuously shrinking critical dimensions, these combinations lead to a reduction in the electrically safe operating area (e-SOA). The ESD protection window (the area within which ESD protection must operate to avoid interfering with normal device operation while preventing device damage) is similarly compressed. Summary of the Invention

[0003] An embodiment of this application provides a device comprising: an integrated chip having a first terminal, a second terminal, a semiconductor substrate, and an electrostatic discharge (ESD) protection device, the ESD protection device including an NPN discharge structure and a PNP triggering device; wherein, the NPN discharge structure includes an n-type doped emitter, a p-type doped base, and an n-type doped collector, each of which is formed in the semiconductor substrate; the PNP triggering device includes a p-type doped emitter, an n-type doped base, and a p-type doped collector, each of which is formed in the semiconductor substrate; the first terminal is connected to the p-type doped emitter via a first connection, to the n-type doped base via a second connection, and to the n-type doped emitter via a third connection; the second terminal is connected to the n-type doped collector via a fourth connection; the p-type doped collector is connected to the p-type doped base via a fifth connection; and the first connection, the second connection, the third connection, the fourth connection, and the fifth connection respectively include a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor formed outside the semiconductor substrate.

[0004] Embodiments of this application provide an integrated chip, including: a semiconductor substrate, including a first terminal, a second terminal, and an electrostatic discharge (ESD) protection device connected between the first terminal and the second terminal, the ESD protection device including an NPN discharge structure activated by a PNP trigger device; wherein, the NPN discharge structure and the PNP trigger device are formed in the semiconductor substrate; the NPN discharge structure includes a first n-type doped region and a second n-type doped region separated by p-type doped regions; the PNP trigger device includes a first p-type doped region and a second p-type doped region separated by n-type doped regions; the first p-type doped region of the PNP trigger device is connected to the p-type doped region of the NPN discharge structure through a metal interconnect structure disposed above the semiconductor substrate.

[0005] Embodiments of this application also provide a method for providing electrostatic discharge protection for an integrated chip, the method comprising: providing an NPN bipolar junction transistor in a semiconductor substrate, the NPN bipolar junction transistor including an n-type doped emitter, a p-type doped base, and an n-type doped collector; providing a PNP bipolar junction transistor in the semiconductor substrate, the PNP bipolar junction transistor including a p-type doped emitter, an n-type doped base, and a p-type doped collector; and connecting an anode to the p-type doped emitter and the n-type doped base. The PNP bipolar junction transistor is connected to the n-type doped emitter; the cathode is connected to the n-type doped collector; the p-type doped collector is connected to the p-type doped base; the positive voltage pulse applied between the anode and the cathode is discharged by causing breakdown in the junction between the n-type doped base and the p-type doped collector, thereby turning on the PNP bipolar junction transistor; and the NPN bipolar junction transistor is turned on by injecting current from the PNP bipolar junction transistor into the p-type doped base.

[0006] Embodiments of this application provide ESD protection devices with high holding voltage and rapid return PNP control. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a graph showing the voltage variation of an ESD protection device with current and its relationship with e-SOA according to some aspects of this teaching;

[0009] Figure 2This is a partial cross-sectional view of an integrated circuit including an ESD protection device according to some embodiments of the present invention;

[0010] Figure 2A It shows Figure 2 A plan view of the ESD protection device;

[0011] Figure 3 This is a flowchart illustrating the operation of an ESD protection device according to some embodiments of the present invention, and a method for modifying the device to adjust the holding voltage;

[0012] Figures 4A-4D It shows in Figure 2 Various current paths appearing in ESD protection devices;

[0013] Figures 5-14 A series of cross-sectional views are provided illustrating a method for manufacturing an ESD protection device according to the present invention. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] While PNP-based ESD protection devices are suitable for providing high-voltage circuit protection in devices utilizing BCD technology, conventional devices either require a large area or need to limit the gate-to-source voltage difference V at the circuit's operating point. GS The problem and the solution provided by this invention are... Figure 1 The current-voltage curve is shown. Figure 1 Including curves 101A-101C, which show the three different V values. GS The current of a transistor operating at level V varies with the drain-source voltage V. DS The changes in current, and curves 103, 105, and 107, represent the changes in current relative to voltage for three different ESD protection devices. Curves 101A-101C terminate at the voltage at which device failure occurs. With V... GS As V increases, the current at saturation (the flattening point of curve 101A-101C) increases, and the voltage at the point of device failure decreases. GS The increase in both of these factors will make ESD protection increasingly difficult.

[0017] Curve 103 represents the voltage variation with current under transmission line pulse (TLP) influence in a conventional PNP-based ESD protection device. The current through a conventional PNP-based ESD protection device only increases with increasing applied voltage. The increased slope prevents curve 103 from intersecting with curves 101B or 101C. This means that at the lower V values ​​of curve 101A… GS At the lower level, rather than at the higher V in curves 101B-101C. GS When operating at a low voltage level, the device corresponding to curve 103 protects the circuit. Curve 105 is for another conventional PNP-based ESD protection device, where the current increases more rapidly with voltage. The device of curve 105 can operate at any voltage level within curves 101A-101C. GS Circuits operating at low voltage levels provide protection, but require a larger area for integrated chips.

[0018] Some aspects of the present invention relate to an integrated chip with an ESD protection device, which in V GSThe system protects high-voltage circuits from voltage pulses between the first and second terminals over a wide voltage range, requiring only a relatively small area. The integrated chip may include a semiconductor substrate with high-voltage and low-voltage regions. The ESD protection device includes an NPN discharge structure and a PNP trigger device, both formed in the semiconductor substrate. The NPN discharge structure includes an n-type doped emitter, a p-type doped base, and an n-type doped collector. The PNP trigger device includes a p-type doped emitter, an n-type doped base, and a p-type doped collector. A first terminal is connected to the p-type doped emitter and n-type doped base of the PNP trigger device. The first terminal is also connected to the n-type doped emitter of the NPN discharge structure. A second terminal is connected to the n-type doped collector of the NPN discharge structure. The p-type doped collector of the PNP trigger device is connected to the p-type doped base of the NPN discharge structure. A TLP causes the base-collector junction in the PNP trigger device to break down, resulting in current flowing through the PNP trigger device. This current is injected into the base of the NPN discharge structure, causing a larger discharge current to flow through the NPN discharge structure. This device combines the advantages of PNP-based ESD protection devices, including high threshold voltage, low leakage current, and resistance to accidental triggering, with the quick-return characteristics of NPN-based ESD protection devices. Overall performance is determined by... Figure 1 Curve 107 is shown. As shown in curve 107, the quick-return characteristic extends the protected V value of the circuit. GS Range. This coverage is achieved without requiring a device area that is almost identical to that required by traditional PNP-based ESD protection devices.

[0019] The base of the NPN discharge structure is floating relative to the first and second terminals. In this context, floating means there is no direct connection between the base and either the first or second terminal. In some embodiments, the p-type doped base is connected only to the p-type doped collector of the PNP trigger device. In some embodiments, the p-type doped base is electrically isolated from the first terminal via an n-type doped emitter and from the second terminal via an n-type doped collector. This configuration allows the NPN discharge structure to be activated only by the PNP trigger device. The base of the PNP trigger device is connected to the first terminal via a relatively high resistance path. In some embodiments, this path includes a buried n-type doped layer.

[0020] NPN discharge structures can be used to regulate the discharge rate and provide the desired holding voltage V. h The holding voltage is the lowest voltage caused by the shunt during discharge (see [reference]). Figure 1 The holding voltage can be adjusted to a minimum value, but this is subject to the constraint of preventing accidental ESD discharge devices from being triggered during normal circuit operation. This constraint is typically V. h >1.1*VDD V DD This is the power supply voltage of the circuit. In some embodiments, V is adjusted by controlling the width of the base of the NPN discharge structure. h As a result of this choice, the width of the base of the NPN discharge structure can differ from the width of its collector, its emitter, or any component of the PNP trigger device.

[0021] The discharge mechanism described above applies to positive voltage pulses. In some embodiments, the ESD protection device may provide a PN junction diode for discharging negative voltage pulses. In some embodiments, the p-type doped side of the PN junction diode is connected to a second terminal and is different from the p-type doped region of the NPN discharge structure and the PNP trigger device. In some embodiments, the n-type doped side of the PN junction overlaps with the n-type doped emitter of the NPN discharge structure. In some embodiments, the n-type doped side of the PN junction overlaps with the n-type doped base of the PNP trigger device. In some embodiments, a first portion of the n-type doped side of the PN junction overlaps with the n-type doped emitter of the NPN discharge structure, while a second portion of the n-type doped side of the PN junction overlaps with the n-type doped base of the PNP trigger device. This sharing provides a compact design. Moreover, the first portion of the n-type doped side of the PN junction provides junction isolation between the p-type doped side of the PN junction (which is connected to the cathode) and the p-type doped base of the PNP trigger device (which is floating).

[0022] Some aspects of this teaching relate to a method for providing electrostatic discharge protection for an integrated chip. The method includes configuring an NPN bipolar junction transistor (BJT) and a PNP bipolar junction transistor (PNP BJT) such that a sufficiently large positive pulse applied between the anode and cathode causes breakdown in the junction between the base and collector of the PNP BJT, turning the transistor on and providing current injected into the base of the NPN BJT. The pulse is then discharged through the NPN BJT. In some embodiments, the method further includes selecting the width of the base of the NPN BJT to control the holding voltage. In some embodiments, the method further includes discharging a negative pulse through a PN diode having contacts connected to the anode and cathode.

[0023] Figure 2An integrated chip 200 having a semiconductor substrate 275 and an ESD protection device 210 is shown according to some aspects of this teaching. The semiconductor substrate 275 may have a high-voltage device region (not shown) and a low-voltage device region (not shown). The integrated chip 200 may also include: an anode 230, which is a first terminal; a cathode 222, which is a second terminal; and optionally, a third terminal 205, which is connected to the semiconductor substrate 275 and can be used to ground the conductor substrate 275. During normal operation, the anode 230 may have a higher voltage than the cathode 222, but the terms anode and cathode are not intended to imply any further limiting meaning. A metal interconnect structure 236 forms connections between the anode 230, the cathode 222, the third terminal 205, and various structures formed in the semiconductor substrate 275.

[0024] ESD protection device 210 includes a PNP trigger device 227, an NPN discharge structure 209, and a PN diode 215. The PNP trigger device 227 includes a p-type doped emitter 242, an n-type doped base 245, and a p-type doped collector 247. The NPN discharge structure 209 includes an n-type doped emitter 258, a p-type doped base 265, and an n-type doped collector 269. The PN diode 215 includes a p-type doped region 255 and an n-type doped region 252. The n-type doped region 252 includes portions of the n-type doped emitter 258 and the n-type doped base 245.

[0025] In some embodiments, the p-type doped region 255 of the PN diode 215 is disposed between the PNP trigger device 227 and the NPN discharge structure 209, occupying different regions of the semiconductor substrate 275. The p-type doped region 255 may include a heavily p-type doped contact region 225, a shallow p-type well 254, and a high-voltage p-type well 257. The n-type doped region 252 may include a heavily n-type doped contact region 226, a shallow n-type well 251, and a high-voltage n-type well 253. The n-type doped region 252 may also include a heavily n-type doped contact region 219, a shallow n-type well 259, and a high-voltage n-type well 261. The heavily n-type doped contact region 206, the shallow n-type well 274, the high-voltage n-type well 272, and the buried n-type layer 273 may provide additional portions of the n-type doped region 252.

[0026] Each of the PNP trigger device 227 and the NPN discharge structure 209 is a bipolar junction transistor (BJT) with three terminals provided by heavily p-type doped (P+) and heavily n-type doped (N+) contact regions. For the PNP trigger device 227, the heavily p-type doped contact region 233 forms the emitter terminal, the heavily n-type doped contact region 226 forms the base terminal, and the heavily p-type doped contact region 229 forms the collector terminal. The heavily n-type doped region 252 also serves as a terminal for the PN diode 215. Optionally, the heavily p-type doped contact region 235 forms a second emitter terminal, and the heavily p-type doped contact region 234 forms a second collector terminal.

[0027] The p-type doped emitter 242 may extend together with the heavily p-type doped contact regions 233 and 235. The p-type doped collector 247 includes a heavily p-type doped contact region 229, a shallow p-type well 249, and a high-voltage p-type well 250. The n-type doped base 245 includes a heavily n-type doped contact region 226, a shallow n-type well 251, a high-voltage n-type well 253, a buried n-type layer 273, and a high-voltage n-type well 243. The base-collector junction 246 of the PNP trigger device 227 is formed at the interface between the high-voltage n-type well 243 and the high-voltage p-type well 250.

[0028] The p-type doped collector 247 may further include a heavily p-type doped contact region 234, a shallow p-type well 239, and a high-voltage p-type well 241. The n-type doped base 245 may further include a high-voltage n-type well 238. Accordingly, the PNP trigger device 227 may further include a second base-collector junction 240 formed between the high-voltage n-type well 238 and the high-voltage p-type well 241, and a third base-collector junction 237 formed between the high-voltage n-type well 238 and the high-voltage p-type well 241.

[0029] For the NPN discharge structure 209, the heavily n-type doped contact region 219 forms the emitter terminal, the heavily p-type doped contact region 217 forms the base terminal, and the heavily n-type doped contact region 213 forms the collector terminal. The heavily n-type doped region 213 also serves as a terminal for the PN diode 215. Optionally, the heavily n-type doped contact region 206 forms the second emitter terminal, and the heavily p-type doped contact region 207 forms the second base terminal.

[0030] The n-type doped emitter 258 includes a heavily n-type doped contact region 219, a shallow n-type well 259, and a high-voltage n-type well 261. The p-type doped base 265 includes a heavily p-type doped contact region 229, a shallow p-type well 263, and a high-voltage p-type well 262. The n-type doped collector 269 includes a heavily n-type doped contact region 213, a shallow n-type well 267, and a high-voltage n-type well 268. The n-type doped collector 269 is isolated from the buried n-type layer 273 by a deep p-type well 266.

[0031] The n-type doped emitter 258 may further include a heavily n-type doped contact region 206, a shallow n-type well 274, and a high-voltage n-type well 272. The p-type doped base 265 may further include a heavily p-type doped contact region 207, a shallow p-type well 271, and a high-voltage p-type well 270. The NPN discharge structure 209 has a base width 264, which is the distance between the high-voltage n-type well 261 and the high-voltage n-type well 268, and also the distance between the high-voltage n-type well 268 and the high-voltage n-type well 272. Different portions of the p-type doped base 265, such as the high-voltage p-type well 262 and the high-voltage p-type well 270, may be different or may be continuous. In some embodiments, it may be formed in a ring around the n-type doped collector 269. Similarly, different portions of the n-type doped emitter 258, such as the high-voltage n-type well 261 and the high-voltage n-type well 272, may be different or may be continuous, and in some embodiments, a ring may be formed around the n-type doped emitter 258 and the p-type doped base 265.

[0032] Figure 2A An exemplary plan view of the ESD protection device 210 is shown. As illustrated in this example, in some embodiments, an NPN discharge structure 209 surrounds a PNP trigger device 227. In some embodiments, the NPN discharge structure 209 also surrounds a PN diode 215. In some embodiments, the PN diode 215 surrounds the PNP trigger device 227. In some embodiments, an n-type doped region 252 connected to an n-type doped base 245 surrounds other elements of the PNP trigger device 227, which includes a p-type doped emitter 242 and a p-type doped collector 247. These surrounding elements may be described as a ring structure. In some embodiments, the p-type doped emitter 242 and the p-type doped collector 247 are strip-shaped rather than ring-shaped. In some embodiments, the p-type doped emitter 242 is provided by a plurality of fingers, each having the same area. In some embodiments, the p-type doped collector 247 is provided by a plurality of fingers, each having the same area. In some embodiments, each of the p-type doped emitter 242 and the p-type doped collector 247 includes three or more fingers.

[0033] The dopant concentration in the n-type doped emitter 258 decreases from the heavily n-type doped contact region 219 to the base-emitter interface 220 of the NPN discharge structure 209. Similarly, the dopant concentration in the n-type doped collector 269 decreases from the heavily n-type doped contact region 213 to the base-collector interface 211 of the NPN discharge structure 209. Both the base-emitter interface 220 and the base-collector interface 211 are formed through interfaces between high-voltage wells and provide a large area for conduction.

[0034] Anode 230 is connected via connector 223 to the heavily n-type doped contact region 226 of the n-type doped base 245, via connector 231 to the p-type doped emitter 242, and via connector 218 to the n-type doped emitter 258, all of which are formed within metal interconnect structure 236. Metal interconnect structure 236 also includes a connector 216 between the p-type doped collector 247 and the n-type doped emitter 258. Cathode 222 is connected via connector 214 to the n-type doped collector 269. Third terminal 205 can be connected via connector 203 to the heavily p-type doped contact region 202. The heavily p-type doped contact region 202 is connected to the semiconductor substrate 275, which is lightly p-type doped, and can be used to ground the semiconductor substrate 275.

[0035] Semiconductor substrate 275 may include a semiconductor body such as a die cut from a single-crystal semiconductor wafer, a silicon-on-insulator (SOI) structure, or any other type of semiconductor body. The semiconductor may be silicon, or another semiconductor material such as SiGe and / or other Group III, IV, and / or V elements, combinations thereof. In some embodiments, semiconductor substrate 275 includes semiconductor body 276 and an epitaxial layer 277 grown on semiconductor body 276. A buried n-type layer 273 may be formed in semiconductor body 276. A deep p-type well 266 may be formed above the buried n-type layer 273 and may be positioned within epitaxial layer 277, within semiconductor body 276, or overlapping with epitaxial layer 277 and semiconductor body 276.

[0036] Heavily n-type doped contact regions 206, 213, 219, and 226 are isolated from heavily p-type doped contact regions 202, 207, 217, 225, and 229 via a shallow trench isolation (STI) structure 201. Heavily p-type doped contact regions 229, 233, 234, and 235 are junction isolated. The junction may be covered by a resist-protected oxide 232. These different isolation structures reflect the greater isolation requirements of the NPN discharge structure 209 compared to the PNP trigger device 227; however, any suitable type of isolation structure can be used in either device. Junction isolation makes the PNP trigger device 227 more compact. The junction isolation provided by the high-voltage n-type well 261 is also used to isolate the floating p-type doped base 265 from the p-type doped region 255, which is the side of the PN diode 215 connected to the cathode 222.

[0037] Figure 3 A flowchart illustrating method 300 is provided, through which ESD protection device 210 operates. Most actions of method 300 can be passively implemented by ESD protection device 210; however, method 300 also includes a group 321 of actions that can be implemented through iterative design processes. Although method 300 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted in a limiting sense. For example, some actions may occur simultaneously with other actions. Furthermore, implementing some aspects or embodiments of the invention does not require all the actions shown in method 300.

[0038] Method 300 begins with action 301, in which the ESD protection device 210 is idle in a state ready for an ESD event. When an ESD event occurs, the ESD protection device 210 responds. According to action 303, if the ESD event is a negative voltage pulse, the ESD protection device 210 responds according to action 323, discharging the negative voltage pulse through a current 401 flowing from the cathode 222 to the anode 230 and selected by the PN diode 215. Figure 4A As shown. Note that current 401 has an alternative path through high-voltage n-type well 261 and another alternative path through high-voltage n-type well 272. These alternative current paths will be recognized by those skilled in the art, and therefore are not elaborated upon to make the figures and related descriptions easier to understand; this practice is reflected in the subsequent description of positive voltage pulse discharge.

[0039] According to action 305, if the ESD event is a positive voltage pulse exceeding a certain threshold, the ESD protection device 210 responds according to action 307. If neither condition is met, the ESD protection device 210 remains inactive and continues to idle in action 301. Action 307 conducts current 403 from the positive voltage pulse to the n-type doped base 245 of the PNP trigger device 227, as... Figure 4B As shown. The current 403, acting as an avalanche current, causes breakdown at the base-collector junction 246 between the n-type doped base 245 and the p-type doped collector 247, generating electrons and holes, and forward biasing the junction 405 between the p-type doped emitter 242 and the n-type doped base 245. This turns on the bipolar junction transistor implemented by the PNP trigger device 227 and generates... Figure 4C The current shown is 407.

[0040] Action 309 conducts current 407 to the p-type doped base 265 of the NPN discharge structure 209. The path of current 403 may include connectors 216 formed within the metal interconnect structure 236. Current 407 discharges from the p-type doped base 265 to the n-type doped collector 269, and turns on the NPN discharge structure 209, thereby generating... Figure 4D The current 409 is shown. Current 409 flows from anode 230 to cathode 222 through NPN discharge structure 209. Action 311 causes a positive voltage pulse discharge through current 409.

[0041] Figure 1 Curve 107 illustrates the relationship between current and voltage across ESD protection device 210 during a positive voltage pulse discharge. As current increases, voltage increases through the holding voltage V. h The minimum value is indicated. Action group 321 indicates that the ESD protection device 210 can be modified to adjust the process of holding voltage. These actions can be performed by building and testing successive versions of the ESD protection device 210, by numerical simulation of the ESD protection device 210, or by a combination of the foregoing.

[0042] Action 313 determines whether the holding voltage is higher than the target range, in which case the safe operating area of ​​the electricity is smaller than its possible range. If the holding voltage is too high, then in action 315 the base width 264 of the NPN discharge structure 209 is reduced. Action 317 determines whether the holding voltage is lower than the target range, in which case the risk of latch-up is considered too high. If the holding voltage is too low, then in action 319 the base width 264 of the NPN discharge structure 209 is increased. Thus, the base width 264 can be adjusted until the holding voltage is within the target range.

[0043] The target range depends on the high voltage V used for the integrated chip 200. DD In some embodiments, V DD 18V or higher. In some embodiments, V DD It is 24V. In some embodiments, the target holding voltage is about 1.1 times the holding voltage, for example, about 26.4V. In some embodiments, the target range for the holding voltage places the holding voltage within 1V of the target holding voltage. In some embodiments, the target range for the holding voltage places the holding voltage within 0.5V of the target holding voltage.

[0044] The base width 264, which provides the desired holding voltage, can be determined based on factors including the most significant V. DD The base width 264 varies due to various factors, including 1 μm to 100 μm. In some embodiments, the base width 264 is in the range of 2 μm to 50 μm. In some embodiments, the base width 264 is in the range of 4 μm to 25 μm. In some embodiments, the base width 264 is in the range of 5 μm to 12 μm.

[0045] Figures 5-14 A series of cross-sectional views 500-1400 are provided, illustrating an integrated chip including an ESD protection device according to the invention at various stages of manufacturing using the process according to the invention. Although Figures 5 to 14 The description relates to a series of actions; however, it should be understood that in some cases the order of the actions can be changed, and the series of actions can be applied to structures other than those illustrated. In some embodiments, some of these actions may be omitted, either entirely or partially. Furthermore, it should be understood that... Figures 5-14 The structure shown is not limited to the manufacturing method, but can exist independently of the method.

[0046] As by Figure 5 As shown in cross-sectional view 500, the process can begin with the formation of a photoresist mask 501 and the implantation of an n-type dopant to form a buried n-type layer 273 near the surface of the semiconductor body 276. The n-type dopant can be phosphorus, antimony, arsenic, or combinations thereof. After ion implantation, the photoresist mask 501 can be stripped. Alternatively, the buried n-type layer 273 can be formed by diffusing an n-type dopant into the semiconductor body 276. The semiconductor body 276 can be lightly p-type doped, or it can have another suitable dopant.

[0047] As by Figure 6 As shown in the cross-sectional view 600, the epitaxial layer 277 can be formed by... Figure 5The epitaxial layer 277 is grown over the structure shown in cross-sectional view 500. The epitaxial layer 277 can be grown together with a p-type dopant at a concentration suitable for a high-voltage p-type well. The p-type dopant can be boron, indium, etc. In some embodiments, the concentration of the p-type dopant is 10... 14 / cm 3 Up to 10 17 / cm 3 Within the range. Alternatively, the epitaxial layer 277 can be undoped or n-type doped, and ion implantation can be used in subsequent steps to form a high-voltage p-type well.

[0048] As by Figure 7 As shown in the cross-sectional view 700, the photoresist mask 703 can be formed on the surface of the photoresist mask. Figure 6 The structure shown in the cross-sectional view 600 is placed above the structure, and an n-type dopant is implanted to form a high-voltage n-type well 701. In some embodiments, the high-voltage n-type well 701 has a concentration of 10 14 / cm 3 Up to 10 17 / cm 3 n-type dopants within the range.

[0049] As by Figure 8 As shown in the cross-sectional view 800, a photoresist mask 801 can be formed, and a p-type dopant can be implanted at high energy to form a deep p-type well 266. Alternatively, the deep p-type well 266 can be formed by diffusing the p-type dopant into the semiconductor body 276 prior to forming the epitaxial layer 277. In some embodiments, the concentration of the p-type dopant in the deep p-type well 266 is 10. 15 / cm 3 Up to 10 18 / cm 3 Within the range.

[0050] As by Figure 9 As shown in cross-sectional view 900, the STI structure 201 can be formed in the epitaxial layer 277. Forming the STI structure 201 may include steps such as: forming a mask, etching trenches in the epitaxial layer 277, filling the trenches with a dielectric, and performing chemical mechanical polishing. The dielectric can be SiO2, high-density plasma (HDP) oxide, or any other suitable dielectric. An isolation structure can also be formed by oxidizing portions of the epitaxial layer 277. The STI structure 201 can be formed earlier or later in this process.

[0051] As by Figure 10As shown in cross-sectional view 1000, a photoresist mask 1003 can be formed, and n-type dopant can be implanted to form a shallow n-type well 1001. In some embodiments, this implantation also provides source / drain regions (not shown) in a low-voltage region of the integrated chip 200. In some embodiments, the concentration of n-type dopant in the shallow n-type well 1001 is 10. 15 / cm 3 Up to 10 18 / cm 3 Within the range.

[0052] As by Figure 11 As shown in the cross-sectional view 1100, a photoresist mask 1103 can be formed, and an n-type dopant can be implanted to form a shallow p-type well 1101. In some embodiments, the concentration of the p-type dopant in the shallow p-type well 1101 is 10. 15 / cm 3 Up to 10 18 / cm 3 Within the range.

[0053] As by Figure 12 As shown in cross-sectional view 1200, a resist protective oxide layer 232 can be formed and patterned on the surface of the oxide layer. Figure 11 Above the structure shown in cross-sectional view 1100. Alternatively, the resist protective oxide layer 232 can be formed earlier in this process. The resist protective oxide layer 232 can be silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SION), any other suitable dielectric, etc.

[0054] As by Figure 13 As shown in the cross-sectional view 1300, a photoresist mask 1303 can be formed, and an n-type dopant can be implanted at low energy to form a heavily n-type doped contact 1301. In some embodiments, the concentration of the n-type dopant in the heavily n-type doped contact 1301 is 10. 20 / cm 3 Or even larger.

[0055] As by Figure 14 As shown in the cross-sectional view 1400, a photoresist mask 1403 can be formed, and p-type dopant can be implanted at low energy to form a heavily p-type doped contact 1301. In some embodiments, the concentration of p-type dopant in the heavily p-type doped contact 1401 exceeds 10. 20 / cm 3 Further processing, including forming the metal interconnect structure 236 in the online back-end (BEOL) process, can produce... Figure 2 The integrated chip 200.

[0056] Some embodiments of the present invention relate to an integrated chip having a first terminal, a second terminal, and a semiconductor substrate. Logic devices may be formed on a first region of the semiconductor substrate, while high-voltage devices may be formed on a second region of the semiconductor substrate. The integrated chip includes an electrostatic discharge (ESD) protection device having an NPN discharge structure and a PNP trigger device. The NPN discharge structure includes an n-type doped emitter, a p-type doped base, and an n-type doped collector, each of which is formed in the semiconductor substrate. The PNP trigger device includes a p-type doped emitter, an n-type doped base, and a p-type doped collector, each of which is formed in the semiconductor substrate. The first terminal is connected to the p-type doped emitter via a first connection, to the n-type doped base via a second connection, and to the n-type doped emitter via a third connection. The second terminal is connected to the n-type doped collector via a fourth connection. The p-type doped collector is connected to the p-type doped base via a fifth connection. The first connection, second connection, third connection, fourth connection, and fifth connection each include a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor formed outside the semiconductor substrate. In some embodiments, except relative to the fifth connection, the p-type doped base is floating. In some embodiments, the second connection from the first terminal to the n-type doped base passes through a buried n-type doped layer within the semiconductor substrate.

[0057] Some embodiments of the present invention relate to an integrated chip having a first terminal, a second terminal, and an electrostatic discharge (ESD) protection device connected between the first and second terminals. The ESD protection device includes an NPN discharge structure activated by a PNP trigger device. The NPN discharge structure and the PNP trigger device are formed in a semiconductor substrate. The NPN discharge structure includes a first n-type doped region and a second n-type doped region spaced apart by p-type doped regions. The PNP trigger device includes a first p-type doped region and a second p-type doped region spaced apart by n-type doped regions. The first p-type doped region of the PNP trigger device is connected to the p-type doped region of the NPN discharge structure via a metal interconnect structure disposed above the semiconductor substrate. In some embodiments, the ESD protection device further includes a PN diode formed in the semiconductor substrate. A first electrode of the PN diode is connected to the first terminal, and a second electrode of the PN diode is connected to the second terminal.

[0058] Some embodiments of the present invention relate to a method for providing electrostatic discharge protection for an integrated chip. The method includes: providing an NPN bipolar junction transistor (BJT) in a semiconductor substrate, the BJT having an n-type doped emitter, a p-type doped base, and an n-type doped collector; and providing a PNP bipolar junction transistor (PNP) in the semiconductor substrate, the PNP BJT having a p-type doped emitter, an n-type doped base, and a p-type doped collector. An anode is connected to the p-type doped emitter, the n-type doped base, and the n-type doped emitter. A cathode is connected to the n-type doped collector. The p-type doped collector is connected to the p-type doped base. According to the method, a positive voltage pulse applied between the anode and cathode is discharged by causing breakdown in the junction between the n-type doped base and the p-type doped collector, thereby turning on the PNP BJT, and then turning on the NPN BJT by injecting current from the PNP BJT into the p-type doped base. In some embodiments, the method further includes discharging a negative voltage pulse applied between the anode and cathode via a PN diode formed in a semiconductor substrate.

[0059] Some embodiments of the present invention relate to a method for adjusting the holding voltage in an electrostatic discharge device according to the present teachings. The method includes increasing the width of the p-type doped base to increase the holding voltage; and decreasing the width of the p-type doped base to decrease the holding voltage.

[0060] An embodiment of this application provides a device comprising: an integrated chip having a first terminal, a second terminal, a semiconductor substrate, and an electrostatic discharge (ESD) protection device, the ESD protection device including an NPN discharge structure and a PNP triggering device; wherein, the NPN discharge structure includes an n-type doped emitter, a p-type doped base, and an n-type doped collector, each of which is formed in the semiconductor substrate; the PNP triggering device includes a p-type doped emitter, an n-type doped base, and a p-type doped collector, each of which is formed in the semiconductor substrate; the first terminal is connected to the p-type doped emitter via a first connection, to the n-type doped base via a second connection, and to the n-type doped emitter via a third connection; the second terminal is connected to the n-type doped collector via a fourth connection; the p-type doped collector is connected to the p-type doped base via a fifth connection; and the first connection, the second connection, the third connection, the fourth connection, and the fifth connection respectively include a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor formed outside the semiconductor substrate. In some embodiments, the first connection, the second connection, the third connection, the fourth connection, and the fifth connection each include a portion of a metal interconnect structure for the integrated chip. In some embodiments, the ESD protection device is configured such that a sufficiently large positive pulse applied between the first terminal and the second terminal can cause junction breakdown between the n-type doped base and the p-type doped collector, resulting in a first current flowing from the n-type doped base to the p-type doped collector, which in turn causes a second current to flow from the p-type doped emitter to the p-type doped collector to the p-type doped base, and discharges through the n-type doped collector, which in turn causes a third current to flow from the n-type doped emitter to the n-type doped collector. In some embodiments, the p-type doped base is floating relative to the first terminal and the second terminal. In some embodiments, the p-type doped base is isolated from the first terminal via the n-type doped emitter; and the p-type doped base is isolated from the second terminal via the n-type doped collector. In some embodiments, the holding voltage for the ESD protection device is determined by the width of the p-type doped base. In some embodiments, the p-type doped emitter includes a heavily p-type doped contact region that forms a junction with the n-type doped base.In some embodiments, the n-type doped emitter includes a first heavily n-type doped contact region connected to the first terminal; the n-type doped collector includes a second heavily n-type doped contact region connected to the second terminal; the n-type doped emitter located at a first junction with the p-type doped base has a lower N-type doping than the first heavily n-type doped contact region; and the n-type doped collector located at a second junction with the p-type doped base has a lower N-type doping than the second heavily n-type doped contact region. In some embodiments, the second connection from the first terminal to the n-type doped base includes a buried n-type doped layer located within the semiconductor substrate. In some embodiments, the NPN discharge structure and the PNP trigger device occupy different regions of the semiconductor substrate. In some embodiments, a PN diode is further included, formed in the semiconductor substrate; wherein the PN diode includes an n-type doped region connected to the first terminal and a p-type doped region connected to the second terminal; and the n-type doped region provides junction isolation between the second terminal and the p-type doped base. In some embodiments, the ESD protection device is configured such that a sufficiently large negative pulse applied between the first terminal and the second terminal discharges through the PN diode. In some embodiments, the n-type doped region overlaps with the n-type doped base. In some embodiments, the n-type doped region overlaps with the n-type doped emitter.

[0061] Embodiments of this application provide an integrated chip, including: a semiconductor substrate, including a first terminal, a second terminal, and an electrostatic discharge (ESD) protection device connected between the first terminal and the second terminal, the ESD protection device including an NPN discharge structure activated by a PNP trigger device; wherein the NPN discharge structure and the PNP trigger device are formed in the semiconductor substrate; the NPN discharge structure includes a first n-type doped region and a second n-type doped region separated by p-type doped regions; the PNP trigger device includes a first p-type doped region and a second p-type doped region separated by n-type doped regions; the first p-type doped region of the PNP trigger device is connected to the p-type doped region of the NPN discharge structure through a metal interconnect structure disposed above the semiconductor substrate. In some embodiments, it further includes: a PN diode formed in the semiconductor substrate; wherein a first electrode of the PN diode is connected to the first terminal; and a second electrode of the PN diode is connected to the second terminal. In some embodiments, the n-type doped region of the PN diode overlaps with the n-type doped region of the PNP trigger device and the first n-type doped region of the NPN discharge structure.

[0062] Embodiments of this application also provide a method for providing electrostatic discharge protection for an integrated chip, the method comprising: providing an NPN bipolar junction transistor in a semiconductor substrate, the NPN bipolar junction transistor including an n-type doped emitter, a p-type doped base, and an n-type doped collector; providing a PNP bipolar junction transistor in the semiconductor substrate, the PNP bipolar junction transistor including a p-type doped emitter, an n-type doped base, and a p-type doped collector; and connecting an anode to the p-type doped emitter and the n-type doped base. The PNP bipolar junction transistor (BJT) is configured to conduct by: connecting the p-type doped emitter to the n-type doped collector; connecting the p-type doped collector to the p-type doped base; discharging the positive voltage pulse applied between the anode and the cathode by causing breakdown in the junction between the n-type doped base and the p-type doped collector; and turning on the NPN bipolar junction transistor by injecting current from the PNP BJT into the p-type doped base. In some embodiments, the BJT further includes: discharging the negative voltage pulse applied between the anode and the cathode using a PN diode formed in the semiconductor substrate. In some embodiments, the BJT further includes: controlling the holding voltage for discharging the positive voltage pulse by selecting the width of the p-type doped base.

[0063] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: An integrated chip has a first terminal, a second terminal, a semiconductor substrate, and an electrostatic discharge protection device, wherein the electrostatic discharge protection device includes an NPN discharge structure and a PNP triggering device; The NPN discharge structure includes an n-type doped emitter, a p-type doped base, and an n-type doped collector, each of which is formed in the semiconductor substrate. The PNP trigger device includes a p-type doped emitter, an n-type doped base, and a p-type doped collector, each of which is formed in the semiconductor substrate. The first terminal is connected to the p-type doped emitter via a first connection, to the n-type doped base via a second connection, and to the n-type doped emitter via a third connection; The second terminal is connected to the n-type doped collector via a fourth connection; The p-type doped collector is connected to the p-type doped base via a fifth connection; and The first connection, the second connection, the third connection, the fourth connection, and the fifth connection each include a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor formed outside the semiconductor substrate.

2. The semiconductor device of claim 1, wherein, The first connection, the second connection, the third connection, the fourth connection, and the fifth connection each include a portion of a metal interconnect structure for the integrated chip.

3. The semiconductor device of claim 1, wherein, The electrostatic discharge protection device is configured such that a sufficiently large positive pulse applied between the first terminal and the second terminal can cause junction breakdown between the n-type doped base and the p-type doped collector, resulting in a first current flowing from the n-type doped base to the p-type doped collector, which in turn causes a second current flowing from the p-type doped emitter to the p-type doped collector to be conducted to the p-type doped base and discharged through the n-type doped collector, which in turn causes a third current flowing from the n-type doped emitter to the n-type doped collector.

4. The semiconductor device of claim 1, wherein, The p-type doped base is floated relative to the first terminal and the second terminal.

5. The semiconductor device according to claim 1, wherein: The p-type doped base is isolated from the first terminal through the n-type doped emitter; and The p-type doped base is isolated from the second terminal through the n-type doped collector.

6. The semiconductor device of claim 1, wherein, The holding voltage for the electrostatic discharge protection device is determined by the width of the p-type doped base.

7. The semiconductor device of claim 1, wherein, The p-type doped emitter includes a heavily p-type doped contact region that forms a junction with the n-type doped base.

8. The semiconductor device according to claim 1, wherein: The n-type doped emitter includes a first heavily n-type doped contact region connected to the first terminal; The n-type doped collector includes a second heavily n-type doped contact region connected to the second terminal; The n-type doped emitter located at the first junction with the p-type doped base has a lower N-type doping than the contact region of the first heavily n-type doped base. and The n-type doped collector located at the second junction with the p-type doped base has a lower N-type doping than the contact region of the second heavily n-type doped base.

9. The semiconductor device of claim 1, wherein, The second connection from the first terminal to the n-type doped base includes a buried n-type doped layer located within the semiconductor substrate.

10. The semiconductor device according to claim 1, wherein, The NPN discharge structure and the PNP triggering device occupy different regions of the semiconductor substrate.

11. The semiconductor device according to claim 1, further comprising: A PN diode is formed in the semiconductor substrate; The PN diode includes an n-type doped region connected to the first terminal and a p-type doped region connected to the second terminal; and The n-type doped region provides junction isolation between the second terminal and the p-type doped base.

12. The semiconductor device according to claim 11, wherein, The electrostatic discharge protection device is configured such that a sufficiently large negative pulse applied between the first terminal and the second terminal discharges through the PN diode.

13. The semiconductor device according to claim 11, wherein, The n-type doped region overlaps with the n-type doped base.

14. The semiconductor device according to claim 11, wherein, The n-type doped region overlaps with the n-type doped emitter.

15. An integrated chip, comprising: A semiconductor substrate includes a first terminal, a second terminal, and an electrostatic discharge protection device connected between the first terminal and the second terminal, the electrostatic discharge protection device including an NPN discharge structure activated by a PNP triggering device; The NPN discharge structure and the PNP triggering device are formed in the semiconductor substrate; The NPN discharge structure includes a first n-type doped region and a second n-type doped region separated by a p-type doped region; The PNP triggering device includes a first p-type doped region and a second p-type doped region separated by an n-type doped region. A metal interconnect structure is disposed above the semiconductor substrate, wherein the metal interconnect structure couples the following structures: The first terminal is coupled to the first n-type doped region of the NPN discharge structure; The second terminal is coupled to the second n-type doped region of the NPN discharge structure; Couple the p-type doped region of the NPN discharge structure to the first p-type doped region of the PNP trigger device; and The second terminal is coupled to the n-type doped region and the second p-type doped region of the PNP trigger device.

16. The integrated chip according to claim 15, further comprising: A PN diode is formed in the semiconductor substrate; Wherein, the p-type doped region of the PN diode is connected to the first terminal; and The n-type doped region of the PN diode is connected to the second terminal.

17. The integrated chip according to claim 16, wherein, The n-type doped region of the PN diode overlaps with the n-type doped region of the PNP trigger device and the first n-type doped region of the NPN discharge structure.

18. A method for providing electrostatic discharge protection for an integrated chip, the method comprising: An NPN bipolar junction transistor is provided in a semiconductor substrate, the NPN bipolar junction transistor including an n-type doped emitter, a p-type doped base, and an n-type doped collector; A PNP bipolar junction transistor is provided in the semiconductor substrate, the PNP bipolar junction transistor including a p-type doped emitter, an n-type doped base, and a p-type doped collector; The anode is connected to the p-type doped emitter, the n-type doped base, and the n-type doped emitter; Connect the cathode to the n-type doped collector; Connect the p-type doped collector to the p-type doped base; The positive voltage pulse applied between the anode and the cathode is discharged by causing breakdown in the junction between the n-type doped base and the p-type doped collector, thereby turning on the PNP bipolar junction transistor; and The NPN bipolar junction transistor is turned on by injecting current from the PNP bipolar junction transistor into the p-type doped base.

19. The method of claim 18, further comprising: A negative voltage pulse discharge is applied between the anode and the cathode by a PN diode formed in the semiconductor substrate.

20. The method of claim 18, further comprising: The holding voltage for discharging the positive voltage pulse is controlled by selecting the width of the base used for the p-type doping.

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