IC carrier for chip packaging and preparation method thereof and chip packaging structure

Abstract

The present invention discloses an IC carrier for chip packaging, a preparation method thereof and a chip packaging structure. The IC carrier includes a frame circuit and a carrier board, the frame circuit includes a plurality of unit circuits arranged in a matrix, a first resin layer and a second resin layer, the unit circuit includes a plurality of electrodes, the electrodes include a top electrode and a bottom electrode, the top electrode and the first resin layer are arranged on the top surface of the second resin layer; the first resin layer includes a top electrode hole corresponding to the top electrode, the top electrode is arranged in the top electrode hole; the second resin layer includes a bottom electrode hole corresponding to the bottom electrode, the bottom electrode is arranged in the bottom electrode hole; the top surface of the top electrode includes a weldable metal layer, the weldable metal layer on the top surface of the top electrode is an alkali corrosion resistant metal layer; the top of the bottom electrode is fixed on the bottom surface of the top electrode, and the carrier board is peelably attached to the bottom surface of the second resin layer and the bottom electrode. The manufacturing process of the top electrode and the bottom electrode of the present invention can be identified by the same alignment reference point, and the inter-layer alignment accuracy is high.

Description

[Technical field]

[0001] The invention relates to chip packaging, and in particular to an IC carrier board used for chip packaging, a preparation method thereof, and a chip packaging structure. [Background Technology]

[0002] The conventional peelable packaging substrate is a substrate in which a frame circuit is manufactured on a metal carrier sheet. The frame circuit includes a plurality of unit circuits arranged in a matrix. After the chip packaging is completed, the metal carrier sheet is peeled off.

[0003] The invention with application number CN202110162067.5 discloses a lead frame for chip packaging and a preparation method. The lead frame includes a frame circuit and a carrier board, the frame circuit includes a plurality of unit circuits arranged in a matrix and a first solder resist ink layer, the unit circuit includes a plurality of electrodes, the electrodes include a top electrode and a bottom electrode; the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer includes a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the carrier board includes a thermosetting adhesive layer, and the thermosetting adhesive layer is removably attached to the first solder resist ink layer and the bottom surface of the bottom electrode.

[0004] The top electrode and bottom electrode of the lead frame (IC carrier) of the invention are made according to the double-sided alignment method. The bottom electrode is made on the first solder resist ink layer of the carrier sheet. After the bottom electrode is completed, the carrier sheet is pasted on the bottom electrode and the first solder resist ink layer. After the carrier sheet is peeled off, it is turned over and the top electrode is made on the other side of the bottom electrode and the first solder resist ink layer. The lead frame and preparation method of the invention require repeated alignment of the reference holes, and the alignment deviation between the top electrode and the bottom electrode is large. [Summary of the invention]

[0005] The technical problem to be solved by the present invention is to provide an IC carrier with high inter-layer alignment accuracy.

[0006] Another technical problem to be solved by the present invention is to provide a method for preparing an IC carrier with high inter-layer alignment accuracy.

[0007] Another technical problem to be solved by the present invention is to provide a chip packaging structure with high inter-layer alignment accuracy of a lead frame.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is an IC carrier for chip packaging, including a frame circuit and a second carrier, the frame circuit includes a plurality of unit circuits arranged in a matrix, a first resin layer and a second resin layer, the unit circuit includes a plurality of electrodes, the electrodes include a top electrode and a bottom electrode, the top electrode and the first resin layer are arranged on the top surface of the second resin layer; corresponding to each unit circuit, the first resin layer includes a top electrode hole corresponding to the top electrode, and the top electrode is arranged in the top electrode hole; the second resin layer includes a bottom electrode hole corresponding to the bottom electrode, and the bottom electrode is arranged in the bottom electrode hole; the top surface of the top electrode includes a solderable metal layer, and the solderable metal layer on the top surface of the top electrode is an alkali-resistant metal layer; the top of the bottom electrode is fixed on the bottom surface of the top electrode, and the second carrier is removably adhered to the second resin layer and the bottom surface of the bottom electrode.

[0009] In the IC carrier described above, the lateral size of the top electrode is larger than the lateral size of the bottom electrode, the projection area of ​​the bottom electrode is contained within the projection area of ​​the top electrode, the second carrier includes an adhesive layer, and the adhesive layer is releasably adhered to the second resin layer and the bottom surface of the bottom electrode; the alkali corrosion-resistant metal layer on the top surface of the top electrode is a nickel-plated layer, a tin-plated layer, a silver-plated layer or a composite coating of at least two of nickel, tin and silver.

[0010] The IC carrier described above, the unit circuit includes a base island, the base island includes an upper base island and a lower base island, the first resin layer includes an upper base island hole corresponding to the upper base island, the second resin layer includes a lower base island hole corresponding to the lower base island; the upper base island is arranged in the upper base island hole, and the lower base island is arranged in the lower base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; the second carrier plate is removably attached to the bottom surfaces of the second resin layer, the lower base island and the bottom electrode; the top surface of the upper base island includes a solderable metal layer, and the solderable metal layer on the top surface of the upper base island is an alkali-resistant metal layer; the lateral size of the upper base island is larger than the lateral size of the lower base island, and the projection area of ​​the lower base island is contained within the projection area of ​​the upper base island.

[0011] A method for preparing the above IC substrate comprises the following steps:

[0012] 401) covering the copper foil on the bottom surface of the first carrier board with a first resin layer;

[0013] 402) forming a plurality of top electrode holes on the first resin layer corresponding to each unit circuit by photolithography or laser drilling;

[0014] 403) plating an alkali corrosion resistant metal layer in the top electrode hole and then plating copper to form a top electrode;

[0015] 404) covering the bottom surface of the first resin layer and the top electrode with a second resin layer;

[0016] 405) forming a plurality of bottom electrode holes on the second resin layer corresponding to each unit circuit by photolithography or laser drilling;

[0017] 406) copper is plated in the bottom electrode hole, and then a solderable metal layer is plated to form a bottom electrode;

[0018] 407) releasably bonding a second carrier plate to the bottom surface of the second resin layer and the bottom electrode;

[0019] 408) peeling off the first carrier board to expose the copper foil;

[0020] 409) Alkaline etching method to remove copper foil.

[0021] The above-mentioned preparation method comprises the following steps:

[0022] 501) In step 401, the first carrier plate is a metal plate, and the copper foil on the bottom surface of the first carrier plate is formed by electroplating on the metal plate;

[0023] 502) In step 403, before plating the alkali corrosion-resistant metal layer, the copper foil in the top electrode hole is etched, and the etching depth of the copper foil is 1 μm to 8 μm;

[0024] 503) In step 407, the bonding force between the bonding layer on the second carrier plate and the second resin layer and the bottom electrode is 100-500 gf / cm.

[0025] A chip packaging structure comprises a carrier and a packaging body, the packaging body comprises a semiconductor chip and a packaging adhesive layer, the carrier comprises a substrate and a unit circuit arranged on the substrate, the unit circuit comprises a plurality of electrodes, the electrodes comprise a top electrode and a bottom electrode, the substrate comprises a first resin layer and a second resin layer, the top electrode and the first resin layer are arranged on the top surface of the second resin layer; the first resin layer comprises a top electrode hole corresponding to the top electrode, the top electrode is arranged in the top electrode hole, the top surface of the top electrode comprises a solderable metal layer, the solderable metal layer on the top surface of the top electrode is an alkali corrosion resistant metal layer; the second resin layer comprises a bottom electrode hole corresponding to the bottom electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode.

[0026] In the chip packaging structure described above, the semiconductor chip is a flip chip, and the electrodes of the flip chip are respectively welded to the weldable metal layer of the corresponding top electrode.

[0027] In the chip packaging structure described above, the semiconductor chip is a face-up chip, which is fixed on a carrier board, and the electrodes of the face-up chip are respectively welded to the weldable metal layer of the corresponding top electrode through bonding wires.

[0028] In the chip packaging structure described above, the unit circuit includes a base island, the base island includes an upper base island and a lower base island, the first resin layer includes an upper base island hole corresponding to the upper base island, and the second resin layer includes a lower base island hole corresponding to the lower base island; the upper base island is arranged in the upper base island hole, and the lower base island is arranged in the lower base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; the top surface of the upper base island includes a solderable metal layer, and the solderable metal layer on the top surface of the upper base island is an alkali-resistant metal layer; the upright chip is fixed on the solderable metal layer on the top surface of the upper base island.

[0029] The manufacturing process of the top electrode and the bottom electrode of the present invention can be identified by the same alignment reference point, and the inter-layer alignment accuracy is high. [Drawings]

[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] Figure 1 It is a schematic diagram of step 1 of the method for preparing a chip packaging carrier according to Example 1 of the present invention.

[0032] Figure 2 It is a schematic diagram of step 2 of the method for preparing a chip packaging carrier according to embodiment 1 of the present invention.

[0033] Figure 3 It is a schematic diagram of step 3 of the method for preparing a chip packaging carrier according to embodiment 1 of the present invention.

[0034] Figure 4 It is a schematic diagram of step 4 of the method for preparing a chip packaging carrier according to Example 1 of the present invention.

[0035] Figure 5 It is a schematic diagram of step 5 of the method for preparing a chip packaging carrier according to Example 1 of the present invention.

[0036] Figure 6 It is a schematic diagram of step 6 of the method for preparing a chip packaging carrier according to Example 1 of the present invention.

[0037] Figure 7 It is a schematic diagram of step 7 of the method for preparing a chip packaging carrier according to Example 1 of the present invention.

[0038] Figure 8 It is a schematic diagram of step 8 of the method for preparing a chip packaging carrier according to Example 1 of the present invention.

[0039] Fig. 9 It is a schematic diagram of step 9 of the method for preparing a chip packaging carrier according to embodiment 1 of the present invention.

[0040] Fig.10 It is a schematic diagram of step 10 of the method for preparing a chip packaging carrier according to embodiment 1 of the present invention.

[0041] Fig.11It is a schematic diagram of a unit of a chip packaging carrier according to Embodiment 1 of the present invention.

[0042] Fig.12 It is a schematic diagram of the chip packaging structure of embodiment 2 of the present invention.

[0043] Fig.13 It is a schematic diagram of a unit of a chip packaging carrier according to embodiment 3 of the present invention.

[0044] Fig.14 It is a schematic diagram of the chip packaging structure of embodiment 4 of the present invention. [Specific implementation method]

[0045] Embodiment 1 of the present invention: The structure of one unit of the IC carrier is as follows Fig.11 As shown, the IC carrier includes a frame circuit and a second carrier board 20, and the frame circuit includes a plurality of unit circuits arranged in a matrix ( Fig.11 Only one unit circuit is shown), the first solder resist ink layer 3 and the second solder resist ink layer 7. Each unit circuit has two electrodes, each electrode includes a top electrode 11 and a bottom electrode 12, and the top electrode 11 and the first solder resist ink layer 3 are arranged on the top surface of the second solder resist ink layer 7. Corresponding to each unit circuit, the first solder resist ink layer 3 has two top electrode holes 31 corresponding to the top electrode 11, and the top electrode 11 is arranged in the top electrode hole 31 on the first solder resist ink layer 3. The top surface of the top electrode 11 is plated with a solderable metal layer 111, and the solderable metal layer 111 is an alkali-resistant metal layer, and the top surface of the solderable metal layer 111 is higher than the first solder resist ink layer 3. The second solder resist ink layer 7 has two bottom electrode holes 71 corresponding to the bottom electrode 12, and the bottom electrode 12 is arranged in the bottom electrode hole 71 of the second solder resist ink layer 7. The top of the bottom electrode 12 is fixed to the bottom surface of the top electrode 11 by electroplating, the bottom surface of the bottom electrode 12 is plated with a solderable metal layer 121, and the second carrier plate 20 is removably adhered to the bottom surface of the second solder resist ink layer 7 and the bottom electrode solderable metal layer 121 through an adhesive layer.

[0046] The bottom electrode 12 is formed by electroplating on the bottom surface of the top electrode 11 , so the lateral dimension of the top electrode 11 is larger than the lateral dimension of the bottom electrode 12 , that is, the projection area of ​​the bottom electrode 12 is included in the projection area of ​​the top electrode 11 .

[0047] The resin layer of the above embodiment 1 uses photosensitive ink, and the corresponding electrode holes are made by photolithography; if the resin layer uses non-photosensitive ink, the corresponding electrode holes can be made by laser drilling.

[0048] Embodiment 1 of the present invention provides a method for preparing an IC substrate, comprising the following steps:

[0049] 1) If Figure 1As shown, photosensitive ink is printed on the copper foil 1 on the bottom surface of the first carrier plate 10 to form a first solder resist ink layer 3. The first carrier plate 10 is a metal plate, which can be a metal plate such as stainless steel, aluminum alloy, etc. that can be plated with metal foil, and the metal foil can be easily peeled off the carrier plate. The copper foil 1 on the bottom surface of the first carrier plate 10 is formed by electroplating on the metal plate, and the stainless steel plate is controlled by pre-treatment of the stainless steel to achieve the effect of direct peeling of the stainless steel plate and the copper foil 1.

[0050] 2) If Figure 2 As shown, two top electrode holes 31 are photoetched on the first solder resist ink layer 3 corresponding to each unit circuit.

[0051] 3) If Figure 3 As shown, the bottom surface of the copper foil 1 in the top electrode hole 31 is etched to a depth of 1 μm to 8 μm.

[0052] 4) If Figure 4 As shown, a solderable metal layer (alkali-resistant metal layer) 111 is plated in the top electrode hole 31, and the thickness of the solderable metal layer (alkali-resistant metal layer) 111 is equal to or less than the depth of etching the bottom surface of the copper foil 1. The alkali-resistant metal layer can be a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite layer of at least two of nickel, tin, and silver. For example, the first metal layer 111 is plated first, and the first metal layer 111 can be a tin-plated layer, a silver-plated layer, or a gold-plated layer; and the second and third metal layers are electroplated on the bottom surface of the first metal layer 111, so that their thickness is equivalent to the first solder resist ink layer 3. The first, second, and third metal layers can be the same metal or different metals.

[0053] 5) If Figure 5 As shown, copper is plated on the basis of the solderable metal layer 111 in the top electrode hole 31 to form the top electrode 11.

[0054] 6) If Figure 6 As shown, photosensitive ink is printed on the bottom surface of the first solder resist ink layer 3 and the top electrode 11 to form a second solder resist ink layer 7 .

[0055] 7) If Figure 7 As shown, two bottom electrode holes 71 are photoetched on the second solder resist ink layer 7 corresponding to each unit circuit.

[0056] 8) If Figure 8 As shown, the bottom surface of the top electrode 11 is copper plated in the bottom electrode hole 71 to form a bottom electrode 12; a solderable metal layer 121 is plated outside the bottom surface of the bottom electrode 12, and the solderable metal layer 121 can be a tin-plated layer, a silver-plated layer or a gold-plated layer.

[0057] 9) If Fig. 9As shown, the second carrier plate 20 is releasably bonded to the bottom surface of the second solder resist ink layer 7 and the bottom electrode solderable metal layer 121. The bonding force between the adhesive layer on the second carrier plate 20 and the second solder resist ink layer 7 and the bottom electrode 12 is 100-500 gf / cm.

[0058] 10) As Fig.10 As shown, the first carrier board 10 is peeled off to expose the copper foil 1.

[0059] 11) If Fig.11 As shown, the copper foil 1 is removed by alkaline etching to obtain the IC carrier of Example 1 of the present invention.

[0060] The chip packaging structure of the second embodiment of the present invention is as follows Fig.12 As shown, the chip packaging structure of Example 2 is packaged using the IC carrier of Example 1. It includes a carrier 100 and a package body 200, the package body 100 includes a flip chip 8A and a packaging glue layer 9, the carrier 100 includes a substrate and a unit circuit arranged on the substrate. The unit circuit includes two electrodes, each electrode includes a top electrode 11 and a bottom electrode 12, the substrate includes a first solder resist ink layer 3 and a second solder resist ink layer 77, and the top electrode 11 and the first solder resist ink layer 3 are arranged on the top surface of the second solder resist ink layer 7. The first solder resist ink layer 3 includes a top electrode hole 31 corresponding to the top electrode 11, the top electrode 11 is arranged in the top electrode hole 31, the top surface of the top electrode 11 includes a solderable metal layer 111, and the solderable metal layer 111 on the top surface of the top electrode 11 is an alkali corrosion-resistant metal layer. The second solder resist ink layer 7 includes a bottom electrode hole 71 corresponding to the bottom electrode 12, the bottom electrode 12 is arranged in the bottom electrode hole 71, and the top of the bottom electrode 12 is fixed on the bottom surface of the top electrode 11. The two electrodes of the flip chip 8A are respectively welded to the weldable metal layer 111 of the corresponding top electrode 11 .

[0061] Embodiment 3 of the present invention: The structure of one unit of the IC carrier is as follows Fig.13 As shown, the structure of the IC carrier of Example 3 is similar to that of the IC carrier of Example 1, and the only difference is that the unit circuit includes a base island and a plurality of electrodes, the base island includes an upper base island 13 and a lower base island 14, the first solder resist ink layer 3 includes an upper base island hole 32 corresponding to the upper base island 13, and the second solder resist ink layer 7 includes a lower base island hole 72 corresponding to the lower base island 14. The upper base island 13 is arranged in the upper base island hole 32, and the lower base island 14 is arranged in the lower base island hole 72. The top of the lower base island 14 is fixed on the bottom surface of the upper base island 13. The second carrier plate 20 is removably attached to the bottom surfaces of the second solder resist ink layer 7, the lower base island 14 and the bottom electrode 12. The top surface of the upper base island 13 includes a solderable metal layer 131, and the solderable metal layer 111 on the top surface of the upper base island 13 is an alkali corrosion-resistant metal layer. The lateral dimension of the upper base island 13 is greater than that of the lower base island 14 , and the projection area of ​​the lower base island 14 is included in the projection area of ​​the upper base island 13 .

[0062] The method for preparing the IC substrate in Example 3 of the present invention is similar to the method for preparing the IC substrate in Example 1, except that:

[0063] 1) In step 2 of embodiment 1, a plurality of top electrode holes 31 are photolithographically formed on the first solder resist ink layer 3 corresponding to each unit circuit, and the upper base island 13 is photolithographically formed at the same time.

[0064] 2) In step 3 of embodiment 1, when etching the bottom surface of the copper foil 1 in the top electrode hole 31, the bottom surface of the copper foil 1 in the upper base island hole 32 is etched at the same time.

[0065] 3) In step 4 of Example 1, a solderable metal layer (alkali corrosion-resistant metal layer) 111 is plated in the top electrode hole 31, and a solderable metal layer 131 is plated in the upper base island hole 32 at the same time.

[0066] 4) In step 5 of embodiment 1, copper is plated simultaneously in the top electrode hole 31 and the upper base island hole 32 to form the top electrode 11 and the upper base island 13.

[0067] 5) In step 7 of embodiment 1, a plurality of bottom electrode holes 71 and lower base island holes 72 are photoetched on the second solder resist ink layer 7 corresponding to each unit circuit.

[0068] 6) In step 8 of Example 1, copper is plated on the bottom surfaces of the top electrode 11 and the upper base island 13 in the bottom electrode hole 71 and the lower base island hole 72 to form the bottom electrode 12 and the lower base island 14; and solderable metal layers 121 and 141 are plated on the outside of the bottom surfaces of the bottom electrode 12 and the lower base island 14.

[0069] The chip packaging structure of the fourth embodiment of the present invention is as follows Fig.12 As shown, the difference from Example 2 is only that:

[0070] 1) The IC substrate of Example 3 is used for packaging.

[0071] 2) The semiconductor chip is a front-mounted chip 8B, which is welded on the weldable metal layer 131 on the top surface of the upper base island 13, and the electrodes of the front-mounted chip 8B are welded to the weldable metal layer 111 of the corresponding top electrode 11 through bonding wires 8C.

[0072] The starting copper foil used in the existing IC carrier board manufacturing process is a copper foil material of a certain thickness, and a carrier sheet or a carrier film is attached to the starting copper foil; the bottom electrode is first made on the exposed surface of the copper foil, and the top electrode is made after peeling and transfer. The process of the above embodiment of the present invention is to make the top electrode first, then make the bottom electrode, and finally peel and transfer; the starting copper foil of the above embodiment of the present invention is directly copper-plated on stainless steel, and the roughness of the stainless steel sheet is controlled by pre-treatment to achieve the effect of direct peeling. Before making the top electrode on the copper foil in the above embodiment of the present invention, a micro-etching / etching process is added to achieve the top electrode convex point requirements; the middle resin layer of the above embodiment of the present invention can use flexible resin instead of photosensitive resin, and laser drilling can be used instead of photosensitive resin exposure and development process.

[0073] The above embodiments of the present invention have the following advantages:

[0074] 1) The top electrode and the bottom electrode are in the same direction, that is, they are both electroplated on the same side of the starting copper foil; they can be identified by the same alignment reference points, and the inter-layer alignment accuracy is high; 2) A stainless steel carrier sheet is used instead of a PET carrier film, which has good rigidity, a smaller expansion and contraction coefficient, and is easy to operate; 3) By first micro-etching / etching a pit on the copper foil and then electroplating the top electrode, the top electrode can be easily protruded from the substrate.

Claims

1. A method for preparing an IC substrate for chip packaging, characterized in that: An IC carrier for chip packaging includes a frame circuit and a second carrier board, wherein the frame circuit includes a plurality of unit circuits arranged in a matrix, the unit circuits include a plurality of electrodes, and the electrodes include a top electrode and a bottom electrode. The IC carrier board is characterized in that the frame circuit includes a first resin layer and a second resin layer, and the top electrode and the first resin layer are arranged on the top surface of the second resin layer; corresponding to each unit circuit, the first resin layer includes a top electrode hole corresponding to the top electrode, and the top electrode is arranged in the top electrode hole; the second resin layer includes a bottom electrode hole corresponding to the bottom electrode, and the bottom electrode is arranged in the bottom electrode hole; the top surface of the top electrode includes a solderable metal layer, and the solderable metal layer on the top surface of the top electrode is an alkali-resistant metal layer; the top of the bottom electrode is fixed on the bottom surface of the top electrode, and the second carrier board is peelably attached to the second resin layer and the bottom electrode on the bottom surface of the first carrier plate; the preparation method comprises the following steps: 101) covering the copper foil on the bottom surface of the first carrier plate with a first resin layer; 102) forming a plurality of top electrode holes on the first resin layer corresponding to each unit circuit by photolithography or laser drilling; 103) plating an alkali corrosion-resistant metal layer in the top electrode hole and then plating copper to form a top electrode; 104) covering the bottom surface of the first resin layer and the top electrode with a second resin layer; 105) forming a plurality of bottom electrode holes on the second resin layer corresponding to each unit circuit by photolithography or laser drilling; 106) plating copper in the bottom electrode hole and then plating a solderable metal layer to form a bottom electrode; 107) releasably bonding the second carrier plate to the bottom surface of the second resin layer and the bottom electrode; 108) peeling off the first carrier plate to expose the copper foil; 109) removing the copper foil by alkaline etching.

2. The preparation method according to claim 1, characterized in that: The lateral dimension of the top electrode is greater than that of the bottom electrode, and the projection area of ​​the bottom electrode is contained within the projection area of ​​the top electrode; the second supporting plate includes an adhesive layer, which is releasably adhered to the second resin layer and the bottom surface of the bottom electrode; the alkali-resistant metal layer on the top surface of the top electrode is a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite coating of at least two of nickel, tin and silver.

3. The preparation method according to claim 1, characterized in that: The unit circuit includes a base island, and the base island includes an upper base island and a lower base island. The first resin layer includes an upper base island hole corresponding to the upper base island, and the second resin layer includes a lower base island hole corresponding to the lower base island; the upper base island is arranged in the upper base island hole, and the lower base island is arranged in the lower base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; the second carrier plate is removably attached to the bottom surfaces of the second resin layer, the lower base island and the bottom electrode; the top surface of the upper base island includes a solderable metal layer, and the solderable metal layer on the top surface of the upper base island is an alkali-resistant metal layer; the lateral size of the upper base island is larger than the lateral size of the lower base island, and the projection area of ​​the lower base island is contained within the projection area of ​​the upper base island.

4. The preparation method according to claim 1, characterized in that: The following steps are involved: 401) In step 101, the first carrier plate is a metal plate, and the copper foil on the bottom surface of the first carrier plate is formed by electroplating on the metal plate; 402) In step 103, before plating the alkali corrosion-resistant metal layer, the copper foil in the top electrode hole is etched, and the etching depth of the copper foil is 1 μm to 8 μm; 403) In step 107, the bonding force between the bonding layer on the second carrier plate and the second resin layer and the bottom electrode is 100-500 gf / cm.

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