Clock correction method, clock data recovery circuit, chip, receiving end and terminal

Abstract

The clock correction method, clock data recovery circuit, chip, receiver, and terminal disclosed herein obtain at least two clock signals of the same frequency output by a phase interpolator; wherein the phase interpolator is configured to maintain a first phase relationship between the at least two clock signals; obtain a phase control code of the phase interpolator when a second phase relationship is formed between the at least two clock signals and a data signal; calculate a phase control code deviation value based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship; generate a target phase control code based on the phase control code deviation value, and configure the phase interpolator to correct the first phase relationship. The scheme in the embodiment disclosed herein achieves high accuracy of data recovery by the CDR circuit, small circuit area occupation, and high precision.

Description

Technical Field

[0001] One or more embodiments of the present specification relate to the field of circuit manufacturing technology, and in particular to a clock correction method, a clock data recovery circuit, a chip, a receiving end, and a terminal. Background Art

[0002] Clock Data Recovery (CDR) circuits are widely used in various high-speed serial communication scenarios, such as optical communications, board-level, and chip-level high-speed signal transmission. Their purpose is to recover a synchronized clock signal from the received data signal.

[0003] Common types of clock data recovery circuits (CDR) are based on phase-locked loops (PLLs), delay-locked loops (DLLs), or phase interpolators (PIs). Figure 1 As shown, taking the four-phase half-speed sampling CDR based on PI as an example, the four clock signals clk_i, clk_q, clk_ib, and clk_qb are used to sample and recover the input data, and the clock frequency is half the transmission frequency of the data signal (data).

[0004] Please also refer to Figure 2 .like Figure 2 As shown, clk_i and clk_q are quadrature clocks, with a 90-degree phase difference. clk_ib and clk_qb are their inverted clock signals. When the CDR is locked, the rising edges of clk_i and clk_ib align with the edges of the data signal. Their respective quadrature clock signals, clk_q and clk_qb, align with the center of the data signal. The data signal is sampled from the center to obtain more accurate data.

[0005] However, in actual situations, since the clock signals clk_i and clk_q may not be in ideal phase quadrature but may have a certain deviation, the data recovered by the CDR may be incorrect and inaccurate.

[0006] Currently, there is an analog circuit-based approach to achieve the correction of the deviation.

[0007] refer to Figure 2The scheme generates a clock signal clk_i_o by synthesizing the non-orthogonal (caused by the deviation) clock signals clk_i and clk_q (for example, phase-weighted addition as the phase of the synthesized signal), and synthesizes clk_ib, which is the inverse of clk_i, and clk_q to generate a clock signal clk_q_o, and clk_i_o and clk_q_o are orthogonal; and generates a clock signal clk_ib_o by synthesizing clk_ib, which is the inverse of the clock signal clk_i, and clk_qb, which is the inverse of clk_q, and clk_qb and clk_i to generate a clock signal clk_qb_o, and clk_ib_o and clk_qb_o are orthogonal.

[0008] However, this approach requires analog circuits to implement the aforementioned relatively complex logic calculations, which occupies a large circuit area and consumes a large amount of power. Summary of the Invention

[0009] In view of this, the purpose of one or more embodiments of this specification is to provide a clock correction method, a clock data recovery circuit, a chip, a receiving end, and a terminal.

[0010] A clock correction method is provided in an embodiment of the present disclosure, including: obtaining at least two clock signals of the same frequency output by a phase interpolator; wherein the phase interpolator is configured to maintain a first phase relationship between the at least two clock signals; obtaining a phase control code of the phase interpolator when a second phase relationship is formed between the at least two clock signals and a data signal respectively; calculating a phase control code deviation value based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship; generating a target phase control code according to the phase control code deviation value, for configuring the phase interpolator to correct the first phase relationship.

[0011] Optionally, the first phase relationship refers to maintaining a preset phase difference between clock signals.

[0012] Optionally, the first phase relationship refers to phase quadrature between clock signals.

[0013] Optionally, the second phase relationship refers to edge alignment of the clock signal and the data signal.

[0014] Optionally, the at least two clock signals include: a first clock signal and a second clock signal that maintain a first phase relationship; a third clock signal that is inverted to the first clock signal, and a fourth clock signal that is inverted to the second clock signal; the phase control code of the phase interpolator obtained when a second phase relationship is formed between the at least two clock signals and the data signal respectively is obtained when the clock signal and the data signal are configured to the same frequency.

[0015] Optionally, the at least two clock signals include a first clock signal and a second clock signal that maintain a first phase relationship; the first phase control code difference between the phase control codes based on the at least two clock signals, and the second phase control code difference corresponding to the first phase relationship, to calculate the phase control code deviation value, including: obtaining the phase control code deviation value based on the difference between the first phase control code difference and the second phase control code difference between the first clock signal and the second clock signal.

[0016] Optionally, the at least two clock signals include: a first clock signal and a second clock signal that maintain a first phase relationship; a third clock signal that is inversely phased to the first clock signal, and a fourth clock signal that is inversely phased to the second clock signal; the first phase control code difference between the phase control codes based on the at least two clock signals, and the second phase control code difference corresponding to the first phase relationship, to calculate the phase control code deviation value, including: obtaining a first difference between the first phase control code difference and the second phase control code difference of the first clock signal and the second clock signal; obtaining a second difference between the first phase control code difference and the second phase control code difference of the third clock signal and the fourth clock signal; and obtaining a phase control code deviation value based on the average of the first difference and the second difference.

[0017] Optionally, the target phase control code is generated according to the phase control code deviation value, and is used to configure the phase interpolator to correct the first phase relationship, including: correcting the first phase relationship between the first clock signal and the second clock signal output by the phase interpolator according to the target phase control code, and correcting the first phase relationship between the third clock signal and the fourth clock signal.

[0018] In an embodiment of the present disclosure, a clock data recovery circuit is provided, comprising: a phase interpolator for outputting at least two clock signals of the same frequency; wherein the phase interpolator is configured to maintain a first phase relationship between the at least two clock signals; a plurality of phase detectors coupled to the phase interpolator, for respectively obtaining a phase difference between each of the clock signals and a data signal; a selector coupled to the plurality of phase detectors, for selecting each clock signal to form a second phase relationship with the data signal, so as to respectively obtain a corresponding phase control code of the phase interpolator; an operator coupled to the selector, for calculating a phase control code deviation value based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship; and generating a target phase control code according to the phase control code deviation value, for configuring the phase interpolator to correct the first phase relationship.

[0019] Optionally, the first phase relationship refers to maintaining a preset phase difference between clock signals.

[0020] Optionally, the first phase relationship refers to phase quadrature between clock signals.

[0021] Optionally, the second phase relationship refers to edge alignment of the clock signal and the data signal.

[0022] Optionally, the at least two clock signals include: a first clock signal and a second clock signal that maintain a first phase relationship; a third clock signal that is inverted to the first clock signal, and a fourth clock signal that is inverted to the second clock signal; the phase control code of the phase interpolator obtained when a second phase relationship is formed between the at least two clock signals and the data signal respectively is obtained when the clock signal and the data signal are configured to the same frequency.

[0023] Optionally, the at least two clock signals include a first clock signal and a second clock signal that maintain a first phase relationship; the first phase control code difference between the phase control codes based on the at least two clock signals, and the second phase control code difference corresponding to the first phase relationship, to calculate the phase control code deviation value, including: obtaining the phase control code deviation value based on the difference between the first phase control code difference and the second phase control code difference between the first clock signal and the second clock signal.

[0024] Optionally, the at least two clock signals include: a first clock signal and a second clock signal that maintain a first phase relationship; a third clock signal that is inverted to the first clock signal, and a fourth clock signal that is inverted to the second clock signal; the first phase control code difference between the phase control codes based on the at least two clock signals, and the second phase control code difference corresponding to the first phase relationship, to calculate the phase control code deviation value corresponding to the phase deviation between the at least two clock signals, including: obtaining a first difference between the first phase control code difference and the second phase control code difference of the first clock signal and the second clock signal; obtaining a second difference between the first phase control code difference and the second phase control code difference of the third clock signal and the fourth clock signal; and obtaining a phase control code deviation value based on the average of the first difference and the second difference.

[0025] Optionally, the target phase control code is generated according to the phase control code deviation value, and is used to configure the phase interpolator to correct the first phase relationship, including: correcting the first phase relationship between the first clock signal and the second clock signal output by the phase interpolator according to the target phase control code, and correcting the first phase relationship between the third clock signal and the fourth clock signal.

[0026] An embodiment of the present disclosure provides a chip including the clock data recovery circuit.

[0027] An embodiment of the present disclosure provides a receiving end, comprising the clock data recovery circuit.

[0028] An embodiment of the present disclosure provides a data communication terminal, including the receiving end.

[0029] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following beneficial effects:

[0030] On the one hand, the technical solution in the embodiment of the present disclosure realizes the correction of the first phase relationship between multiple clock signals in the CDR based on the digital circuit, thereby improving the accuracy of the recovered data; and, the technical solution has simple calculation logic, small circuit area and low power consumption.

[0031] On the other hand, by using the deviation correction in the embodiment of the present disclosure, the influence of the process voltage temperature (PVT) of the circuit devices in the CDR (such as the phase interpolator, etc.) on the clock signal is reduced, so a CDR circuit with higher precision can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only one or more embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram showing the waveforms of the clock and data signals of a four-phase half-rate sampling CDR in an example is shown.

[0034] Figure 2 exhibit Figure 1 Schematic diagram of the signal synthesis of the four clock signals of the four-phase half-speed sampling CDR.

[0035] Figure 3 A flowchart illustrating a clock correction method in an embodiment of the present disclosure is shown.

[0036] Figure 4 A schematic diagram showing the waveforms of the clock signals and data signals in the four-phase full-speed sampling CDR in an embodiment of the present disclosure is shown.

[0037] Figure 5 A schematic diagram showing the structure of a CDR circuit in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0039] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of this specification should have the usual meaning understood by people with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in one or more embodiments of this specification do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0040] As described in the background art, in current clock data recovery (CDR) circuits based on phase interpolation (PI), the actual phase difference between the multiple clock signals output by the PI deviates from the ideal phase difference. For example, Figure 2 The four clock signals shown have an ideal phase difference of 90 degrees. Their ideal phases are 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively. However, due to factors such as PVT in actual circuits, there may be a deviation between the ideal phase difference and the actual phase difference. For example, Figure 2 The actual phase difference between the clock signals clk_i and clk_q may be less than 90 degrees or greater than 90 degrees.

[0041] As described in the background, analog circuits are currently used to synthesize clk_i and clk_q to generate clk_i_o, and clk_ib and clk_q to generate clk_q_o. Using the differential principle, this allows clk_i_o and clk_q_o to be orthogonal. Similarly, clk_ib and clk_qb are synthesized to generate clk_ib_o, and clk_qb and clk_i are synthesized to generate clk_qb_o, achieving orthogonality between clk_ib_o and clk_qb_o. However, implementing this logic calculation process using analog circuits consumes a large amount of circuit area and consumes high power.

[0042] In view of this, the embodiments of the present disclosure provide technical solutions to these problems.

[0043] like Figure 3 FIG2 is a flow chart showing a clock correction method according to an embodiment of the present invention. The clock correction method can be applied to a CDR circuit based on a phase interpolator.

[0044] The clock correction method is used to correct the clock signal of a phase interpolator. For example, the phase interpolator can be located in a clock data recovery (CDR) circuit, and data sampling is performed by correcting the clock signal output by the phase interpolator to obtain more accurate data.

[0045] The process of the clock correction method includes:

[0046] Step S301: Obtain at least two clock signals with the same frequency output by a phase interpolator.

[0047] The phase interpolator is configured to maintain a first phase relationship between the at least two clock signals.

[0048] In some examples, the first phase relationship refers to maintaining a preset phase difference between the clock signals, such as a 90-degree phase difference (ie, phase quadrature). Figure 2 In the embodiment, the four-phase clock signals clk_i, clk_q, clk_ib and clk_qb maintain a first phase relationship of orthogonal phases between the two clock signals clk_i and clk_q, and between clk_ib and clk_qb.

[0049] The frequencies of the at least two clock signals are the same, and a preset phase difference is maintained between them.

[0050] In some examples, when one of clk_i, clk_q, clk_ib, and clk_qb shifts in phase, the others may shift accordingly to maintain the first phase relationship.

[0051] In some examples, the phase interpolator controls the phase of the clock signal through a phase control code. Taking a 7-bit binary phase control code as an example, the accuracy that can be achieved is 2 to the power of 7, that is, 128 phase angles are achieved to measure a 360-degree phase, and the phase offset corresponding to each phase angle is 360 degrees / 128=2.8125 degrees, that is, the change from the phase control code "0000001" to "0000010" indicates that the phase of each clock signal is offset (for example, delayed in the time domain) by 2.8125 degrees. Of course, the phase control code of the phase interpolator here is only an example, and its specific number of bits can be selected according to the actual sampling accuracy requirements, but it is not limited to this.

[0052] The phase of each clock signal, clk_i, clk_q, etc., can be represented by a phase control code of a phase interpolator. The ideal phase difference between the clock signals clk_i and clk_q is 90 degrees. If they are aligned, the ideal offset difference of the phase control code should also correspond to 90 degrees. For example, 1 / 4 of the 128 phase angles is 32. However, in reality, the actual phase difference between clk_i and clk_q is not 90 degrees due to deviation.

[0053] It should be noted that although the above example uses a phase interpolator that outputs four clock signals with four phases (with a phase difference of 90 degrees between the clock signals), in other examples, a phase interpolator that outputs an even number of clock signals greater than four (such as 6, 8, 10, 12, 16, etc.) can also be used. For example, six clock signals with six phases have a phase difference of 60 degrees between the clock signals; wherein the phase of clk1 corresponds to 0 degrees (or 360 degrees), the phase of clk2 corresponds to 60 degrees, and the phase of clk3 corresponds to 120 degrees. The clock signal clk4 obtained by inverting clk1 corresponds to a phase of 180 degrees, the clock signal clk5 obtained by inverting clk2 corresponds to a phase of 240 degrees, and the clock signal clk4 obtained by inverting clk3 corresponds to a phase of 300 degrees. And so on, and the example is not limited to four phases.

[0054] Step S302: Acquire a phase control code of the phase interpolator when a second phase relationship is formed between the at least two clock signals and the data signal respectively.

[0055] In the disclosed embodiment, the difference between the ideal and actual phase control codes of the clock signals to be calibrated is used to calculate a deviated phase control code difference, which is then used to correct the first phase relationship between the clock signals. The clock signals to be calibrated are each brought into the same second phase relationship with the data signal, generating an actual phase difference that can be compared with the ideal phase difference and represented by the magnitude of the phase control code of the phase interpolator. Therefore, step S02 is required to obtain the phase control code for each clock signal when it forms the second phase relationship.

[0056] In some examples, the second phase relationship refers to edge alignment between the clock signal and the data signal, such as alignment of the rising edge of the clock signal with the leading edge of a bit in the data signal. Figure 1 The example corresponds to a four-phase half-speed CDR circuit. The frequency of the clock signal is half the frequency of the data signal. One bit in each data signal corresponds to half a clock signal period. Therefore, the rising edges of clk_i and clk_ib are aligned with the leading edges of the preceding and following bits in the data signal, respectively. The rising edges of clk_q and clk_qb are offset by 90 degrees relative to each other and aligned with the data centers of the corresponding bits in the data signal.

[0057] Since clk_ib and clk_qb are obtained by inverting clk_i and clk_q, respectively, their phase deviation is much smaller than the phase deviation between clk_i and clk_q. Therefore, we can first consider correcting the phase deviation between the I and Q clock signals (I refers to clk_i and clk_ib, and Q refers to clk_q and clk_qb). Therefore, we can make the frequency of the data signal and the clock signal the same, so that the rising edges of clk_i and clk_ib are aligned with the edges and center of the bits in the data signal, or the rising edges of clk_q and clk_qb are aligned with the edges and center of the bits in the data signal. Then, accurate data recovery can be performed using the two positive and negative phase clocks in I or Q, which is more conducive to focusing on signal correction between the I and Q clock signals.

[0058] To this end, the full-speed mode of the CDR circuit can be used to make the data signal and the clock signal have the same frequency, that is, Figure 4 shown.

[0059] like Figure 4 , which shows a waveform diagram of each clock signal and data signal in a four-phase full-speed sampling CDR in an embodiment of the present disclosure.

[0060] exist Figure 4 In this example, a second phase relationship is formed between clk_i and the data signal, exemplarily shown as edge alignment. Specifically, the rising edge of clk_i is aligned with the edge of a bit in the data signal. Since the same frequency is set, the rising edge of clk_ib is aligned with the center of the data of the corresponding bit in the data signal. Thus, CDR data sampling and subsequent data recovery can now be performed using the two positive and negative clock signals clk_i and clk_ib of the same clock.

[0061] Similarly, when the phase of clk_q is shifted to align its rising edge with the rising edge of the data signal, a second phase relationship is formed between the clk_q and the data signal, and the rising edge of clk_qb is centered at the center of the corresponding bit in the data signal. It can be seen that at this time, the two positive and negative phase clock signals of the Q clock, clk_q and clk_qb, can be used for CDR data sampling and data recovery.

[0062] Therefore, it is beneficial to separate the I and Q clocks to obtain accurate phase control codes, and it is beneficial to correct the phase deviation between the I and Q clock signals.

[0063] Since the ideal phase difference between clk_q and clk_i is 90 degrees, clk_q is Figure 4In the example, the phase is shifted 90 degrees to the left to form a second phase relationship with the data signal aligned with the rising edge. Furthermore, since clk_i, clk_q, clk_ib, and clk_qb still maintain the first phase relationship, that is, a phase difference of 90 degrees, when the phase of clk_q shifts 90 degrees to the left, the phase of clk_ib also shifts 90 degrees to the left. Therefore, after the second phase relationship is formed between clk_q and the data signal, when it is the turn of clk_ib to form the second phase relationship with the data signal, clk_ib also only needs to shift 90 degrees to the left. Similarly, the second phase relationship between clk_qb and the data signal is also formed. It should be noted that a 90-degree left shift is only one phase offset method. For example, it can also be a 90-degree left shift plus n 360-degrees, or a 270-degree right shift plus n 360-degrees, where n is an integer of 0, 1, 2, etc.

[0064] It can be understood that in the above example, from forming a second phase relationship (for example, edge alignment) between clk_i and the data signal, to changing to forming a second phase relationship between clk_q and the data signal, the ideal difference between the two corresponding phase control codes should be a value corresponding to 90 degrees, that is, 1 / 4 of the 128 phase angles corresponding to 360 degrees, which is "32"; however, the actual phase difference between clk_i and clk_q may not be 90 degrees, and the actual phase control code difference corresponding to 90 degrees will have a phase control code deviation relative to "32".

[0065] Therefore, the phase control code deviation can be calculated using the phase control codes when the above-mentioned clock signals respectively form the second phase relationship with the data signal.

[0066] Continue to refer Figure 3 , step S303: calculating a phase control code deviation value based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship.

[0067] In some examples, four clock signals are used as an example, namely, a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The first clock signal and the second clock signal maintain a first phase relationship, such as Figure 4 The ideal phase difference between clk_i and clk_q in the clock signal is 90 degrees. The third clock signal is inversely proportional to the first clock signal, for example Figure 4 The fourth clock signal is inverted to the second clock signal, for example Figure 4 clk_qb in.

[0068] By configuring the phase interpolator, the output clk_i, clk_q, clk_ib, and clk_qb are respectively formed with the data signal into a second phase relationship (e.g., edge-aligned), thereby obtaining corresponding phase control codes: the first phase control code Ci, the second phase control code Cq, the third phase control code Cib, and the first phase control code Cqb.

[0069] In a specific implementation, the difference between the first phase control code Ci and the second phase control code Cq can be calculated to obtain Ci-Cq; and the difference between the third phase control code Cib and the fourth phase control code Cqb can be calculated to obtain Cib-Cqb; when the ideal first phase relationship between clk_i and clk_q is the first phase relationship, Ci-Cq and Cib-Cqb should be 1 / 4 of the 128 phase angles corresponding to 360 degrees, that is, 32. Then, when the actual phase deviation is calculated according to the phase control code, the first difference and the second difference corresponding to the two parts of the deviation can be obtained, which are Ci-Cq-32 and Cib-Cqb-32, respectively.

[0070] Optionally, the phase control code deviation value may be obtained based on the average of the first difference and the second difference. For example, if the phase control code deviation value is set to skew, the calculation formula may be:

[0071] skew=((Ci-Cq-32)+(Cib-Cqb-32)) / 2

[0072] The 32 here comes from 128 / 4, where 128 is the number of phase angles and also corresponds to the phase accuracy, and 4 is the number of clock signals with different phases output by the phase interpolator. Similarly, if the number of phase control code bits to be used is b and the number of clock signals is s, then the 32 in the formula can be expanded to 2. b / s, the calculation formula of the phase control code deviation value can be generalized as:

[0073] skew=((Ci-Cq-2 b / s)+(Cib-Cqb-2 b / s)) / 2

[0074] It should be noted that the purpose of taking the average is to take into account the possibility of small deviations between the positive and negative phase clocks, so the differential idea is used to take the average to eliminate them.

[0075] Back to Figure 3 , proceed to step S304: generate a target phase control code according to the phase control code deviation value, for configuring the phase interpolator to correct the first phase relationship.

[0076] For example, if skew = 4, it means that the phase difference between clk_i and clk_q exceeds 90 degrees by 4 corresponding phase angles, such as 4*360 / 128=11.25 degrees. Then, the phase difference between clk_i and clk_q can be reduced by 11.25 degrees by adjusting the phase of clk_q to the corresponding Cq plus 4 to achieve correction.

[0077] Similarly, clk_qb is offset to the corresponding Cqb plus 4 to achieve actual phase quadrature with clk_ib. Alternatively, in other examples, the corrected clk_qb can be obtained by inverting the corrected clk_q.

[0078] It is understood that the above example uses clk_i and its inverse clk_ib as references, and thus exemplarily illustrates that correction is achieved by adjusting the phases of clk_q and clk_qb. However, in other examples, the above correction can also be achieved by adjusting the phases of clk_i and clk_ib, such as by subtracting 4 from Ci and Cib.

[0079] It can be understood that although the above embodiment uses four clock signals with four phases (the first phase relationship is that the IQ clock signal phases are orthogonal) as an example for correction, if the number of clock signals is smaller, such as 2, 3, etc., the above correction method can still be performed according to needs, so it is not limited to the example of this number of clock signals and the first phase relationship.

[0080] In addition, the acquisition of each phase control code in step S302 can be performed in the full-speed mode of the CDR circuit (the clock signal and the data signal have the same frequency); while the CDR circuit may operate normally in the half-speed mode and can sample more data. Therefore, when executing step S303, the CDR circuit can switch from the full-speed mode to the half-speed mode, perform the phase correction and start normal operation.

[0081] It should be noted that the above-mentioned clock correction method only describes the logical implementation of correcting the phase deviation of the output clock signal of the phase interpolator in the CDR circuit. The logical implementation can be completed through a hardware circuit, such as a digital logic circuit; or, it can also be completed through software, such as through software simulation through an EDA simulation tool; or, it can also be completed by running software through a hardware circuit, such as importing an integrated circuit design (design) simulation into a hardware simulation platform, such as through a processor running program instructions in a memory, wherein the processor includes but is not limited to one or more combinations of a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), etc.; the memory includes but is not limited to one or more combinations of random access memory (RAM), read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), and a flash memory.

[0082] Take hardware circuit implementation as an example, Figure 5 FIG. 1 is a schematic diagram showing the structure of a CDR circuit in an embodiment of the present disclosure. The CDR circuit can implement the clock correction method in the above embodiment.

[0083] The CDR circuit 500 may include: a phase interpolator 501, multiple phase detectors 502a-502d, a selector 503, and an operator 504. It can be understood that the CDR circuit is a loop with negative feedback. Accordingly, the phase interpolator 501, multiple phase detectors 502a-502d, selector 503, and operator 504 sequentially receive the outputs of the former as inputs and generate corresponding outputs as inputs of the latter. The output of the operator 504 or its representation is fed back to the phase interpolator 501 to adjust the phase of the clock signal output by the phase interpolator 501. Therefore, it can be understood that the CDR circuit is an iterative calculation circuit, with one iteration from the phase interpolator 501, multiple phase detectors 502a-502d, selector 503, operator 504 to the feedback phase interpolator 501. This iterative process can adjust the deviation between the clock signals.

[0084] In some examples, before calibration is completed, the CDR circuit can be in a non-operating mode, such as a "bypass mode." Specifically, the CDR operating mode can be set using a first mode control signal, such as byp. For example, byp=1 indicates that the CDR circuit is in bypass mode; byp=0 indicates that the CDR circuit is in normal operating mode, etc.

[0085] In some embodiments, the half-speed or full-speed frequency mode of the CDR circuit can be controlled by a second mode control signal. For example, the second mode control signal is represented by os. When os is 0, it is a half-speed mode, and the operating frequency of the clock signal is adjusted to half the frequency of the data signal, for example Figure 2 As shown; when os = 1, the CDR circuit is in full-speed mode, and the clock signal and data signal frequency are the same, for example Figure 4 shown.

[0086] In some examples, when the CDR circuit is in this bypass and full-speed frequency mode, a preset reference signal with the same frequency and fixed phase as the clock signal can be used as the data signal, such as Figure 4 The data code stream uses "0011" as a cycle.

[0087] The phase interpolator 501 is configured to output at least two clock signals of the same frequency; wherein the phase interpolator 501 is configured to maintain a first phase relationship between the at least two clock signals. For example, the phase interpolator 501 outputs Figure 4 The four phase clock signals are clk_i, clk_q, clk_ib, and clk_qb.

[0088] In some examples, the phase interpolator 501 can set different phases according to an input reference clock signal to obtain the above-mentioned clock signals. The reference clock signal can be provided by, for example, a phase-locked loop (not shown).

[0089] The multiple phase detectors 502a to 502d are coupled to the phase interpolator 501 and are used to respectively obtain the phase difference between each of the clock signals and the data signal. In a specific example, the number of phase detectors can correspond to the clock signals output by the phase interpolator 501 (or exceed the number of clock signals) and input a corresponding clock signal. The data signal is input to each phase detector 502a, 502b, 502c, and 502d to respectively calculate the phase difference between the data signal and each clock signal. For example Figure 5 In the example, four phase detectors 502a-502d are shown, which respectively identify the phase difference between the clock signals clk_i, clk_q, clk_ib, and clk_qb and the data signal (data), and output the phase difference, which is represented as err0, err1, err2, and err3. It will be understood that although this example shows four phase detectors corresponding to four clock signals, in other examples, the number of phase detectors can vary with the number of clock signals, and the example is not limited to the figure.

[0090] Selector 503, coupled to the plurality of phase detectors 502a-502d, is configured to select each clock signal to form a second phase relationship with the data signal, thereby obtaining a corresponding phase control code for phase interpolator 501. For example, the CDR circuit adjusts the phase of cli_i until err0 output by phase detector 502a is 0, indicating that the second phase relationship is formed between clk_i and the data signal. This allows each clock signal to form a second phase relationship with the data signal.

[0091] In some embodiments, the CDR circuit can select a state in which a clock signal and a data signal form a second phase relationship based on a state switching signal (which can be set to clk_align). Specifically, for example, the state switching signal can be input to the selector 503 to select the corresponding phase difference output. The operator 504 then calculates the target phase control code corresponding to the clock signal. The target phase control code is the phase control code corresponding to the second phase relationship between the clock signal and the data signal. The operator 504 then feeds the target phase control code back to the phase interpolator 501, causing it to output a clock signal with the corresponding phase.

[0092] For example, assuming that the state switching signal represents clk_align, the phase difference between clk_q and the data signal is 90 degrees. When clk_align=1 and clk_q is selected to be aligned with the data signal edge, the selector 503 selects err1 to input the operator 504 to obtain the target phase control code for clk_q and other clk_i, clk_ib, and clk_qb to be shifted left by 90 degrees; the corresponding phase control code is fed back to the phase interpolator 501 to configure the phase interpolator 501 to output the clock signals of clk_i, clk_q, clk_ib, and clk_qb that are shifted left by 90 degrees compared to the previous phase.

[0093] The operator 504 is coupled to the selector 503 and is used to calculate a phase control code skew based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship; and generate a target phase control code according to the phase control code deviation value, which is used to configure the phase interpolator 501 to correct the first phase relationship.

[0094] In a specific example, the CDR circuit can be controlled by the state switching signal to obtain the phase control codes Ci, Cq, Cib, and Cqb of clk_i, clk_q, clk_ib, and clk_qb when the second phase relationship is formed, so as to calculate the phase relationship according to the above calculation formula skew=((Ci-Cq-2 b / s)+(Cib-Cqb-2 bThe current round skew can be calculated by using the value of err1 / s)) / 2. This value can be added to err. For example, if the phase difference between clk_i and clk_q is positive, the corresponding phase control code skew value is 2, indicating that the skew needs to be reduced. Therefore, the operator 504 can add 2 to the corresponding phase control code generated based on err1 of clk_q to achieve orthogonality with the actual phase between clk_i and clk_q, thereby achieving correction.

[0095] In some examples, the I clock (referring to clk_i, clk_ib) and the Q clock (referring to clk_q, clk_qb) can be controlled by different target phase control codes respectively. For example, the target phase control code corresponding to the clk_i and clk_ib phases is pi_code_i, and the target phase control code corresponding to the clk_q and clk_qb phases is pi_code_q; after correction, the difference between pi_code_i and pi_code_q can be 32+skew, corresponding to an actual phase difference of 90 degrees between clk_i and clk_q.

[0096] The above process is coherently repeated below through specific examples.

[0097] In State 0, byp=1 and os=1 are set for the CDR circuit, and the input data is a specific code stream such as "00110011...", whose phase is fixed and has the same frequency as the CDR circuit clock signal. Set clk_align=0.

[0098] In State1, the value of clk_align is 0, and the CDR circuit will lock from right to left. After locking, clk_i will align with the data edge, and the pi_code value at this time will be recorded as Ci. Then, change the value of clk_align to 1 to enter State2.

[0099] In State2, the value of clk_align is 1, the CDR locks from right to left, and each clock signal shifts 90 degrees to the left. After locking, clk_q aligns with the data edge, and the pi_code value at this time is recorded as Cq. Then change the value of clk_align to 2 to enter State3.

[0100] In State3, with the value of clk_align set to 2, the CDR will lock from right to left, shifting each clock signal 90 degrees to the left. After locking, clk_ib will align with the data edge, and the pi_code value at this time will be recorded as Cib. Then, change the value of clk_align to 3 to enter State4.

[0101] In State4, the value of clk_align is 3, the CDR circuit will lock from right to left, and each clock signal will shift 90 degrees to the left. After locking, clk_qb will align with the data edge, and the pi_code value at this time will be recorded as Cqb.

[0102] After that, change the values of byp and os to 0, indicating that the CDR circuit is set to normal operating mode and half-speed mode, and enters state5.

[0103] State 5 indicates the normal operation of the CDR circuit. The pi_code values obtained in the previous states can be used to calculate the skew between the I and Q clock signals. The skew calculation formula is shown in the previous section.

[0104] The first phase relationship between the clock signals output by the phase interpolator 501 can be corrected by using the deviation. For example, the calculated deviation can be corrected by Figure 5 The CDR circuit takes the target phase control code into account, which is then fed back to the phase interpolator 501 to generate the I and Q clock signals after the deviation is corrected.

[0105] In some examples, a decoder 505 may be coupled between the operator 504 and the phase interpolator 501 to identify the target phase control code (e.g., 7 bits in binary) output by the operator 504 into a form usable by the phase interpolator 501 (e.g., 34 bits in binary).

[0106] The present disclosure also provides a chip including the clock data recovery circuit described above. The chip can be implemented as a system on chip (SoC), FPGA, or other ASIC for processing data based on a high-speed serial communication protocol.

[0107] The disclosed embodiments may also provide a receiving end including the aforementioned clock and data recovery circuit. In a possible example, the receiving end is a data signal receiving end in a SERDES architecture to implement high-speed serial signal transmission. SER-DES is a combination of a serializer (SERializer) and a deserializer (DESerializer).

[0108] It can be understood that the receiving end can be, for example, an integrated circuit module in a chip that sends and receives signals to each other, or it can be, for example, an optical communication device in an optical communication network scenario, or it can be, for example, a communication module or communication device in other scenarios, and its specific application scenario is not limited.

[0109] In the embodiments of the present disclosure, a data communication terminal may be provided, including the receiving end. In a specific implementation example, the data communication terminal may be, for example, an optical network communication device, an Internet network communication device, or a television set-top box (or a smart TV, etc.). In the uncalibrated initial state of the data communication terminal, when it detects an input signal (such as a transmission signal obtained by connecting to a communication cable such as an internet cable or a video cable), the process of State 0 to State 5 described above may be triggered.

[0110] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following beneficial effects:

[0111] On the one hand, the technical solution in the embodiment of the present disclosure realizes the correction of the first phase relationship between multiple clock signals in the CDR based on the digital circuit, thereby improving the accuracy of the recovered data; and, the technical solution has simple calculation logic, small circuit area and low power consumption.

[0112] On the other hand, by using the deviation correction in the embodiment of the present disclosure, the influence of the process voltage temperature (PVT) of the circuit devices in the CDR (such as the phase interpolator, etc.) on the clock signal is reduced, so a CDR circuit with higher precision can be achieved.

[0113] It should be noted that the foregoing description of this specification is based on specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0114] The foregoing description describes specific embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0115] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present specification as described above, which are not provided in detail for the sake of simplicity.

[0116] In addition, to simplify the description and discussion, and so as not to obscure one or more embodiments of the present specification, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, devices may be shown in block diagram form to avoid obscuring one or more embodiments of the present specification, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which one or more embodiments of the present specification will be implemented (i.e., these details should be fully within the purview of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that one or more embodiments of the present specification may be implemented without these specific details or with variations in these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0117] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0118] The one or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification shall be included within the scope of protection of this disclosure.

Claims

1. A clock correction method, characterized in that: Applicable to a clock data recovery circuit based on a phase interpolator; the method comprises: Acquire at least two clock signals of the same frequency output by a phase interpolator; wherein the phase interpolator is configured to maintain a first phase relationship between the at least two clock signals; Acquire a phase control code of the phase interpolator when a second phase relationship is formed between the at least two clock signals and the data signal respectively; Calculating a phase control code deviation value based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship; A target phase control code is generated according to the phase control code deviation value, and is used to configure the phase interpolator to correct the first phase relationship.

2. The method according to claim 1, characterized in that The first phase relationship refers to maintaining a preset phase difference between the clock signals.

3. The method according to claim 1, characterized in that The first phase relationship refers to the phase quadrature between the clock signals.

4. The method according to claim 1, wherein The second phase relationship refers to that the clock signal and the data signal are edge-aligned.

5. The method according to claim 1 or 3, characterized in that The at least two clock signals include: a first clock signal and a second clock signal that maintain a first phase relationship; a third clock signal that is inverted to the first clock signal, and a fourth clock signal that is inverted to the second clock signal; the phase control code of the phase interpolator obtained when a second phase relationship is formed between the at least two clock signals and the data signal respectively is obtained when the clock signal and the data signal are configured to have the same frequency.

6. The method according to claim 1, characterized in that The at least two clock signals include: a first clock signal and a second clock signal maintaining a first phase relationship; a third clock signal having an opposite phase to the first clock signal; and a fourth clock signal having an opposite phase to the second clock signal. Calculating a phase control code deviation value based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship includes: Obtaining a first difference between a first phase control code difference and a second phase control code difference of the first clock signal and the second clock signal; Obtaining a second difference between the first phase control code difference and the second phase control code difference of the third clock signal and the fourth clock signal; A phase control code deviation value is obtained based on an average of the first difference and the second difference.

7. The method according to claim 6, characterized in that Generating a target phase control code according to the phase control code deviation value, for configuring the phase interpolator to correct the first phase relationship, comprises: The first phase relationship between the first clock signal and the second clock signal output by the phase interpolator is corrected according to the target phase control code, and the first phase relationship between the third clock signal and the fourth clock signal is corrected.

8. A clock data recovery circuit, characterized in that: include: A phase interpolator, configured to output at least two clock signals of the same frequency; wherein the phase interpolator is configured to maintain a first phase relationship between the at least two clock signals; a plurality of phase detectors, coupled to the phase interpolator, for respectively obtaining a phase difference between each of the clock signals and the data signal; A selector, coupled to the plurality of phase detectors, for selecting a second phase relationship between each clock signal and the data signal, so as to obtain a corresponding phase control code of the phase interpolator; An operator, coupled to the selector, is configured to calculate a phase control code deviation value based on a first phase control code difference value between the phase control codes of the at least two clock signals and a second phase control code difference value corresponding to the first phase relationship; and to generate a target phase control code according to the phase control code deviation value, for configuring the phase interpolator to correct the first phase relationship.

9. The circuit according to claim 8, characterized in that The first phase relationship refers to maintaining a preset phase difference between the clock signals.

10. The circuit according to claim 8, characterized in that The first phase relationship refers to the phase quadrature between the clock signals.

11. The circuit according to claim 8, characterized in that The second phase relationship refers to that the clock signal and the data signal are edge-aligned.

12. The circuit according to claim 8 or 10, characterized in that The at least two clock signals include: a first clock signal and a second clock signal that maintain a first phase relationship; a third clock signal that is inverted to the first clock signal, and a fourth clock signal that is inverted to the second clock signal; the phase control code of the phase interpolator obtained when a second phase relationship is formed between the at least two clock signals and the data signal respectively is obtained when the clock signal and the data signal are configured to have the same frequency.

13. The circuit according to claim 8, characterized in that The at least two clock signals include: a first clock signal and a second clock signal maintaining a first phase relationship; a third clock signal having an opposite phase to the first clock signal; and a fourth clock signal having an opposite phase to the second clock signal. Calculating a phase control code deviation value corresponding to the phase deviation between the at least two clock signals based on a first phase control code difference between the phase control codes of the at least two clock signals and a second phase control code difference corresponding to the first phase relationship includes: Obtaining a first difference between a first phase control code difference and a second phase control code difference of the first clock signal and the second clock signal; Obtaining a second difference between the first phase control code difference and the second phase control code difference of the third clock signal and the fourth clock signal; A phase control code deviation value is obtained based on an average of the first difference and the second difference.

14. The circuit according to claim 13, characterized in that Generating a target phase control code according to the phase control code deviation value, for configuring the phase interpolator to correct the first phase relationship, comprises: The first phase relationship between the first clock signal and the second clock signal output by the phase interpolator is corrected according to the target phase control code, and the first phase relationship between the third clock signal and the fourth clock signal is corrected.

15. A chip, characterized in that: The method comprises the clock data recovery circuit according to any one of claims 8 to 14.

16. A receiving end, characterized in that: The method comprises the clock data recovery circuit according to any one of claims 8 to 14.

17. A data communication terminal, characterized in that: Comprising the receiving end as claimed in claim 16.

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