Circuit structure and method of multi-bit XOR operation based on SRAM array

Abstract

The present invention relates to a circuit structure and method for performing multi-bit XOR operations based on an SRAM array. The circuit structure for performing multi-bit XOR operations based on an SRAM array includes N×N SRAM memory cells arranged in an array. For SRAM memory cells located in the same column, the sources of all transistors T5 are electrically connected to a bit line BL, and the sources of all transistors T6 are electrically connected to a bit line BLB. For SRAM memory cells located in the same row, the first row of 8T-SRAM cells and the second row of 8T-SRAM cells of all SRAM memory cells share a reset transistor; and the third row of 7T-SRAM cells of all SRAM memory cells share a copy auxiliary unit. The present invention can correctly perform multi-bit XOR operations in the digital domain. Compared to calculations in the analog domain, digital domain calculations have higher accuracy and do not require more complex A / D circuits, reducing circuit area and complexity.

Description

Technical Field

[0001] The present invention relates to a static random access memory (SRAM), and in particular to a circuit structure and method for multi-bit XENOR operation based on an SRAM array. Background Art

[0002] Existing technology can perform addition, subtraction, and multiplication within SRAM memory. However, due to the limitations of recognition and convolutional neural networks, the multiplication and accumulation of inputs and weights—the computational process of convolutional neural networks—is required and applicable in many applications. However, binary multiplication is typically implemented in the analog domain, accumulating voltage on bit lines and reading the result through an ADC. This presents a significant linearity challenge, requiring a high-precision ADC or auxiliary circuitry to correct linearity, which is challenging to implement. Therefore, an efficient, simple, and high-precision computational circuit is urgently needed. Summary of the Invention

[0003] Based on this, it is necessary to provide a circuit structure and method for multi-bit XOR operation based on SRAM array to address the problem that accumulating voltage on the bit line and reading the accumulated result through ADC leads to complex circuit and insufficient accuracy.

[0004] The present invention is achieved by adopting the following technical solutions:

[0005] A circuit structure for multi-bit XOR operation based on an SRAM array, comprising:

[0006] N×N SRAM memory cells are distributed in an array, and the SRAM memory cells include three rows of SRAM cells, wherein:

[0007] In the first row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to the word line WL, the node Q is electrically connected to the gate of transistor T7, and the node QB is electrically connected to the gate of transistor T8; the sources of transistors T7 and T8 are electrically connected to the computation word line CWL1, the drain of transistor T7 is electrically connected to the bit line CBL, the drain of transistor T8 is electrically connected to the bit line CBLB, the source and drain of reset transistor T9 are connected to the bit lines CBL and CBLB respectively, and the gate of reset transistor T9 is electrically connected to the reset signal Reset.

[0008] In the second row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to word line WL, node Q is electrically connected to the gate of transistor T7, and node QB is electrically connected to the gate of transistor T8; the sources of transistors T7 and T8 are electrically connected to node OUT, an output port of an exclusive OR operation result, the drain of transistor T7 is electrically connected to bit line CBL of the first row, and the drain of transistor T8 is electrically connected to bit line CBLB of the first row;

[0009] In the 7T-SRAM cell of the third row, the gates of transistors T5 and T6 are electrically connected to word line WL, the gate of transistor T7 is electrically connected to write word line WWL, the source of T7 is electrically connected to node Q, the drain of T7 is electrically connected to node OUT, and the sources of transistors T1 and T3 are electrically connected to the copy assist unit;

[0010] In the SRAM memory cells located in the same column, the sources of all transistors T5 are electrically connected to the bit line BL, and the sources of all transistors T6 are electrically connected to the bit line BLB;

[0011] The SRAM memory cells in the same row, the first row 8T-SRAM cells and the second row 8T-SRAM cells of all SRAM memory cells share a reset transistor T9; the third row 7T-SRAM cells of all SRAM memory cells share a copy assist unit.

[0012] Furthermore, the replication auxiliary unit includes:

[0013] a transistor T8 , wherein the gate of T8 is electrically connected to the power control signal CD, the source of T8 is electrically connected to VDD, and the drain of T8 is electrically connected to the source of T1 ;

[0014] The transistor T9 has a gate electrically connected to the power control signal CS, a source electrically connected to VSS, and a drain electrically connected to the source of T3.

[0015] Furthermore, all SRAM cells in the same row share a word line WL, all 8T-SRAM cells in the first row share a calculation word line CWL, and all 7T-SRAM cells in the third row share a write word line WWL.

[0016] Furthermore, the SRAM unit includes NMOS transistors T3 to T6 and PMOS transistors T1 to T2. T1 to T4 form two cross-coupled inverters, one end of which is electrically connected to the node Q and the other end of which is electrically connected to the node QB.

[0017] Furthermore, during the operation process of the multi-bit XNOR operation circuit structure based on the SRAM array, the reset signal Reset is turned on in advance, the bit lines CBL and CBLB and the node OUT are set to "0", and then the reset signal Reset is turned off to activate the calculation word line CWL.

[0018] In one embodiment, assuming that in the SRAM memory cell, the data stored in the 8T-SRAM cells in the first row is “1”, and the data stored in the 8T-SRAM cells in the second row is “1”;

[0019] The transistor T7 of the 8T-SRAM cell in the first row is activated, and the transistor T8 is turned off. The computation word line CWL discharges to the bit line CBL through the transistor T7. The voltage of the bit line CBL increases, and the bit line CBLB remains at "0".

[0020] The transistor T7 of the 8T-SRAM cell in the second row is turned on, the transistor T8 is turned off, and the bit line CBL is discharged to the node OUT through the transistor T7;

[0021] The node OUT is charged through the transistors T7 of the 8T-SRAM cells in the first and second rows, and the output result is "1".

[0022] In one embodiment, assuming that in the SRAM memory cells, the data stored in the 8T-SRAM cells in the first row is "1", and the data stored in the 8T-SRAM cells in the second row is "0";

[0023] The transistor T7 of the 8T-SRAM cell in the first row is activated, and the transistor T8 is turned off. The computation word line CWL discharges to the bit line CBL through the transistor T7. The voltage of the bit line CBL increases, and the bit line CBLB remains at "0".

[0024] The transistor T8 of the 8T-SRAM cell in the second row is turned on, and the transistor T7 is turned off. The bit line CBL cannot discharge to the node OUT, and the output result of the node OUT is "0".

[0025] In one embodiment, assuming that in the SRAM memory cells, the data stored in the 8T-SRAM cells in the first row is “0”, and the data stored in the 8T-SRAM cells in the second row is “0”;

[0026] The transistor T8 of the 8T-SRAM cell in the first row is activated, and the transistor T7 is turned off. The computation word line CWL is discharged to the bit line CBLB through the transistor T8. The voltage of the bit line CBLB increases, and the bit line CBL remains at "0".

[0027] The transistor T8 of the 8T-SRAM cell in the second row is turned on, the transistor T7 is turned off, and the bit line CBLB is discharged to the node OUT through the transistor T8;

[0028] The node OUT is charged through the transistors T8 of the 8T-SRAM cells in the first and second rows, and the output result is "1".

[0029] In one embodiment, assuming that in the SRAM memory cells, the data stored in the 8T-SRAM cells in the first row is “0”, and the data stored in the 8T-SRAM cells in the second row is “1”;

[0030] The transistor T8 of the 8T-SRAM cell in the first row will be activated, and the transistor T7 will be turned off. The computing word line CWL will discharge to the bit line CBLB through the transistor T8. The voltage of the bit line CBLB will increase, and the bit line CBL will remain at "0".

[0031] The transistor T7 of the 8T-SRAM cell in the second row is turned on, and the transistor T8 is turned off. The bit line CBLB cannot discharge to the node OUT, and the output result of the node OUT is "0".

[0032] The present invention also includes an operation method for a circuit structure of a multi-bit XOR operation based on an SRAM array. The circuit structure of the multi-bit XOR operation based on an SRAM array is the aforementioned circuit structure of the multi-bit XOR operation based on an SRAM array, and is characterized in that the operation method comprises the following steps:

[0033] Performing a zero operation on the bit lines CBL, CBLB and the node OUT through the reset signal Reset in the SRAM storage cell and the calculation word line CWL;

[0034] After the calculation bit lines CBL and CBLB are reset to zero, the reset signal Reset is turned off and the calculation word line CWL is activated, causing the 8T-SRAM cells in the first row and the 8T-SRAM cells in the second row to calculate, and the calculation results are temporarily stored in the node OUT;

[0035] Adjust the write word line WWL timing to set the power control signal CD to high level and the power control signal CS to low level, copy the calculation result temporarily stored in the node OUT, and store the copied result in the 7T-SRAM cell in the third row.

[0036] The technical solution provided by the present invention has the following beneficial effects:

[0037] 1. It can correctly complete multi-bit XOR operations in the digital domain. Compared with the calculation in the analog domain, the calculation in the digital domain has higher accuracy and does not require more complex A / D circuits, which greatly reduces the circuit area and complexity.

[0038] 2. After the XOR calculation is completed, the result is stored in the 7T-SRAM unit of another row without destroying the original stored data involved in the calculation.

[0039] 3. Each row of 8T-SRAM cells involved in the circuit calculation is shared, so multiple bits can be calculated together, greatly improving the parallelism of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Schematic diagram of the circuit structure of a multi-bit XOR operation based on an SRAM array of the present invention;

[0041] Figure 2 for Figure 1 Schematic diagram of the SRAM cell structure of the first and second rows of SRAM storage cells;

[0042] Figure 3 for Figure 1 Schematic diagram of the structure of the SRAM storage unit;

[0043] Figure 4 for Figure 2 Schematic diagram of the circuit timing waveform of the XOR operation of two rows of SRAM cells;

[0044] Figure 5 for Figure 1 Working waveform diagram of the calculation process. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] like Figure 1 As shown, this embodiment provides a circuit structure for multi-bit XOR operations based on an SRAM array, including an N×N array of SRAM memory cells, M reset signal groups (Resets), M computation word line groups (CWLs), M write word line groups (WWLs), and M power control signals (CDs and CSs). In addition, the entire circuit structure also needs to be driven by word lines WL.

[0047] like Figure 2 and Figure 3As shown, the SRAM memory cell includes three rows of SRAM memory cells, wherein: in the first row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to the word line WL, the node Q is electrically connected to the gate of transistor T7, and the node QB is electrically connected to the gate of transistor T8; the sources of transistors T7 and T8 are electrically connected to the calculation word line CWL, the drain of transistor T7 is electrically connected to the bit line CBL, the drain of transistor T8 is electrically connected to the bit line CBLB, the source and drain of reset transistor T9 are connected to the bit line CBL and CBLB respectively, and the gate of reset transistor T9 is electrically connected to the reset signal Reset. In the second row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to the word line WL, the node Q is electrically connected to the gate of transistor T7, and the node QB is electrically connected to the gate of transistor T8; the sources of transistors T7 and T8 are electrically connected to the output port node OUT of the exclusive OR operation result, the drain of transistor T7 is electrically connected to the bit line CBL of the first row, and the drain of transistor T8 is electrically connected to the bit line CBLB of the first row; in the third row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to the word line WL, the gate of transistor T7 is electrically connected to the write word line WWL, the source of T7 is electrically connected to the node Q, the drain of T7 is electrically connected to the node OUT, and the sources of transistors T1 and T2 are electrically connected to the copy assist unit.

[0048] In the SRAM memory cells located in the same column, the sources of all transistors T5 are electrically connected to the bit line BL, and the sources of all transistors T6 are electrically connected to the bit line BLB. In the SRAM memory cells located in the same row, all SRAM memory cells (8T-SRAM cells in the first row and 8T-SRAM cells in the second row) share a reset transistor T9; all SRAM memory cells (7T-SRAM cells in the third row) share a copy assist unit.

[0049] like Figure 3 As shown, the first row includes 6T-SRAM cells and transistors T7 and T8, forming an 8T-SRAM cell; the second row includes 6T-SRAM cells and transistors T7 and T8, forming an 8T-SRAM cell; and the third row includes 6T-SRAM cells and transistor T7, forming a 7T-SRAM cell. Reset transistor T9 acts as a switch to turn the two bit lines on and off, thereby setting the calculation bit lines CBL and CBLB to "0" before calculation, preparing the calculations for the first and second rows. It also resets the residual charge from the previous cycle. The two data involved in the calculation are stored in the Q nodes of the first and second rows, respectively.

[0050] T1-T6 are traditional 6T-SRAM cells, where T1 to T2 are PMOS transistors, T3 to T6 are NMOS transistors, and T1 to T4 form two cross-coupled inverters, one end of which is electrically connected to node Q and the other end is electrically connected to node QB. The two rows involved in the calculation are the Q nodes of two rows of 8T-SRAM cells, and the results generated are logic "1" and logic "0" based on the digital domain.

[0051] like Figure 3 As shown, the result of the XOR operation will be stored in the OUT node, and the node OUT result will be written to the 7T-SRAM unit in the third row through the copy auxiliary unit.

[0052] The target of the replication is the result of the exclusive-OR operation on the first and second rows of SRAM cells. The replication target is the 7T-SRAM cell in the third row of SRAM cells. Transistors T8 and T9 are shared by the entire replication row, meaning that the replication process is performed simultaneously on all 7T-SRAM cells in a row.

[0053] Transistor T7 is a copy transfer transistor, which is controlled by the write word line WWL. The source of T7 is electrically connected to the Q node of the third row of 7T-SRAM cells, and the drain of T7 is connected to the output node OUT of the above two rows of operations.

[0054] By adjusting the timing of the write word line WWL, the result of the OUT node can be written into the third row of 7T-SRAM cells.

[0055] Due to the characteristics of 6T-SRAM cells, single-ended writes cannot write data to 6T-SRAM cells without adding a replication assist unit. This is because the 6T-SRAM cell has a reverse coupling structure, and the Q node and QB node will maintain each other, making it difficult to destroy the data through single-ended writes.

[0056] Therefore, transistors T8 and T9 are added. When the write word line WWL is turned on, transistors T8 and T9 are activated simultaneously. That is, the CD signal is high for a short moment, and the CS signal is low for a short moment. At this point, the reverse coupling structure in the 6T-SRAM cell is destroyed, and single-ended writing can be achieved. One end of the source of transistor T8 is connected to VDD, and the other end of the drain is connected to the VDD of the inverter at one end of the Q node. Therefore, transistor T8 can control the power supply voltage VDD of one inverter in the 6T-SRAM.

[0057] One end of the source of the transistor T9 is connected to VSS, and the other end of the drain is connected to the VSS of the inverter at one end of the Q node, so the VSS of one inverter in the 6T-SRAM cell can be controlled through the transistor T8.

[0058] It should be noted that the CD signal and the CS signal need to be turned on for a very short time, and the calculation result copying process must be completed within this short time.

[0059] Before calculation, the timing of the control signal needs to be adjusted to make the timing meet the theoretical requirements of the circuit design. At the same time, the circuit analysis uses a line load model, so the voltage increase and decrease are all caused by the charging and discharging of the capacitor.

[0060] like Figure 4 Figure 2 shows a schematic diagram of the circuit timing waveforms for performing a two-row XOR operation according to an embodiment of the present invention. Taking an SRAM memory cell as an example, during the operation, the reset signal Reset needs to be activated before the calculation of the word line CWL signal, setting CBL, CBLB, and node OUT to "0". Only after the reset signal Reset is turned off can CWL be activated to ensure that CBL, CBLB, and OUT are fully discharged.

[0061] Assume that after reset is complete and the computational word line is activated, the data stored in the first row of 8T-SRAM cells is "1" and the data stored in the second row of 8T-SRAM cells is "1". Transistor T7 in the first row will be activated, and transistor T8 will not turn on. The computational word line discharges to CBL through T7. Due to the bit line capacitance (the circuit's line load capacitance, which is added between CBL and CBLB during simulation, with the other end grounded), the voltage on CBL increases, while CBLB remains at zero. At the same time, transistor T7 (located at the same position as in the first row) at the Q node of the second row of 8T-SRAM cells will turn on, and transistor T8 will turn off. Since the drain of transistor T7 is connected to CBL, CBL will discharge to node OUT through transistor T7 in the second row. Due to the presence of capacitance, node OUT will be charged through the two conducting transistors T7. The logical result is "1".

[0062] Assume that after reset is complete and the computational word line is activated, the data stored in the first row of 8T-SRAM cells is "1" and the data stored in the second row of 8T-SRAM cells is "0". Transistor T7 in the first row will be activated, and transistor T8 will not be turned on. The computational word line discharges to CBL through T7. Due to the bit line capacitance, the voltage on CBL increases, and CBLB remains zero. At the same time, transistor T8 (located at the same position as in the first row) under the Q node of the second row of 8T-SRAM cells will be turned on, and transistor T7 will be turned off. Since the drain of transistor T7 is connected to CBL and the drain of transistor T8 is connected to CBLB, the logic voltage on CBL is "1" and the voltage on CBLB is "0". Even though transistor T8 in the second row is turned on, transistor T7 in the second row is closed, resulting in the upper voltage of CBL not being able to discharge to node OUT, so the voltage of node OUT remains "0".

[0063] Assume that after reset is complete and the computation word line is activated, the data stored in the first row of 8T-SRAM cells is "0" and the data stored in the second row of 8T-SRAM cells is "0". Transistor T8 in the first row will be activated, and transistor T7 will not be turned on. The computation word line discharges to CBLB through T8. Due to the bit line capacitance, the CBLB voltage increases, and CBL remains zero. At the same time, transistor T8 (located at the same position as the first row) under the Q node of the second row of 8T-SRAM cells will be turned on, and transistor T7 will be turned off. Since the drain of transistor T8 is connected to CBLB, CBLB will discharge to the OUT node through transistor T8 in the second row. Due to the presence of capacitance, the OUT node will be charged through the two turned-on transistors T8. The logical result is "1".

[0064] Assume that after reset is complete and the computation word line is activated, the data stored in the first row of 8T-SRAM cells is "0" and the data stored in the second row of 8T-SRAM cells is "1". Transistor T8 in the first row will be activated, and transistor T7 will not turn on. The computation word line discharges to CBLB through T8. Due to the bit line capacitance, the voltage on CBLB increases, and CBL remains at zero. At the same time, transistor T7 (located at the same position as in the first row) under the Q node of the second row of 8T-SRAM cells will turn on, and transistor T8 will turn off. Since the drain of transistor T7 is connected to CBL and the drain of transistor T8 is connected to CBLB, the logic voltage on the CBLB line is "1" and the voltage on CBL is "0". Even though transistor T7 in the second row is turned on, transistor T8 in the second row is closed, resulting in the voltage on CBLB not being able to discharge to node OUT, so the voltage on node OUT remains "0".

[0065] The following table shows the truth table for the XOR calculation in this embodiment. As shown in the table, Q1 and Q1B represent the data stored in the first row of 8T-SRAM cells. Q2 and Q2B represent the data stored in the second row of 8T-SRAM cells, and Q3 and Q3B represent the data stored in the third row of 7T-SRAM cells. As can be seen from the truth table, after the calculation is completed, the Q node in the third row stores the XOR result of the first two rows, and the QB node in the third row stores the XOR result of the first two rows.

[0066] XOR calculation truth table

[0067]

[0068] like Figure 5The figure shows the actual working waveform of the calculation process of the embodiment of the present invention. During the period when the calculation word line is turned on and activated, the calculation needs to be completed and written into the SRAM cell. The figure shows the actual change of voltage. As mentioned above, the logic voltage of the node OUT is "1", but it is not the power supply voltage VDD. It is lower than VDD by the threshold voltage of two transistors. However, it does not affect the correctness of the calculation result. The voltage change of the node OUT to the logic voltage "1" is controlled by the calculation word line CWL. And the high level cannot reach the value of VDD. Q3 and Q3B in the figure represent the process of changing the originally stored data into the calculation result in the third row of SRAM cells. It can be seen that since the calculation result is different from the data originally stored in the SRAM cell, the data in the SRAM cell will be rewritten.

[0069] In summary, the SRAM storage unit correctly completes multi-bit XOR operations. The XOR result can be stored back in the third row without destroying the original data. The XOR result is then written to another row not involved in the calculation via a transmission pipe, without destroying the original output value. Furthermore, all columns in a row are operated simultaneously, improving the circuit's parallelism and throughput. The circuit structure is simple and requires no complex peripheral circuitry.

[0070] Based on the aforementioned circuit structure for multi-bit XOR operation based on an SRAM array, an operation method for the circuit structure for multi-bit XOR operation based on an SRAM array is provided, comprising the following steps:

[0071] S1: The bit lines CBL, CBLB and nodes are reset to zero through the reset signal Reset in the SRAM memory cell and the calculation word line CWL;

[0072] S2: After the calculation bit lines CBL and CBLB are set to zero, the reset signal Re is turned off and the calculation word line CWL is activated. The 8T-SRAM cells in the first row and the 8T-SRAM cells in the second row are caused to calculate, and the calculation results are temporarily stored in the node OUT.

[0073] S3: Adjust the write word line WWL timing, set the power control signal CD to high level and the power control signal CS to low level, copy the calculation result temporarily stored in the node OUT, and store the copied result in the 7T-SRAM cell in the third row.

[0074] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A circuit structure for multi-bit XOR operation based on an SRAM array, comprising: N×N SRAM memory cells are distributed in an array, and the SRAM memory cells include three rows of SRAM cells, wherein: In the first row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to word line WL, node Q is electrically connected to the gate of transistor T7, and node QB is electrically connected to the gate of transistor T8; the sources of transistors T7 and T8 are electrically connected to computation word line CWL, the drain of transistor T7 is electrically connected to bit line CBL, the drain of transistor T8 is electrically connected to bit line CBLB, the source and drain of reset transistor T9 are connected to bit lines CBL and CBLB, respectively, and the gate of reset transistor T9 is electrically connected to reset signal Reset; In the second row of 8T-SRAM cells, the gates of transistors T5 and T6 are electrically connected to word line WL, node Q is electrically connected to the gate of transistor T7, and node QB is electrically connected to the gate of transistor T8; the sources of transistors T7 and T8 are electrically connected to node OUT, an output port of an exclusive OR operation result, the drain of transistor T7 is electrically connected to bit line CBL of the first row, and the drain of transistor T8 is electrically connected to bit line CBLB of the first row; In the 7T-SRAM cell of the third row, the gates of transistors T5 and T6 are electrically connected to word line WL, the gate of transistor T7 is electrically connected to write word line WWL, the source of T7 is electrically connected to node Q, the drain of T7 is electrically connected to node OUT, and the sources of transistors T1 and T2 are electrically connected to the copy assist unit; In the SRAM memory cells located in the same column, the sources of all transistors T5 are electrically connected to the bit line BL, and the sources of all transistors T6 are electrically connected to the bit line BLB; The SRAM memory cells in the same row, the first row 8T-SRAM cells and the second row 8T-SRAM cells of all SRAM memory cells share a reset transistor T9; the third row 7T-SRAM cells of all SRAM memory cells share a copy assist unit.

2. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 1, characterized in that: The replication auxiliary unit includes: a transistor T8 , wherein the gate of T8 is electrically connected to the power control signal CD, the source of T8 is electrically connected to VDD, and the drain of T8 is electrically connected to the source of T1 ; The transistor T9 has a gate electrically connected to the power control signal CS, a source electrically connected to VSS, and a drain electrically connected to the source of T3.

3. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 2, characterized in that: All SRAM memory cells in the same row share a common word line WL. All 8T-SRAM cells in the first row share a common calculation word line CWL, and all 7T-SRAM cells in the third row share a common write word line WWL.

4. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 3, characterized in that: The SRAM unit includes NMOS transistors T3 to T6 and PMOS transistors T1 to T2. T1 to T4 form two cross-coupled inverters, one end of which is electrically connected to the node Q and the other end of which is electrically connected to the node QB.

5. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 4, characterized in that: During the operation process of the multi-bit XOR operation circuit structure based on the SRAM array, the reset signal Reset is turned on in advance to set the bit lines CBL and CBLB and the node OUT to "0", and then the reset signal Reset is turned off to activate the calculation word line CWL.

6. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 5, characterized in that: Assume that in the SRAM memory cell, the data stored in the 8T-SRAM cell in the first row is "1", and the data stored in the 8T-SRAM cell in the second row is "1"; The transistor T7 of the 8T-SRAM cell in the first row is activated, and the transistor T8 is turned off. The computation word line CWL discharges to the bit line CBL through the transistor T7. The voltage of the bit line CBL increases, and the bit line CBLB remains at "0". The transistor T7 of the 8T-SRAM cell in the second row is turned on, the transistor T8 is turned off, and the bit line CBL is discharged to the node OUT through the transistor T7; The node OUT is discharged through the transistors T7 of the first and second rows of 8T-SRAM cells, and the output result is "1".

7. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 5, characterized in that: Assume that in the SRAM memory cell, the data stored in the 8T-SRAM cells in the first row is "1", and the data stored in the 8T-SRAM cells in the second row is "0"; The transistor T7 of the 8T-SRAM cell in the first row is activated, and the transistor T8 is turned off. The computation word line CWL discharges to the bit line CBL through the transistor T7. The voltage of the bit line CBL increases, and the bit line CBLB remains at "0". The transistor T8 of the 8T-SRAM cell in the second row is turned on, and the transistor T7 is turned off. The bit line CBL cannot discharge to the node OUT, and the output result of the node OUT is "0".

8. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 5, characterized in that: Assume that in the SRAM memory cell, the data stored in the 8T-SRAM cell in the first row is "0", and the data stored in the 8T-SRAM cell in the second row is "0"; The transistor T8 of the 8T-SRAM cell in the first row is activated, and the transistor T7 is turned off. The computation word line CWL discharges to the bit line CBLB through the transistor T8. The voltage of the bit line CBLB increases, and the bit line CBL remains at "0". The transistor T8 of the 8T-SRAM cell in the second row is turned on, the transistor T7 is turned off, and the bit line CBLB is discharged to the node OUT through the transistor T8; The node OUT is charged through the transistors T8 of the 8T-SRAM cells in the first and second rows, and the output result is "1".

9. The circuit structure of multi-bit XOR operation based on SRAM array according to claim 5, characterized in that: Assume that in the SRAM memory cells, the data stored in the 8T-SRAM cells in the first row is "0", and the data stored in the 8T-SRAM cells in the second row is "1"; The transistor T8 of the 8T-SRAM cell in the first row will be activated, and the transistor T7 will be turned off. The computing word line CWL will discharge to the bit line CBLB through the transistor T8. The voltage of the bit line CBLB will increase, and the bit line CBL will remain at "0". The transistor T7 of the 8T-SRAM cell in the second row is turned on, and the transistor T8 is turned off. The bit line CBLB cannot discharge to the node OUT, and the output result of the node OUT is "0".

10. A method for operating a circuit structure for a multi-bit XOR operation based on an SRAM array, wherein the circuit structure for operating a multi-bit XOR operation based on an SRAM array is the circuit structure for operating a multi-bit XOR operation based on an SRAM array according to any one of claims 1 to 9, characterized in that: The operation method comprises the following steps: Performing a zeroing operation on the bit lines CBL, CBLB and nodes through the reset signal Reset in the SRAM memory cell and the calculation word line CWL; After the calculation bit lines CBL and CBLB are reset to zero, the reset signal Reset is turned off and the calculation word line CWL is activated, causing the 8T-SRAM cells in the first row and the 8T-SRAM cells in the second row to calculate, and the calculation results are temporarily stored in the node OUT; Adjust the write word line WWL timing to set the power control signal CD to high level and the power control signal CS to low level, copy the calculation result temporarily stored in the node OUT, and store the copied result in the 7T-SRAM cell in the third row.

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