Display substrate and display device

Abstract

A display substrate and a display device. The sub-pixels in the display substrate include a light-emitting element and a pixel circuit. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode. The pixel circuit includes a first connection portion, a driving transistor, and a threshold compensation transistor. The first pole of the threshold compensation transistor is electrically connected to the first pole of the driving transistor, and the second pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor through the first connection portion. The sub-pixel includes a first color sub-pixel pair, and the first color sub-pixel pair includes a first pixel block and a second pixel block. The ratio of the overlapping area between the orthographic projection of the second electrode of the first pixel block on the substrate and the orthographic projection of the first connection portion on the substrate to the overlapping area between the orthographic projection of the second electrode of the second pixel block on the substrate and the orthographic projection of the first connection portion on the substrate is 0.8 to 1.2, thereby reducing the load difference of the gate nodes of the driving transistors in the two first color sub-pixels.

Description

[0001] This application is a divisional of the Chinese patent application No. 202080001419.2, entitled "Display Substrate and Display Device", which entered the Chinese national phase on August 3, 2020. The Chinese patent application No. 202080001419.2 is a patent application that entered the Chinese national phase from the PCT application No. PCT / CN2020 / 106413 filed on July 31, 2020. The PCT application No. PCT / CN2020 / 106413 claims the priority of the PCT application No. PCT / CN2019 / 098708 filed on July 31, 2019, and the priority of the PCT application No. PCT / CN2019 / 098731 filed on July 31, 2019. For all purposes, the content disclosed in the above PCT applications is hereby incorporated by reference in its entirety as part of this application. Technical Field

[0002] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0003] With the development of organic light-emitting diode display technology, such as active-matrix organic light-emitting diode (AMOLED) display technology, people's requirements for display effects are getting higher and higher. The design of pixel circuits in display products is crucial for the display characteristics of AMOLED products. At present, how to improve the display characteristics of organic light-emitting display devices has become the research focus of organic light-emitting display devices. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display substrate and a display device.

[0005] At least one embodiment of the present disclosure provides a display substrate, including: a substrate; a plurality of sub-pixels located on the substrate, each sub-pixel including a light-emitting element and a pixel circuit, the light-emitting element including a first electrode, a light-emitting layer, and a second electrode stacked in sequence, the second electrode being located between the light-emitting layer and the substrate, the pixel circuit including a first connection portion, a driving transistor, and a threshold compensation transistor located between the second electrode and the substrate, the first connection portion extending in a first direction, a first pole of the threshold compensation transistor being electrically connected to a first pole of the driving transistor, and a second pole of the threshold compensation transistor being electrically connected to a gate of the driving transistor through the first connection portion. The plurality of sub-pixels include at least one first-color sub-pixel pair and a plurality of other-color sub-pixels, each first-color sub-pixel pair including a first pixel block and a second pixel block arranged in a second direction, a minimum distance between the first pixel block and the second pixel block in each first-color sub-pixel pair being not greater than a minimum distance between two same-color sub-pixels among the plurality of other-color sub-pixels, an included angle between the second direction and the first direction being in a range of 80° to 100°; the first pixel block including a first effective light-emitting area, the second pixel block including a second effective light-emitting area, in the first pixel block, a minimum distance between a positive projection of the first connection portion on a straight line extending in the second direction and a positive projection of the first effective light-emitting area on the straight line being a first distance, or the positive projection of the first connection portion on the straight line extending in the second direction overlapping with the positive projection of the first effective light-emitting area on the straight line; in the second pixel block, a minimum distance between a positive projection of the first connection portion on the straight line and a positive projection of the second effective light-emitting area on the straight line being a second distance, the first distance being less than the second distance; in the first pixel block, an overlapping area between a positive projection of the second electrode on the substrate and a positive projection of the first connection portion on the substrate being a first overlapping area, in the second pixel block, an overlapping area between a positive projection of the second electrode on the substrate and a positive projection of the first connection portion on the substrate being a second overlapping area, a ratio of the first overlapping area to the second overlapping area being 0.8 to 1.2.

[0006] For example, in an embodiment of the present disclosure, in the first pixel block, an area of the second electrode covering the first connection portion is 60% to 90%; in the second pixel block, an area of the second electrode covering the first connection portion is 60% to 90%.

[0007] For example, in an embodiment of the present disclosure, the display substrate further includes: data lines, which are disposed on the same layer as the first connection portion and extend along the first direction. The plurality of sub-pixels further include at least one second color sub-pixel, and the shape of the effective light-emitting region of each second color sub-pixel is a long strip extending along the second direction.

[0008] For example, in an embodiment of the present disclosure, in the first pixel block, the gate of the threshold compensation transistor is located on the side of the first connection portion away from the first effective light-emitting region; in the second pixel block, the gate of the threshold compensation transistor is located on the side of the first connection portion close to the second effective light-emitting region.

[0009] For example, in an embodiment of the present disclosure, the second electrode of each sub-pixel includes a main electrode and a connection electrode. In the first pixel block, the shape of the main electrode is substantially the same as the shape of the first effective light-emitting region, the orthographic projection of the first effective light-emitting region on the substrate is located within the orthographic projection of the main electrode on the substrate, and the first effective light-emitting region overlaps with the first connection portion; in the second pixel block, the shape of the main electrode is substantially the same as the shape of the second effective light-emitting region, the orthographic projection of the second effective light-emitting region on the substrate is located within the orthographic projection of the main electrode on the substrate, and the second effective light-emitting region does not overlap with the first connection portion.

[0010] For example, in an embodiment of the present disclosure, in the first color sub-pixel pair, the second electrode further includes an auxiliary electrode connecting the main electrode and the connection electrode. The connection electrode extends along the first direction. In the first pixel block, the auxiliary electrode is located on the side of the main electrode away from the second effective light-emitting region; in the second pixel block, the auxiliary electrode is located on the side of the main electrode away from the first effective light-emitting region.

[0011] For example, in an embodiment of the present disclosure, in the second pixel block, the straight line where the first edge, which extends along the first direction and is away from the second effective light-emitting region, of the edge of the portion of the connection electrode close to the auxiliary electrode intersects with the first connection portion, and the second edge, which is away from the second effective light-emitting region, of the auxiliary electrode is located on the side of the first connection portion away from the second effective light-emitting region so that the auxiliary electrode covers the first connection portion.

[0012] For example, in an embodiment of the present disclosure, the second edge extends along the first direction, and the straight line where the second edge is located is on the side of the straight line where the first edge is located away from the second effective light-emitting region.

[0013] For example, in an embodiment of the present disclosure, in the first pixel block, a straight line where a third edge of an edge extending along the first direction in a portion of the connection electrode close to the auxiliary electrode and away from the first effective light-emitting region is located on a side of the first connection portion away from the first effective light-emitting region.

[0014] For example, in an embodiment of the present disclosure, in the second pixel block, an edge of a portion of the auxiliary electrode close to the connection electrode and away from the second effective light-emitting region is not collinear with the first edge of the connection electrode; in the first pixel block, a fourth edge of a portion of the auxiliary electrode close to the connection electrode and away from the first effective light-emitting region is collinear with the third edge of the connection electrode.

[0015] For example, in an embodiment of the present disclosure, the pixel circuit of each sub-pixel further includes a first light-emitting control transistor and a second connection portion disposed on the same layer as the first connection portion. A first pole of the first light-emitting control transistor is electrically connected to a first pole of the driving transistor, a second pole of the first light-emitting control transistor is electrically connected to the connection electrode through the second connection portion. In the first pixel block, the second connection portion is farther away from the first effective light-emitting region than the first connection portion in the second direction; in the second pixel block, the second connection portion is closer to the second effective light-emitting region than the first connection portion in the second direction.

[0016] For example, in an embodiment of the present disclosure, the display substrate further includes: a planarization layer located between the film layer where the second connection portion is located and the film layer where the connection electrode is located. The planarization layer includes a plurality of vias penetrating therethrough, and the connection electrode in each sub-pixel is electrically connected to the second connection portion through the vias. The via corresponding to the first pixel block is farther away from the first effective light-emitting region than the first connection portion of the first pixel block in the second direction; the via corresponding to the second pixel block is closer to the second effective light-emitting region than the first connection portion of the second pixel block in the second direction.

[0017] For example, in an embodiment of the present disclosure, in the pixel circuit of each sub-pixel, the threshold compensation transistor includes a first gate and a second gate. In the first pixel block, the first gate is located on a side of the second gate close to the first effective light-emitting region. A straight line where the third edge of the connection electrode is located overlaps with the first gate, and an edge of a portion of the auxiliary electrode away from the connection electrode and away from the first effective light-emitting region in the second direction is located on a side of the first gate away from the first effective light-emitting region so that the auxiliary electrode covers at least a portion of the first gate.

[0018] For example, in an embodiment of the present disclosure, in the first pixel block, the auxiliary electrode includes a first portion and a second portion connected to each other. The first portion is connected to the connection electrode, the second portion covers at least a part of the first gate, an edge of the first portion extending in the first direction is on the same straight line as the third edge, and an edge of the second portion extending in the first direction is farther from the first effective light-emitting region in the second direction than the edge of the first portion extending in the first direction.

[0019] For example, in an embodiment of the present disclosure, the second portion is located on a side of the second gate away from the connection electrode in the first direction.

[0020] For example, in an embodiment of the present disclosure, in the first pixel block, the auxiliary electrode covers a part of the active layer between the positive projections of the first gate and the second gate on the active layer.

[0021] For example, in an embodiment of the present disclosure, the plurality of sub-pixels further includes at least one third-color sub-pixel. The shape of the effective light-emitting region of the third-color sub-pixel is a long strip extending in the second direction. The second electrode of the third-color sub-pixel further includes an auxiliary electrode located on a side of the main electrode away from the connection electrode and connected to the main electrode. In the third-color sub-pixel, the threshold compensation transistor includes a first gate and a second gate. The second gate is located on a side of the first gate close to the effective light-emitting region of the third-color sub-pixel in the first direction. The auxiliary electrode covers a part of the active layer between the positive projections of the second gate and the first gate on the active layer.

[0022] For example, in an embodiment of the present disclosure, the first color sub-pixel pair is a green sub-pixel pair, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0023] For example, in an embodiment of the present disclosure, the shapes of the first effective light-emitting region and the second effective light-emitting region include a pentagon, a circle, or a water droplet shape, and the shapes of the effective light-emitting regions of the second color sub-pixel and the third color sub-pixel include a hexagon or an ellipse.

[0024] For example, in an embodiment of the present disclosure, the display substrate further includes: a power supply signal line extending along the first direction, the power supply signal line being on the same layer as the data line and arranged alternately; a scan signal line extending along the second direction and located on a side of the film layer where the data line is located facing the substrate; a reset power supply signal line extending along the second direction and located between the film layer where the scan signal line is located and the film layer where the data line is located; a reset control signal line extending along the second direction and arranged on the same layer as the scan signal line; and a light emission control signal line extending along the second direction and arranged on the same layer as the scan signal line. The pixel circuit of each sub-pixel further includes a data writing transistor, a storage capacitor, a second light emission control transistor, a first reset transistor, and a second reset transistor. A first pole of the data writing transistor is electrically connected to a second pole of the driving transistor, a second pole of the data writing transistor is electrically connected to the data line, and a gate of the data writing transistor is electrically connected to the scan signal line; a first pole of the storage capacitor is electrically connected to the power supply signal line, a second pole of the storage capacitor is electrically connected to a gate of the driving transistor; a gate of the threshold compensation transistor is electrically connected to the scan signal line to receive a compensation control signal; a first pole of the first reset transistor is electrically connected to the reset power supply signal line, a second pole of the first reset transistor is electrically connected to a gate of the driving transistor, and a gate of the first reset transistor is electrically connected to the reset control signal line; a first pole of the second reset transistor is electrically connected to the reset power supply signal line, a second pole of the second reset transistor is electrically connected to a second electrode of the light emitting element, and a gate of the second reset transistor is electrically connected to the reset control signal line; a first pole of the second light emission control transistor is electrically connected to the power supply signal line, a second pole of the second light emission control transistor is electrically connected to a second pole of the driving transistor, and a gate of the second light emission control transistor is electrically connected to the light emission control signal line; a gate of the first light emission control transistor is electrically connected to the light emission control signal line.

[0025] For example, in an embodiment of the present disclosure, the data line includes a first data line, the power supply signal line includes a first power supply signal line, and in a direction perpendicular to the substrate, the second electrodes of the second color sub-pixels overlap with the first data line, the first power supply signal line, and the second connection portion. In the overlapping portions of the first data line, the first power supply signal line, and the second connection portion with the second electrode, the first power supply signal line and the first data line are located on both sides of the second connection portion, and the second connection portion includes a first sub-connection portion connected to each other and a first spacer located on the side of the first sub-connection portion close to the first power supply signal line. Both the first sub-connection portion and the first spacer overlap with the second electrode. In the first direction, the size of the first sub-connection portion is larger than the size of the first spacer, and the ratio of the minimum distance between the edges of the first sub-connection portion and the first data line close to each other to the minimum distance between the edges of the first spacer and the first power supply signal line close to each other is 0.8 to 1.2.

[0026] For example, in an embodiment of the present disclosure, a straight line passing through the midpoint of the line connecting the two endpoints of the effective light-emitting region of the second color sub-pixel opposite to each other in the second direction and extending in the first direction overlaps with the second connection portion.

[0027] For example, in an embodiment of the present disclosure, the data line further includes a second data line, the first data line and the second data line are alternately arranged, the power supply signal line further includes a second power supply signal line, the second power supply signal line and the first power supply signal line are alternately arranged, and in a direction perpendicular to the substrate, the second electrodes of the second color sub-pixels overlap with the first data line, the first power supply signal line, the second connection portion, the second data line, and the second power supply signal line. In the overlapping portions, the second power supply signal line is located on the side of the first data line away from the second connection portion, and the second data line is located on the side of the first power supply signal line away from the second connection portion.

[0028] For example, in an embodiment of the present disclosure, the shape of the first sub-connection portion is a rectangle extending in the first direction, and a straight line passing through the center of the effective light-emitting region of the second color sub-pixel and extending in the first direction is located on the side close to the first spacer of a straight line passing through the center of the first sub-connection portion and extending in the first direction.

[0029] For example, in an embodiment of the present disclosure, the pixel circuit further includes a third connection portion disposed on the same layer as the data line. The third connection portion extends along the first direction. A first pole of the first reset transistor is electrically connected to the reset power signal line through the third connection portion. Along a direction perpendicular to the substrate, an effective light-emitting region of the second color sub-pixel overlaps with the third connection portion, and a straight line passing through the center of the effective light-emitting region of the second color sub-pixel and extending along the first direction overlaps with the third connection portion. The second connection portion is located on one side of a straight line passing through the center of the effective light-emitting region of the second color sub-pixel and extending along the second direction, and at least a part of the third connection portion is located on the other side of this straight line.

[0030] For example, in an embodiment of the present disclosure, the display substrate further includes: an interlayer insulating layer located between the film layer where the data line is located and the substrate. In the third color sub-pixel, the connection electrode is connected to the second connection portion through a first via hole penetrating the planarization layer, and the second connection portion is electrically connected to the pixel circuit through a first connection hole penetrating the interlayer insulating layer. Along a direction perpendicular to the substrate, neither the first via hole nor the first connection hole overlaps with the main electrode, and the orthographic projections of the first via hole and the first connection hole on a first straight line extending along the first direction overlap.

[0031] For example, in an embodiment of the present disclosure, in the second color sub-pixel, the connection electrode is connected to the second connection portion through a second via hole penetrating the planarization layer. The first via hole is located on a side of the effective light-emitting region of the third color sub-pixel close to the effective light-emitting region of the second color sub-pixel in the first direction, and the second via hole is located on a side of the effective light-emitting region of the second color sub-pixel close to the effective light-emitting region of the third color sub-pixel in the first direction. A first connection line connecting the first via hole and the second via hole is not parallel to the second direction, and the second electrodes of the second color sub-pixel and the third color sub-pixel do not overlap in the second direction.

[0032] For example, in an embodiment of the present disclosure, in the second color sub-pixel, the second connection portion is electrically connected to the pixel circuit through a second connection hole penetrating the interlayer insulating layer, and a second connection line connecting the first connection hole and the second connection hole is parallel to the second direction.

[0033] For example, in an embodiment of the present disclosure, the effective light-emitting region of the second color sub-pixel includes a first long side and a second long side extending along the second direction, the second long side is located on a side of the first long side away from the second via hole, and along a direction perpendicular to the substrate, an extension line of the first long side overlaps with the first via hole; the effective light-emitting region of the third color sub-pixel includes a third long side and a fourth long side extending along the second direction, the fourth long side is located on a side of the third long side away from the first via hole, and along the third direction, an extension line of the third long side overlaps with the second via hole.

[0034] For example, in an embodiment of the present disclosure, in the first sub-pixel block, the second connection portion is electrically connected to the pixel circuit through a third connection hole penetrating through the interlayer insulating layer, in the second sub-pixel block, the second connection portion is electrically connected to the pixel circuit through a fourth connection hole penetrating through the interlayer insulating layer, and a connection line connecting the third connection hole and the fourth connection hole substantially coincides with the second connection line. At least one embodiment of the present disclosure provides a display device including the above display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0036] Figure 1 FIG. is a partial planar structure schematic diagram of a display substrate provided according to an embodiment of the present disclosure;

[0037] Figure 2 is Figure 1 an equivalent diagram of the pixel circuit of each sub-pixel shown;

[0038] Figure 3A FIG. is a partial planar structure schematic diagram of a stacked structure of an active semiconductor layer and a first conductive layer of a partial pixel circuit provided according to an embodiment of the present disclosure;

[0039] Figure 3B FIG. is a partial planar structure schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, and a second conductive layer provided according to an embodiment of the present disclosure;

[0040] Figure 3C FIG. is a schematic diagram of the positions of via holes in each insulating layer provided according to an embodiment of the present disclosure;

[0041] Figure 3D FIG. is a partial planar structure schematic diagram of a source-drain metal layer provided according to an embodiment of the present disclosure;

[0042] Figure 3ESchematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer provided according to an embodiment of the present disclosure;

[0043] Figure 4 Schematic diagram of the second electrode of the light-emitting element of each sub-pixel and the effective light-emitting area provided according to an embodiment of the present disclosure;

[0044] Figure 5A Schematic diagram of a stacked structure of the light-emitting element of each sub-pixel and the source-drain metal layer provided according to an embodiment of the present disclosure;

[0045] Figure 5B Schematic diagram of a stacked structure of the light-emitting element of each sub-pixel and the active semiconductor layer, the first conductive layer, and the source-drain metal layer provided according to an embodiment of the present disclosure;

[0046] Figure 5C Schematic diagram of a stacked structure of the light-emitting element of each sub-pixel and the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer provided according to an embodiment of the present disclosure;

[0047] Figure 5D Along Figure 5C Cross-sectional view taken along the line A1A2 shown;

[0048] Figure 5E Along Figure 5C Cross-sectional view taken along the line A3A4 shown;

[0049] Figure 5F Along Figure 5C Cross-sectional view taken along the line A5A6 shown;

[0050] Figure 5G Along Figure 5C Cross-sectional view taken along the line A7A8 shown;

[0051] Figure 5H Cross-sectional view taken along the line A9A10 shown in an example of an embodiment of the present disclosure; Figure 5C Cross-sectional view taken along the line A9A10 shown;

[0052] Figure 5I Cross-sectional view taken along the line A9A10 shown in another example of an embodiment of the present disclosure; Figure 5C Cross-sectional view taken along the line A9A10 shown;

[0053] Figure 5J Along Figure 5C Cross-sectional view taken along the line A11A12 shown;

[0054] Figure 6 Schematic diagram of a partial cross-sectional structure of a display substrate;

[0055] Figure 7FIG. 0 is a partial cross-sectional structural schematic diagram of another display substrate; and

[0056] Figure 8 FIG. 4 is a schematic diagram of a pixel arrangement structure in a display substrate. DETAILED DESCRIPTION

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0058] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and the like used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0059] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present disclosure include the strict "parallel", "perpendicular", "same" and other features, as well as the cases with certain errors such as "substantially parallel", "substantially perpendicular", and "substantially same". Considering the measurement and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measurement system), it means within the acceptable deviation range for a specific value determined by those of ordinary skill in the art. The "center" in the embodiments of the present disclosure may include the position strictly located at the geometric center and the position of the approximate center within a small area around the geometric center. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0060] In the research, the inventors of the present application found that in the GGRB pixel arrangement structure, each pixel includes a red sub-pixel, a blue sub-pixel, and a pair of green sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. When there is a difference in the gate node load of the driving transistors included in the pixel circuits of the two green sub-pixels included in the pair of green sub-pixels, it will cause a difference in the brightness when the two green sub-pixels included in the pair of green sub-pixels emit light.

[0061] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a substrate and a plurality of sub-pixels located on the substrate. Each sub-pixel includes a light-emitting element and a pixel circuit. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode which are sequentially stacked. The second electrode is located between the light-emitting layer and the substrate. The pixel circuit includes a first connection portion, a driving transistor, and a threshold compensation transistor located between the second electrode and the substrate. The first connection portion extends in a first direction. A first pole of the threshold compensation transistor is electrically connected to a first pole of the driving transistor. A second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor through the first connection portion. The plurality of sub-pixels include at least one pair of first-color sub-pixels and a plurality of other-color sub-pixels. Each pair of first-color sub-pixels includes a first pixel block and a second pixel block arranged in a second direction. A minimum distance between the first pixel block and the second pixel block in each pair of first-color sub-pixels is not greater than a minimum distance between two same-color sub-pixels among the plurality of other-color sub-pixels. An included angle between the second direction and the first direction is in a range of 80° to 100°. The first pixel block includes a first effective light-emitting region. The second pixel block includes a second effective light-emitting region. In the first pixel block, a minimum distance between a positive projection of the first connection portion on a straight line extending in the second direction and a positive projection of the first effective light-emitting region on the straight line is a first distance, or the positive projection of the first connection portion on the straight line extending in the second direction and the positive projection of the first effective light-emitting region on the straight line overlap. In the second pixel block, a minimum distance between a positive projection of the first connection portion on the straight line and a positive projection of the second effective light-emitting region on the straight line is a second distance, and the first distance is less than the second distance. In the first pixel block, an overlapping area between a positive projection of the second electrode on the substrate and a positive projection of the first connection portion on the substrate is a first overlapping area. In the second pixel block, an overlapping area between a positive projection of the second electrode on the substrate and a positive projection of the first connection portion on the substrate is a second overlapping area. A ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2. In the embodiments of the present disclosure, in two first-color sub-pixels included in a pair of first-color sub-pixels, a ratio of overlapping areas between second electrodes of two light-emitting elements and corresponding two first connection portions is 0.8 to 1.2, which can reduce a load difference of gate nodes of driving transistors in the two first-color sub-pixels, thereby reducing a brightness difference between the two first-color sub-pixels to improve display characteristics of the display substrate.

[0062] The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the drawings.

[0063] Figure 1 FIG. is a partial plan structure schematic diagram of a display substrate provided according to an embodiment of the present disclosure. As Figure 1 shown, the display substrate includes a substrate 1 and a plurality of sub-pixels 10 located on the substrate 1. For example, as Figure 1As shown, a plurality of sub-pixels 10 are arranged into a plurality of repeating units 20. Each repeating unit 20 includes a second-color sub-pixel 200, a pair of first-color sub-pixels 100, and a third-color sub-pixel 300 arranged along a first direction (the X direction shown in the figure). The pair of first-color sub-pixels 100 includes two first-color sub-pixels 110 and 120 arranged along a second direction (the Y direction shown in the figure, a direction different from the first direction). The plurality of repeating units 20 are arranged along the first direction to form a plurality of repeating unit groups. The plurality of repeating unit groups are arranged along the second direction, and adjacent repeating unit groups among the plurality of repeating unit groups are offset from each other along the first direction, that is, there is a certain offset amount between adjacent repeating unit groups along the first direction. Therefore, sub-pixels of the same color in adjacent repeating unit groups are not aligned in the second direction. The pixel arrangement patterns in odd-numbered repeating unit groups are the same, and the pixel arrangement patterns in even-numbered repeating unit groups are the same.

[0064] For example, the offset amount between adjacent repeating unit groups in the first direction is approximately half of the size of the repeating unit 20 in the first direction. For example, the size of the repeating unit 20 in the first direction is the pitch of the repeating unit 20 in the first direction. Here, the pitch refers to the distance between the centers of the effective light-emitting regions of two second-color sub-pixels 200 in two adjacent repeating units 20 along the first direction. Here, the center of the effective light-emitting region refers to the geometric center of the planar shape of the effective light-emitting region.

[0065] For example, the above-mentioned second direction and the first direction are respectively two directions in the same plane, and the included angle between the two directions is in the range of 80° to 100°. For example, this plane is the plane on which the pixels are arranged. Here, the repeating unit only refers to the repetition of sub-pixels, and other structures can be different or the same. In addition, the above-mentioned repetition means that the approximate positions, shapes, and sizes are similar. In some cases, for the needs of wiring or opening holes, the shapes are slightly different, such as having openings at different positions.

[0066] For example, as Figure 1 shown, the shape of the effective light-emitting region 201 of the second-color sub-pixel 200 is a long strip extending along the second direction. For example, the shape of the effective light-emitting region 301 of the third-color sub-pixel 300 is a long strip extending along the second direction. For example, the display substrate further includes a data line 420 located on the substrate 1, and the data line 420 extends along the first direction. Thus, the included angle between the extending direction of the effective light-emitting region of the second-color sub-pixel and the extending direction of the data line is in the range of 80° to 100°. When the extending direction of the opening of the fine metal mask (FMM) used for evaporating each color sub-pixel and the extending direction of the data line have an included angle in the range of 80° to 100°, for example, 90°, the extending direction of the effective light-emitting region of the second-color sub-pixel is the same as the extending direction of the FMM opening.

[0067] For example, as Figure 1 shown, the shapes of the effective light-emitting regions 201 and 301 of the second color sub-pixels 200 and the third color sub-pixels 300 include hexagons or ellipses. In addition, although the shapes of the second color sub-pixels and the third color sub-pixels in the figure include angles strictly formed by two line segments, in some embodiments, the shapes of the effective light-emitting regions of the second color sub-pixels and the third color sub-pixels can both be rounded-corner figures, such as ellipses. That is, based on the above-mentioned hexagon shape, the corners of the effective light-emitting regions of the second color sub-pixels and the third color sub-pixels are rounded. For example, when forming the opening of the pixel defining layer, the part at the corner of the opening will form a rounded-corner shape, so that the shape of the formed effective light-emitting region is a rounded-corner shape. The hexagons in the embodiments of the present disclosure can include standard hexagons or approximate hexagons, for example, rounded-corner hexagons and other generally hexagonal shapes with a hexagon outline.

[0068] For example, the embodiments of the present disclosure schematically show that the first color sub-pixel pair 100 is a green sub-pixel pair, the second color sub-pixel 200 is a red sub-pixel, and the third color sub-pixel 300 is a blue sub-pixel. However, it is not limited thereto, and the names of the color sub-pixels can be interchanged. In the embodiments of the present disclosure, the sub-pixel pair including two identical color sub-pixels is the green sub-pixel pair; along the extension direction of the data line, the width of the effective light-emitting region of the red sub-pixel is less than the width of the effective light-emitting region of the blue sub-pixel; the length of the effective light-emitting region of the red sub-pixel is greater than the length of the effective light-emitting region of the blue sub-pixel.

[0069] For example, Figure 2 is Figure 1 the equivalent diagram of the pixel circuits of the sub-pixels shown. As Figure 2 shown, each sub-pixel 10 includes a light-emitting element 11 and a pixel circuit 12 for driving the light-emitting element 11 to emit light. The light-emitting element 11 includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence, and the second electrode is located between the light-emitting layer and the substrate. For example, Figure 5E schematically shows that the light-emitting element includes a first electrode 310, a light-emitting layer 330, and a second electrode 320, and the second electrode 320 is located between the light-emitting layer 330 and the substrate 1. For example, the display substrate further includes a reset power signal line, a scan signal line, a power signal line, a reset control signal line, and a light-emitting control signal line located on the substrate 1. For example, in the embodiments of the present disclosure, the names of the first electrode and the second electrode can be interchanged.

[0070] For example, as Figure 2As shown, each pixel circuit 12 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. A first pole of the threshold compensation transistor T2 is connected to a first pole of the driving transistor T3, and a second pole of the threshold compensation transistor T2 is connected to a gate of the driving transistor T3; a first pole of the first reset control transistor T7 is connected to a reset power signal line to receive a reset signal Vinit, and a second pole of the first reset control transistor T7 is connected to the light emitting unit; a first pole of the data writing transistor T4 is connected to a second pole of the driving transistor T3. For example, as Figure 2 shown, the pixel circuit of each sub-pixel further includes a storage capacitor C, a first light emitting control transistor T6, a second light emitting control transistor T5, and a second reset transistor T1. A gate of the data writing transistor T4 is electrically connected to a scan signal line to receive a scan signal Gate; a first pole of the storage capacitor C is electrically connected to a power signal line, and a second pole of the storage capacitor C is electrically connected to a gate of the driving transistor T3; a gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive a compensation control signal; a gate of the first reset transistor T7 is electrically connected to a reset control signal line to receive a reset control signal Reset(N+1); a first pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive a reset signal Vinit, a second pole of the second reset transistor T1 is electrically connected to a gate of the driving transistor T3, and a gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive a reset control signal Reset(N); a gate of the first light emitting control transistor T6 is electrically connected to a light emitting control signal line to receive a light emitting control signal EM; a first pole of the second light emitting control transistor T5 is electrically connected to the power signal line to receive a first power signal VDD, a second pole of the second light emitting control transistor T5 is electrically connected to a second pole of the driving transistor T3, a gate of the second light emitting control transistor T5 is electrically connected to the light emitting control signal line to receive a light emitting control signal EM, and a first electrode of the light emitting element 11 is connected to a voltage terminal VSS. The above-mentioned power signal line refers to a signal line for outputting a voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0071] For example, the scan signal and the compensation control signal can be the same. That is, the gates of the data writing transistor T3 and the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gates of the data writing transistor T3 and the threshold compensation transistor T2 can also be electrically connected to different signal lines respectively. That is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, so that the gates of the data writing transistor T3 and the threshold compensation transistor T2 can be separately controlled, increasing the flexibility of controlling the pixel circuit.

[0072] For example, the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 can be the same. That is, the gates of the first light emission control transistor T6 and the second light emission control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gates of the first light emission control transistor T6 and the second light emission control transistor T5 can also be electrically connected to different light emission control signal lines respectively, and the signals transmitted by the different light emission control signal lines can be the same or different.

[0073] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same. That is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gates of the first reset transistor T7 and the second reset transistor T1 can also be electrically connected to different reset control signal lines respectively. At this time, the signals on the different reset control signal lines can be the same or different.

[0074] For example, as Figure 2 shown, when the display substrate is working, in the first stage of the screen display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage of the screen display, the data is stored in the N1 node through the data writing transistor T4, the driving transistor T3, and the threshold compensation transistor T2; in the third light emission stage, the second light emission control transistor T5, the driving transistor T3, and the first light emission control transistor T6 are all turned on, and the light emitting element is forward-conducted to emit light.

[0075] It should be noted that in the embodiments of the present disclosure, the pixel circuit of the sub-pixel can be Figure 2In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, structures including other numbers of transistors may also be used, such as 7T2C structure, 6T1C structure, 6T2C structure, or 9T2C structure. The embodiments of the present disclosure do not limit this. As long as the data writing transistors T4 of two pixel circuits are connected, and the N4 nodes of two pixel circuits are connected to commonly drive the same light emitting unit to emit light.

[0076] Figure 3A FIG. is a partial planar structure schematic diagram of the active semiconductor layer and the first conductive layer stack structure of a part of the pixel circuit provided according to the embodiments of the present disclosure. As Figure 3A shown, the active semiconductor layer 3100 can be formed by patterning a semiconductor material. The active semiconductor layer 3100 can be used to fabricate the active layers of the above-mentioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light emitting control transistor T5, first light emitting control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes the active layer patterns (channel regions) and doping region patterns (source / drain doping regions) of the transistors in each sub-pixel, and the active layer patterns and doping region patterns of the transistors in the same pixel circuit are integrally provided.

[0077] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region can be made conductive through doping and other means to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor in each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doping region pattern (i.e., the source region and the drain region) and an active layer pattern, and the active layers of different transistors are separated by a doping structure.

[0078] For example, the active semiconductor layer 3100 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0079] For example, the display substrate includes a gate insulating layer located on the side of the active semiconductor layer away from the substrate, which is used to insulate the above-mentioned active semiconductor layer 3100 from the first conductive layer 3200 (i.e., the gate metal layer) formed subsequently. For example, the display substrate includes a first conductive layer 3200, and the first conductive layer 3200 is disposed on the gate insulating layer, so as to be insulated from the active semiconductor layer 3100. The first conductive layer 3200 may include the second pole CC2 of the capacitor C, a plurality of scan signal lines 430 extending along the second direction (the Y direction in the figure), a plurality of reset control signal lines 440, a plurality of light emission control signal lines 450, and the gates of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the first reset control transistor T7.

[0080] For example, as Figure 3A shown, the gate of the data writing transistor T3 may be the overlapping portion of the scan signal line 430 and the active semiconductor layer 3100; the gate of the first light emission control transistor T6 may be the first overlapping portion of the light emission control signal line 450 and the active semiconductor layer 3100, and the gate of the second light emission control transistor T5 may be the second overlapping portion of the light emission control signal line 450 and the active semiconductor layer 3100. The gate of the second reset transistor T1 is the first overlapping portion of the reset control signal line 440 and the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is the second overlapping portion of the reset control signal line 440 and the active semiconductor layer 3100. The threshold compensation transistor T2 may be a thin film transistor with a double gate structure. The first gate T2-g1 of the threshold compensation transistor T2 may be the overlapping portion of the protruding structure P protruding from the scan signal line 430 and the active semiconductor layer 3100, and the second gate T2-g2 of the threshold compensation transistor T2 may be the overlapping portion of the scan signal line 430 and the active semiconductor layer 3100. As Figure 3A shown, the gate of the driving transistor T1 may be the second pole CC2 of the capacitor C.

[0081] It should be noted that Figure 3A each of the dashed rectangular boxes in shows the overlapping portions of the active semiconductor layer 3100 and the first conductive layer 3200, that is, the channel regions. As the channel regions of the respective transistors, the active semiconductor layers on both sides of each channel region are made conductive through processes such as ion doping as the first pole and the second pole of the respective transistors. The source and drain of the transistor may be symmetric in structure, so there may be no physical difference between its source and drain. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control pole, one of the poles is directly described as the first pole and the other as the second pole. Therefore, the first pole and the second pole of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0082] For example, as Figure 3A shown, the scan signal line 430, the reset control signal line 440, and the light emission control signal line 450 are arranged along the first direction (X direction). The scan signal line 430 is located between the reset control signal line 440 and the light emission control signal line 450.

[0083] For example, in the first direction, the second pole CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scan signal line 430 and the light emission control signal line 450. The protruding structure P protruding from the scan signal line 430 is located on the side of the scan signal line 430 away from the light emission control signal line 450.

[0084] For example, a first insulating layer is formed on the first conductive layer 3200 described above to insulate the first conductive layer 3200 from the second conductive layer 3300 formed subsequently.

[0085] Figure 3B It is a partial plan view structure diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the second conductive layer provided according to an embodiment of the present disclosure. As Figure 3B shown, the second conductive layer 330 includes the first pole CC1 of the capacitor C and a plurality of reset power signal lines 410 extending along the second direction. The first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.

[0086] For example, the second conductive layer 330 further includes a plurality of covering portions S. Each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and the active semiconductor layer 3100 located between the positive projections of the two gates on the active semiconductor layer 3100. Along the direction perpendicular to the substrate, the covering portion S overlaps with the active semiconductor layer 3100 between the two gates.

[0087] For example, a second insulating layer is formed on the second conductive layer 3300 described above to insulate the second conductive layer 3300 from the source-drain metal layer 3400 formed subsequently.

[0088] For example, Figure 3C It is a schematic diagram of the via positions in each insulating layer provided according to an embodiment of the present disclosure, Figure 3D It is a partial plan view structure diagram of the source-drain metal layer provided according to an embodiment of the present disclosure, Figure 3E It is a stacked structure diagram of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer provided according to an embodiment of the present disclosure. As Figures 3C to 3E shown, the source-drain metal layer 3400 includes a data line 420 and a power signal line 460 extending along the second direction. The data line 420 passes through the gate insulating layer 2 ( Figures 5D to 5H shown), the first insulating layer 3 (Figures 5D to 5H as shown) and the via hole 3005 of the second insulating layer 4( Figures 5D to 5H as shown) is electrically connected to the second pole of the data writing transistor T2. The power supply signal line 460 is electrically connected to the first pole of the second light-emitting control transistor T5 through the via hole 3009 penetrating through the gate insulating layer 2, the first insulating layer 3, and the second insulating layer 4. The power supply signal line 460 and the data line 420 are alternately arranged in the first direction. The power supply signal line 460 is electrically connected to the first pole CC1 of the capacitor C (for example, the first pole 120-CC1 of the capacitor C of the second pixel block 120, or the first pole 300-CC1 of the capacitor C of the third color sub-pixel 300) through the via hole 3007 penetrating through the second insulating layer 4. For example, the above-mentioned second insulating layer 4 is an interlayer insulating layer.

[0089] For example, the double-gate type threshold compensation transistor can reduce the leakage current. For example, the active semiconductor layer between the two channels of the double-gate type threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is vulnerable to the influence of the surrounding line voltage and jumps, which will affect the leakage current of the threshold compensation transistor T2, and further affect the light emission brightness. In order to keep the voltage of the active semiconductor layer between the two channels of the threshold compensation transistor T2 stable, the covering portion S is designed to form a capacitor with the active semiconductor layer between the two channels of the threshold compensation transistor T2. The covering portion S can be connected to the power supply signal line 460 to obtain a constant voltage. Therefore, the voltage of the active semiconductor layer in the floating state can be kept stable. The covering portion S overlaps with the active semiconductor layer between the two channels of the double-gate type threshold compensation transistor T2, and can also prevent the active semiconductor layer between the two gates from being illuminated and changing its characteristics. For example, it can prevent the voltage of this part of the active semiconductor layer from changing to prevent crosstalk. For example, as Figures 3C to 3E shown, the power supply signal line 460 can be electrically connected to the covering portion S through the via hole 3003 penetrating through the second insulating layer to provide a constant voltage for the covering portion S.

[0090] For example, a passivation layer 5 and a planarization layer 6( Figures 5D to 5H as shown) can be sequentially arranged on the side of the above-mentioned source-drain metal layer 3400 away from the substrate. For example, the planarization layer 6 can be located on the side of the passivation layer 5 away from the substrate. Of course, the embodiments of the present disclosure are not limited thereto. For example, the positions of the planarization layer 6 and the passivation layer 5 can be interchanged, that is, the passivation layer can be located on the side of the planarization layer away from the source-drain metal layer, or, as Figure 5I shown, only the planarization layer 6 is provided and the passivation layer 5 is not provided.

[0091] For example, as Figures 3C to 3E , Figure 5DAs shown, the pixel circuit of each sub-pixel further includes a first connection portion 510 disposed on the same layer as the data line 420, and the first connection portion 510 extends in the first direction. The second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connection portion 510. The first end of the first connection portion 510 is connected to the second pole of the threshold compensation transistor T2 (such as the second pole 110-T2-2 of the threshold compensation transistor T2 in the first pixel block 110, or the second pole 120-T2-2 of the threshold compensation transistor T2 in the second pixel block 120, or the second pole 200-T2-2 of the threshold compensation transistor T2 in the second color sub-pixel 200) through a via 3004 penetrating the gate insulating layer 2, the first insulating layer 3, and the second insulating layer 4. The second end of the first connection portion 510 is connected to the gate of the driving transistor T3 (such as the gate 110-T3-g of the driving transistor T3 in the first pixel block 110, or the gate 120-T3-g of the driving transistor T3 in the second pixel block 120) through a via 3006 penetrating the first insulating layer 3 and the second insulating layer 4. The pixel circuit of each sub-pixel further includes a second connection portion 520 and a third connection portion 530 disposed on the same layer as the data line 420. The second connection portion 520 is connected to the second pole of the first light-emitting control transistor T6 through a via 3008 penetrating the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3. One end of the third connection portion 530 is connected to the first pole of the first reset transistor T7 through a via 3002 penetrating the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3. The other end of the third connection portion 530 is connected to the reset power signal line 410 through a via 3001 penetrating the second insulating layer. For example, the first connection portion 510 overlaps with the first pole CC1 of the capacitor C (such as the first pole 110-CC1 in the first pixel block 110, or the first pole 120-CC1 in the second pixel block 120).

[0092] For example, Figure 4 Schematic diagram of the second electrode and the effective light-emitting region of the light-emitting element of each sub-pixel provided according to an embodiment of the present disclosure Figure 5A Schematic diagram of the laminated structure of the light-emitting element and the source-drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure Figure 5B Schematic diagram of the laminated structure of the light-emitting element and the active semiconductor layer, the first conductive layer, and the source-drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure Figure 5C Schematic diagram of the laminated structure of the light-emitting element and the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure. As Figures 4 to 5CAs shown, each pair of first-color sub-pixels 100 includes a first pixel block 110 and a second pixel block 120 arranged along the second direction (Y direction). The first pixel block 110 includes a first effective light-emitting region 101, and the second pixel block 120 includes a second effective light-emitting region 102. In the first pixel block 110, the minimum distance between the orthographic projection of the first connection portion 510 on a straight line extending along the second direction and the orthographic projection of the first effective light-emitting region 101 on the straight line is the first distance, or the orthographic projection of the first connection portion 510 on the straight line extending along the second direction overlaps with the orthographic projection of the first effective light-emitting region 101 on the straight line; in the second pixel block 120, the minimum distance between the orthographic projection of the first connection portion 510 on the straight line and the orthographic projection of the second effective light-emitting region 102 on the straight line is the second distance, and the first distance is less than the second distance. In the first pixel block 110, the overlapping area between the orthographic projection of the second electrode 112 on the substrate and the orthographic projection of the first connection portion 510 on the substrate is the first overlapping area; in the second pixel block 120, the overlapping area between the orthographic projection of the second electrode 122 on the substrate and the orthographic projection of the first connection portion 510 on the substrate is the second overlapping area. The ratio of the first overlapping area to the second overlapping area is, for example, 0.8 to 1.2, and for example, 0.9 to 1.1.

[0093] In an embodiment of the present disclosure, the display substrate further includes other color sub-pixels, and the minimum distance between the first pixel block and the second pixel block in each pair of first-color sub-pixels is not greater than the minimum distance between two same-color sub-pixels among the plurality of other color sub-pixels. For example, if the pair of first-color sub-pixels is a pair of green sub-pixels and the other color sub-pixels include red sub-pixels, then the minimum distance between the two green sub-pixels in the pair of green sub-pixels is less than the minimum distance between the two red sub-pixels.

[0094] For example, in the first pixel block 110, the minimum distance between the center of the orthographic projection of the first connection portion 510 on a straight line extending along the second direction and the center of the orthographic projection of the first effective light-emitting region 101 on the straight line is the first distance; in the second pixel block 120, the minimum distance between the center of the orthographic projection of the first connection portion 510 on the straight line and the center of the orthographic projection of the second effective light-emitting region 102 on the straight line is the second distance, and the first distance is less than the second distance.

[0095] In the first color sub-pixel pair, when the distance between the geometric center of the first effective light-emitting region and the edge of the first connection portion of the first pixel block close to the first effective light-emitting region is not equal to the distance between the geometric center of the second effective light-emitting region and the edge of the first connection portion of the second pixel block close to the second effective light-emitting region, it is easy to have different areas of the two first connection portions in the two first color sub-pixels covered by the two second electrodes, resulting in different capacitances formed between the first connection portions and the second electrodes in the two first color sub-pixels of the same first color sub-pixel pair. Furthermore, there are differences in the gate node loads of the driving transistors in the two first color sub-pixels, and there are differences in the brightness when the two first color sub-pixels emit light.

[0096] In the embodiments of the present disclosure, the ratio of the overlapping areas of the two second electrodes and the two first connection portions in the two first color sub-pixels of the same first color sub-pixel pair is set to 0.8 to 1.2, for example, 0.9 to 1.1. For example, the ratios of the overlapping areas of the two second electrodes and the two first connection portions in the two first color sub-pixels of the same first color sub-pixel pair are substantially equal, which can minimize the differences in the gate node loads of the driving transistors in the two first color sub-pixels to ensure that the brightnesses of the two first color sub-pixels when emitting light are as similar as possible.

[0097] For example, the ratio of the first overlapping area to the second overlapping area is 1, that is, the two overlapping areas are exactly the same, so as to ensure that the brightnesses of the two first color sub-pixels when emitting light are the same.

[0098] For example, in the first pixel block 110, the second electrode 112 covers 60 to 90% of the area of the first connection portion 510; in the second pixel block 120, the second electrode 122 covers 60 to 90% of the area of the first connection portion 510. For example, in the first pixel block 110, the second electrode 112 covers 70 to 80% (the benefits of covering these areas) of the area of the first connection portion 510; in the second pixel block 120, the second electrode 122 covers 70 to 80% of the area of the first connection portion 510. For example, considering that there is a certain distance between the second electrode of the second pixel block and the second electrode of the third color sub-pixel (described later), the area of the first connection portion covered by the second electrode of the second pixel block cannot be too large, for example, 70%. In order to ensure that the area of the first connection portion covered by the second electrode of the first pixel block is substantially the same as the area of the first connection portion covered by the second electrode of the second pixel block, the area of the first connection portion covered by the second electrode of the first pixel block is set to, for example, 70%.

[0099] For example, as Figures 4 to 5C shown, the relative positional relationship between the gate of the threshold compensation transistor T2 and the first connection portion 510 in each pixel circuit is basically the same. For example, the first connection portion 510 is located between the gate of the threshold compensation transistor T2 and the second pole of the data writing transistor T4.

[0100] For example, the shapes and sizes of the two effective light-emitting regions in the first color sub-pixel pair 100 are substantially the same, and are axially symmetrically distributed about a straight line passing through the midpoint of the line connecting the centers of the two effective light-emitting regions and extending in the first direction as the central axis.

[0101] For example, the shapes of the first effective light-emitting region 101 and the second effective light-emitting region 102 may include a pentagon, a circle, or a water droplet shape. For example, the shapes of the first effective light-emitting region 101 and the second effective light-emitting region 102 may be pentagons. The pentagon includes a set of parallel opposite sides (parallel to the second direction) and a vertical side (parallel to the first direction). The vertical side is perpendicular to the set of parallel opposite sides. The two vertical sides of the two effective light-emitting regions in each first color sub-pixel pair 100 are adjacent to each other, and each pentagon includes a sharp corner opposite to the vertical side. The two sharp corners of the two effective light-emitting regions in each first color sub-pixel pair 100 are away from each other. For example, the distance between the two sharp corners of the two effective light-emitting regions in the first color sub-pixel pair 100 is greater than the length of the effective light-emitting regions of the second color sub-pixel 200 and the third color sub-pixel 300.

[0102] In addition, although the shape of the effective light-emitting region of the first color sub-pixel in the figure includes a strictly formed angle by two line segments, in some embodiments, the shapes of the effective light-emitting regions of the first color sub-pixels may all be rounded corner figures, such as a circle or a water droplet shape. That is, on the basis of the above pentagon shape, the corners of the effective light-emitting regions of the first color sub-pixels are rounded. For example, when forming the opening of the pixel defining layer, the part at the corner of the opening will form a rounded corner shape, so that the shape of the formed light-emitting region is a rounded corner shape.

[0103] For example, as Figures 4 to 5C shown, the first effective light-emitting region 101 and the second effective light-emitting region 102 are located between the two first connection portions 510 in the first color sub-pixel pair 100, and the perpendicular bisector M1 of the line connecting the midpoints of the two vertical sides of the first effective light-emitting region 101 and the second effective light-emitting region 102 is located on the side of the perpendicular bisector M2 of the line connecting the midpoints of the two first connection portions 510 close to the first connection portion 510 of the first pixel block 110. Thus, the distance from the center of the first effective light-emitting region to the corresponding first connection portion is less than the distance from the center of the second effective light-emitting region to the corresponding first connection portion.

[0104] For example, as Figures 4 to 5CAs shown, in the first pixel block 110, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 away from the first effective light-emitting region 101. That is, in the first pixel block 110, the first connection portion 510 is closer to the first effective light-emitting region 101 than the gate of the threshold compensation transistor T2. In the second pixel block 120, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 close to the second effective light-emitting region 102. That is, in the second pixel block 120, the gate of the threshold compensation transistor T2 is closer to the second effective light-emitting region 102 than the first connection portion 510. Thus, the distance from the first connection portion of the second pixel block to the center of the second effective light-emitting region is greater than the distance from the first connection portion of the first pixel block to the first effective light-emitting region.

[0105] For example, as Figures 4 to 5C shown, the maximum length of the second electrode 122 of the second pixel block 120 in the second direction is greater than the maximum length of the second electrode 112 of the first pixel block 110 in the second direction, so that the overlapping areas of the second electrodes of the two first-color sub-pixels with the corresponding first connection portions are substantially equal.

[0106] For example, as Figures 4 to 5C shown, the second electrode of each sub-pixel includes a main electrode and a connection electrode. For example, the second electrode 112 in the first pixel block 110 includes a main electrode 1121 and a connection electrode 1122. The shape of the main electrode 1121 is substantially the same as the shape of the first effective light-emitting region 101, such as a pentagon. For example, the orthographic projection of the first effective light-emitting region on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, the orthographic projection of the main electrode 1121 on the substrate overlaps with the orthographic projection of the first connection portion 510 on the substrate. For example, the second electrode 122 in the second pixel block 120 includes a main electrode 1221 and a connection electrode 1122. The shape of the main electrode 1221 is substantially the same as the shape of the second effective light-emitting region 102, such as a pentagon. For example, the orthographic projection of the second effective light-emitting region on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, the orthographic projection of the main electrode 1221 on the substrate does not overlap with the orthographic projection of the first connection portion 510 on the substrate.

[0107] For example, as Figures 4 to 5C shown, in the first-color sub-pixel pair 100, the second electrode further includes an auxiliary electrode connecting the main electrode and the connection electrode. For example, the second electrode 112 in the first pixel block 110 further includes an auxiliary electrode 1123 connecting the main electrode 1121 and the connection electrode 1122. The connection electrode 1122 extends in the first direction. For example, the second electrode 121 in the second pixel block 120 further includes an auxiliary electrode 1223 connecting the main electrode 1221 and the connection electrode 1222.

[0108] For example, asFigures 4 to 5C As shown, in the first pixel block 110, the auxiliary electrode 1123 is located on the side of the main electrode 1121 away from the second effective light-emitting region 102. In the second pixel block 120, the auxiliary electrode 1223 is located on the side of the main electrode 1221 away from the first effective light-emitting region 101. That is, the two auxiliary electrodes of the first color sub-pixel pair are located on the sides of the two effective light-emitting regions away from each other.

[0109] For example, as Figures 4 to 5C shown, the second electrodes in each of the first color sub-pixels are of an integral structure, that is, the second electrode includes a main electrode, an auxiliary electrode, and a connecting electrode that are of an integral structure. In the embodiments of the present disclosure, for the sake of clearly describing the shape of the second electrode in the first color sub-pixel and its relationship with other structures, the second electrode in the first color sub-pixel is divided into a main electrode, an auxiliary electrode, and a connecting electrode.

[0110] For example, as Figures 4 to 5C shown, in the first color sub-pixel pair 100, the shapes and sizes of the two main electrodes 1121 and 1221 are substantially the same, the shapes of the two auxiliary electrodes 1123 and 1223 are different, and the shapes of the two connecting electrodes 1122 and 1222 are different.

[0111] For example, as Figures 4 to 5C shown, for example, the first edge 1001 of the edge extending in the first direction in the part of the connecting electrode 1222 close to the auxiliary electrode 1223 and away from the second effective light-emitting region 102 overlaps with the orthographic projection of the first connecting portion 510 on the substrate. For example, in the second pixel block 120, the second edge 1002 of the part of the auxiliary electrode 1223 away from the connecting electrode and away from the second effective light-emitting region 102 in the Y direction is located on the side of the first connecting portion 510 away from the second effective light-emitting region 102 so that the auxiliary electrode 1223 covers at least part of the first connecting portion 510. For example, the part of the connecting electrode 1222 away from the auxiliary electrode 1223 is configured to be connected to the second connecting portion 520. According to the size of the via hole provided in the planarization layer, the width of the part of the connecting electrode 1222 away from the auxiliary electrode 1223 in the Y direction is greater than the width of the part of the connecting electrode 1222 close to the auxiliary electrode 1223 in the Y direction. Thus, the edge of the part of the connecting electrode 1222 away from the auxiliary electrode 1223 and extending in the first direction and away from the second effective light-emitting region 102 is not in a straight line with the first edge 1001.

[0112] For example, as Figures 4 to 5CAs shown, in the first pixel block 110, for the portion of the connection electrode 1122 near the auxiliary electrode 1123, the third edge 1003 of the edge extending in the first direction and away from the first effective light-emitting region 101 is located on the side of the first connection portion 510 away from the first effective light-emitting region 101. For example, the positive projection of the third edge 1003 of the portion of the connection electrode 1122 near the auxiliary electrode 1123 on the substrate does not overlap with the positive projection of the first connection portion 510 on the substrate. For example, the portion of the connection electrode 1122 away from the auxiliary electrode 1123 is configured to be connected to the second connection portion 520. According to the size of the vias provided in the planarization layer, the width of the portion of the connection electrode 1122 away from the auxiliary electrode 1123 in the Y direction is greater than the width of the portion of the connection electrode 1122 near the auxiliary electrode 1123 in the Y direction. Thus, the edge of the portion of the connection electrode 1122 away from the auxiliary electrode 1123 and extending in the first direction and away from the first effective light-emitting region 101 is not in a straight line with the third edge 1003.

[0113] For example, as Figures 4 to 5C shown, in the first pixel block 110, the fourth edge 1004 of the portion of the auxiliary electrode 1123 in contact with the connection electrode 1122 (such as the first part 1123-1 of the auxiliary electrode 1123 described later) and away from the first effective light-emitting region 101 is in the same straight line as the third edge 1003 of the connection electrode 1122 to facilitate the fabrication of the second electrode.

[0114] For example, in the second pixel block 120, the edge of the portion of the auxiliary electrode 1223 near the connection electrode 1222 and away from the second effective light-emitting region 102 is not in a straight line with the first edge 1001 of the connection electrode 1222. For example, in the second pixel block 120, the second edge 1002 of the portion of the auxiliary electrode 1223 away from the connection electrode 1222 and extending in the first direction and away from the second effective light-emitting region 102 is not in a straight line with the first edge 1001 of the connection electrode 1222. For example, in the second pixel block 120, the straight line where the second edge 1002 of the auxiliary electrode 1223 is located is on the side of the straight line where the first edge 1001 of the connection electrode 1221 is located and away from the second effective light-emitting region 102 to achieve coverage of the first connection portion 510. For example, the connecting edge between the first edge 1001 and the second edge 1002 can be a straight edge intersecting the X direction, but is not limited thereto, and can also be a broken line edge or a curved edge.

[0115] In the embodiments of the present disclosure, for the sake of convenience in fabrication, it is schematically shown that the above-mentioned first edge, second edge, third edge, and fourth edge are all straight edges, but this is not limited thereto, and they can also be curved edges or broken line edges as long as the extending direction is along the X direction.

[0116] Since the third edge of the connection electrode of the first pixel block is located on the side of the connection electrode away from the first effective light-emitting region, it is also possible to cover the first connection portion when the edge of the portion of the auxiliary electrode in contact with the connection electrode is on the same straight line as the third edge of the connection electrode. Therefore, the edges of the portions of the auxiliary electrode and the connection electrode close to each other away from the first connection portion can be designed to be on the same straight line for convenient fabrication.

[0117] The straight line where the first edge of the connection electrode of the second pixel block intersects with the first connection portion. If the second edge of the auxiliary electrode of the second pixel block is on the same straight line as the first edge of the connection electrode, the area of the first connection portion covered by the auxiliary electrode of the second pixel block is different from the area of the corresponding first connection portion covered by the auxiliary electrode of the first pixel block, which will cause a difference in the brightness of the two first color sub-pixels. Therefore, in the embodiments of the present disclosure, the first edge of the connection electrode of the second pixel block and the second edge of the auxiliary electrode are not on the same side, and the straight line where the second edge of the auxiliary electrode is located is on the side of the straight line where the first edge of the connection electrode is located away from the second effective light-emitting region, so that the overlapping area between the auxiliary electrode and the first connection portion in the two first color sub-pixels of the first color sub-pixel pair is basically the same, reducing the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the brightness difference between the two first color sub-pixels to improve the display characteristics of the display substrate.

[0118] For example, as Figures 3C to 5C shown, the pixel circuit of each sub-pixel further includes a second connection portion 520 provided on the same layer as the first connection portion 510. The second connection portion 520 is electrically connected to the second pole of the first light-emitting control transistor T6 through a via hole 3008 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer. The connection electrode of the second electrode of each sub-pixel is connected to the second connection portion through a via hole penetrating through the planarization layer, thereby realizing the connection with the first light-emitting control transistor.

[0119] For example, in the first pixel block 110, the second connection portion 520 is farther away from the first effective light-emitting region 101 than the first connection portion 510 in the second direction. Therefore, the connection electrode 1122 is farther away from the first effective light-emitting region 101 than the first connection portion 510 in the second direction. For example, in the second pixel block 120, the second connection portion 520 is closer to the second effective light-emitting region 102 than the first connection portion 510 in the second direction. Therefore, the connection electrode 1222 is closer to the second effective light-emitting region 102 than the first connection portion 510 in the second direction.

[0120] For example, as Figures 3C to 5CAs shown, a planarization layer is provided between the film layer where the second connection portion 520 is located and the film layer where the connection electrode is located, or a passivation layer and a planarization layer are provided between the film layer where the second connection portion 520 is located and the film layer where the connection electrode is located. The planarization layer includes a plurality of vias 3010 penetrating therethrough, and the connection electrodes in each sub-pixel are electrically connected to the second connection portion 520 through the vias 3010. For example, the corresponding via 3010 in the first pixel block 110 is farther from the first effective light-emitting region 101 than the first connection portion 510 in the first pixel block 110 in the second direction. Thus, the connection electrode 1122 is farther from the first effective light-emitting region 101 than the first connection portion 510 in the second direction. For example, the corresponding via 3010 of the second pixel block 120 is closer to the second effective light-emitting region 102 than the first connection portion 510 in the second pixel block 120 in the second direction. Thus, the connection electrode 1222 is closer to the second effective light-emitting region 102 than the first connection portion 510 in the second direction.

[0121] For example, as Figures 4 to 5J shown, in the first pixel block 110, the first gate 110-T2-g1 of the threshold compensation transistor T2 is located on the side closer to the first effective light-emitting region 101 than the second gate 110-T2-g2 in the second direction. The straight line where the third edge 1003 of the connection electrode 1122 is located overlaps with the first gate T2-g1, and the edge of the auxiliary electrode 1123 (for example, the second portion 1123-2 of the auxiliary electrode 1123 described later) far from the first effective light-emitting region 101 is located on the side of the first gate T2-g1 far from the first effective light-emitting region 101 so that the auxiliary electrode 1123 covers the first gate T2-g1. For example, as Figure 5G shown, both the protruding structure P and the covering portion S (described later) overlap with the active semiconductor layer of the threshold compensation transistor T2. In the embodiment of the present disclosure, by providing an auxiliary electrode covering the first gate of the threshold compensation transistor in the first pixel block, it is possible to prevent external light from directly irradiating the channel region of the threshold compensation transistor and avoid the characteristic shift of the threshold compensation transistor caused by the light irradiation during the display of the display substrate.

[0122] For example, as Figures 4 to 5CAs shown, in the first pixel block 110, the auxiliary electrode 1123 includes a first part 1123-1 and a second part 1123-2 that are connected to each other. The first part 1123-1 is connected to the connection electrode 1122. The second part 1123-2 covers at least a part of the first gate T2-g1 of the threshold compensation transistor T2. The fourth edge 1004 of the first part 1123-1 extending in the first direction and the third edge 1003 of the connection electrode 1122 are on the same straight line. And the edge of the second part 1123-2 extending in the first direction is farther from the first effective light-emitting region 101 in the Y direction than the fourth edge 1004. For example, the second part 1123-2 is located on the side of the second gate T2-g2 of the threshold compensation transistor T2 away from the connection electrode 1122 in the first direction. For example, in the first pixel block 110, the auxiliary electrode 1123 covers a part of the active layer between the first gate T2-g1 and the second gate T2-g2 of the threshold compensation transistor T2.

[0123] In the embodiment of the present disclosure, a protrusion protruding away from the first effective light-emitting region is provided in the auxiliary electrode of the first pixel block to cover the first gate of the threshold compensation transistor and a part of the active layer between the first gate and the second gate. This can ensure that even if there is a certain degree of alignment offset during the formation of the second electrode of the first pixel block, it can still cover a channel region of the threshold compensation transistor, prevent the transistor characteristics from shifting due to light illumination, and further prevent the writing of the gate potential of the driving transistor from being affected.

[0124] In the embodiment of the present disclosure, the threshold compensation transistor has a double-gate structure and has two channel regions. The second gate of the threshold compensation transistor in the first pixel block is not covered by the second electrode. To ensure that at least one channel region of the threshold compensation transistor is in an occluded state to ensure the characteristics of the threshold compensation transistor, a protrusion protruding away from the first effective light-emitting region is provided in the auxiliary electrode of the first pixel block, which can ensure that the first gate of the threshold compensation transistor is completely covered by the second electrode.

[0125] For example, the second electrode of the first pixel block covers one of the two gates of the threshold compensation transistor, and the second electrode of the second pixel block covers the two gates of the threshold compensation transistor.

[0126] For example, along the direction perpendicular to the substrate, the main electrode of the second electrode of the first pixel block overlaps with the covering part S, and the main electrode of the second electrode of the second pixel block overlaps with the covering part S.

[0127] For example, as Figures 1 to 5CAs shown, the second electrode 320 of the third color sub-pixel 300 further includes an auxiliary electrode 323 located on the side of the main electrode 321 away from the connection electrode 322 and connected to the main electrode 321. The shape of the main electrode 321 of the third color sub-pixel 300 is the same as the shape of the effective light-emitting region 301, for example, both are hexagonal or elliptical. The connection electrode 322 is connected to the second connection portion 520 through a via 3010 penetrating the planarization layer to achieve connection with the first light-emitting control transistor T6.

[0128] For example, as Figures 1 to 5H shown, in the third color sub-pixel 300, the second gate 300-T2-g2 of the threshold compensation transistor T2 is located on the side of the first gate 300-T2-g1 close to the effective light-emitting region 301 of the third color sub-pixel 300, and the auxiliary electrode 323 covers a part of the active layer between the second gate T2-g2 and the first gate T2-g1. For example, as Figure 5H shown, the protruding structure P and the covering portion S (described later) both overlap with the active semiconductor layer of the threshold compensation transistor T2. In the embodiments of the present disclosure, the threshold compensation transistor has a double-gate structure with two channel regions. The first gate of the threshold compensation transistor in the third color sub-pixel is not covered by the second electrode. In order to ensure that at least one channel region of the threshold compensation transistor is in an occluded state to ensure the characteristics of the threshold compensation transistor, a protruding bump is provided on the side of the main electrode of the third color sub-pixel away from the connection electrode to form an auxiliary electrode. Thus, even if there is a certain degree of alignment offset during the formation of the second electrode, one channel region of the threshold compensation transistor can still be completely covered, preventing the transistor characteristics from shifting due to light irradiation, and further preventing the gate potential of the driving transistor from being affected during writing.

[0129] For example, the above light-emitting element can be a light-emitting element or an inorganic light-emitting element.

[0130] For example, as Figure 5D shown, a pixel defining layer 7 is provided on the side of the second electrode of each color sub-pixel away from the substrate. The pixel defining layer 7 includes an opening 070 to expose a part of the second electrode. When the subsequent organic light-emitting layer is formed in the opening 070 of the pixel defining layer 7, the organic light-emitting layer contacts the second electrode, so that this part can drive the organic light-emitting layer to emit light.

[0131] For example, Figure 6 is a schematic cross-sectional structure diagram of a part of a display substrate. As Figure 6As shown, the display substrate includes a film layer 010, and the film layer 010 includes a substrate, an active semiconductor layer located on the substrate, and at least one conductive layer located on the side of the active semiconductor layer away from the substrate. The display substrate further includes a source-drain metal layer 011 located on the film layer 010. For example, the source-drain metal layer 011 may include traces such as data lines and power signal lines. The display substrate further includes a planarization layer 012 located on the side of the source-drain metal layer 011 away from the film layer 010, an anode 013 located on the side of the planarization layer 012 away from the source-drain metal layer 011, and a pixel definition layer 014 located on the side of the anode 013 away from the planarization layer 012. The pixel definition layer 014 includes a plurality of openings 015-017 for defining the light-emitting regions of sub-pixels. The plurality of openings 015-017 expose a part of the anode 013. When the subsequent organic light-emitting layer is formed in the openings 015-017 of the pixel definition layer 014, the organic light-emitting layer is in contact with the anode 013, so that this part can drive the organic light-emitting layer to emit light.

[0132] As Figure 6 shown, when the thickness of the source-drain metal layer 011 is relatively large, for example, the thickness can be 0.6-0.9 micrometers, it will cause the surface of the planarization layer 012 located on the source-drain metal layer 011 facing the anode 013 to be uneven. For example, the distance between the surface of the planarization layer 012 away from the film layer 010 directly above the source-drain metal layer 011 (such as data lines, power signal lines, and patterns of the same layer and the same material as them) and the surface of the film layer 010 away from the planarization layer 012 is h1, and the distance between the surface of the planarization layer 012 away from the film layer 010 directly above the area where the source-drain metal layer 011 is not provided and the surface of the film layer 010 away from the planarization layer 012 is h2, and h1>h2.

[0133] As Figure 6As shown, within the opening 016, a source-drain metal layer 011 is disposed directly beneath a part of the flat layer 012, and no source-drain metal layer 011 is disposed directly beneath another part. Thus, the surface of the flat layer 012 facing the anode 013 within the opening 016 is uneven, resulting in an uneven surface of the anode 013 located on the flat layer 012. For example, for the anode 013 within the opening 016, the distance between the surface of the anode 013 away from the film layer 010 directly above the source-drain metal layer 011 and the surface of the film layer 010 away from the anode 013 is h3, and the distance between the surface of the anode 013 away from the film layer 010 at the position where no source-drain metal layer 011 is disposed and the surface of the film layer 010 away from the anode 013 is h4, and h3 > h4. Thus, the anode 013 within the opening 016 is "tilted". Similarly, the anode 013 within the opening 015 will also be "tilted", and due to the difference in the position of the source-drain metal layer 011, the "tilt direction" of the anode 013 within the opening 015 is different from the "tilt direction" of the anode 013 within the opening 016, resulting in inconsistent light emission intensities in different directions for the sub-pixels corresponding to the openings 015 and 016. Taking the direction indicated by the arrow in the Y direction as the right, the light intensities emitted from the sub-pixel light-emitting regions defined by the openings 015 and 016 to the left and right sides are inconsistent. No source-drain metal layer 011 is disposed directly beneath the anode 013 within the opening 017. Therefore, the surface of the anode 013 within the opening 017 is substantially flat and not "tilted", and the light emission intensities in different directions for the sub-pixel light-emitting region defined by the opening 017 are consistent. For the light-emitting regions of three adjacent sub-pixels of different colors defined by the openings 015 - 017, the anode 013 within the opening 015 is "tilted" to the left, the anode 013 within the opening 016 is "tilted" to the right, and the anode 013 within the opening 017 is not tilted. Thus, the "tilt directions" of the anodes 013 of different color sub-pixels are different, resulting in mismatched light intensities emitted from the light-emitting regions of the three sub-pixels to the left and right sides. A display device using such a display substrate will exhibit large viewing angle color shift. When viewed by the human eye, a color shift phenomenon similar to redness on one side and blueness on the other side will occur.

[0134] For example, in the first pixel block, the orthographic projection of the second electrode on the substrate substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate substrate; in the second pixel block, the orthographic projection of the second electrode on the substrate substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate substrate.

[0135] For example, in each color sub-pixel, the overlapping area between the orthographic projection of the second connecting portion on the substrate substrate and the orthographic projection of the first pole of the capacitor on the substrate substrate is very small.

[0136] For example, as Figure 5C and Figure 5JAs shown, the second electrode of the second color sub-pixel covers vias 3009 and 3021 that connect the source-drain metal layer and the active semiconductor layer.

[0137] In another example of the embodiments of the present disclosure, as Figures 3A to 5C shown, the plurality of data lines 420 includes a plurality of first data lines 421, and the plurality of power signal lines 460 includes a plurality of first power supply signal lines 461. For example, along a third direction perpendicular to the substrate, the second electrode 220 of the second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, and the second connection portion 520. Among the portions where the first data line 421, the first power signal line 461, and the second connection portion 520 overlap with the second electrode 220, the first power signal line 461 and the first data line 421 are located on both sides of the second connection portion 520, and the minimum distance d1 ( Figure 5B as shown) between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other and the minimum distance d2 ( Figure 5B as shown) between the edges of the second connection portion 520 and the first data line 421 that are close to each other have a ratio of 0.8 to 1.2. For example, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 0.9 to 1.1. For example, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 1.

[0138] In the embodiments of the present disclosure, setting the distances between the second connection portion and the adjacent data line and power signal line to be approximately equal can reduce the height difference between the middle region (the region that does not overlap with the data line and power signal line) and the two side regions (the regions that overlap with the data line and power signal line) of the second electrode of the second color sub-pixel, improve the flatness of the second electrode of the second color sub-pixel, and improve color deviation.

[0139] For example, the minimum distance between the first data line 421 and the first power signal line 461 can be 20 to 25 micrometers, and the maximum dimension of the second connection portion 520 in the Y direction can be 15 to 20 micrometers. The embodiments of the present disclosure are not limited thereto, as long as the distances between the first data line, the second connection portion, and the first power signal line are not less than 3 micrometers.

[0140] For example, as Figures 3A to 5CAs shown, along the third direction, the effective light-emitting regions 202 of the second-color sub-pixels 200 overlap with the first data lines 421, the first power signal lines 461, and the second connection portions 520. In the portions where the first data lines 421, the first power signal lines 461, and the second connection portions 520 overlap with the effective light-emitting region 201 of the second-color sub-pixels 200, the ratio of the distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 0.8 to 1.2, for example, 0.9 to 1.1. Thus, the height difference between the middle region and the two side regions of the second electrode of the second-color sub-pixel can be reduced, and the flatness of the second electrode in the effective light-emitting region of the second-color sub-pixel can be improved to improve color deviation.

[0141] For example, as Figures 3A to 5C shown, in the portion where the second connection portion 520 overlaps with the effective light-emitting region 202 of the second-color sub-pixels 200, the distance between the second connection portion 520 and the first data line 421 is substantially equal to the distance between the second connection portion 520 and the first power signal line 461, which can further ensure the flatness of the second electrode located in the effective light-emitting region of the second-color sub-pixel to improve color deviation.

[0142] For example, as Figures 3A to 5C shown, the distances to the two end points of the effective light-emitting region 201 of the second-color sub-pixels 200 in the Y direction (the direction intersecting with the data line extension direction) are substantially equal, and the orthographic projection of the straight line extending along the X direction on the substrate overlaps with the orthographic projection of the second connection portion 520 on the substrate. For example, the orthographic projection of the straight line passing through the midpoint of the line connecting the two end points of the effective light-emitting region 201 of the second-color sub-pixels 200 that are opposite to each other in the Y direction and extending along the X direction on the substrate overlaps with the orthographic projection of the second connection portion 520 on the substrate. For example, the orthographic projection of the straight line passing through the midpoint of the line connecting the two end points of the effective light-emitting region 201 of the second-color sub-pixels 200 in the Y direction (the direction intersecting with the data line extension direction) and extending along the X direction on the substrate overlaps with the orthographic projection of the second connection portion 520 on the substrate. Thus, relative to the distribution positions of the first data line and the first power signal line, in the embodiments of the present disclosure, the center line of the effective light-emitting region 201 of the second-color sub-pixels 200 extending along the first direction overlaps with the second connection portion, which can improve the symmetry of the second electrode and improve color deviation.

[0143] For example, as Figures 3A to 5CAs shown, the second connection portion 520 includes a first sub-connection portion 521 connected to each other and a first spacer 522 located on the side of the first sub-connection portion 521 close to the first power signal line 461. The second electrode 220 of the second color sub-pixel 200 is electrically connected to the second pole of the first light-emitting control transistor T6 through the first sub-connection portion 521. For example, the first spacer and the first sub-connection portion are an integral structure. Dividing the second connection portion into the first sub-connection portion and the first spacer in the embodiments of the present disclosure can clearly show the positional relationship between the second connection portion, the second electrode of the second color sub-pixel, and the effective light-emitting region.

[0144] For example, as Figures 3A to 5C shown, the shape of the first sub-connection portion 521 is a rectangle extending in the X direction. The straight line passing through the center of the effective light-emitting region 201 of the second color sub-pixel 200 and extending in the X direction does not coincide with the second straight line passing through the center of the first sub-connection portion 521 and extending in the X direction. For example, the center line passing through the center of the effective light-emitting region 201 of the second color sub-pixel 200 is located on the side close to the first spacer 522 of the center line passing through the center of the first sub-connection portion 521. Thus, the whole of the first sub-connection portion is offset to the left relative to the center line of the second color sub-pixel extending in the X direction (with the direction indicated by the arrow in the Y direction being to the right). If the first spacer is not provided, the height difference between the two sides of the center line of the second electrode of the second color sub-pixel will be relatively large, and the symmetry of the second electrode is poor, which is likely to cause color deviation in the Y direction. In the embodiments of the present disclosure, by providing a first spacer between the first sub-connection portion and the first power signal line, the position where the second connection portion overlaps with the second electrode of the second color sub-pixel is located in the middle region of the effective light-emitting region of the second color sub-pixel, which can reduce the height difference between the middle region and the two side regions of the second electrode of the second color sub-pixel and improve the symmetry, which is beneficial to ensuring that the light-emitting intensities in all directions of the effective light-emitting region are consistent to improve color deviation.

[0145] For example, as Figures 3A to 5CAs shown, the shape of the second connection portion 520 in the second color sub-pixel 200 is L-shaped, and along the X direction, the size of the first sub-connection portion 521 is larger than the size of the first spacer 522. For example, the second electrode 220 of the second color sub-pixel 200 includes a main electrode 221 and a connection electrode 222 connected to each other. The shape of the main electrode 221 is the same as the shape of the effective light-emitting region 201, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light-emitting region of the second color sub-pixel on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, along the direction perpendicular to the substrate, a part of the first sub-connection portion 521 overlaps with the main electrode 221, and another part of the first sub-connection portion 521 overlaps with the connection electrode 222 and is connected to the connection electrode 222 through a via 3010 in the planarization layer. The first spacer 521 only overlaps with the main electrode 221 and does not overlap with the connection electrode 222. For example, the via 3010 (such as the first via 3011 described later) is farther from the effective light-emitting region 201 of the second color sub-pixel 200 than the first spacer 522. For example, more than 90% of the orthographic projection of the second connection portion 520 of the second color sub-pixel 200 on the substrate falls within the orthographic projection of the second electrode 220 on the substrate. In the embodiments of the present disclosure, the first spacer can be only provided at the position of the second electrode of the first color sub-pixel to cooperate with the first sub-connection portion to improve the flatness and symmetry of the second electrode. In the embodiments of the present disclosure, it is schematically shown that no first spacer is provided outside the position where the second electrode is located, but this is not limited thereto, and the shape of the second connection portion in the second color sub-pixel can also be designed according to the process conditions and the actual requirements of the product.

[0146] For example, as Figures 3A to 5CAs shown, along the third direction, the effective light-emitting region 201 of the second color sub-pixel 200 overlaps with the third connection portion 530, and a straight line passing through the geometric center of the effective light-emitting region 201 and extending along the X direction overlaps with the third connection portion 530. For example, the connection electrode 222 is located on a side of the straight line passing through the geometric center of the effective light-emitting region 201 and extending along the Y direction and away from the third connection portion 530. For example, the third connection portion 530 is substantially located in the middle region of the effective light-emitting region 201 of the second color sub-pixel 200. For example, the second connection portion 520 and the third connection portion 530 are respectively located on both sides of the straight line passing through the center of the effective light-emitting region 201 of the second color sub-pixel 200 and extending along the Y direction, that is, the second connection portion 520 and the third connection portion 530 are respectively located on both sides of the center line extending along the Y direction of the effective light-emitting region 201 of the second color sub-pixel 200. For example, the second connection portion 520 is located on one side of the straight line passing through the center of the effective light-emitting region 201 of the second color sub-pixel 200 and extending along the Y direction, and at least a part of the third connection portion 530 is located on the other side of the straight line. Compared with the data lines and power supply signal lines distributed in the regions on both sides of the effective light-emitting region, in the embodiments of the present disclosure, the source-drain metal layer covered by the middle region of the second electrode of the second color sub-pixel is less. By providing the first spacer block, and arranging the overlapping portions of the third connection portion and the second connection portion including the first spacer block with the effective light-emitting region of the second color sub-pixel in the middle region of the effective light-emitting region, the height difference between the middle region and the two side regions of the second electrode located in the effective light-emitting region can be reduced, the flatness can be improved, and thus the color shift can be improved.

[0147] For example, as Figures 3A to 5C As shown, the plurality of data lines 420 further includes a plurality of second data lines 422, and the plurality of second data lines 422 and the plurality of first data lines 421 are on the same layer and are alternately arranged. The plurality of power supply signal lines 460 further includes a plurality of second power supply signal lines 462, and the plurality of second power supply signal lines 462 and the plurality of first power supply signal lines 461 are on the same layer and are alternately arranged. For example, along the third direction, the second electrode 220 of each second color sub-pixel 200 overlaps with the first data line 421, the first power supply signal line 461, the second connection portion 520, the second data line 422, and the second power supply signal line 462, and in the overlapping portions, the second power supply signal line 462 is located on a side of the first data line 421 away from the second connection portion 520, and the second data line 422 is located on a side of the first power supply signal line 461 away from the second connection portion 520. That is, the second electrode 220 of the second color sub-pixel 200 overlaps with two data lines 420 and two power supply signal lines 460, and the first data line 421 and the second power supply signal line 462 are arranged on one side of the second connection portion 520, and the second data line 422 and the first power supply signal line 461 are arranged on the other side of the second connection portion 520.

[0148] For example, asFigures 3A to 5C As shown, the effective light-emitting region 201 of each second-color sub-pixel 200 overlaps with the first data line 421, the first power supply signal line 461, the second data line 422, and the second power supply signal line 462. In the overlapping part, the ratio of the overlapping area of the first power supply signal line 461 and the second data line 422 with the effective light-emitting region 201 to the overlapping area of the second power supply signal line 462 and the first data line 421 with the effective light-emitting region 201 is 0.8 to 1.2, for example, 0.9 to 1.1. In the embodiments of the present disclosure, both side regions of the effective light-emitting region of the second-color sub-pixel overlap with the data line and the power supply signal line, and the overlapping areas of the source-drain metal layers on both sides of the second connection portion of the second-color sub-pixel with the effective light-emitting region are substantially equal. Thus, it can be ensured that the overlapping part of the effective light-emitting region of the second-color sub-pixel with the source-drain metal layer has good symmetry, which is beneficial to preventing color deviation.

[0149] For example, as Figures 3A to 5C shown, the first data line 421 overlapping with the second electrode 220 of the second-color sub-pixel 200 is electrically connected to the second pole of the data writing transistor T4 of the first pixel block 110, and the second power supply signal line 462 overlapping with the second electrode 220 of the second-color sub-pixel 200 is electrically connected to the first pole of the second light-emitting control transistor T5 of the first pixel block 110. For example, both the first data line 421 and the second power supply signal line 420 overlapping with the second electrode 220 of the second-color sub-pixel 200 overlap with the second electrode 112 of the first pixel block 110. For example, the second electrode 112 of the first pixel block 110 has two overlapping parts with the first data line 421 and the second power supply signal line 462, and the two overlapping parts are respectively located on both sides of a straight line that divides the effective light-emitting region of the first pixel block 110 into two equal-area parts and extends in the first direction. Thus, the second electrode of the first pixel block has good symmetry and flatness in the Y direction, which is beneficial to preventing the occurrence of color deviation.

[0150] For example, as Figures 3A to 5C shown, the first power supply signal line 461 overlapping with the second electrode 220 of the second-color sub-pixel 200 is electrically connected to the first pole of the second light-emitting control transistor T5 of the second-color sub-pixel 200, and the second data line 422 overlapping with the second electrode 220 of the second-color sub-pixel 200 is electrically connected to the second pole of the data writing transistor T4 of the second-color sub-pixel. For example, the second electrode 122 of the second pixel block 120 has two overlapping parts with the second data line 422 and the first power supply signal line 461, and the two overlapping parts are respectively located on both sides of a straight line passing through the center of the second effective light-emitting region 201 of the second pixel block 120 and extending in the X direction. Thus, the second electrode of the second pixel block has good symmetry and flatness in the Y direction, which is beneficial to preventing the occurrence of color deviation.

[0151] For example, as Figures 3A to 5C shown, along the direction perpendicular to the substrate, on the side edge of the main electrode 1221 of the second pixel block 120 away from the auxiliary electrode 1223, there is an overlap with the first connection portion 510 of the second color sub-pixel 200.

[0152] For example, as Figures 3A to 5C shown, along the direction perpendicular to the substrate, the second electrode 320 of each third color sub-pixel 300 overlaps with the first data line 421, the first power supply signal line 461, the second data line 422, and the second power supply signal line 462. For example, along the direction perpendicular to the substrate, the effective light-emitting region 301 of each third color sub-pixel 300 overlaps with the first data line 421, the first power supply signal line 461, the second data line 422, and the second power supply signal line 462. For example, the first data line 421 and the second power supply signal line 462 are located on one side of the center line extending in the X direction of the effective light-emitting region 301 of the third color sub-pixel 300, and the second data line 422 and the first power supply signal line 461 are located on the other side of the above center line. For example, along the direction perpendicular to the substrate, in the overlapping portions of the second electrode 320 of each third color sub-pixel 300 with the first data line 421, the first power supply signal line 461, the second data line 422, and the second power supply signal line 462, the ratio of the overlapping area of the first power supply signal line 461 and the second data line 442 with the effective light-emitting region 301 to the overlapping area of the second power supply signal line 462 and the first data line 421 with the effective light-emitting region 301 is, for example, 0.8 to 1.2, and for example, 0.9 to 1.1. Then, the portions of the second electrode 320 of the third color sub-pixel 300 located in the two side regions (the regions where the data line and the power supply signal line overlap with the second electrode) overlap with the source-drain metal layer, and the overlapping portions are symmetrically distributed approximately, which is beneficial to reducing color deviation.

[0153] For example, both the second electrode 320 and the effective light-emitting region 301 of the third color sub-pixel 300 overlap with the second connection portion 520. Among the first data line 421, the first power supply signal line 461, and the portion where the second connection portion 520 overlaps with the second electrode 320, the first power supply signal line 461 and the first data line 421 are located on both sides of the second connection portion 520, and the ratio of the minimum distance between the edges of the second connection portion 520 and the first power supply signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is not greater than 2.5, for example, not greater than 2. For example, a straight line passing through the center of the effective light-emitting region 301 of the third color sub-pixel 300 and extending in the X direction overlaps with the second connection portion 520. In the embodiments of the present disclosure, by arranging the second connection portion of the third color sub-pixel in the middle region of the effective light-emitting region, the height difference of the second electrode at the middle region of the effective light-emitting region and the two side regions (the regions where the data line and the power supply signal line overlap with the effective light-emitting region) can be reduced, which is beneficial to reducing color deviation.

[0154] For example, as Figures 3A to 5C shown, the second connection portion 520 of the third color sub-pixel 300 includes a second sub-connection portion 523 and a second spacer 524 that are connected to each other. The second spacer 524 is located on the side of the second sub-connection portion 523 close to the center of the effective light-emitting region 301 of the third color sub-pixel 300. For example, along the direction perpendicular to the substrate, the second spacer 524 overlaps with the effective light-emitting region 301, and the second sub-connection portion 523 does not overlap with the effective light-emitting region 301. For example, the second sub-connection portion and the second spacer are an integral structure. In the embodiments of the present disclosure, schematically dividing the second connection portion into the second sub-connection portion and the second spacer can clearly show the positional relationship between the second connection portion, the second electrode of the third color sub-pixel, and the effective light-emitting region.

[0155] For example, as Figures 3A to 5C shown, the second electrode 320 of the third color sub-pixel 300 includes a main electrode 321 and a connection electrode 322 that are connected to each other. The shape of the main electrode 321 of the third color sub-pixel 300 is the same as the shape of the effective light-emitting region 301, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light-emitting region of the third color sub-pixel on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, along the direction perpendicular to the substrate, the main electrode 321 overlaps with the second spacer 524, and the connection electrode 322 overlaps with and is connected to the second sub-connection portion 523. For example, along the direction perpendicular to the substrate, the main electrode 321 and the second sub-connection portion 523 are substantially non-overlapping.

[0156] For example, as Figures 3A to 5CAs shown, along the direction perpendicular to the substrate, the first connection portion 510 of the third color sub-pixel 300 overlaps with the effective light-emitting region 301, and at least a part of the first connection portion 510 of the third color sub-pixel 300 and the second spacer 524 are respectively located on both sides of the fourth straight line passing through the center of the effective light-emitting region 301 and extending along the Y direction. In the embodiment of the present disclosure, the effective light-emitting region of the third color sub-pixel and the second electrode overlap with the first connection portion. By providing the second spacer at the edge of the effective light-emitting region away from the first connection portion, the height difference in the X direction of the middle region of the second electrode of the third color sub-pixel can be reduced, which is beneficial to improving the color shift of the third color sub-pixel.

[0157] For example, as Figures 3A to 5C shown, the shape of the second sub-connection portion 523 in the second connection portion 520 of the third color sub-pixel 300 is rectangular. The side of the second sub-connection portion 523 close to the first power signal line 461 is connected to the second electrode 320 through the via 3010 in the planarization layer, and the side of the second sub-connection portion 523 close to the first data line 421 is connected to the second pole of the first light-emitting control transistor T6 through the via 3008 passing through the gate insulating layer, the first insulating layer, and the second insulating layer. The rectangular shape in the embodiment of the present disclosure includes a standard rectangular shape and an approximate rectangular shape. For example, the approximate rectangular shape may include a rounded rectangle and other shapes with an overall contour approximately rectangular.

[0158] For example, as Figures 3A to 5C shown, the shape of the second spacer 524 in the second connection portion 520 of the third color sub-pixel 300 is rectangular, and the two sides of the second spacer 524 extending along the X direction are flush with the two sides of the second sub-connection portion 523 extending along the X direction, so that the shape of the second connection portion of the third color sub-pixel is rectangular. In the embodiment of the present disclosure, while adding the second spacer to reduce the height difference in the X direction of the middle region of the second electrode of the third color sub-pixel and the height difference in the Y direction of the second electrode, setting the shape of the second connection portion as rectangular can facilitate fabrication.

[0159] Figure 7 It is a schematic cross-sectional structure diagram of a part of another display substrate. Figure 7 The shown display substrate includes Figure 6 the shown film layer 010, source-drain metal layer 011, planarization layer 012, anode 013, and pixel defining layer 014. As Figure 7 shown, the planarization layer 012 in the display substrate includes a via 018 so that the anode 013 can be electrically connected to the source-drain metal layer 011. The pixel defining layer 014 includes an opening 019 to expose a part of the anode 013. When the subsequent organic light-emitting layer is formed in the opening 019, the organic light-emitting layer contacts the anode 013 to form an effective light-emitting region.

[0160] As shown in Figure 7 the figure, via 018 is located outside the effective light-emitting region. Since the anode 013 around the via 018 is inclined, a certain distance should be set between the effective light-emitting region and the via 018 to ensure the flatness of the anode 013 in the effective light-emitting region, thereby avoiding color deviation of the display substrate.

[0161] Figure 8 It is a schematic diagram of the pixel arrangement structure in a display substrate. As shown in Figure 8 the figure, the display substrate includes data lines 042 extending in the X direction. The display substrate further includes a red sub-pixel 021, a pair of green sub-pixels 022, and a blue sub-pixel 023. The effective light-emitting regions of the red sub-pixel 021 and the blue sub-pixel 023 extend in the Y direction. For example, each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The light-emitting element includes an anode, a light-emitting layer, and a cathode stacked in sequence in a direction away from the substrate. The anode is connected to the connection portion 031 through a via 0310 to realize connection with the thin-film transistor in the pixel circuit. For example, the vias 0310 corresponding to the red sub-pixel 021, the pair of green sub-pixels 022, and the blue sub-pixel 023 are arranged in a straight line in the Y direction. For example, the anode 0211 of the red sub-pixel 021 is connected to the connection portion 031 through a via 0310. A notch is provided on the long side of the effective light-emitting region 0211 of the red sub-pixel 021 close to the via 0310 to avoid the via 0310, and a suitable spacing (preset spacing), such as 3 microns, is ensured between the effective light-emitting region 0211 and the via 0310. Similarly, a notch needs to be provided on the long side of the effective light-emitting region of the blue sub-pixel 023 close to the via 0310 to avoid the via 0310, and the preset spacing between the effective light-emitting region and the via 0310 is ensured. The preset spacing refers to the minimum distance between the edge of the effective light-emitting region and the edge of the via (such as 3 microns) to ensure that the via does not affect the light-emitting direction of the edge of the effective light-emitting region.

[0162] For example, the minimum distance between the edge of the third via of the first pixel block and the edges of the effective light-emitting regions of the second color sub-pixel and the fourth color sub-pixel is approximately equal, and both are greater than 3 microns. For example, the minimum distance between the fourth via of the second pixel block and the edges of the effective light-emitting regions of the second color sub-pixel and the fourth color sub-pixel is greater than 3 microns.

[0163] For example, the positive projection of the second electrode of the second color sub-pixel on the substrate overlaps with the positive projection of the reset power signal line on the substrate.

[0164] In another example of the embodiments of the present disclosure, as shown in Figures 4 to 5FAs shown, the second electrode 220 of the second color sub-pixel 200 is connected to the second connection portion 520 through a first via 3011 penetrating the flat layer, and the second electrode 320 of the third color sub-pixel 300 is connected to the second connection portion 520 through a second via 3012 penetrating the flat layer. The minimum distance between the orthographic projection of the effective light-emitting region 201 of the second color sub-pixel 200 on a straight line along the X direction (the extending direction of the data line 420) and the orthographic projection of the effective light-emitting region 301 of the third color sub-pixel 300 on the above straight line is less than the sum of the sizes of the projections of the first via and the preset distance between the edge of the first via and the edge of the effective light-emitting region on the above straight line. The first via 3011 is located on the side of the effective light-emitting region 201 of the second color sub-pixel 200 closer to the effective light-emitting region 301 of the third color sub-pixel 300 in the X direction, and the second via 3012 is located on the side of the effective light-emitting region 301 of the third color sub-pixel 300 closer to the effective light-emitting region 201 of the second color sub-pixel 200 in the X direction. The first connection line 3101 connecting the first via 3011 and the second via 3012 is not parallel to the Y direction. For example, the orthographic projections of the first via 3011, the fourth via 3014, and the third via 3013 on the substrate overlap with the orthographic projection of the light-emitting control signal line 450 on the substrate. For example, the orthographic projection of the second via 3012 on the substrate does not overlap with the orthographic projection of the light-emitting control signal line 450 on the substrate. The above first connection line is a straight line.

[0165] For example, the first connection line 3101 connecting the first via 3011 and the second via 3012 may refer to the connection line between the center of the first via and the center of the second via; it may also refer to the connection line between the point of the first via closest to the effective light-emitting region of the second color sub-pixel and the point of the second via farthest from the effective light-emitting region of the third color sub-pixel; it may also refer to the connection line between the point of the first via farthest from the effective light-emitting region of the second color sub-pixel and the point of the second via closest to the effective light-emitting region of the third color sub-pixel.

[0166] For example, the second electrodes of the second color sub-pixel and the third color sub-pixel do not overlap in the second direction.

[0167] In the embodiments of the present disclosure, the distance between the effective light-emitting regions of the second color sub-pixels and the third color sub-pixels in the X direction is small. For example, if it is less than the sum of the size of the first via and the preset pitch, then if the first via is arranged within the pitch between the effective light-emitting regions of the second color sub-pixels and the third color sub-pixels in the X direction, it will cause a conflict in the position between the first via and the effective light-emitting region of the second color sub-pixels, affecting the light emission of the second color sub-pixels. In the embodiments of the present disclosure, according to the positions of the effective light-emitting regions of the second color sub-pixels and the third color sub-pixels, the positions of the vias (such as at least one of the first via and the second via) located in the planarization layer are adjusted. For example, the connection line between the first via and the second via corresponding to the second color sub-pixels and the third color sub-pixels respectively is not parallel to the extension direction of the scanning signal line, which can ensure the planarization of the second electrodes of the second color sub-pixels and the third color sub-pixels, so as to ensure the consistency of the light emission intensity in all directions of the effective light-emitting regions and effectively improve color deviation.

[0168] For example, as Figures 4 to 5C shown, the included angle between the first connection line 3101 and the Y direction is 5° to 15°. In the embodiments of the present disclosure, by adjusting the positions of the first via and the second via, the probability of color deviation of the second color sub-pixels and the third color sub-pixels can be reduced.

[0169] For example, as Figures 4 to 5C shown, the second via 3012 is located on the side close to the effective light-emitting region 201 of the second color sub-pixels 200 of the second straight line 3102 passing through the first via 3011 and extending along the Y direction. For example, the positive projection of the first via 3011 on the straight line extending in the X direction does not overlap with the positive projection of the second via 3012 on this straight line. In the embodiments of the present disclosure, the distances between the effective light-emitting regions of the second color sub-pixels and the first via and between the effective light-emitting regions of the third color sub-pixels and the second via are set to be relatively large, which can ensure that the vias do not affect the planarization of the second electrodes located in the effective light-emitting regions, so that the light emission intensity in all directions of the effective light-emitting regions is consistent and the color deviation is effectively improved.

[0170] For example, as Figures 4 to 5CAs shown, in the second color sub-pixel 200, the second connection portion 520 is electrically connected to the second pole of the first light-emitting control transistor T6 through a first connection hole 3021 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer; in the third color sub-pixel 300, the second connection portion 520 is electrically connected to the second pole of the first light-emitting control transistor T6 through a second connection hole 3022 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer, and a second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 is parallel to the Y direction. For example, the second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 may refer to the connection line between the center of the first connection hole and the center of the second connection hole; it may also refer to the connection line between the point of the first connection hole closest to the effective light-emitting area of the second color sub-pixel and the point of the second connection hole farthest from the effective light-emitting area of the third color sub-pixel; it may also refer to the connection line between the point of the first connection hole farthest from the effective light-emitting area of the second color sub-pixel and the point of the second connection hole closest to the effective light-emitting area of the third color sub-pixel.

[0171] For example, as Figures 4 to 5C shown, the effective light-emitting area 201 of the second color sub-pixel 200 includes a first long side 1011 and a second long side 1012 extending in the Y direction, the second long side 1012 is located on the side of the first long side 1011 away from the first via hole 3011, and along the third direction perpendicular to the substrate, the extension line of the first long side 1011 overlaps with the second via hole 3012. For example, the orthographic projection of the second via hole 3012 on a straight line extending in the X direction overlaps with the orthographic projection of the second connection hole 3022 on this straight line. In the embodiments of the present disclosure, when adjusting the position of the second via hole, considering the position of the second connection hole, the position of the second via hole penetrating through the planarization layer is not significantly adjusted in the X direction relative to the position of the second connection hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer, so as to reduce the impact on the overall pixel circuit structure.

[0172] For example, as Figures 4 to 5CAs shown, the effective light-emitting region 301 of the third color sub-pixel 300 includes a third long side 1013 and a fourth long side 1014 extending in the Y direction. The fourth long side 1014 is located on the side of the third long side 1013 away from the second via 3012, and in the direction perpendicular to the substrate, the extension line of the fourth long side 1014 overlaps with the first via 3011. For example, in the direction perpendicular to the substrate, the first connection hole 3021 overlaps with the effective light-emitting region 201 of the second color sub-pixel 200. The first via 3011 is farther from the effective light-emitting region 201 of the second color sub-pixel 200 than the first connection hole 3021, and the orthographic projection of the first via 3011 on the straight line extending in the X direction does not overlap with the orthographic projection of the first connection hole 3021 on this straight line. In the embodiments of the present disclosure, when adjusting the position of the first via, it is necessary to consider that the position of the first via penetrating the planarization layer is slightly adjusted in the X direction relative to the position of the first connection hole penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, and also ensure the distance between the first via and the effective light-emitting region of the second color sub-pixel to prevent affecting the uniformity of the light-emitting intensity in all directions of the effective light-emitting region.

[0173] For example, as Figures 4 to 5C shown, the shortest distance between the first long side 1011 of the effective light-emitting region 201 of the second color sub-pixel 200 and the orthographic projection of the first via 3011 on the substrate is the first distance, and the shortest distance between the third long side 1013 of the effective light-emitting region 301 of the third color sub-pixel 300 and the orthographic projection of the second via 3012 on the substrate is the second distance. The ratio of the first distance to the second distance is 0.8 to 1.2, for example, 0.9 to 1.1. For example, the first distance and the second distance are exactly equal. For example, both the first distance and the second distance are greater than 3 micrometers. The above-mentioned "shortest distance between the first long side 1011 and the orthographic projection of the first via 3011 on the substrate" refers to the distance between the point on the orthographic projection of the first via closest to the orthographic projection of the first long side and the orthographic projection of the first long side. The above-mentioned "shortest distance between the third long side 1013 and the orthographic projection of the second via 3012 on the substrate" refers to the distance between the point on the orthographic projection of the second via closest to the orthographic projection of the third long side and the orthographic projection of the third long side. In the embodiments of the present disclosure, by setting a relatively large distance between the via provided in the planarization layer and the edge of the effective light-emitting region of the sub-pixel, it is possible to prevent the via from affecting the flatness of the second electrode in the effective light-emitting region, thereby ensuring the uniformity of the light-emitting intensity in all directions and effectively improving color deviation.

[0174] For example, as Figures 4 to 5CAs shown, the first long side 1011 of the effective light-emitting region 201 of the second color sub-pixel 200 is a straight side, and the third long side 1013 of the effective light-emitting region 301 of the third color sub-pixel 300 is a straight side. In the embodiments of the present disclosure, when adjusting the positions of the first via and the second via, while ensuring that the via positions do not affect the effective light-emitting region, it is also possible to avoid the edge of the effective light-emitting region being designed with a notch shape to avoid the via, and avoid designing an opening of a special-shaped pixel defining layer, which can reduce problems in the process preparation.

[0175] For example, as Figures 4 to 5C shown, the second electrode 112 of the first pixel block 110 in the first color sub-pixel pair 100 is connected to the second connection portion 520 through the third via 3013 penetrating the planarization layer, and the second electrode 122 of the second pixel block 120 in the first color sub-pixel pair 100 is connected to the second connection portion 520 through the fourth via 3014 penetrating the planarization layer. The first connection line 3103 connecting the third via 3013 and the fourth via 3014 is substantially parallel to the Y direction. In the embodiments of the present disclosure, the third via and the fourth via are arranged on a straight line extending along the Y direction, which can facilitate the process fabrication while ensuring the distance between the via and the corresponding effective light-emitting region.

[0176] For example, the first connection line 3103 connecting the third via 3013 and the fourth via 3014 may refer to the connection line between the center of the third via and the center of the fourth via; it may also refer to the connection line between the point of the third via closest to the first effective light-emitting region and the point of the fourth via closest to the second effective light-emitting region; it may also refer to the connection line between the point of the third via farthest from the first effective light-emitting region and the point of the fourth via farthest from the second effective light-emitting region.

[0177] For example, as Figures 4 to 5C shown, the straight line where the first connection line 3103 is located passes through the first via 3011 and does not pass through the second via 3012. In the embodiments of the present disclosure, the first via connected to the second electrode of the second color sub-pixel, the third via and the fourth via connected to the second electrodes of the first color sub-pixel pair are substantially located on a straight line parallel to the scanning signal line. While ensuring that the distance between the first via and the corresponding effective light-emitting region is greater than 3 micrometers, it is also convenient for fabrication.

[0178] For example, as Figures 4 to 5C shown, along the third direction perpendicular to the substrate, the straight line where the third long side 1013 of the effective light-emitting region 301 of the second color sub-pixel 300 is located overlaps with both the third via 3013 and the fourth via 3014.

[0179] For example, as Figures 4 to 5CAs shown, in the Y direction, a third via hole 3013 or a fourth via hole 3014 is provided between the first via hole 3011 and the second via hole 3012. That is, the third via hole and the fourth via hole are provided on both sides of the first via hole in the Y direction, or the third via hole and the fourth via hole are provided on both sides of the second via hole in the Y direction.

[0180] For example, as Figures 4 to 5C shown, in the first sub-pixel block 110, the second connection portion 520 is electrically connected to the second pole of the first light-emitting control transistor T6 through a third connection hole 3023 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer; in the second sub-pixel block 120, the second connection portion 520 is electrically connected to the second pole of the first light-emitting control transistor T6 through a fourth connection hole 3024 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer, and a fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 substantially coincides with the second connection line 3200.

[0181] For example, the fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 may refer to the connection line between the center of the third connection hole and the center of the fourth connection hole; it may also refer to the connection line between the point of the third connection hole closest to the first effective light-emitting region and the point of the fourth connection hole closest to the second effective light-emitting region; it may further refer to the connection line between the point of the third connection hole farthest from the first effective light-emitting region and the point of the fourth connection hole farthest from the second effective light-emitting region.

[0182] It should be noted that in the embodiments of the present disclosure, the first direction represents the extension direction of the data line, the second direction represents the extension direction of the scanning signal line, and the names of the above two directions can be interchanged; in the embodiments of the present disclosure, the first connection portion represents the connection portion connecting the second pole of the threshold compensation transistor and the gate of the driving transistor, the second connection portion represents the connection portion connecting the second pole of the first light-emitting control transistor and the second electrode of the light-emitting element, and the third connection portion represents the connection portion connecting the first pole of the first reset transistor and the reset power signal line. The names of the above three connection portions can be interchanged.

[0183] Another embodiment of the present disclosure provides a display device, which includes any one of the above display substrates.

[0184] For example, the display device provided by the embodiments of the present disclosure may be an organic light-emitting diode display device.

[0185] For example, in the display device provided by the embodiments of the present disclosure, in the first color sub-pixel pair, for example, the two first color sub-pixels included in the green sub-pixel pair, the ratio of the overlapping area between the second electrodes of the two light-emitting elements and the corresponding two first connection portions is 0.8 to 1.2, for example, 0.9 to 1.1, which can reduce the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the brightness difference between the two first color sub-pixels to improve the display characteristics of the display substrate.

[0186] For example, in the display device provided by the embodiments of the present disclosure, by providing an auxiliary electrode covering one of the two gates of the threshold compensation transistor in one of the green sub-pixels in the first color sub-pixel pair, for example, the green sub-pixel pair, it is possible to prevent external light from directly irradiating the channel region of the threshold compensation transistor and avoid the characteristic shift of the threshold compensation transistor caused by light during the display of the display substrate, thereby preventing the influence on the writing of the gate potential of the driving transistor.

[0187] For example, in the display device provided by the embodiments of the present disclosure, by setting the distances between the second connection portions of the second color sub-pixels, for example, the red sub-pixels, and the adjacent data lines and power signal lines to be approximately equal, the height difference between the middle region (the region without overlap with the data lines and power signal lines) and the two side regions (the regions with overlap with the data lines and power signal lines) of the second electrode of the second color sub-pixel can be reduced, improving the flatness of the second electrode of the second color sub-pixel and improving color deviation.

[0188] For example, in the display device provided by the embodiments of the present disclosure, the effective light-emitting region and the second electrode of the third color sub-pixel, for example, the blue sub-pixel, overlap with the first connection portion. By providing a second spacer at the edge of the effective light-emitting region away from the first connection portion, the height difference of the middle region of the second electrode of the third color sub-pixel in the extending direction of the scanning signal line and the extending direction of the data line can be reduced, which is beneficial to improving the color deviation of the third color sub-pixel.

[0189] For example, in the display device provided by the embodiments of the present disclosure, according to the positions of the effective light-emitting regions of the second color sub-pixel and the third color sub-pixel, the positions of the vias (such as at least one of the first via and the second via) in the planarization layer are adjusted. For example, the connection line between the first via and the second via corresponding to the second color sub-pixel and the third color sub-pixel respectively is not parallel to the extending direction of the scanning signal line, which can ensure the flatness of the second electrodes of the second color sub-pixel and the third color sub-pixel, so as to ensure the consistency of the light-emitting intensity in all directions of the effective light-emitting region and effectively improve color deviation.

[0190] The following points need to be noted:

[0191] (1) In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0192] (2) Where there is no conflict, the features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0193] The above description is only an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: a substrate substrate; a plurality of sub-pixels located on the substrate substrate, each of the sub-pixels including a light-emitting element and a pixel circuit, the light-emitting element including a first electrode, a light-emitting layer, and a second electrode stacked in sequence, the second electrode being located between the light-emitting layer and the substrate substrate, the pixel circuit including a driving transistor and a storage capacitor located between the second electrode and the substrate substrate, and a gate of the driving transistor being multiplexed as one plate of the storage capacitor; wherein, the plurality of sub-pixels include at least one first color sub-pixel pair and a plurality of other color sub-pixels, each of the first color sub-pixel pairs including a first pixel block and a second pixel block, the pixel circuit further includes a threshold compensation transistor, a first pole of the threshold compensation transistor is electrically connected to a first pole of the driving transistor, a second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor, the threshold compensation transistor includes a first gate and a second gate, and the second electrode of the light-emitting element of the first pixel block shields the first gate.

2. The display substrate according to claim 1, wherein, the first pixel block and the second pixel block included in the same first color sub-pixel pair are arranged along a row direction, the other color sub-pixels include second color sub-pixels and third color sub-pixels, the second color sub-pixels and the third color sub-pixels are located in adjacent rows, the display substrate further includes a planarization layer located between the pixel circuit and the second electrode of the light-emitting element, wherein, the planarization layer includes a plurality of vias penetrating therethrough, and the second electrode of the light-emitting element in each of the sub-pixels is electrically connected to a corresponding pixel circuit through the vias, in adjacent rows of sub-pixels, a positive projection of the via of the third color sub-pixel on a straight line extending in a column direction overlaps a positive projection of an effective light-emitting area of the second color sub-pixel on the straight line.

3. The display substrate according to claim 1, further comprising: a plurality of data lines extending in a first direction; a plurality of power signal lines extending in the first direction, wherein, the other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels, and along a direction perpendicular to the substrate substrate, the second electrode of the light-emitting element of at least one third color sub-pixel overlaps two data lines and two power signal lines.

4. The display substrate according to claim 3, wherein, along a direction perpendicular to the substrate substrate, an effective light-emitting area of the light-emitting element of the at least one third color sub-pixel overlaps two data lines.

5. The display substrate according to claim 1, further comprising: a plurality of data lines extending in a first direction; a plurality of power signal lines extending in the first direction, wherein, the other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels, and along a direction perpendicular to the substrate substrate, the second electrode of the light-emitting element of at least one second color sub-pixel overlaps two data lines.

6. The display substrate according to claim 1, wherein, The multiple sub-pixels include a plurality of first color sub-pixel pairs arranged in a second direction. The plurality of first color sub-pixel pairs include a plurality of first pixel blocks and a plurality of second pixel blocks arranged alternately in the second direction. The two distances between the effective light-emitting regions of the first pixel block and the effective light-emitting regions of the two second pixel blocks located on both sides of the effective light-emitting region of the first pixel block in the second direction are different; The display substrate further includes a data line extending in a first direction, and the included angle between the second direction and the first direction is in the range of 80° to 100°.

7. The display substrate according to claim 6, wherein, The other color sub-pixels further include a plurality of second color sub-pixels and a plurality of third color sub-pixels, The pixel circuits of the multiple sub-pixels include pixel circuit rows arranged in a column direction. Each pixel circuit row includes pixel circuits arranged in a row direction. The centers of the effective light-emitting regions of some of the second color sub-pixels and some of the third color sub-pixels connected to the pixel circuits in the same pixel circuit row are not on a straight line.

8. The display substrate according to claim 7, wherein, The other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels. The second electrode of the light-emitting element of the third color sub-pixel includes a main electrode and a connection electrode. The connection electrode is configured to be electrically connected to the pixel circuit. In a direction perpendicular to the substrate, the effective light-emitting region of the third color sub-pixel overlaps with the main electrode, and the main electrode of the third color sub-pixel overlaps with the second gate.

9. The display substrate according to claim 7, wherein, The second electrode of the light-emitting element of at least one color sub-pixel includes a main electrode and a connection electrode. The connection electrode is configured to be electrically connected to the pixel circuit. In a direction perpendicular to the substrate, the effective light-emitting region of the at least one color sub-pixel overlaps with the main electrode; In the first color sub-pixel pair, the second electrode of the light-emitting element further includes an auxiliary electrode, and the auxiliary electrode covers a part of the active layer between the positive projections of the first gate and the second gate on the active layer.

10. The display substrate according to claim 1, wherein, The pixel circuit further includes a threshold compensation transistor, a first light-emitting control transistor, a first connection part, and a second connection part located between the second electrode of the light-emitting element and the substrate. The first pole of the threshold compensation transistor is electrically connected to the first pole of the driving transistor. The second pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor through the first connection part. The first pole of the first light-emitting control transistor is electrically connected to the first pole of the driving transistor. The second pole of the first light-emitting control transistor is electrically connected to the second electrode of the light-emitting element through the second connection part; The other color sub-pixels include second color sub-pixels and third color sub-pixels, and the shape of the second connection part of the second color sub-pixel is different from the shape of the second connection part of the third color sub-pixel.

11. The display substrate according to claim 10, further Including: A light emission control signal line, extending along the row direction and provided on the same layer as the gate of the driving transistor, wherein the second connection portion overlaps with the light emission control signal line and does not overlap with the gate of the driving transistor.

12. The display substrate according to claim 1, wherein, In the first color sub-pixel pair, the second electrode of each light-emitting element includes a main electrode and a connection electrode, the connection electrode is configured to be electrically connected to the pixel circuit, in a direction perpendicular to the substrate, the effective light-emitting region in the first pixel block overlaps with the main electrode, and the effective light-emitting region in the second pixel block overlaps with the main electrode; In the first color sub-pixel pair, the shapes of the two main electrodes are substantially the same and the sizes are substantially the same, and the shapes of the two connection electrodes are different.

13. The display substrate according to claim 12, wherein, In the first color sub-pixel pair, the second electrode of the light-emitting element further includes an auxiliary electrode; In the first color sub-pixel pair, the shapes of the two auxiliary electrodes are different.

14. The display substrate according to claim 10, further including: Multiple data lines, extending along a first direction; wherein, the center line extending along the first direction in the effective light-emitting region of the second color sub-pixel overlaps with the second connection portion.

15. The display substrate according to claim 14, further including: A power supply signal line, extending along the first direction, the power supply signal line is on the same layer as the data line and is alternately arranged, the power supply signal line includes a first power supply signal line; The second connection portion includes a first sub-connection portion connected to each other and a first pad located on a side of the first sub-connection portion close to the first power supply signal line, The center line passing through the center of the second color sub-pixel's effective light-emitting region and extending along the first direction is located on a side close to the first pad of the center line passing through the center of the first sub-connection portion and extending along the first direction.

16. The display substrate according to claim 15, wherein, The shape of the second connection portion in the second color sub-pixel is L-shaped, and along the first direction, the size of the first sub-connection portion is larger than the size of the first pad.

17. The display substrate according to claim 15, wherein, The data line includes a first data line and a second data line, the first data line and the second data line are alternately arranged, the power supply signal line further includes a second power supply signal line, the second power supply signal line and the first power supply signal line are alternately arranged; The effective light-emitting region of the third color sub-pixel overlaps with the first data line, the first power supply signal line, the second data line, and the second power supply signal line.

18. The display substrate according to claim 17, wherein, In a direction perpendicular to the substrate, among the overlapping portions of the second electrodes of the third color sub-pixels with the first data line, the first power supply signal line, the second data line, and the second power supply signal line, the ratio of the overlapping area of the first power supply signal line and the second data line with the effective light-emitting region to the overlapping area of the second power supply signal line and the first data line with the effective light-emitting region is 0.8 to 1.

2.

19. A display device, comprising the display substrate according to any one of claims 1-18.

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