Compiling method, chip, electronic device and computer readable storage medium for executing program

Abstract

Embodiments of the present disclosure disclose a compiling method of an execution program, a chip, an electronic device and a computer readable storage medium. The compiling method of the execution program comprises: obtaining a total amount of data of each subprogram in an original program; determining a number of processing cores required for executing each subprogram according to the total amount of data of each subprogram; grouping the subprograms according to the number of processing cores required for executing each subprogram; determining a storage location of intermediate data of the grouping; determining a location of a synchronization point; and compiling the original program into an execution program according to the grouping, the storage location of the intermediate data of the grouping and the location of the synchronization point. The storage location of the intermediate data of the grouping is determined in the above method, so that the data exchange between the processing core and the external memory is reduced, and the technical problem that the program in the prior art needs to frequently access the external memory when executed is solved.

Description

Technical Field

[0001] This disclosure relates to the fields of program compilation and processors, and more particularly to a method for compiling an executable program, a chip, an electronic device, and a computer-readable storage medium. Background Technology

[0002] When multi-core CPUs or GPUs perform neural network tasks, there are generally two processing methods:

[0003] The first type involves each processing core handling its own task independently, without interference between cores, as shown in the attached diagram. Figure 1a As shown; the second type involves some or all processing cores processing a task in parallel, with each core completing a portion of the task, as shown in the attached figure. Figure 1b As shown.

[0004] In both methods described above, the compiler, based on the structure of the neural network and following the characteristics of traditional multi-core CPUs or GPUs, compiles a suitable program to perform neural network calculations. The cache within each processing core is transparent to the program and cannot be directly accessed independently. All data reads and writes during computation are performed by the processing cores based on DDR (Double Data Rate) memory access addresses. Neural network computation generates a large amount of intermediate data, and most of the intermediate data between layers is unrelated. Due to the spatial and temporal locality of the cache, it easily suffers from a low hit rate in neural network computation, frequently accessing DDR memory, thus reducing the computation speed of the neural network and reducing power consumption. Summary of the Invention

[0005] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] To address the technical problems of inflexible task scheduling and complex control in existing technologies for processing kernels, this disclosure proposes the following technical solution:

[0007] In a first aspect, embodiments of this disclosure provide a method for compiling an executable program, comprising:

[0008] Obtain the total amount of data for each subroutine in the original program;

[0009] The number of processing cores required to execute each subroutine is determined based on the size of the data storage area of ​​the multiple processing cores and the total amount of data of each subroutine;

[0010] The subroutines are grouped according to the number of processing cores required to execute each subroutine, and a corresponding number of processing cores are allocated to each group;

[0011] Determine the storage location of the intermediate data in the group;

[0012] The location of the synchronization point is determined based on the size of the parameters of each subroutine and the size of the parameter storage area of ​​the processing core;

[0013] The original program is compiled into an executable program based on the group, the storage location of the intermediate data of the group, and the location of the synchronization point.

[0014] Furthermore, determining the storage location of the intermediate data of the group includes:

[0015] Determine the number of times the group will be executed in a loop;

[0016] If the current loop execution count is not the last one, then the intermediate data of the group is stored in the external storage area;

[0017] If the current loop execution count is the last one, then the intermediate data of the group is stored in the data storage area of ​​the processing core belonging to the next group.

[0018] Furthermore, the step of grouping the subroutines according to the number of processing cores required to execute each subroutine, and allocating a corresponding number of processing cores to the groups, includes:

[0019] The subroutines are grouped according to the number of processing cores required to execute each subroutine and the total number of processing cores;

[0020] The number of processing cores allocated to each group is determined by the number of processing cores required to execute the subroutines in each group and the total number of processing cores; wherein the same number of processing cores are allocated to the same group.

[0021] Furthermore, the original program includes multiple subroutines, which are executed sequentially. Determining the grouping of the subroutines based on the number of processing cores required to execute each subroutine and the total number of processing cores includes:

[0022] Obtain the number of processing cores required to execute each subroutine in turn;

[0023] The first value of the subroutine is calculated as a value that is divisible by the total number of processing cores and is not less than the number of processing cores required to execute the subroutine; wherein, each subroutine corresponds to one first value;

[0024] Subroutines corresponding to consecutive identical first values ​​are grouped together as a single subroutine.

[0025] Furthermore, the original program includes multiple subroutines, which are executed sequentially. Determining the grouping of the subroutines based on the number of processing cores required to execute each subroutine and the total number of processing cores includes:

[0026] Obtain the number N of processing cores required to execute each subroutine sequentially. i Where i represents the subroutine number;

[0027] Get the current N i The maximum value Nmax1 in the range;

[0028] Get the subroutine number j1 with the largest number among all subroutines corresponding to Nmax1;

[0029] The subroutines preceding j1 are identified as the group corresponding to j1.

[0030] Furthermore, the step of allocating a corresponding number of processing cores to the group based on the number of processing cores required to execute the subroutines in each group and the total number of processing cores includes:

[0031] The number of processing cores Ng1 corresponding to the group j1 is calculated as the value that is divisible by the total number of processing cores M0 and is not less than Nmax1.

[0032] Furthermore, the method also includes:

[0033] Treat the subroutines after j1 as all subroutines, and Ng1 as the total number of processing cores. Continue to execute the steps of determining the group and the number of processing cores corresponding to the group to obtain the group corresponding to j2 and the number of processing cores Ng2 of the group corresponding to j2.

[0034] If Ng2 equals Ng1, then merge the group corresponding to j1 and the group corresponding to j2 into one group;

[0035] If Ng2 is not equal to Ng1, then the group corresponding to j2 is treated as a new group.

[0036] Furthermore, the method also includes:

[0037] Continue executing the steps above to determine the grouping and the number of processing cores corresponding to the grouping, treating the subroutines after j2 as all subroutines and Ng2 as the total number of processing cores, until all subroutines have corresponding groups.

[0038] Furthermore, compiling the original program into an executable program based on the grouping, the storage location of the intermediate data of the grouping, and the location of the synchronization point includes:

[0039] The original program is compiled into an executable program based on the group, the number of times the group is executed in a loop, the storage location of the intermediate data corresponding to the current execution number, and the location of the synchronization point.

[0040] Secondly, embodiments of this disclosure provide a chip, comprising:

[0041] Multiple processing cores and a synchronization signal generator; each processing core includes a data storage area and a parameter storage area;

[0042] The plurality of processing cores are grouped according to the execution program, wherein the processing cores in each group are used to execute the plurality of program segments corresponding to the group of subroutines in the execution program; wherein the data storage area is used to store the input data and output data of the plurality of program segments, and the parameter storage area is used to store the parameters of the plurality of program segments;

[0043] The synchronization signal generator is used to send a synchronization signal to all processing cores when all processing cores executing the program segment have finished executing.

[0044] Thirdly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement the compilation method of any of the executable programs described in the second aspect above.

[0045] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the compilation method of any of the executable programs described in the second aspect above.

[0046] Fifthly, embodiments of this disclosure provide a computer program product, characterized in that: it includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any of the compilation methods of the executable program described in the second aspect above.

[0047] In a sixth aspect, embodiments of this disclosure provide a computing device, characterized in that it includes any of the chips described in the second aspect.

[0048] This disclosure provides a method for compiling an executable program, a chip, an electronic device, and a computer-readable storage medium. The method includes: obtaining the total data volume of each subroutine in the original program; determining the number of processing cores required to execute each subroutine based on the size of the data storage area of ​​the plurality of processing cores and the total data volume of each subroutine; grouping the subroutines according to the number of processing cores required to execute each subroutine, and allocating a corresponding number of processing cores to each group; determining the storage location of intermediate data in each group; determining the location of a synchronization point based on the size of the parameters of each subroutine and the size of the parameter storage area of ​​the processing cores; and compiling the original program into an executable program based on the group, the storage location of the intermediate data in the group, and the location of the synchronization point. The method determines the storage location of intermediate data in each group, reducing data exchange between the processing cores and external memory, thus solving the technical problem in the prior art where programs need to frequently access external memory during execution.

[0049] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0050] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0051] Figure 1a and 1b This is a schematic diagram of existing technology;

[0052] Figure 2 A flowchart illustrating the compilation method of the executable program provided in this embodiment of the disclosure;

[0053] Figure 3 A further flowchart illustrating the compilation method of the executable program provided in this embodiment of the disclosure;

[0054] Figure 4 A further flowchart illustrating the compilation method of the executable program provided in this embodiment of the disclosure;

[0055] Figure 5 A further flowchart illustrating the compilation method of the executable program provided in this embodiment of the disclosure;

[0056] Figure 6A further flowchart illustrating the compilation method of the executable program provided in this embodiment of the disclosure;

[0057] Figure 7 A further flowchart illustrating the compilation method of the executable program provided in this embodiment of the disclosure;

[0058] Figure 8a Example diagram of a chip provided in an embodiment of this disclosure;

[0059] Figure 8b This is a schematic diagram of the neural network to be compiled in an embodiment of this disclosure;

[0060] Figures 9a-9e This is a schematic diagram illustrating the process of the grouping subroutine being executed by the processing core in an embodiment of this disclosure. Detailed Implementation

[0061] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0062] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0063] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0064] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0065] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0066] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0067] Figure 2 This is a flowchart illustrating a method for compiling an executable program according to an embodiment of the present disclosure. The method is used in a system comprising multiple processing cores, each processing core including a storage area for storing relevant data of the executable program. The relevant data of the executable program includes input data, output data, program instruction data, and parameter data, etc. Correspondingly, the storage area includes a data storage area for storing the input and output data of the executable program, a program storage area for storing the program instruction data, and a parameter storage area for storing the parameter data.

[0068] The method includes:

[0069] Step S201: Obtain the total amount of data for each subroutine in the original program.

[0070] The total amount of data in the subroutine is the sum of the size of the input data and the size of the output data of the subroutine.

[0071] For example, the original program is a neural network, and the subroutine is a layer of the neural network.

[0072] In this optional embodiment, the original program includes multiple subroutines. When the original program is executed, the subroutines are executed sequentially in order. The output data of a subroutine is the input data of the next subroutine or the output data of the original program.

[0073] When the original program is a neural network, step S201 includes:

[0074] Analyze the size of the input and output data of each layer in the neural network; generate the total data volume of each layer in the neural network, which is the sum of the input and output data sizes. Neural networks can typically be represented as a graph, with each layer including the size of the input and output data, such as the dimensions of the input and output data. Therefore, the total data volume of each sub-network layer in the neural network can be obtained by analyzing the graph representing the neural network.

[0075] It is understood that the original program can be any other type of program, and the subroutine of the original program can be a program module divided according to functional modules in the original program or a program module that obtains output data from output data according to the program execution order.

[0076] Since the original program may contain intermediate data during execution, such as the output data of the subroutines mentioned above, in order to avoid accessing the storage area outside the processing core for each or some intermediate data, the total amount of data for each subroutine of the original program is first calculated in this step.

[0077] return Figure 2 The compilation method for the executable program further includes:

[0078] Step S202: Determine the number of processing cores required to execute each subroutine based on the size of the data storage area of ​​the multiple processing cores and the total amount of data of each subroutine.

[0079] After obtaining the total data volume of each subroutine of the original program, in step S202, the size of the data storage area of ​​the multiple processing cores is obtained, and the number of processing cores required to execute the original program is calculated based on the total data volume of the subroutines and the size of the data storage area. The total size of the data storage area of ​​the processing cores used to execute the original program is not less than the total data volume of the subroutines, so that the storage area outside the processing cores does not need to be accessed during calculation.

[0080] Optionally, step S202 includes:

[0081] Step S301: Calculate the quotient of the total data volume of each subroutine and the size of the data storage area of ​​the processing core;

[0082] Step S302: Round up the value of each quotient and use it as the number of processing cores required to execute each subroutine.

[0083] In step S301, assuming the data storage area of ​​each processing core is the same size, multiple quotients are obtained by dividing the total data of each subroutine by the size of the data storage area. These quotients may or may not be integers. Therefore, in step S302, the integer value of these quotients is used as the number of processing cores required to execute each subroutine. It can be understood that in the result calculated in step S302, each subroutine corresponds to a number of processing cores required to execute it. When the data storage area of ​​each processing core is not the same size, the minimum value of the data storage area in each processing core can be used as the size of the data storage area used to calculate the quotient, ensuring that each processing core can store the input and output data of each subroutine without using external memory.

[0084] return Figure 2 The compilation method for the executable program further includes:

[0085] Step S203: Group the subroutines according to the number of processing cores required to execute each subroutine, and allocate a corresponding number of processing cores to the group.

[0086] In this embodiment of the disclosure, subroutines are grouped, and subroutines in the same group use the same number of processing cores when executed.

[0087] Optionally, step S203 includes:

[0088] Step S401: Determine the grouping of the subroutines based on the number of processing cores required to execute each subroutine and the total number of processing cores;

[0089] Step S402: Allocate a corresponding number of processing cores to the group according to the number of processing cores required to execute the subroutines in each group and the total number of processing cores; wherein, the same number of processing cores are allocated to the same group.

[0090] In steps S401 and S402 above, the number of processing cores required to execute each subroutine is determined based on the number of processing cores required to execute each subroutine and the total number of processing cores. Then, subroutines that require the same number of processing cores are grouped into a subroutine group, and the required number of processing cores is allocated to each subroutine group.

[0091] The plurality of subroutines are executed sequentially; for example, the plurality of subroutines are multi-layer subnetworks in a neural network. Optionally, in one embodiment, step S401 includes:

[0092] Step S501: Obtain the number of processing cores required to execute each subroutine in sequence;

[0093] Step S502: Calculate a value that is divisible by the total number of processing cores and is not less than the number of processing cores required to execute the subroutine, and use this value as the first value of the subroutine; wherein, each subroutine corresponds to one first value;

[0094] Step S503: Sequentially determine the subroutines corresponding to consecutive identical first values ​​as a group of subroutines.

[0095] In step S501 above, the number of processing cores required to execute each subroutine is obtained sequentially according to the order of the subroutines. For example, the number of processing cores required to execute each subroutine are N1, N2, ... N. l , where N i This represents the number of processing cores required to execute the i-th subroutine. Here, i is an integer greater than 1 and less than l, where l is the number of subroutines.

[0096] In step S502 above, a value that divides the total number of processing cores and is not less than the number of processing cores required to execute the subroutine is calculated as the first value of the subroutine. This first value divides the total number of processing cores and is not less than N. i The minimum value. For example, when the total number of processing cores M0 = 9 and N1 = 4, 4 is not divisible by 9, so 4 is incremented by 1 to get 5. 5 is also not divisible by 9, so 5 is incremented by 1, and so on, until it is incremented to 9. 9 is divisible by 9, so 9 is taken as the first value corresponding to the first subroutine. In this step, each subroutine can obtain its corresponding first value.

[0097] In step S503, subroutines corresponding to consecutive identical first values ​​are grouped into a subroutine group. Specifically, for example, if the original program has 5 subroutines executed sequentially, with corresponding first values ​​of 4, 3, 3, 3, and 1, then the first subroutine forms the first subroutine group, the second, third, and fourth subroutines form the second subroutine group, and the fifth subroutine forms the third subroutine group.

[0098] Upon or after obtaining the subroutine group, the number of processing cores corresponding to each subroutine group can be determined based on the first value. In this embodiment, the first value corresponds to the number of processing cores corresponding to each subroutine. As in the example above where M=9 and N1=4, although executing the first subroutine only requires 4 processing cores, in order to avoid wasting processing power, the total number of processing cores needs to be evenly distributed. Therefore, all 9 processing cores are allocated to the first subroutine for execution.

[0099] Optionally, in another embodiment, step S401 includes:

[0100] Obtain the number N of processing cores required to execute each subroutine sequentially. i Where i represents the subroutine number;

[0101] Get the current N i The maximum value N in max1 ;

[0102] Get all N max1 The subroutine with the largest number in the corresponding subroutine is subroutine j1;

[0103] The subroutines preceding j1 are identified as the group corresponding to j1.

[0104] Since subroutines with low processing core requirements can be executed by a higher number of processing cores than their required number, in this embodiment, the current N is first obtained. i The maximum value N in max1 And obtain all N max1If the subroutine with the largest number is numbered j1, then j1 and the subroutines before j1 can actually be executed using the same number of processing cores, and therefore can be grouped into the same subroutine group.

[0105] In another embodiment, step S402 includes:

[0106] Calculate the total number M0 that can divide the processing cores and is not less than N. max1 The value is used as the number of processing cores Ng1 for the group corresponding to j1.

[0107] The calculation process is the same as the process of calculating the first value of a subroutine in step S502 above, and will not be repeated here. In this embodiment, the calculated Ng1 is used as the number of processing cores corresponding to the entire subroutine group.

[0108] After the above steps, it may be impossible to group all subroutines. Therefore, in this embodiment, the method further includes:

[0109] Treat the subroutines after j1 as all subroutines, and Ng1 as the total number of processing cores. Continue to execute the steps of determining the group and the number of processing cores corresponding to the group to obtain the group corresponding to j2 and the number of processing cores Ng2 of the group corresponding to j2.

[0110] If Ng2 equals Ng1, then merge the group corresponding to j1 and the group corresponding to j2 into one group;

[0111] If Ng2 is not equal to Ng1, then the group corresponding to j2 is treated as a new group.

[0112] In the above steps, the number of all subroutines and the total number of processing cores are all subsets of the original number of subroutines and the total number of processing cores. The steps of determining the subroutine group and the number of processing cores corresponding to the group are continued to be executed to obtain the group corresponding to j2 and the number of processing cores Ng2 of the group corresponding to j2.

[0113] Next, it is determined whether Ng2 and Ng1 are equal. If they are equal, the group corresponding to j1 and the group corresponding to j2 use the same data processing core and can be merged into a single subroutine group. If Ng2 is not equal to Ng1, then the group corresponding to j2 is treated as a new group.

[0114] Next, in order to complete the grouping of all subroutines, the subroutines after j2 are treated as all subroutines, and Ng2 is treated as the total number of processing cores. The above steps of determining the grouping and the number of processing cores corresponding to the grouping are continued until all subroutines have corresponding groups.

[0115] Return to Appendix Figure 2The compilation method for the executable program further includes:

[0116] Step S204: Determine the storage location of the intermediate data of the group;

[0117] In this disclosure, the intermediate data generated by the processing cores within a group includes the group's output data, which is stored in memory outside the processing core or in memory within the processing core. Typically, to ensure full utilization of the computing power of the processing cores between groups, the group usually executes multiple times in a loop to perform multiple tasks. After each loop, the output data is stored in memory outside the processing core, such as in the on-chip shared memory area (SM), to serve as input data for subsequent groups. However, if all intermediate data is stored in memory outside the processing core, it will affect the efficiency of the processing core in reading input data.

[0118] To solve this problem, optionally, step S204 includes:

[0119] Step S601: Determine the number of times the group will be executed in a loop;

[0120] Step S602: If the current loop execution count is not the last time, then the intermediate data of the group is stored in the external storage area.

[0121] Step S603: If the current loop execution count is the last one, then the intermediate data of the group is stored in the data storage area of ​​the processing core belonging to the next group.

[0122] Furthermore, if a task is executed sequentially according to the grouping order, there may be a problem of wasted computing power during the computation process. For example, if each processing core group in the first group corresponds to 8 processing cores, and each processing core group in the second group corresponds to 4 processing cores, then the data output from each task executed by the first group can only be used by the 4 processing cores in one processing core group of the second group, while the other 4 processing cores will be idle. To avoid wasting computing power, the first group can execute two tasks in a loop, thus outputting two sets of data to the two processing core groups in the next group respectively.

[0123] Therefore, in step S601, the number of times the group is executed in a loop is determined. This step includes: calculating the number of processing cores in the next group of the group as the number of times the group is executed in a loop.

[0124] The number of processing cores in the group is defined as A. k Where k represents the group number, then A k =M k-1 / N gk M k-1=N g(k-1) That is, the number of processing cores in the k-th group is the quotient of the number of processing cores in a processing core group of the (k-1)-th group and the number of processing cores in a processing core group of the k-th group; since the output data generated by the multiple loop calculations of the k-th group needs to be used as the input data for one calculation of the (k+1)-th group, the number of loop executions C of the k-th group is... k =A (k+1) Where last represents the maximum number of the subroutine group; 1≤k≤last, and C last =1; M0 represents the total number of processing cores.

[0125] In actual implementation, if we disregard the wasted computing power of the processing cores within the group, the number of iterations can be less than C. k The value of will not be elaborated here.

[0126] In steps S602 and S603, a judgment condition is set to determine whether the current loop execution count is the last loop execution of the group. If it is not the last loop, it means that the group still needs to continue to execute other tasks, and the processing core still needs to obtain input data for other tasks of the current group. Therefore, the intermediate data generated in the current loop needs to be stored in the external storage area. If it is the last loop, it means that the group does not need to continue to execute other tasks. When the processing core executes a task next time, it will execute the task of the next group in the allocation method of the next group. At this time, the intermediate data generated in the current group loop does not need to be stored in the external storage area, but can be directly stored in the data storage area of ​​the processing core in the next group as the input data of the next group. In this way, when the next group executes a task, it can reduce the number of times it obtains input data from the external storage area, thereby speeding up the execution speed of the processing core.

[0127] During the execution of steps S602 and S603 above, when a group is executing tasks in a loop, all groups preceding that group are also included and executed in a loop.

[0128] For example, for the first group LG1, the number of its processing cores is A1, and its loop count is A2, which is the same as the number of processing cores in the second group LG2. LG1 needs to execute A2 times to generate A1*A2 output data to meet the input data volume required for parallel computation by all processing cores in LG2. During the cyclic execution of tasks in LG1, except for the A2th iteration, the processing cores retrieve input data from the external storage area, and the output data is temporarily stored in this external storage area. However, in the A2th iteration, the processing core retrieves input data from the external storage area, and the output data is split according to LG2's data splitting rules and directly written to the processing core storage area of ​​any processing core group in LG2. This reduces data exchange with external storage areas during LG2's task execution.

[0129] For LG2, after obtaining the results of the LG1 loop execution, i.e., the A1*A2 outputs of LG1, it can only calculate one set of input data that satisfies the parallel operation of the processing cores of one processing core group in the third group LG3. If the processing core groups of LG3 need to run in parallel, the above-mentioned LG2 needs to loop A3 times. It should be noted that the A3 times here refers to LG2, and each loop of LG2 needs to include A2 loops of LG1. The process of each loop of LG1 is the same as the description of the LG1 loop above, and will not be repeated here. Overall, except for the A3th loop, in each other loop, the processing core obtains input data from the external storage area of ​​the processing core, and the output data after calculation is temporarily stored in the external storage area; while in the A3th loop, the processing core obtains input data from the external storage area of ​​the processing core, and the output data after calculation is split according to the data splitting rules of LG2 and directly written into the processing core storage area of ​​any processing core group of LG2. In this way, when LG2 executes a task, the amount of data exchange with the external storage area can be reduced; since LG2 has A1*A2 processing cores in groups, and each processing core group runs A3 times, there are a total of A1*A2*A3 outputs after the loop ends, which can meet the input data volume when all processing cores in LG3 are processed in parallel.

[0130] As described in the loop process above, each group's loop contains nested loops of all the previous groups. For any group LGm, the loop always starts from LG1 and iterates A(m+1) times, producing Nm outputs to satisfy the input data required for parallel computation by each processing core of the (m+1)th group LG(m+1), where Nm = A1 * A2 * ... * A(m+1). Thus, during the loop execution, for each group, it's unnecessary to store all intermediate computation results outside the processing core's memory, nor is it necessary to store the intermediate computation results of all previous groups outside the processing core's memory. Only the input data required for parallel computation by each processing core within this group—that is, the intermediate computation results of previous groups—needs to be stored outside the processing core's memory. In other words, any group can begin computation as soon as it receives the input data necessary for parallel computation by all processing cores, avoiding excessive accumulation of intermediate data, reducing access to the storage area outside the processing core, and fully utilizing the storage area within the processing core.

[0131] Return to Appendix Figure 2 The compilation method for the executable program further includes:

[0132] Step S205: Determine the location of the synchronization point based on the size of the parameters of each subroutine and the size of the parameter storage area of ​​the processing core.

[0133] The instructions of the subroutine between the two synchronization points are the program instructions that the processing core needs to execute within a synchronization cycle.

[0134] The parameter storage area of ​​the processing kernel is used to store the parameters of subroutines in the original program, such as the size of the convolutional kernels, weight values, and stride used in each layer of the convolutional neural network. The size of the parameter storage area in the processing kernel determines the number of program instructions that can be executed in a synchronization cycle. If the parameter storage area in the processing kernel can store all the parameters of the next layer of the subnetwork, then in a synchronization cycle, the processing kernel can complete the calculation of a layer of the subnetwork without reading parameters from the storage area outside the processing kernel. In this case, the synchronization point can be set at the end of the program instructions of each subnetwork. However, in some cases, the parameter storage area of ​​the processing kernel is relatively small and cannot store all the parameters of a layer of the subnetwork. In this case, it is necessary to insert a synchronization point in the subnetwork to determine the position where the parameters stored in the parameter storage area can be executed.

[0135] Furthermore, step S205 above includes:

[0136] Step S701: Determine the number of parameters of the subroutine that the parameter storage area of ​​the processing core can store based on the size of the parameter storage area of ​​the processing core and the size of the parameters of the subroutine.

[0137] Step S702: Determine the location of the synchronization point of the subroutine based on the number of parameters of the subroutine that can be stored in the parameter storage area of ​​the processing core.

[0138] In this embodiment, the number of parameters that the parameter storage area can store can be determined by the size of the subroutine's parameters and the size of the parameter storage area. The positions of the synchronization points of the multiple subroutines are then determined based on the number of parameters. For example, if the size of the subroutine's parameters is 50KB and the size of the parameter storage area is 25KB, a synchronization point needs to be inserted at the midpoint of the subroutine. This process of determining the synchronization point positions is performed for each subroutine, resulting in the positions of all synchronization points in the original program.

[0139] Furthermore, after obtaining the location of the synchronization point, step S205 further includes: adding a synchronization instruction at the location of the synchronization point; wherein the synchronization instruction is used to cause the system comprising multiple processing cores to generate a synchronization signal. That is, after the processing cores have executed the program instructions between the synchronization points, they continue to execute the synchronization instruction. Optionally, after the processing cores execute the synchronization instruction, they generate a synchronization request signal, requesting the system comprising multiple processing cores to generate a synchronization signal. The system includes a synchronization signal generator. After receiving the synchronization request signal issued by each processing core participating in the program execution in the system, the synchronization signal generator generates a synchronization signal, causing the multiple processing cores to enter the next different cycle to execute subsequent program instructions.

[0140] Return to Appendix Figure 2 The compilation method for the executable program further includes:

[0141] Step S206: Compile the original program into an executable program according to the group, the storage location of the intermediate data of the group, and the location of the synchronization point.

[0142] The executable program includes multiple program segments, generated with the synchronization point as the dividing point. Each program segment includes instructions from the original program and control instructions required by the processing core to execute the instructions in the original program. The control instructions include synchronization instructions between program segments, intermediate data storage instructions, and task grouping instructions generated according to the grouping. The task grouping instructions are used to divide the processing core into at least one group to execute a group of program segments specified in the task grouping instructions. Each group of program segments corresponds to a program segment corresponding to a subroutine in a subroutine group. As described above, synchronization points are inserted in the subroutines, and multiple program segments are divided by the synchronization point. Therefore, the instructions contained in a program segment may be some or all of the instructions in a subroutine, or instructions from multiple subroutines.

[0143] The control instructions are used by the processing core to read parameters and / or the next program segment required for the next synchronization cycle in each synchronization cycle. The program segment also includes the aforementioned synchronization instructions at the end to generate a synchronization request signal. The number of processing cores is used to generate allocation information and / or grouping information in the executable program, used by the system comprising multiple processing cores to group the multiple processing cores and allocate program segments, parameters, and input data when executing the executable program.

[0144] The intermediate data storage instruction is used to indicate the storage location of the intermediate data generated by each group in each cycle. For example, the intermediate data generated in the last cycle of each group is pre-set to be stored in the internal storage area of ​​the processing core of the next group; the intermediate data generated in other cycles is stored in the external storage area of ​​the processing core.

[0145] It is understood that the external storage area of ​​the processing core described in this disclosure includes storage areas within a multi-processor core system, such as on-chip shared memory, or storage areas outside the multi-processor core system, such as DDR memory.

[0146] The compilation method described above compiles the original program into an executable program suitable for execution on a multi-processor system. The compilation of the executable program is based on the total amount of input and output data and the size of the parameters of the original program. This enhances the compatibility between the executable program and the multi-processor system, improving the effective computing power of the multi-processor system. In addition, the intermediate data generated by the original program can be moved within the multi-processor system as much as possible, reducing data exchange with external memory, thereby reducing latency, reducing the pressure on the bandwidth of external memory, and also reducing the power consumption of the entire multi-processor system. The original program is optimized, reducing the amount of intermediate data written outside the processing core, reducing the demand for on-chip processing core external storage space, and thus reducing the cost of the chip.

[0147] In this embodiment, step S206 further includes:

[0148] The original program is compiled into an executable program based on the group, the number of times the group is executed in a loop, the storage location of the intermediate data corresponding to the current execution number, and the location of the synchronization point.

[0149] In this embodiment, information about the number of times each group is executed in a loop is added. This allows multiple input data sets to be used during the actual execution of the original program, enabling the earlier-numbered groups to execute multiple times in a loop, thus obtaining input data for the later-numbered groups to execute multiple tasks in parallel, making fuller use of the processing core's computing power. The intermediate data is stored in different locations for different loop counts to save external storage space on the processing core.

[0150] For example, the number of times the group is executed in a loop is used to generate control instructions in the executor, so that after each group finishes executing the current task, it determines whether to continue to obtain input data for the next task based on the number of times the group is executed in a loop.

[0151] Furthermore, in or after step S202, after calculating the number of processing cores required to execute each subroutine in this step, the amount of input data for each processing core can be further calculated, that is, the input data of each subroutine is evenly distributed to each processing core in the group of processing cores. Specifically, the input data can be divided into N equal parts. i The input data is divided into parts; however, in some cases, the input data may overlap between processing cores. In this case, it is necessary to calculate the number N of processing cores required to execute each subroutine. i Adjustments are made in time so that N i Satisfy: M0≥D m +D in / N i Where M0 is the size of the data storage area for the processing core, and D... m This refers to the incremental data generated due to data overlap when an additional processing core is added. Therefore, the input data allocated to each processing core is D. m +D in / N i After subroutine grouping, the number of processing cores corresponding to each group is not less than the number of processing cores required by each subroutine in the group. Therefore, the number of processing cores corresponding to the subroutine group is used as the N mentioned above. i The above conditions are also met. In this way, the size of the input data that each processing core needs to receive, as well as the segmentation method of the input data for each subroutine, can be determined in advance for a task.

[0152] The above embodiments disclose a method for compiling an executable program. This method includes: obtaining the total data volume of each subroutine in the original program; determining the number of processing cores required to execute each subroutine based on the size of the data storage area of ​​the multiple processing cores and the total data volume of each subroutine; grouping the subroutines according to the number of processing cores required to execute each subroutine, and allocating a corresponding number of processing cores to each group; determining the storage location of intermediate data in each group; determining the location of a synchronization point based on the size of the parameters of each subroutine and the size of the parameter storage area of ​​the processing cores; and compiling the original program into an executable program based on the group, the storage location of the intermediate data in the group, and the location of the synchronization point. The above method determines the storage location of intermediate data in each group, reducing data exchange between the processing cores and external memory, thus solving the technical problem in the prior art where programs need to frequently access external memory during execution.

[0153] Figure 8a This is an example of a schematic diagram of a system including multiple processing cores provided in an embodiment of this disclosure. Figure 8a As shown, in this example, the system comprising multiple processing cores is a chip, and the chip 800 includes:

[0154] Multiple processing cores 801 and a synchronization signal generator 802; wherein each processing core includes a data storage area 803 and a parameter storage area;

[0155] The plurality of processing cores 801 are used to group according to the execution program, wherein the processing core in each group is used to execute the plurality of program segments corresponding to the group of subroutines in the execution program; wherein the data storage area is used to store the input data and output data of the plurality of program segments, and the parameter storage area is used to store the parameters of the plurality of program segments;

[0156] The synchronization signal generator 802 is used to send a synchronization signal to all processing cores when all processing cores executing the program segment have finished executing.

[0157] Furthermore, the chip 800 may also include a shared memory area 804 for storing the output data output by the plurality of processing cores executing each subroutine group.

[0158] The following is through Figure 8a The chip structure shown illustrates the compilation process of the aforementioned executable program. For example... Figure 8aAs shown, the chip 800 includes four processing cores, namely C1, C2, C3 and C4. Each processing core includes a 1MB data storage area, a parameter storage area and a program storage area (not shown). The chip also includes a 10MB shared memory area. An external memory DDR is connected to the chip to store the input data, parameters and final output data of the original program.

[0159] The original program uses a 5-layer neural network as an example, and its structure and the total amount of input and output data for each layer are as follows: Figure 8b As shown, the first layer L1 of the neural network has an input of 2200KB and an output of 1000KB; the second layer L2 has the same input size as the first layer (1000KB) and an output of 1200KB; the third layer L3 has the same input size as the second layer (1200KB) and an output of 400KB; the fourth layer L4 has the same input size as the third layer (400KB) and an output of 800KB; and the fifth layer L5 has the same input size as the fourth layer (800KB) and an output of 10KB.

[0160] The compilation method of the above-described executable program is executed by a neural network compiler. According to an embodiment of the compilation method of the above-described executable program, the neural network compiler first executes step S201 to analyze the neural network, obtain the sum of the input and output data of each layer, and generate a total data table for each layer, as shown in Table 1:

[0161] Layer InData(KB) OutData(KB) Total Data (KB) L1 2200 1000 3200 L2 1000 1200 2200 L3 1200 400 1600 L4 400 800 1200 L5 800 10 810

[0162] Table 1

[0163] Next, the steps in S202 above are executed. Based on the total data volume of each layer and the size of the data storage area of ​​the processing core, the number of processing cores required to execute the original program is calculated. If a decimal is generated during the calculation, it is rounded up to the nearest integer. The calculation results are shown in Table 2 below:

[0164] Layer Calculation of Core Number Core Number L1 3200 / 1000＝3.2 4 L2 2200 / 1000＝2.2 3 L3 1600 / 1000＝1.6 2 L4 1200 / 1000＝1.2 2 L5 810 / 1000＝0.81 1

[0165] Table 2

[0166] The calculation results indicate that executing the first-layer subnetwork program requires 4 processing cores; executing the second-layer subnetwork program requires 3 processing cores; executing the third and fourth-layer subnetwork programs requires 2 processing cores; and executing the fifth-layer subnetwork program requires 1 processing core.

[0167] The sub-network is then grouped according to the steps in step S203. The steps for grouping the sub-network using a method in one embodiment of step S203 are as follows:

[0168] First, the number of processing cores required for each sub-network is obtained sequentially. The results are shown in Table 2 above. Each layer corresponds to one number of processing cores, where N1 = 4, N2 = 3, N3 = 2, N4 = 2, and N5 = 1.

[0169] Next, a value that is divisible by the total number of processing cores and is not less than the number of processing cores required to execute the sub-network is calculated as the first value of the sub-network. The first values ​​corresponding to each layer of the sub-network are obtained through calculation, as shown in Table 3 below:

[0170] Layer Core Number1 L1 4 L2 4 L3 2 L4 2 L5 1

[0171] Table 3

[0172] Then, the sub-networks corresponding to consecutive first values ​​are determined as a subroutine group, as shown in Table 3. L1 and L2 are the first group, L3 and L4 are the second group, and L5 is the third group.

[0173] The process of determining subroutine grouping described above can also be achieved through another embodiment of step S203 above. The steps for grouping the subnetwork are as follows:

[0174] Find the maximum number of cores N required to execute each subnetwork. max1 In this example, the layer requiring the maximum number of cores is the first sub-network, which is designated as L1. And N max1 =4, meaning that when executing the first-layer subnetwork program, to ensure that the input and output data are not written outside the processing cores during the operation, at least 4 processing cores are required. At this time, Ng1=4, A1=1, and group LG1 contains the first-layer subnetwork. The allocation of processing cores is shown in the table below:

[0175] Layer Group of Cores Cores of Layer Group Layer Group L1 A1＝1 <![CDATA[Ng1=4]]> LG1 L2 L3 L4 L5

[0176] At this point, the first grouping has been preliminarily completed;

[0177] Then, in the remaining subnetworks, find the maximum number of cores N required to execute each subnetwork. max2 In this example, the subnetwork requiring the maximum number of cores is the second-layer subnetwork. We take the second layer as L2, and N... max2 =3, meaning that when executing the second-layer sub-network program, to ensure that the input and output data are not written out of the processing cores during the operation, at least 3 processing cores are required; however, since Ng1 = 4, it is not divisible by N. max2Therefore, we can only choose Ng2 = 4 and A2 = 1. Since A2 = 1 = A1, we need to merge LG2 into group LG1 for this grouping. The grouping results are shown in the table below:

[0178] Layer Group of Cores Cores of Layer Group Layer Group L1 A1＝1 Ng1 = 4 LG1 L2 A1＝1 Ng1 = 4 LG1 L3 L4 L5

[0179] During the calculation, N max2 Ng2, A2 and layer group LG2 will be reset for use in the next grouping.

[0180] At this point, the second grouping has been preliminarily completed;

[0181] Continue in the remaining layers to find the maximum number of cores N required to execute each subnetwork. max2 In this example, the layers requiring the maximum number of cores are the subroutines in layers 3 and 4. In this case, we take layer 4, which has the highest number of cores, as L2, and both are N. max2 =2, meaning that when executing the sub-network programs of the 3rd and 4th layers, to ensure that the input and output data are not written out of the processing cores during the operation, at least 2 processing cores are required; since Ng1=4, it is divisible by N. max2 Therefore, Ng2 = 2, A2 = 2, and group LG2 contains the 3rd and 4th layer subnetworks. Thus, the grouping situation is shown in the table below:

[0182] Layer Group of Cores Cores of Layer Group Layer Group L1 A1＝1 Ng1 = 4 LG1 L2 A1＝1 Ng1 = 4 LG1 L3 A2＝2 Ng2=2 LG2 L4 A2＝2 Ng2=2 LG2 L5

[0183] This marks the initial completion of the third round of nuclear allocation.

[0184] Continue in the remaining layers to find the maximum number of cores N required to execute each subnetwork. max3 In this example, the layer requiring the maximum number of cores is a 5-layer subroutine. In this case, the 5th layer with the highest number of cores is taken as L3, and N max3 =1, meaning that when executing the 5th layer sub-network program, only one core is needed to ensure that input and output data are not written out of the processing core during the operation; since Ng2=2, it is divisible by N. max3 Therefore, Ng3 = 1, A3 = 2, and group LG3 contains the 5th layer subnetwork. Thus, the grouping situation is shown in the table below:

[0185]

[0186]

[0187] At this point, the compiler has completed the process of allocating kernels to the neural network at the graph level.

[0188] All five sub-networks are divided into three groups. The subroutines in each group are executed by the same number of processing cores. Intermediate data calculated by the sub-networks in the same group do not need to be written to the external storage space of the processing cores. For example, LG1 includes a first-layer and a second-layer sub-network. The result of the calculation of the first-layer sub-network is the output data, which will be directly used as the input data of the second-layer sub-network. It does not need to use the external storage area SM or the external storage area DDR.

[0189] After determining the subnetwork groups, step S601 in step S204 can be executed to obtain the number of loop executions for each group, as shown in the above grouping, according to C. k =A (k+1) And C last =1 gives the number of loop executions for each group, as shown in Table 4:

[0190] Layer Group Group of Cores Number of Loops LG1 A1 = 1, A2 = 2 C1＝2 LG 2 A2 = 2, A3 = 2 C2＝2 LG 3 A3＝2 C3＝1

[0191] Table 4

[0192] After obtaining the sub-network grouping and grouping cycle number division scheme, the storage location of the intermediate data of the groups obtained according to steps S602 and S603 is further determined. Then, the embodiment in step S205 is continued to be executed. Based on the parameters of each layer and the size of the parameter storage area in the processing core, the location of the synchronization point is determined. This ensures that in each synchronization cycle, each processing core can read parameters from the parameter storage area inside the processing core for neural network calculation, and can read the parameters to be used in the next synchronization cycle from the external memory area, i.e., DDR, into the parameter storage area inside the processing core. According to the location of the synchronization point, a synchronization instruction is inserted at the location of the synchronization point.

[0193] The embodiment in step S206 is then executed to generate the executable program to be executed in the processing core. This process can call a traditional compiler to generate executable program segments, each program segment being generated by the program of the neural network between two synchronization points.

[0194] like Figures 9a-9c This is a schematic diagram of the process of each group being executed by the processing core.

[0195] Figure 9a This is a schematic diagram of the first loop when the first group is executed by the processing core. As shown in Table 4 above, the first group needs to be executed by the processing core twice. Figure 9aThe diagram shows the first loop calculation process of the first group. The L1 input data in the first group LG1 is divided. The total L1 input data is 2200KB, which is divided into four 550KB inputs (sometimes it is not necessarily completely equal; some data may need to be used by multiple cores. In this case, this part of the data will be sent to multiple cores simultaneously, so the input data of each core will be greater than 550KB). These data are then sent to the four processing cores in the chip, namely C1, C2, C3, and C4. When each of them completes part of the calculation of the first sub-network L1, it will produce one-quarter of the total L1 output data of 1000KB, which is 250KB. The four processing cores use their own L1 output data as their respective L2 inputs (not necessarily each L2). The output of L1 can be used as its L2 input. Part of the output data of one core may need to be sent to another core and used as its L2 input along with its L1 output data. In this way, data exchange may occur between processing cores, but this data exchange is all done within the cores on the chip (without reading or writing to the external storage space of the processing core or the external storage space of the chip). When they each complete their L2 part of the calculation, they will produce a quarter of the total L2 output data of 1200KB, that is, 300KB. The partial outputs of all processing cores that execute this group of subroutines are combined to obtain the total L2 output data of 1200KB. Since A2=2 and this calculation is the first loop, the 1200KB output data is stored in the shared storage space SM outside the processing core.

[0196] Figure 9b This diagram illustrates the second loop execution of the first group by the processing cores. The calculation process of the second loop is the same as the first loop, but the handling of the final calculation results differs. The calculation results of each processing core do not need to be written to the SM (Synchronous Data Storage). Instead, some cores directly store the output data in their own data storage area, while others send the output data to other processing cores. The processing method is determined by the processing core allocation scheme of the second group (LG2). If the processing core allocation of LG2 is C1 and C2 as one group, and C3 and C4 as another group, then the calculation results of C3 and C4 in LG1 can be sent to C1 and C2 (whether the calculation results of C3 and C4 are sent to which core of C1 and C2, or whether they are split for transmission, is determined by the data splitting scheme; in this example, the result of C3 is sent to C1, and the result of C4 is sent to C2, as shown in the diagram). Thus, during the loop calculation of the first group, only the result of the first loop calculation needs to be saved to the SM, which is 1.2MB in size.

[0197] Figure 9c This is a schematic diagram of the first loop when the second group is executed by the processing core. As shown in Table 4 above, the second group needs to be executed by the processing core twice. Figure 9cAs shown, in the first loop calculation of the second group, C1 and C2 directly use the data in the processing core data storage area as the input data for this loop calculation, that is, the result of the last loop calculation of the first group LG1; C3 and C4 will take out 1.2MB of data from the SM to retrieve the result of the loop calculation of the first group LG1 before the last loop calculation, and use it as the input data for this calculation; after the calculation is completed, the output result of 1.6MB of data will be stored in the SM.

[0198] Figure 9d This diagram illustrates the second loop execution of the second group by the processing core. The second loop calculation of the second group re-executes the loop calculation of the first group to obtain the complete input data required for the second loop calculation of the second group. Similarly, C1 and C2 directly use the data in the processing core's data storage area as the input data for this loop calculation, i.e., the result of the last loop calculation of the first group LG1; C3 and C4 retrieve 1.2MB of data from the SM (Synchronous Storage Unit) as the result of the first group LG1's loop calculation before the last loop calculation. After the second loop calculation of the second group is completed, the calculation results of each processing core do not need to be written to the SM. Instead, some processing cores directly store the output data in their own data storage area, while others send the output data to other processing cores. The processing method is determined by the processing core allocation scheme of the third group LG3. In this example, the result of C2 is sent to C1, and the result of C4 is sent to C3. Thus, the space occupied by the SM during the second group's loop calculation is: 1.6MB of the calculation result during the first loop calculation, and 1.2MB of the temporary calculation result generated by the first group's loop calculation during the second loop, totaling 2.8MB.

[0199] Figure 9e This is a schematic diagram illustrating the process when the third group is executed by the processing core. The third group loop is the last group loop, with a loop count of 1, so only the calculation of the third group LG3 needs to be completed. All its input data has been prepared; the input data for C1 and C3 are within this processing core, while the input data for C2 and C4 are obtained from SM.

[0200] In the example above, the first group first performs a loop calculation twice to obtain the input data needed for the second group's first loop calculation. The second group then performs its first loop calculation and stores the result in the SM (Solution Module). When the second group performs its second loop calculation, the first group needs to perform the same loop calculation twice more to obtain the input data needed for its second loop calculation. After obtaining the input data for its second loop calculation, the second group performs its second loop calculation, having now looped twice to obtain the input data needed for the third group. The second group directly stores the result of its second loop calculation into the processing core of the third group. The other processing cores of the third group retrieve the result of the second group's first loop calculation from the SM to obtain the complete input data for the third group. Finally, the third group performs one loop to obtain the final output data. Thus, each group immediately performs its loop calculation after obtaining the complete input data. This nested loop among multiple groups ensures that the computing power of the four processing cores is fully utilized during task execution, preventing any idle computing power.

[0201] When the chip executes the execution program, through the above... Figures 9a-9e The input data is segmented in a certain way. Then, the processing core executes the program segment in the executable program according to the input data and parameters. Each time a synchronization instruction is executed, a synchronization request is generated and sent to the synchronization signal generator. When the synchronization signal generator receives the synchronization request from each processing core in the chip, it generates a synchronization signal and sends it to each processing core, so that each processing core enters the next synchronization cycle and continues to execute the program segment of the executable program with new parameters until the executable program is completed and the output result is obtained.

[0202] As can be seen from the above examples, the original program is compiled using the executable program compilation method in this embodiment, and the executable program is executed using the chip in this embodiment. When executing the executable program, for each processing core, since it uses the same parameters, the computational load of each processing core is the same in each synchronization cycle. This ensures that the computation time of all processing cores is consistent in each synchronization cycle, avoiding the computational power loss caused by different processing cores having different computation times and the processing core that completes its computation first having to wait for the processing core that completes its computation later. This greatly improves the effective computing power of the chip. Furthermore, since all processing cores use the same parameters, the parameters only need to be read from the DDR once and can be shared by all processing cores, greatly improving the parameter reuse rate, reducing the demand for DDR bandwidth, and also reducing power consumption.

[0203] This disclosure also provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement the compilation method of any of the executable programs described in the embodiments.

[0204] This disclosure also provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the compilation method of any of the executable programs described in the foregoing embodiments.

[0205] This disclosure also provides a computer program product, characterized in that it includes computer instructions, which, when executed by a computing device, can execute any of the compilation methods of the executable program described in the foregoing embodiments.

[0206] This disclosure also provides a computing device, characterized in that it includes any of the chips described in the embodiments.

[0207] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0208] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0209] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0210] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A method for compiling an executable program, used in a system including multiple processing cores, characterized in that, include: Obtain the total data volume of each subroutine in the original program, wherein the total data volume of the subroutine is the sum of the size of the input data and the size of the output data of the subroutine; The number of processing cores required to execute each subroutine is determined based on the size of the data storage area of ​​the multiple processing cores and the total amount of data of each subroutine; The subroutines are grouped according to the number of processing cores required to execute each subroutine, and a corresponding number of processing cores are allocated to each group; Determine the storage location of the intermediate data in the group; The location of the synchronization point is determined based on the size of the parameters of each subroutine and the size of the parameter storage area of ​​the processing core; The original program is compiled into an executable program based on the group, the storage location of the intermediate data of the group, and the location of the synchronization point.

2. The compilation method for the executable program as described in claim 1, characterized in that, Determining the storage location of the intermediate data of the group includes: Determine the number of times the group will be executed in a loop; If the current loop execution count is not the last one, then the intermediate data of the group is stored in the external storage area; If the current loop execution count is the last one, then the intermediate data of the group is stored in the data storage area of ​​the processing core belonging to the next group.

3. The compilation method of the executable program as described in any one of claims 1 or 2, characterized in that, The step of grouping the subroutines according to the number of processing cores required to execute each subroutine, and allocating a corresponding number of processing cores to each group, includes: The subroutines are grouped according to the number of processing cores required to execute each subroutine and the total number of processing cores; The number of processing cores allocated to each group is determined by the number of processing cores required to execute the subroutines in each group and the total number of processing cores; wherein the same number of processing cores are allocated to the same group.

4. The compilation method for the executable program as described in claim 3, characterized in that, The original program includes multiple subroutines, which are executed sequentially. Determining the grouping of the subroutines based on the number of processing cores required to execute each subroutine and the total number of processing cores includes: Obtain the number of processing cores required to execute each subroutine in sequence; The first value of the subroutine is calculated as a value that is divisible by the total number of processing cores and is not less than the number of processing cores required to execute the subroutine; wherein, each subroutine corresponds to one first value; Subroutines corresponding to consecutive identical first values ​​are grouped together as a single subroutine.

5. The compilation method for the executable program as described in claim 3, characterized in that, The original program includes multiple subroutines, which are executed sequentially. Determining the grouping of the subroutines based on the number of processing cores required to execute each subroutine and the total number of processing cores includes: Obtain the number N of processing cores required to execute each subroutine sequentially. i Where i represents the subroutine number; Get the current N i The maximum value Nmax1 in the range; Get the subroutine number j1 with the largest number among all subroutines corresponding to Nmax1; The subroutines preceding j1 are identified as the group corresponding to j1.

6. The compilation method for the executable program as described in claim 5, characterized in that, The step of allocating a corresponding number of processing cores to the group based on the number of processing cores required to execute the subroutines in each group and the total number of processing cores includes: The number of processing cores Ng1 corresponding to the group j1 is calculated as the value that is divisible by the total number of processing cores M0 and is not less than Nmax1.

7. The compilation method for the executable program as described in claim 6, characterized in that, The method further includes: Treat the subroutines after j1 as all subroutines, and Ng1 as the total number of processing cores. Continue to execute the steps of determining the group and the number of processing cores corresponding to the group to obtain the group corresponding to j2 and the number of processing cores Ng2 of the group corresponding to j2. If Ng2 equals Ng1, then merge the group corresponding to j1 and the group corresponding to j2 into one group; If Ng2 is not equal to Ng1, then the group corresponding to j2 is treated as a new group.

8. The compilation method for the executable program as described in claim 7, characterized in that, The method further includes: Continue executing the steps above to determine the number of groups and their corresponding number of processing cores, treating the subroutines after j2 as all subroutines and Ng2 as the total number of processing cores, until all subroutines have corresponding groups.

9. The compilation method for the executable program as described in claim 2, characterized in that, The step of compiling the original program into an executable program based on the group, the storage location of the intermediate data of the group, and the location of the synchronization point includes: compiling the original program into an executable program based on the group, the number of times the group is executed in a loop, the storage location of the intermediate data corresponding to the current execution number, and the location of the synchronization point.

10. A chip, characterized in that, include: Multiple processing cores and synchronization signal generators; Each processing core includes a data storage area and a parameter storage area; wherein the plurality of processing cores are grouped according to the execution program, and the processing cores in each group are used to execute multiple program segments corresponding to the group of subroutines in the execution program; The data storage area is used to store the input and output data of the multiple program segments, the parameter storage area is used to store the parameters of the multiple program segments, and the total data of the subroutine is the sum of the size of the input data and the size of the output data of the subroutine. The synchronization signal generator is used to send a synchronization signal to all processing cores when all processing cores executing the program segment have finished executing.

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