System and method for addressing caches with split indexes

Abstract

Cache memory mapping techniques are presented. A cache can include an index configuration register. The register can configure the location of an upper index portion and a lower index portion of a memory address. The portions can be combined to create a combined index. The configurable split index addressing structure can be used to reduce the rate of cache conflicts that occur between multiple processors decoding video frames in parallel, among other applications.

Description

[0001] This application is a divisional application of application number 201680028652.3, entitled "System and method for addressing cache using partitioned indexes".

[0002] Cross-referencing of related patent applications

[0003] This application claims priority to U.S. Patent Application No. 14 / 716,588, filed May 19, 2015, entitled “SYSTEMS AND METHODS FORADDRESSING A CACHE WITH SPLIT-INDEXES”, the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0004] This application generally relates to addressing configurable central processing unit (CPU) caches using a segmented indexed address structure. Background Technology

[0005] Computer processor performance has increased exponentially over the past half-century. Continuous improvements in processing performance require the ongoing development of new technologies and methods. One known performance improvement technique involves the use of processor caches. Caches offer significantly improved data access times to main memory, but their storage capacity is limited. Due to the performance enhancements they provide, caches have seen almost universal adoption in the field.

[0006] Another technique for improving processor performance is the parallel use of multiple processors. In these scenarios, when a system uses multiple processors, the individual processing cores can share access to a single cache. This advantageously allows each processor to read data cached by another processor. However, if each of the multiple processors accesses different portions of a file in parallel, the memory accessed by each processor is likely to be spatially distant (i.e., likely located at distant rows and columns in memory). For this reason, in such scenarios, the likelihood of processors requesting data mapped to the same cache line, resulting in a significant conflict, is quite high. Cache conflicts are costly, forcing processors to alternatively read from main memory, leading to considerable performance degradation. Therefore, there is a need to improve cache performance when parallel processors are likely to access spatially distant portions of a file in memory. Summary of the Invention

[0007] In accordance with the disclosed subject matter, systems and methods for addressing configurable caches using segmented indexes are provided. In some embodiments, a method for storing elements of future autonomous memory into a cache includes: associating each of a plurality of cache lines from a cache memory with a different index of a plurality of indexes, wherein one of the plurality of indexes includes a first composite index; defining a first set of bits from a first address associated with a first memory location from said main memory as a first index portion and defining a second set of bits from the first address as a second index portion; generating the first composite index by concatenating the first index portion and the second index portion; and mapping at least the first memory location to a first cache line from the plurality of cache lines based on the first composite index.

[0008] The method may further include defining a third set of bits from the first address as an offset, wherein the offset determines a position within the first cache line of the first memory location. The method may further include storing multiple data blocks from frames of high-definition video stored in the main memory within the plurality of cache lines. The method may further include scheduling read and write requests from a first processor and a second processor to the cache memory. The method may further include: reading a first data block located in a first column of the main memory via the first processor; simultaneously reading a second data block located in the first column of the main memory via the second processor; and storing the first data block and the second data block into the cache memory.

[0009] In some embodiments, a cache for storing data elements from main memory includes: a cache memory including a plurality of cache lines each referenced by a different index among a plurality of indexes, wherein one of the plurality of indexes includes a first composite index; an index configuration register configured to define a first set of bits from a first address associated with a first memory location from the main memory as a first index portion and to define a second set of bits from the first address as a second index portion; an index generation module configured to receive the first index portion and the second index portion as defined by the index configuration register, and to generate the first composite index by concatenating the first index portion and the second index portion; and a memory address mapping module for mapping at least the first memory location to a first cache line from the plurality of cache lines based on the first composite index.

[0010] The index configuration register can also be configured to define a third set of bits from the first address as an offset, wherein the offset determines a position within the first cache line of the first memory location. The plurality of cache lines can be configured to store a plurality of data blocks from frames of high-definition video stored in the main memory. The memory address mapping module can also be configured to map at least two of the plurality of data blocks from a row of the frames of the high-definition video to a cache line from the plurality of cache lines. The cache can also include an access arbitration module configured to schedule read and write requests from the first processor and the second processor to the cache memory. The access arbitration module can also be configured to allow simultaneous read and write requests from the first processor and the second processor to different cache lines from the plurality of cache lines.

[0011] In some embodiments, a non-transitory computer-readable storage medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed by a computer system, causing the computer system to perform a method for storing elements of future autonomous memory into a cache, the method comprising: associating each of a plurality of cache lines from a cache memory with different indices of a plurality of indices, wherein one of the plurality of indices includes a first composite index; defining a first set of bits from a first address associated with a first memory location from the main memory as a first index portion and defining a second set of bits from the first address as a second index portion; generating the first composite index by concatenating the first index portion and the second index portion; and mapping at least the first memory location to a first cache line from the plurality of cache lines based on the first composite index. Attached Figure Description

[0012] The various purposes, features, and advantages of the disclosed subject matter can be found in the following detailed description of the disclosed subject matter, together with the following appendix. Figure 1 As will be more fully understood upon consideration, the same reference numerals identify the same elements in the accompanying drawings. The drawings are schematic and not intended to be drawn to scale. For clarity, not every component is labeled in every drawing. Not every component of every embodiment of the disclosed subject matter is shown unless illustrated as necessary to allow those skilled in the art to understand the disclosed subject matter.

[0013] Figure 1 An exemplary computer memory and an associated addressing scheme are illustrated.

[0014] Figure 2 The diagram illustrates the relationship with Figure 1An associated exemplary cache entry address structure.

[0015] Figure 3 The diagram illustrates the address structure of the additional cache entries.

[0016] Figure 4 The illustration shows an exemplary mapping of cache to memory.

[0017] Figure 5 The illustration shows an exemplary processing system that can be used in conjunction with a cache having a segmented index address structure, according to some embodiments.

[0018] Figure 6 An exemplary computing and storage system according to some embodiments is illustrated.

[0019] Figures 7A-7C The illustration shows an exemplary segmented index cache entry address structure according to some embodiments.

[0020] Figures 8A-8C The illustration shows the processing of blocks in an image frame according to some embodiments.

[0021] Figures 9A-9B The illustration shows a cache mapping onto an image patch according to some embodiments.

[0022] Figure 10 An exemplary cache mapping scheme to an image frame is illustrated according to some embodiments. Detailed Implementation

[0023] In the following description, numerous specific details are set forth regarding the systems and methods with respect to the disclosed subject matter, as well as the environments in which such systems and methods may operate, in order to provide a thorough understanding of the disclosed subject matter. However, it will be apparent to those skilled in the art that the disclosed subject matter can be practiced without such specific details, and that certain features well-known in the art are not described in detail to avoid complicating the disclosed subject matter. Furthermore, it should be understood that the examples provided below are exemplary, and other systems and methods within the scope of the disclosed subject matter are contemplated.

[0024] The embodiments of this disclosure aim to improve cache performance in parallel processing systems. Cache memory has been used by processors to improve performance for decades. Generally, cache memory is a small memory capable of fast read times at least an order of magnitude shorter than those from main memory. As a trade-off, this fast-execution cache memory must be small to allow for performance improvements. For this reason, it is important to use efficient methods to select the location where data should be stored in the cache memory.

[0025] When parallel processors share a cache, they can each read and write to lines in the cache in parallel. Typically, queuing systems arbitrate concurrent requests to prevent conflicts. This scheme is advantageous as long as it's impossible for a processor to read data mapped to overlapping areas of the cache. However, utilizing a shared cache will result in performance degradation whenever two processors attempt to read from different lines in memory that happen to map to the same line in the cache (in other words, when a conflict exists). If it is known that each of the parallel processors accesses different lines in memory, certain cache addressing schemes can be employed to eliminate the possibility of cache conflicts due to accesses from multiple processors. One such technique (called a split-index address structure) is particularly well-suited to mitigating conflicts arising from certain cache access patterns and is described below.

[0026] One form of processing that can leverage cache memory improvements through such a scheme is high-definition video decoding. While many formats are still in use today, one format widely adopted in the field is H.264 / MPEG-4 Part 10 Advanced Video Coding (H.264 or MPEG-4 AVC). To improve decoding time for high-definition video playback, multiple processing cores can each write to a single cache shared among the cores. Although the remaining discussion generally pertains to H.264 video, other forms of video compression or other forms of processing unrelated to video compression can benefit from the storage methods disclosed herein.

[0027] A characteristic of high-definition video, and especially H.264 video, is that when a video frame is buffered into memory, the entire frame is stored in memory as a contiguous block of addresses, such that the address of the first byte on a line in the buffer is also the address of the first byte on a line in the video frame. In other words, even if the memory buffer is wider than the width of the video frame, a line of the video frame is stored on a line in the memory buffer. This buffer filling scheme is called "tiling" into memory and can be utilized when the horizontal "step" of the memory (the width of a line in memory) is greater than the horizontal resolution of the video frame. This allows some space beyond the end of each line to remain unused, thus filling the line to a certain physical boundary.

[0028] When decoding video frames that have been tiled into memory, different processors can decode different lines of the video frame in parallel. For example, a first processor can decode the first line, while a second processor decodes the second line. Because cache lines are typically mapped such that consecutive lines in the cache map to consecutive columns within a single line of memory, each of the multiple processors may use a block of data that happens to map to the same cache line as another processor at a given time. In this situation, a conflict arises because a single line of the cache cannot store two different blocks. Therefore, at least one of the blocks being accessed by the multiple processors must be retrieved from main memory. To reduce the cache miss rate shared among multiple processors, embodiments of this disclosure propose techniques specific to storage methods associated with H.264 high-definition video, or other block-based video algorithms such as MPEG or MPEG2. However, it should be understood that these techniques can be extended to improve cache performance in other parallelized high-definition video processing or other suitable data processing aspects.

[0029] The H.264 video format contains many unique features that can be used in conjunction with the segmented index cache entry address structure described below. In H.264, video data is stored as a series of individual frames. These stored frames are further subdivided into large, discrete blocks of information called “macroblocks,” which will be discussed in more detail below. When reconstructing the compressed video stream, certain frames called “reference frames” are saved and used to reconstruct intermediate frames that lie between the reference frames in time. Intermediate frames are reconstructed as the difference between the frame to be rendered and the nearest reference frame in memory. This method of generating video frames based on the difference between the current frame and the reference frame is called “motion compensation” and provides significant compression, but also requires additional processing power.

[0030] The following example provides background technology on the mapping of main memory to cache lines. Figure 1 An exemplary main memory 100 is provided for illustrating certain elements of a typical cache. Figure 1 This represents a simple main memory with a total capacity of 32 bytes. Main memory 100 is organized into four rows and four columns, totaling 16 units. Figure 1 Exemplary column 102, exemplary row 104, and exemplary cell 106 are also shown.

[0031] Figure 1In the main memory 100, each row (e.g., row 104) contains 8 bytes, and each column (e.g., column 102) contains 4 bytes. The intersections between rows and columns define a total of 16 cells, each containing 2 bytes. For example, cell 106 contains 2 bytes of data, and this cell represents the intersection between column 102 and row 104. Figure 1 As can be seen, each byte in main memory is assigned a unique binary address. This address is simply a binary number representing the location of a specific byte of data in main memory. Figure 1 The 32-byte main memory requires a total of 5 bits to uniquely represent each available memory location.

[0032] In main memory 100, addresses are assigned using a left-to-right, top-to-bottom method. For example... Figure 1 This indicates that each address shifted from left to right in line 104 is one greater than the previous address. Using this organization, it's noticeable that in the 5-bit memory address representing a byte in main memory 100, the two most significant bits (bits 3 and 4) indicate the line number in main memory. For example, in... Figure 1 In the first row of 104, the two most significant bits represent "00" for the first row of main memory. Similarly, the two most significant bits of the following rows represent "01", "10", and "11" for the second, third, and fourth rows of main memory, respectively.

[0033] The next two most significant bits (bits 1 and 2) indicate the column number in main memory. For example, in Figure 1 In the first column (102), bits 1 and 2 represent "00" for the first column in memory. Similarly, bits 1 and 2 of the following columns represent "01", "10", and "11" for the second, third, and fourth columns in main memory, respectively. Finally, the least significant bit (bit 0) represents a specific byte within the main memory cell. Referring to this memory organization, a simple cache memory that can be used in conjunction with this memory will be described.

[0034] The reference diagram illustrates a 32-byte main memory. Figure 1 We will consider an 8-byte cache that can be associated with main memory. For an 8-byte cache storing entries associated with 32 bytes of main memory, the cache is able to maintain 1 / 4 of the entries in main memory at a given point in time. The methods used to select entries to be stored in and removed from the cache will be described in more detail below. Unlike main memory 100, the cache is not organized into rows and columns; instead, each word of main memory it can store will typically have one entry. (See reference...) Figure 1Considering the case of an 8-byte cache, each word is 2 bytes (because each unit at the intersection of rows and columns contains 2 bytes), and therefore the cache will have 4 rows.

[0035] Figure 2 An example cache entry address structure 200 is provided for storing entries in an 8-byte cache in main memory 100. The cache entry address structure 200 contains a tag 202, an index 204, and an offset 206. In this example, the cache entry address structure 200 is 5 bits long, which is the same length as the unique address of each byte in memory 100. It should be understood that the cache entry address structure can be of any length depending on the size of the main memory it addresses, but it should generally be the same length as the address in main memory. In this example, tag 202 is 2 bits, index 204 is 2 bits, and offset 206 is 1 bit. Each possible value of the cache entry address structure 200 uses tag 202, index 204, and offset 206 to provide a unique mapping to a single byte in the cache.

[0036] Index 204 of cache entry 200 indicates the cache line to which cache entry address structure 200 is mapped. Because index 204 comprises 2 bits, a maximum of 2^32 bits can be used in the cache. 2 = 4 lines. Offset 206 of cache entry address structure 200 represents a specific byte within the cache line referenced by cache entry address structure 200. Because offset 206 includes 1 bit, each cache line contains exactly 2 1 = 2 bytes of data. Therefore, this cache can store 4 bytes of data at any given time. * 2 = 8 bytes of data. Further, in this example, every 8 bytes of main memory (e.g., main memory locations 00000 to 00111, 01000 to 01111, 10000 to 10111, etc.) is mapped to a unique location in the cache. Finally, tag 202 is a unique identifier including the uppermost bits of the main memory location mapped to the cache. In this example, tag 202 includes 2 bits (continuing the earlier example, the uppermost bits are the first two digits of address 00000). As a result of this structure, all main memory locations sharing the same 3 least significant bits (e.g., main memory locations 00011, 01011, 10011, and 11011) will be mapped to the same location in the cache. Tag 202 stores the additional information necessary to determine which of these four possible entries is currently stored in the cache. This simplified cache and main memory is provided for illustrative purposes, and much larger caches and main memories are used for processing high-definition video. Additionally, see references... Figure 1 and Figure 2 The simple cache described is unsuitable for processing video using multiple processors for the reasons that will be described below.

[0037] A large cache entry address structure will now be presented according to some embodiments of this disclosure. Figure 3 A sample cache entry address structure for a typical cache is provided. Cache entry address structure 300 contains a tag 302, an index 304, and an offset 306. In this example, cache entry address structure 300 is 18 bits long. However, it should be understood that the cache entry address structure can be of any length depending on the size of the cache. In this example, tag 302 is 10 bits, index 304 is 5 bits, and offset 306 is 3 bits. Each possible value of cache entry address structure 300 uses tag 302, index 304, and offset 306 to provide a unique mapping to a single byte in the cache.

[0038] Index 304 of cache entry 300 indicates the cache line to which cache entry address structure 300 is mapped. Because index 304 comprises 5 bits, it can have a maximum of 2^35 bits in the cache. 5 = 32 lines. Offset 306 of cache entry address structure 300 represents a specific byte within the cache line referenced by cache entry address structure 300. Because offset 306 includes 3 bits, each cache line contains exactly 2 3 = 8 bytes of data. Therefore, this cache can store 32 bytes of data at any given time. * 8 = 256 bytes of data. Further, in this example, each 256 bytes of main memory (main memory locations 0x00000 to 0x000FF, 0x00000 to 0x001FF, 0x00000 to 0x002FF, etc.) is mapped to a unique location in the cache. Finally, tag 302 is a unique identifier that includes the top bits of the main memory location mapped to the cache. In this example, tag 302 includes 10 bits (continuing the earlier example, the top bits are the first three digits of address 0x00000).

[0039] The total number of bytes that can be uniquely mapped in a cache entry is related to the number of bits in the entry—for example, cache entry 300 can uniquely map 2 bytes. 18 = 256 kilobytes (kB) of data. This cache entry address structure is typically used to address cache entries according to the various cache types in the industry.

[0040] To further illustrate mapping memory entries to having Figure 3Consider the following example of a cache entry address structure concept. Figure 4 Provides the ability to be copied to have, for example, in Figure 3 The cache entries are organized in a simple main memory structure 400 within the cache. Main memory 400 may include a horizontal width 402 and a vertical height 404. Additionally, the width of a single cell in the memory may be represented by 406.

[0041] In one example Figure 4 The main memory 400 in the example has a horizontal width of 402, which is 512 bytes. Continuing this example, a 256-byte cache is mapped onto this memory. In utilizing... Figure 3 In the typical cache of the cache entry address structure disclosed herein, the cache is organized into 32 lines of 8 bytes each. Figure 4 In the example, the cache is mapped sequentially such that each consecutive index maps to a memory entry in an adjacent column. Therefore, each row of the cache is directly mapped to a consecutive column within a specific row of main memory 400. When the cache is mapped in this way, the offset bits (bits 3 to 7) are used. Figure 3 The least significant bit of the cache entry address structure represents a consecutive column within a row of main memory 400. This organization of consecutive entries within a row to consecutive lines in the cache is a result of the structure of the cache entry address structure 300. Specifically, the index bits of the cache entry address structure 300 are located in the least significant portion of the entry. The corresponding portion of the main memory address references the row in main memory. Using this structure, the cache must be mapped to main memory as described above.

[0042] Embodiments of this disclosure provide that cache entry addresses are associated with the above Figure 3 The cache uses 300 different formats to store cache entries in their address structures. These caches utilize an address structure where cache entries are divided into upper and lower parts by an index. This structure will be called a "segment index" and will be described in more detail below. Segmenting cache entries significantly reduces the likelihood of cache conflicts when using parallel processors to decode high-definition video or other data. For example, in these and other contexts, the segment index can increase the locality of parallel access to video frames.

[0043] Figure 5 An exemplary processing system 500 that can be utilized according to some embodiments of the present disclosure is illustrated. Figure 5 In this, the processing subsystem 500 includes processors 502A, 502B, 502C and 502D and a Level 2 (L2) cache 504.

[0044] Processors 502A, 502B, 502C, and 502D can be any hardware having a central processing unit (CPU) core capable of processing computer instructions. Processors 502A, 502B, 502C, and 502D may also be implemented using hardware employing application-specific integrated circuits (ASICs), programmable logic arrays (PLAs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or any other integrated circuits. As an example, processors 502A, 502B, 502C, and 502D suitable for executing computer programs include any one or more processors such as dedicated microprocessors, digital signal processors, and dedicated digital computers. Generally, processors 502A, 502B, 502C, and 502D receive instructions and data from read-only memory or random access memory, or both.

[0045] L2 cache 504 includes a fast execution memory capable of caching entries from any of processors 502A, 502B, 502C, and 502D. In one embodiment, L2 cache 504 is a shared cache that allows simultaneous access by processors 502A, 502B, 502C, and 502D. In one embodiment, L2 cache 504 can be addressed using a segmented index address structure as described in more detail below.

[0046] Figure 6 An exemplary computing and storage system 600 is provided that can be utilized according to some embodiments of this disclosure. Figure 6 In this system, computing and storage system 600 includes storage module 602 and computing system 604. Storage module 602 includes high-capacity memory 606. Computing system 604 includes main memory 608 and processing subsystem 500.

[0047] The high-capacity memory 606 within storage module 602 can be directly connected to the main memory 608 within computing system 604. In one embodiment, the high-capacity memory 606 can be a non-volatile physical storage medium capable of storing large amounts of data. In one embodiment, the main memory 608 can be any memory capable of dynamically storing and accessing data entries. In an exemplary embodiment, the main memory 608 can be a random access memory (RAM) capable of storing entries from the high-capacity memory 606. Processing subsystem 500 can communicate directly with main memory 608. L2 cache 504 can also cache entries stored in main memory 608. In one embodiment, L2 cache 504 can utilize a segmented index address structure as described below to store entries.

[0048] Figures 7A-7C Examples of segmented index cache entries according to some embodiments of this disclosure are provided. Figures 7A-7C In the cache, the address structure of a cache entry includes an offset, a top label and a bottom label, as well as a top index and a bottom index.

[0049] Figure 7A Examples of cache entry address structures for small caches according to certain embodiments of this disclosure are provided. The cache entry address structure 700A includes an upper tag 702A, an upper index 704A, a lower tag 706A, a lower index 708A, and an offset 710A. In this example, the cache entry address structure 700A is 18 bits long. However, it should be understood that the cache entry address structure can be of any length depending on the size of the cache. In this example, the upper tag 702A is 5 bits, the upper index 704A is 4 bits, the lower tag 706A is 5 bits, the lower index 708A is 1 bit, and the offset 710A is 3 bits. It should be noted that although the index and tag are divided into upper and lower parts, they maintain the same length as the corresponding tag and index in a conventional cache entry address.

[0050] The combination of the upper index 704A and the lower index 708A of the cache entry address structure 700A still represents the cache line to which the cache entry address structure 700A is mapped. Because the upper index 704A and the lower index 708A together contain 5 bits, a maximum of 2^35 bits can be used in the cache. 5 = 32 lines. Offset 710A of cache entry address structure 700A still represents a specific byte within the cache line referenced by cache entry address structure 700A. Because offset 710A includes 3 bits, each cache line contains exactly 2 3 = 8 bytes of data. Therefore, this cache can store 32 bytes of data at any given time. * 8 = 256 bytes of data. Similar to the previous example, this 256-byte block of memory maps to a unique location in the cache. Finally, the cascading of the upper tag 702A and the lower tag 706A includes a unique identifier for the memory location mapped to the cache. In this example, the cascading tag consists of 10 bits.

[0051] The specific bits selected for the upper portion 704A and lower portion 708A of the index have special significance for the mapping of cache entries. The lower portion 708A is selected to represent the column of memory it maps to (e.g., the column of memory 500). The lower portion of index 708A is only 1 bit long, and therefore it can represent only one of two columns. The remaining portion of the index (the upper portion 704A) is selected to represent the row of memory it maps to. In this example, the upper portion 704A of the index is 4 bits long, and therefore it can represent one of 16 columns. The organization of cache entries thus significantly changes the location of memory elements within the cache.

[0052] It should be noted that, in Figure 2 and Figure 3 In the example, the index bits represent only different columns of a particular row due to their position in the cache entry address structure (in Figure 2 In the diagram, bits 1 and 2 represent columns, while bits 3 and 4 represent rows. If in... Figure 2 By swapping the bits representing the tag and index, cache entries will represent different rows within the same column. (See reference) Figure 7A The positions of the split indices are carefully chosen because they represent the least significant bits of the row and column addresses in memory.

[0053] Figure 7B and Figure 7C The illustration shows a cache entry address structure corresponding to a larger memory according to some embodiments of the present disclosure. Figure 7B In this example, the cache entry address structure 700B includes an upper tag 702B, an upper index 704B, a lower tag 706B, a lower index 708B, and an offset 710B. In this example, the cache entry address structure 700B is 32 bits long. However, it should be understood that the cache entry address structure can be of any length depending on the size of the cache. In this example, the upper tag 702B is 12 bits, the upper index 704B is 9 bits, the lower tag 706B is 4 bits, the lower index 708B is 1 bit, and the offset 710B is 6 bits.

[0054] Assuming a bidirectional set-associative cache, the cache represented by this entry address structure is determined as follows. Since the offset is 6 bits, each line of this cache contains 2... 6 = 64 bytes. Furthermore, since the lower 708B portion of the split index is 1 bit and the upper portion is 9 bits, we know that each "block" of memory mapped into the cache is 2 bytes wide. 1 = 2 columns and height 2 9= 512 lines, and the size is 64 kB. Because this cache is bidirectional set-associative, the total size of the cache is 2. 6 * 2 1 * 2 9 * 2 1 = 2 17 = 128 kB.

[0055] exist Figure 7C In this example, the cache entry address structure 700C includes an upper tag 702C, an upper index 704C, a lower tag 706C, a lower index 708C, and an offset 710C. The cache entry address structure 700C is 32 bits long. Specifically, the upper tag 702C is 13 bits, the upper index 704C is 8 bits, the lower tag 706C is 3 bits, the lower index 708C is 2 bits, and the offset 710C is 6 bits.

[0056] Assuming a bidirectional set-associative cache, the cache represented by this entry address structure is determined as follows. Since the offset is 6 bits, each line of this cache contains 2... 6 = 64 bytes. Furthermore, since the lower part of the segmented index, 708B, is 2 bits and the upper part is 8 bits, we know that each "block" of memory mapped into the cache is 2 bytes wide. 2 = 4 columns and height 2 8 = 256 lines, and the size is 64 kB. Because this cache is bidirectional set-associative, the total size of the cache is 2. 6 * 2 1 * 2 9 * 2 1 = 2 17 = 128 kB. Use Figure 7A , Figure 7B and Figure 7C In the format described herein, caches can be organized into arbitrary block arrangements mapped onto memory.

[0057] Figures 8A-8C and Figures 9A-9B The illustration shows the application of a segmented index address structure to a video decoding system that utilizes multiple processors in parallel. Specifically, Figures 8A-8C Provide an example image decoded in H.264 video format or other data format. Figure 8A The illustration is broken down into frames of an image (e.g., a wrench) that comprise macroblocks, and Figure 8Band Figure 8C The same image is shown during different stages of the decoding process.

[0058] Figure 8A A grid, according to some embodiments, is provided that is overlaid on a sample image frame. Figure 8A In this example, the grid consists of 8 rows and 16 columns, resulting in a total of 128 blocks. It should be understood that this example illustrates the 128 blocks that make up the image for illustrative purposes only, and in practice, high-definition video frames will consist of many more macroblocks. Processors 502A (P1), 502B (P2), 502C (P3), and 502D (P4) each decode different rows of the image frame. For example, in... Figure 8A In this process, processor 502A decodes the first line (line 0), processor 502B decodes the second line (line 1), processor 502C decodes the third line (line 3), and processor 502D decodes the fourth line (line 3). Upon completing processing one line, each processor advances four lines to continue processing. Therefore, processor 502A decodes the fifth line (line 4), processor 502B decodes the sixth line (line 5), processor 502C decodes the seventh line (line 6), and processor 502D decodes the eighth line (line 7).

[0059] Figure 8B The illustration shows the decoding of image frames at a stage after processing has begun. Figure 8B In the image frame, the currently processed block is indicated by a gray highlighted box. At this stage, processor 502A processes blocks in columns 5-8 of row 0, processor 502B processes blocks in columns 4-7 of row 1, processor 502C processes blocks in columns 3-6 of row 2, and processor 502D processes blocks in columns 2-5 of row 3. It should be understood that a typical processor will decode four blocks simultaneously when decoding high-definition video. However, processors may decode more or fewer blocks and rows simultaneously depending on speed and memory limitations. Additionally, typically, processors will decode blocks in different columns of the image frame simultaneously, such as... Figure 8B As shown in the diagram, but this is not necessary.

[0060] Figure 8CThe diagram illustrates the decoding of an image frame at a later stage of processing. At this stage, processor 502A processes blocks in column 16 of row 0 of the image frame and blocks in columns 0-2 of row 4 of the image frame; processor 502B processes blocks in columns 14-15 of row 1 of the image frame and blocks in columns 0-1 of row 5 of the image frame; processor 502C processes blocks in columns 13-15 of row 2 of the image frame and blocks in column 0 of row 6 of the image frame; and processor 502D processes blocks in columns 12-15 of row 3 of the image frame. As described above, like... Figures 8A-8C As shown, the simultaneous processing of rows of image frames by different processors can be made possible by tiling the image frames into memory.

[0061] Figure 9A and Figure 9B The diagram illustrates cache lines according to some embodiments. Figures 8A-8C The mapping on blocks of image frames. Figure 9A The diagram illustrates the cache line mapping based on a typical cache, while Figure 9B The diagram illustrates the cache line mapping using the segmented index cache address structure described above.

[0062] exist Figure 9A The image illustrates the mapping of cache lines for a typical 16-byte cache. For illustrative purposes, each block in an image frame is assumed to consist of one byte. Figure 9A This illustrates how, for a typical cache, each block within each line of an image frame is mapped to a different line in the cache. (Example from...) Figure 9A As can be seen, when four blocks are processed simultaneously by each of different processors, this can lead to conflicts where more than one processor uses blocks mapped to the same location in the cache. For example, in Figure 9A In this scenario, processors 502A, 502B, and 502C each simultaneously read the block mapped to line 5 of the cache. Therefore, at least two of these access requests will result in cache misses, leading to performance degradation. Such conflicts occur when a previously decoded image is accessed concurrently as a reference image by multiple parallel processors. Because the parallel processors are each working on spatially closed blocks of the image, there is a high probability that the portions of the reference image they require will overlap. Due to... Figure 9A In the cache layout, different parts of the reference image needed by each processor will be mapped to the same location in the cache.

[0063] exist Figure 9B In accordance with some embodiments of this disclosure, a mapping of cache lines of a cache that has been mapped using a segmented index structure is provided. Figure 9BThis illustrates how blocks within each row of an image frame can be mapped to cache lines in a repetitive manner. For example, the first four blocks of row 1 of the image frame are mapped to cache lines 0-3, as shown below. Figure 9A As shown. However, compared with in Figure 9A Unlike in the previous example, the next four blocks in line 1 also map to cache lines 0-3. Every four blocks in this image frame within line 1 map to the same set of cache lines, such as... Figure 9B As shown in the image, each block of each row decoded by processor 502A can only be mapped to cache lines 0-3. Similarly, each block of each row decoded by processor 502B can only be mapped to cache lines 4-7. When the cache is mapped to the image frame in this way, it is clear that processors 502A-502D cannot access blocks mapped to the same cache lines as another processor. Therefore, this arrangement eliminates cache conflicts caused by simultaneous access from different processors.

[0064] The specific mapping of cache lines to image frames to avoid conflicts depends on the number of processors and the number of blocks processed in parallel by a single processor. The cache should uniquely map the lines of an image frame to as many blocks as a given processor can process simultaneously. Figure 9B In this context, four blocks can be processed simultaneously, and therefore each line of an image frame requires at least four lines of cache. Furthermore, because four processors are used, at least four unique sets of blocks should be available, one set for each processor. These constraints lead to... Figure 9B The arrangement of the cache lines selected for the 16-byte cache in the memory. It should be noted that if the cache is larger than necessary, any mapping scheme that meets the above requirements is suitable for avoiding conflicts arising from multiprocessor systems. Therefore, this scheme allows data to be laid flat in main memory and mapped to cache lines according to the specific needs of the application software.

[0065] Figure 10 The illustration shows a specific arrangement of an H.264 image frame 1000 being decoded by a parallel processor according to some embodiments. Figure 10 It contains lines 1002 and 1004. Each line stores any number of macroblocks associated with an image frame of the H.264 video, while noting that each line of memory stores only a macroblock associated with a single line of data in the image frame.

[0066] Based on this arrangement, cache entry addresses are organized such that every fifth macroblock maps to the same cache entry (e.g., in...). Figures 7A-7CIn the earlier discussion, the lower part of the index was 2 bits, allowing it to map to 4 columns. Therefore, every fifth macroblock in row 1002 will map to the same row in the cache, and every fifth macroblock in row 1004 will map to the same row in the cache. However, no macroblock in row 1002 will map to any of the same cache lines as the macroblocks in row 1004, and no macroblock in row 1004 will map to any of the same cache lines as the macroblocks in row 1002. Importantly, in one embodiment, different rows of image frames are decoded in parallel by different processors. By organizing the cache in this way, various processors using a shared cache will never attempt to overwrite portions of the cache used by other processors. This has the effect of significantly reducing cache misses by preventing processors from fighting for cache space, thereby effectively improving the overall cache hit rate.

[0067] It should be understood that although several different arrangements have been described in this paper, the features of each can be advantageously combined in various forms to achieve advantages.

[0068] In the foregoing specification, applications have been described with reference to specific examples. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the connection can be any type of connection suitable for transmitting signals from or to a corresponding node, unit, or device, such as via an intermediate device. Thus, unless otherwise implied or stated, the connection can be, for example, a direct connection or an indirect connection.

[0069] It should be understood that the architectures described herein are merely exemplary, and many other architectures can in fact achieve the same functionality. In an abstract but still precise sense, any arrangement of components used to achieve the same functionality is effectively “associated” so that the desired functionality is accomplished. Therefore, any two components combined in this paper to accomplish a particular functionality can be considered “associated” with each other so that the desired functionality is accomplished, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” with each other to accomplish the desired functionality.

[0070] Furthermore, those skilled in the art will recognize that the boundaries between the functionalities of the operations described above are merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed across additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments.

[0071] However, other modifications, changes, and alternatives are possible. Therefore, the specification and drawings should be considered in an illustrative rather than a limiting sense.

[0072] In the claims, any reference numerals placed between parentheses should not be construed as limiting the claims. The word “comprising” does not exclude the presence of other elements or steps besides those listed in the claims. Furthermore, the terms “a” or “an” as used herein are defined as one or more. Additionally, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an,” the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed as implying that introducing another claim element by the indefinite article “a” or “an” limits any particular claim containing such introduced claim element to an invention containing only one such element. The same applies to the use of definite articles. Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements. The simple fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used for benefit.

Claims

1. A processor subsystem, comprising: One or more processor cores, the one or more processor cores being used to communicate with memory; as well as A cache including multiple cache lines, the cache being used for: Determine the first index of the first set of bits from the first address associated with the first location of the memory; Determine a second index from the second group of bits from the first address, wherein the second group of bits from the first address is separated from the first group of bits from the first address by a third group of bits from the first address; as well as The data from the first location in the memory is stored in a first cache line of the cache line referenced by a combined index, the combined index being based on a combination of the first index and the second index.

2. The processor subsystem of claim 1, wherein the cache is used to cascade the first index and the second index to determine the combined index.

3. The processor subsystem of claim 1 or 2, wherein the cache is further configured to combine the third set of bits of the first address and the fourth set of bits of the first address to determine an identifier for identifying the first location of the memory.

4. The processor subsystem of claim 3, wherein the cache is used to concatenate the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.

5. The processor subsystem of claim 3, wherein the cache is used to determine the location in the first cache line to which the first location of the memory is mapped, the cache being used to determine the location based on a fifth set of bits of the first address.

6. The processor subsystem according to claim 1 or 2, wherein at least one of the first group of bits of the first address, the second group of bits of the first address, or the third group of bits of the first address has a size of one bit.

7. The processor subsystem according to claim 1 or 2, wherein the one or more processor cores include at least two processor cores, and corresponding processor cores of the at least two processor cores are configured to simultaneously access different cache lines of the cache lines.

8. An apparatus comprising: Cache lines referenced by indexes; A means for determining a first index portion and a second index portion from corresponding first and second sets of bits of a first address associated with a first location of memory, wherein the first and second sets of bits of the first address are separated by a third set of bits of the first address. as well as A means for mapping the first location of the memory to a first cache line of the cache line referenced by a first index of the index, the means for mapping being configured to determine the first index in the index based on a combination of the first index portion and the second index portion, the cache being configured to store data from the first location of the memory into the first cache line of the cache line.

9. The apparatus of claim 8, wherein the means for mapping is used to concatenate the first index portion and the second index portion to determine the first index in the index.

10. The device of claim 8 or 9, wherein the means for determining is configured to combine the third set of bits of the first address and the fourth set of bits of the first address to determine an identifier for identifying the first location of the memory.

11. The device of claim 10, wherein the means for determining is used to concatenate the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.

12. The apparatus of claim 10, wherein the means for determining is used to determine the location in the first cache line to which the first location of the memory is mapped, the location being determined based on a fifth set of bits of the first address.

13. The device according to claim 8 or 9, wherein at least one of the first group of bits of the first address, the second group of bits of the first address, or the third group of bits of the first address has a size of one bit.

14. The apparatus of claim 8 or 9, further comprising means for scheduling at least two processor cores to simultaneously access different cache lines of the cache lines.

15. A method comprising: Use logic circuitry to determine the first index of the first set of bits from the first address associated with the first location in the memory; The second index of the second set of bits from the first address is determined by logic circuitry, wherein the second set of bits from the first address is separated from the first set of bits by the third set of bits from the first address; as well as The data from the first location in the memory is stored in a first cache line that is referenced by a plurality of cache lines by a combined index, the combined index being based on a combination of the first index and the second index.

16. The method of claim 15, further comprising cascading the first index and the second index to determine the combined index.

17. The method of claim 15 or 16, further comprising combining the third set of bits of the first address and the fourth set of bits of the first address to determine an identifier for identifying the first location of the memory.

18. The method of claim 17, wherein combining the third set of bits of the first address and the fourth set of bits of the first address includes concatenating the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.

19. The method of claim 17, further comprising determining the location in the first cache line to which the first location of the memory is mapped, based on a fifth set of bits of the first address.

20. The method according to claim 15 or 16, wherein at least one of the first group of bits of the first address, the second group of bits of the first address, or the third group of bits of the first address has a size of one bit.

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