Chip and integrated chip

Abstract

A chip (100) comprising: an interconnection layer (110) and a plurality of dies disposed on the interconnection layer (110), the plurality of dies comprising a first die (1) and a second die (2), the first die (1) and the second die (2) being directly interconnected by routing lines in an edge region, wherein the edge region indicates a region outside a frame in the interconnection layer (110), the frame indicating a peripheral boundary of the plurality of dies in the interconnection layer (110). Since the edge region in the interconnection layer (110) is free of signal routing lines and is not disturbed by other data signals, the direct interconnection between the first die (1) and the second die (2) by routing lines in the edge region can reduce the delay of the data signals transmitted between the two dies and improve the data transmission efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a chip and an integrated chip. Background Technology

[0002] With the development of semiconductor technology, electronic devices are becoming thinner and smaller, integrating more performance and features into an increasingly smaller space. As a result, chip packaging technology has become more important in the electronic device industry chain.

[0003] Typically, wafers are cut into multiple dies. As chip size increases, the number of dies integrated in a single package continues to increase, and the multiple dies integrated in a single package need to communicate with each other.

[0004] In the prior art, for multiple dies integrated in a single package, these dies are interconnected through the area enclosed by the outer boundaries of the dies. This results in complex routing in this area, with more data signal interference, and therefore, a relatively large delay in transmitting data signals in this area.

[0005] In the field of high-performance computing, for multiple dies integrated in a single package, some die pairs (i.e., two dies) are sensitive to the delay of data transmission signals, that is, low data transmission signal delay is required. Obviously, the solutions in the above-mentioned prior art cannot meet the requirements of low data transmission signal delay. Summary of the Invention

[0006] This application provides a chip and an integrated chip that can reduce the latency of data signal transmission between die pairs and improve data transmission efficiency. To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0007] In a first aspect, this application provides a chip, comprising:

[0008] An interconnect layer and a plurality of dies disposed on the interconnect layer, the plurality of dies including a first die and a second die, the first die and the second die being interconnected by traces through an edge region, wherein the edge region indicates the area outside the border of the interconnect layer, and the border indicates the peripheral boundary of the plurality of dies in the interconnect layer.

[0009] Since there is little or no trace interference or signal interference in the edge area, the first die and the second die can be interconnected by traces in the edge area, which can reduce the delay of data signal transmission between die pairs and improve data transmission efficiency.

[0010] In one possible implementation, the first and second dies are not adjacent. That is, non-adjacent die pairs are interconnected via traces in the edge region.

[0011] In one possible implementation, the plurality of dies further includes a third die, with the first and third dies being adjacent to each other. The first and third dies are interconnected via traces within a border region of the interconnect layer, where the border region indicates the area enclosed by the border in the interconnect layer. In other words, adjacent die pairs are interconnected via traces within this border region.

[0012] In one possible implementation, the second and third dies are adjacent to each other, and the second and third dies are interconnected through traces in the border area of ​​the interconnect layer.

[0013] In one possible implementation, the first die and the second die are adjacent to each other.

[0014] In one possible implementation, the border is a top border of the bare wafer, which is used to indicate the boundary formed by the outermost bare wafer among the plurality of bare wafers.

[0015] In one possible implementation, the border is a die angle border, which is used to indicate the boundary formed by the connection of the vertices of the plurality of dies.

[0016] In one possible implementation, the border is a die gap border, which is used to indicate the gap area covering the plurality of dies and the boundary of the plurality of die areas.

[0017] In one possible implementation, the border is determined based on the size, shape, and arrangement of the plurality of bare pieces.

[0018] In one possible implementation, the chip is packaged as a fan-out package, and the interconnect layer is a redistribution layer.

[0019] In one possible implementation, the chip is packaged in CoWoS form, and the interconnect layer is an interposer layer.

[0020] In one possible implementation, the chip is packaged as a multi-chip assembly, with the interconnect layer serving as a substrate.

[0021] In one possible implementation, each of the plurality of dies includes microbumps, and the plurality of dies are interconnected by traces through the microbumps.

[0022] Secondly, this application provides an integrated chip, including a first chip and a second chip, wherein the first chip is the chip described in the first aspect or any implementation thereof, and the first chip and the second chip are packaged together. Attached Figure Description

[0023] Figure 1aA schematic diagram is provided showing how multiple dies within a single package communicate by crossing an intermediate die;

[0024] Figure 1b Provided with Figure 1a Corresponding cross-sectional view;

[0025] Figure 2a A schematic diagram of the top border of the three bare wafers provided in the embodiments of this application;

[0026] Figure 2b A schematic diagram of the angle borders of the three bare wafers provided in the embodiments of this application;

[0027] Figure 2c A schematic diagram of the gap border between the three bare wafers provided in an embodiment of this application;

[0028] Figure 3a A schematic diagram of the borders of three bare wafers provided in yet another embodiment of this application;

[0029] Figure 3b A schematic diagram of the borders of the five bare wafers provided in an embodiment of this application;

[0030] Figure 4a Provided for the embodiments of this application Figure 2a A schematic diagram showing the routing on the top edge of the bare die;

[0031] Figure 4b Provided for the embodiments of this application Figure 2b A schematic diagram of routing on the edge of the provided die.

[0032] Figure 4c For the purposes of this application's embodiments, in Figure 2c A schematic diagram showing the routing on the bare die gap border;

[0033] Figure 5 The embodiments provided in this application are related to Figure 4a , Figure 4b and Figure 4c Corresponding cross-sectional diagram;

[0034] Figure 6a A schematic diagram showing the routing of nine bare wafers along the top edge of the bare wafers in an embodiment of this application;

[0035] Figure 6b A schematic diagram showing the routing of nine bare wafers according to the wafer angle borders provided in this embodiment of the application;

[0036] Figure 6c A schematic diagram showing the routing of nine bare wafers according to the wafer gap borders provided in this embodiment of the application;

[0037] Figure 7a The embodiments provided in this application are related to Figure 6a , Figure 6b and Figure 6c Corresponding cross-sectional diagram;

[0038] Figure 7b Provided for yet another embodiment of this application Figure 6a , Figure 6b and Figure 6c Corresponding cross-sectional diagram;

[0039] Figure 8a This is a schematic diagram illustrating the routing of three bare dies along the top edge of the bare dies in accordance with a fan-out package, as provided in an embodiment of this application.

[0040] Figure 8b The embodiments provided in this application are related to Figure 8a Corresponding cross-sectional view;

[0041] Figure 9a A schematic diagram showing the routing of three bare dies along the top edge of the bare dies according to the CoWoS package provided in this application embodiment;

[0042] Figure 9b The embodiments provided in this application are related to Figure 9a Corresponding cross-sectional view;

[0043] Figure 10a This is a schematic diagram illustrating the routing of three bare dies along the top edge of the bare dies according to the MCM package provided in this embodiment of the application.

[0044] Figure 10b The embodiments provided in this application are related to Figure 10a The corresponding cross-sectional view. Detailed Implementation

[0045] For multiple dies integrated within a single package, these dies are interconnected through the area (border area) enclosed by their outer boundaries. Typically, adjacent dies are interconnected directly through this area, while non-adjacent dies are interconnected by crossing an intermediate die (which is adjacent to both non-adjacent dies). That is, one die transmits data signals to the intermediate die, and the intermediate die then transmits the data signals to the other die. Therefore, the intermediate die acts as a relay. This method of interconnection across the intermediate die can also be called indirect routing.

[0046] Figure 1a A schematic diagram is provided showing how multiple dies integrated within a single package communicate with each other by traversing an intermediate die. Figure 1aTaking the fan-out package (FOP) in 2.5D packaging technology as an example, a single package integrates three dies: die 1, die 2, and die 3. Below these three dies is the redistribution layer. Layer (RDL) and substrate. Die 1 and die 2 are not adjacent. Die 3, as the intermediate die between die 1 and die 2, is adjacent to both die 1 and die 2. Since die 3 is adjacent to both die 1 and die 2, direct traces are routed between die 3 and both die 1 and die 2 to achieve interconnection. Die 1 and die 2 are not adjacent. Therefore, when transmitting data signals between die 1 and die 2, the data signal is first transmitted to die 3, and then die 3 transmits the data signal out. For example, die 1 transmits the data signal to die 3, and die 3 then transmits the data signal to die 2, thus enabling die 1 to transmit the data signal to die 2. That is, die 1 and die 3 are interconnected by crossing die 2. It should be noted that... Figure 1a It is a top view. Figure 1b Is with Figure 1a The corresponding cross-sectional view, from Figure 1b The layered relationship between the substrate, redistribution layer and die can be seen more clearly in the image.

[0047] Obviously, since non-adjacent die 1 and die 2 are interconnected by crossing die 3, i.e., interconnected indirectly, the transmission delay is affected, resulting in a relatively high transmission delay. For adjacent die 3 and die 1 (or die 2), since they are directly connected by a trace, the delay is usually lower. However, in certain specific scenarios, such as when the direct trace is subject to more interference from other signals, the delay may still be high.

[0048] To address the latency issue in transmitting data signals between die pairs within a single package of multiple dies, this application proposes a scheme for interconnecting communication by routing traces in the edge region. This approach can reduce the latency of data signal transmission between die pairs and improve data transmission efficiency.

[0049] Before introducing the specific implementation of this application, let's first introduce the relevant terminology used in this application:

[0050] A bare die (also called a bare chip, bare shard, or wafer) is an unpackaged chip cut from a wafer. Each bare die is an independent, unpackaged chip with an independent function and cannot be directly used in actual circuits. Because bare dies are highly susceptible to damage from external environmental factors such as temperature, impurities, and physical forces, they need to be sealed in a sealed space with corresponding pins to be used as a basic component.

[0051] Interconnect layer: The interconnect layer is a layer located below multiple dies integrated within a single package; that is, the dies are placed on top of this interconnect layer, and communication between the dies is typically achieved through traces within the interconnect layer. In specific implementations, the interconnect layer can be a redistribution layer (RDL), an interposer, a substrate, or an embedded multi-die interconnect bridge (EMIB). The interconnect layer may contain multiple dielectric layers, as well as conductive layers sandwiched between the dielectric layers.

[0052] Bounding box: Since multiple dies can be integrated within a single package, the outer boundary of these dies is called the bounding box. Because dies are generally disposed above the interconnect layer, the bounding box referred to in this application refers to the outer boundary of multiple dies located within the interconnect layer.

[0053] Border region: The area enclosed by the border in the interconnect layer;

[0054] Edge region: The area outside the border region in the interconnect layer;

[0055] Adjacent dies: Multiple dies are integrated within a single package. These dies can form a border area. If two dies are interconnected within the border area without crossing other dies, i.e., they are directly interconnected, then these two dies are considered adjacent dies.

[0056] Non-adjacent dies: Die pairs that do not belong to the above-mentioned adjacent dies are non-adjacent dies.

[0057] Regarding the entire text, the following points need to be clarified:

[0058] 1. In the following description of the embodiments of this application, sometimes it is referred to as "first bare die" and sometimes as "bare die 1". In fact, "first bare die" is "bare die 1". Similarly, "second bare die" is "bare die 2", "third bare die" is "bare die 3", and so on. "Nth bare die" is "bare die N", where N is a positive integer. In the accompanying drawings of this application, for the sake of convenience, the terms "bare die 1", "bare die 2", and "bare die N" are used uniformly. The multiple involved in the embodiments of this application refers to two or more.

[0059] 2. In the description of the embodiments of this application, the terms "first" and "second" are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0061] Since multiple dies can be integrated within a single package, and each die may have a different size and shape, and the arrangement of the multiple dies can be varied, the border of the multiple dies integrated within a single package is affected by the size, shape, and arrangement of the multiple dies.

[0062] In some cases, the size, shape, and arrangement of multiple dies integrated within a single package determine that the borders of these dies can be classified into three types, which will be described below:

[0063] 1. Die Top Bounding Box

[0064] The top border of a die refers to the boundary formed by the outermost dies among all dies within a single package; typically, this boundary is a rectangular boundary.

[0065] For example, Figure 2a A top border of three bare dies is provided, which are disposed on the interconnect layer. The three bare dies are a first bare die (bare die 1), a second bare die (bare die 2), and a third bare die (bare die 3). The first and second bare dies are the same size, while the third bare die is different in size from the first and second bare dies. The three bare dies are the same shape, which can all be considered as rectangles. The three bare dies are arranged in rows. The first and second bare dies are not adjacent, and the third bare die is located between the first and second bare dies. The third bare die is adjacent to both the first and second bare dies.

[0066] exist Figure 2a In the diagram, the dashed box represents the border. Since this dashed box is a rectangular border formed by the boundaries of the outermost of the three bare pieces, it is the top border of the bare piece. Furthermore, Figure 2a The document also defines the border region and the edge region. The area enclosed by the border in the interconnect layer (including the area where the diagonal line is located and the area covered by the three bare dies) is the border region, and the area outside the border in the interconnect layer is the edge region.

[0067] 2. Die Angle Bounding Box

[0068] The die angle border refers to the boundary formed by connecting the vertices of all dies within a single package.

[0069] For example, Figure 2bA die angle border containing three dies is provided, which are located above the interconnect layer. The three dies are a first die (die 1), a second die (die 2), and a third die (die 3). The first and second dies are the same size, while the third die is different in size from the first and second dies. The three dies are the same shape, which can all be considered as rectangles. The three dies are arranged in rows. The first and second dies are not adjacent, and the third die is located between the first and second dies. The third die is adjacent to both the first and second dies.

[0070] exist Figure 2b In the diagram, the dashed box represents the border. Since this dashed box is the boundary formed by the lines connecting the vertices of the three bare pieces, it is therefore the angular border of the bare pieces. Furthermore, Figure 2b The document also defines the border region and the edge region. The area enclosed by the border in the interconnect layer (including the area where the diagonal line is located and the area covered by the three bare dies) is the border region, and the area outside the border in the interconnect layer is the edge region.

[0071] 3. Die Gap Bounding Box

[0072] The die gap border refers to the boundary that covers the gap area between all dies within a single package and the boundary of all die areas. The gap can be a gap formed between two dies or a gap formed between two or more dies.

[0073] For example, Figure 2c A die gap border containing three dies is provided, which are located above the interconnect layer. The three dies are a first die (die 1), a second die (die 2), and a third die (die 3). The first die and the second die are the same size, while the third die is different in size from the first and second dies. The three dies are the same shape, which can all be considered as rectangles. The three dies are arranged in rows. The first die and the second die are not adjacent, and the third die is located between the first die and the second die. The third die is adjacent to both the first die and the second die.

[0074] exist Figure 2c In the diagram, the dashed box represents the border. Part of the dashed box covers the boundaries of the three die regions, while the other part covers the boundaries of the gaps between the dies. For example, it covers the upper and lower boundaries (excluding the left and right boundaries) of the gap between die 1 and die 3, and the upper and lower boundaries (excluding the left and right boundaries) of the gap between die 2 and die 3. Furthermore... Figure 2cThe document also defines the border region and the edge region. The area enclosed by the border in the interconnect layer (including the area where the diagonal line is located and the area covered by the three bare dies) is the border region, and the area outside the border in the interconnect layer is the edge region.

[0075] Regarding the above description, the following points need to be clarified:

[0076] 1. When introducing the three types of bezels above, three bare dies are used as an example for explanation. In practice, the number of bare dies integrated in a single package can be multiple, such as five, seven or nine. This application does not limit the number of multiple chips integrated in a single package.

[0077] 2. In the above description of the three types of borders, in addition to using three bare dies as an example, the size, shape and arrangement of the three bare dies were also described. For example, the first and second bare dies are the same size, the third bare die is different in size from the first and second bare dies, the three bare dies have the same shape, and the three bare dies are arranged in rows, etc. In practice, the size, shape and arrangement of multiple bare dies integrated in a single package can be in various forms, such as different sizes, different shapes or arranged in columns, etc. This application does not limit the size, shape and arrangement of multiple chips integrated in a single package.

[0078] From the above Figure 2a , Figure 2b and Figure 2c As can be seen, in some cases, the size, shape, and arrangement of multiple dies integrated within a single package determine that the borders of these dies can be divided into the three types mentioned above. However, in other cases, the size, shape, and arrangement of multiple dies integrated within a single package determine that the borders of these dies have only one type, or in other words, they are essentially the same type when divided according to the three types mentioned above. The following will further explain these cases.

[0079] Scenario 1: Multiple dies integrated within a single package are of the same size and shape, and are arranged in a certain pattern, such as in rows or columns. In this case, the borders of these multiple dies are of only one type.

[0080] For example, Figure 3a A border containing three bare dies is provided, which are located above the interconnect layer. The three bare dies are a first bare die (bare die 1), a second bare die (bare die 2), and a third bare die (bare die 3). The three bare dies are the same size and shape, and are arranged in rows. The first bare die and the second bare die are not adjacent, and the third bare die is located between the first bare die and the second bare die. The third bare die is adjacent to the first bare die and the second bare die, respectively.

[0081] exist Figure 3aIn the image, the dashed box represents the border. If the border is formed according to the three types mentioned above, you will find that the final border is the same, as shown below. Figure 3a As shown in the image. Furthermore, Figure 3a The document also defines the border region and the edge region. The area enclosed by the border in the interconnect layer (including the area where the diagonal line is located and the area covered by the three bare dies) is the border region, and the area outside the border in the interconnect layer is the edge region.

[0082] Scenario 2: When multiple dies integrated within a single package have different sizes and shapes, and their arrangement follows a certain pattern, such as being arranged in rows or columns, then the type of the borders of these multiple dies is also only one.

[0083] For example, Figure 3b A border containing five bare dies is provided, which are located above the interconnect layer. These five dies are designated as a first die (die 1), a second die (die 2), a third die (die 3), a fourth die (die 4), and a fifth die (die 5). The first, second, fourth, and fifth dies are identical in size and shape, but the size and shape (positive direction) of the first four dies and the size and shape (longitudinal direction) of the third die are different. These five dies are arranged according to... Figure 3b The arrangement is as shown, with the first bare plate not adjacent to the second and fifth bare plates, the second bare plate not adjacent to the first and fourth bare plates, the fourth bare plate not adjacent to the second and fifth bare plates, the fifth bare plate not adjacent to the first and fourth bare plates, and the third bare plate adjacent to the other four bare plates.

[0084] exist Figure 3b In the image, the dashed box represents the border. If the border is formed according to the three types mentioned above, you will find that the final border is the same, as shown below. Figure 3b As shown in the image. Furthermore, Figure 3b The document also defines the border region and the edge region. The area enclosed by the border in the interconnect layer (including the area where the diagonal line is located and the area covered by the three bare dies) is the border region, and the area outside the border in the interconnect layer is the edge region.

[0085] Regarding the above description, the following points need to be clarified:

[0086] 1. The above only lists two scenarios. In reality, there may be many other scenarios that result in only one type of border for multiple bare dies within a single package. This application does not limit the other scenarios not listed.

[0087] 2. The two scenarios listed above are illustrated using three and five bare dies as examples, respectively. In practice, the number of bare dies integrated in a single package may be multiple, such as seven or nine. This application does not limit the number of multiple chips integrated in a single package.

[0088] The above mainly describes the border, border area and edge area of ​​multiple dies integrated in a single package. The following will introduce the routing of dies in the edge area to achieve interconnection among these multiple dies.

[0089] like Figure 4a , 4b As shown in 4c, this application embodiment provides a chip 100, which includes an interconnect layer 110 and a plurality of dies disposed on the interconnect layer. The plurality of dies includes a first die (die 1) and a second die (die 2). The first die and the second die are interconnected by traces through an edge region, wherein the edge region indicates the area outside the border of the interconnect layer, and the border indicates the peripheral boundary of the plurality of dies in the interconnect layer.

[0090] Since there are no signal traces in the edge region of the interconnect layer 110, it will not be interfered with by other data signals. Therefore, the interconnection between the first die and the second die through the edge region traces can reduce the delay of data signal transmission between the two dies and improve data transmission efficiency.

[0091] In the first implementation, the first and second dies are adjacent, meaning they are interconnected through traces in the edge region (i.e., the non-border region) of the interconnect layer. As mentioned above, adjacent dies are generally interconnected directly in the border region. Typically, direct trace routing in the border region results in relatively low latency. However, in certain scenarios, such as when the traces are subject to significant signal interference, high latency may occur. This implementation can address the high latency issues arising in these specific scenarios. Considering the limited application scenarios of this implementation, this application does not provide further elaboration or corresponding accompanying drawings.

[0092] In the second implementation, such as Figure 4a , 4b As shown in 4c, the first and second dies are not adjacent; that is, the non-adjacent dies are interconnected through traces in the edge region (i.e., non-border region) of the interconnect layer. Compared to interconnecting non-adjacent dies by crossing an intermediate die (i.e., interconnecting through indirect traces), this implementation, where the first and second dies are interconnected through edge region traces, can reduce the latency of data signal transmission between these two dies.

[0093] Furthermore, in the second implementation described above, there may be adjacent dies among the plurality of dies. Since there are no other dies between adjacent dies, they can be directly interconnected through the border area of ​​the plurality of dies in the interconnect layer. For example... Figure 4a , 4b As shown in 4c, there is a third die (die 3) between the non-adjacent first die and second die. The third die is adjacent to the first die and the third die is directly interconnected through the border area. The third die is adjacent to the second die and the third die is directly interconnected through the border area.

[0094] The following will further explain the routing method of multiple dies in the chip provided by the second implementation method in the above embodiments, taking into account each border type. It should be noted that, due to... Figure 2a , 2b 2c and 2c respectively provide a top border, corner border, and gap border for a bare piece containing three bare pieces, therefore, Figure 4a , 4b And 4c are respectively targeting Figure 2a , 2b The routing diagram for 2c.

[0095] 1. Routing on the top edge of the bare chip.

[0096] Figure 4a In order to be in Figure 2a A schematic diagram showing the routing on the top edge of the provided bare die. Figure 4a It can be seen that, Figure 4a and Figure 2a The difference lies in the addition of routing methods for three bare dies within a single package. Among them, bare die 1 and bare die 3 are adjacent and interconnected directly through the border area. Bare die 3 and bare die 2 are adjacent and interconnected directly through the border area. Bare die 1 and bare die 2 are not adjacent and interconnected through the edge area.

[0097] 2. Run traces on the edge of the bare die.

[0098] Figure 4b In order to be in Figure 2b A schematic diagram showing the routing on the edge of the provided die. Figure 4b It can be seen that, Figure 4b and Figure 2b The difference lies in the addition of routing methods for three bare dies within a single package. Among them, bare die 1 and bare die 3 are adjacent and interconnected directly through the border area. Bare die 3 and bare die 2 are adjacent and interconnected directly through the border area. Bare die 1 and bare die 2 are not adjacent and interconnected through the edge area.

[0099] 3. Run traces on the edge of the gap between the bare wafers.

[0100] Figure 4c In order to be in Figure 2c A schematic diagram showing routing on the die gap border. (Provided by...) Figure 4c It can be seen that, Figure 4c and Figure 2c The difference lies in the addition of routing methods for three bare dies within a single package. Among them, bare die 1 and bare die 3 are adjacent and interconnected directly through the border area. Bare die 3 and bare die 2 are adjacent and interconnected directly through the border area. Bare die 1 and bare die 2 are not adjacent and interconnected through the edge area.

[0101] It should be noted that the above Figure 4a , 4b Both 4c and 4c are top views. Figure 5 Provided with Figure 4a , 4b The cross-sectional view corresponding to 4c, and Figure 4a , 4b The cross-sectional view is the same as that corresponding to 4c. Because... Figure 5 It's a cross-sectional view, so it can't be viewed from... Figure 5 It can be seen that the traces of bare chip 1 and bare chip 3, as well as the traces of bare chip 3 and bare chip 2, pass through the border area, and cannot be seen from... Figure 5 It can be seen that the traces of bare die 1 and bare die 2 pass through the edge region. Additionally, Figure 5 Each die contains a microbump (uBump, uB), which is used to implement the interconnection of traces between dies.

[0102] The above Figure 4a , 4b The following example uses a 4c package with three dies integrated into a single package to illustrate the concept. To further illustrate that a single package can have multiple dies integrated, the following example uses a package with nine dies integrated into a single package.

[0103] Figure 6a , 6b The 6c package offers a routing scheme that integrates nine dies within a single package, where... Figure 6a This is a diagram illustrating the routing of nine bare wafers along their top borders. Figure 6b This is a schematic diagram showing the routing of nine bare wafers according to their angled borders. Figure 6c This is a schematic diagram showing the routing of nine bare wafers according to the wafer gap borders.

[0104] Depend on Figure 6a , 6bAs shown in section 6c, the nine bare dies are, in order, die 1, die 2, die 3, die 4, die 5, die 6, die 7, die 8, and die 9. Die 2 is adjacent to both die 1 and die 3, therefore, die 2 is interconnected with both die 1 and die 3 via traces in the border area; die 4 is adjacent to both die 1 and die 5, therefore, die 4 is interconnected with both die 1 and die 5 via traces in the border area; die 6 is adjacent to both die 1 and die 7, therefore, die 6 is interconnected with both die 1 and die 7 via traces in the border area; die 8 is adjacent to both die 1 and die 9, therefore, die 8 is interconnected with both die 1 and die 9 via traces in the border area. It should be noted that not every two adjacent dies will be interconnected. If there is no data communication requirement between two adjacent dies, then no interconnection is necessary. For example, Figure 6a , Figure 6b and Figure 6c There are multiple pairs of adjacent dies (die 2 and die 4, die 7 and die 9, etc.). Since there is no need for data communication between these adjacent dies, they are not interconnected by traces through the border area.

[0105] Furthermore, by Figure 6a , Figure 6b and Figure 6c It is known that die 1 is not adjacent to dies 3, 5, 7, and 9. Therefore, die 1 is interconnected with dies 3, 5, 7, and 9 via edge-area traces. Similarly, not every two non-adjacent dies will be interconnected. If there is no data communication requirement between two non-adjacent dies, then interconnection is unnecessary. For example, Figure 6a , Figure 6b and Figure 6c There are multiple pairs of non-adjacent dies (die 3 and die 7, die 5 and die 9, etc.). Since there is no need for data communication between these non-adjacent dies, they are not interconnected through edge areas.

[0106] It should be noted that the above Figure 6a , 6b Both 6c and 6c are top views. Figure 7a and 7b Provided with Figure 6a , 6b The two cross-sectional views corresponding to 6c, among which, Figure 7a The cutting is performed on the same side as bare films 5, 4, 1, 8, and 9. Figure 7b The cutting is performed on the same side as bare plates 3, 2, 1, 6, and 7. (The above...) Figure 4a , 4b Both 4c and 4c can correspond to these two cross-sectional diagrams. And the above... Figure 5 Similarly, in Figure 7a and Figure 7bIt is not possible to tell whether the traces between the bare chips are through the border area or the edge area.

[0107] In 2.5D packaging technology, packaging techniques for multiple dies include fan-out packaging (FOP), CoWoS (Chip-on-Wafer-on-Substrate), and Multi-Chip Module (MCM). For different packaging forms, the interconnect layers can take different forms. The following will further explain the interconnect layers for different packaging forms. It should be noted that the following descriptions of each packaging form use the top edge of the die for routing. In fact, the other two edge methods can also be applied to these three packaging forms. For the sake of brevity, this application will not further explain the application of the other two edge methods to these three packaging forms.

[0108] 1. FOP package

[0109] In FOP packaging, the interconnect layer is RDL, below the RDL is the substrate, and above the RDL are multiple bare dies.

[0110] Figure 8a A schematic diagram is provided showing how to interconnect three bare dies within a single FOP package by routing traces along the top edge of the dies. Figure 8a and Figure 4a The difference lies in the fact that the interconnect layer is a redistribution layer and the substrate below the redistribution layer.

[0111] Correspondingly, Figure 8b Provided with Figure 8a The corresponding cross-sectional view, from Figure 8b The layers between the substrate, redistribution layer, and die are clearly visible.

[0112] 2. CoWoS packaging

[0113] In CoWoS packaging, the interconnect layer is the interposer, below which is the substrate, and above which are multiple dies.

[0114] by Figure 9a For example, Figure 9a A schematic diagram is provided showing how to interconnect three dies within a single package using the CoWoS package configuration, with traces routed along the top edge of the dies. Figure 9a and Figure 4a The difference is that the interconnect layer consists of an interposer and a substrate below the interposer.

[0115] Correspondingly, Figure 9b Provided with Figure 9a The corresponding cross-sectional view, from Figure 9bThe layers between the substrate, interposer, and die are clearly visible.

[0116] 3. MCM packaging

[0117] In MCM packaging, the interconnect layer is the substrate, and above the substrate are multiple bare dies.

[0118] Figure 10a A schematic diagram is provided showing how to interconnect three dies within a single MCM package by routing traces along the top edge of the dies. Figure 10a and Figure 4a The difference is that the interconnect layer is a substrate.

[0119] Correspondingly, Figure 10b Provided with Figure 10a The corresponding cross-sectional view, from Figure 10b The layers between the substrate and the bare die are clearly visible.

[0120] Based on the above embodiments, this application also provides an integrated chip, which includes a first chip and a second chip. The first chip is the chip provided in the above embodiments, and the second chip can be the chip provided in the above embodiments or other forms of chips. The first chip and the second chip are packaged together. The first chip can be packaged together with the second chip through package on package (POP), fan out wafer level package (FOWLP) or other packaging methods. This application does not limit this.

[0121] It should be noted that the “chip” described in this application can be a chip product that has been fully packaged, or a chip product that has not been fully packaged (or “semi-packaged”), or even a chip product that has not been packaged at all. This application does not limit the definition of the chip.

[0122] It should be noted that although the above embodiments of this application indicate that non-adjacent dies within a single package are interconnected via edge region traces, this does not require that all non-adjacent dies be interconnected via edge region traces. In practice, multiple pairs of non-adjacent dies may exist within a single package. For some of these non-adjacent dies, which are sensitive to latency when transmitting data signals, i.e., require low latency, they are interconnected via edge region traces. For other adjacent dies, which are not sensitive to latency when transmitting data, they can be interconnected by crossing intermediate dies. Although this method results in higher latency, it utilizes the larger border area of ​​the interconnect layer, allowing for more and longer traces and supporting greater communication bandwidth. Conversely, since the border area is generally smaller and narrower, the communication bandwidth supported by traces within the border area of ​​the interconnect layer is limited.

[0123] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip, characterized by The chip comprises: an interconnection layer; a plurality of dies disposed on the interconnection layer, the plurality of dies comprising a first die and a second die, the first die and the second die being non-adjacent, the first die and the second die being interconnected by routing only through an edge region, wherein the edge region indicates a region in the interconnection layer other than a frame, the frame being a die angle frame used to indicate a smallest boundary of a group of lines connecting vertices of the plurality of dies, or the frame being a die gap frame used to indicate a boundary covering a gap region between the plurality of dies and a region of the plurality of dies.

2. The chip of claim 1, wherein, The plurality of dies further comprises a third die, the first die and the third die being adjacent, the first die and the third die being interconnected by routing through a frame region in the interconnection layer, the frame region indicating a region in the interconnection layer enclosed by the frame.

3. The chip of claim 2, wherein, The second die and the third die are adjacent, the second die and the third die being interconnected by routing through the frame region in the interconnection layer.

4. The chip of any one of claims 1-3, wherein, The frame is determined based on sizes, shapes and arrangements of the plurality of dies.

5. The chip of any one of claims 1-3, wherein, The chip is in a fan-out package, and the interconnection layer is a redistribution layer.

6. The chip of any one of claims 1-3, wherein, The chip is in a CoWoS package, and the interconnection layer is an interposer.

7. The chip of any one of claims 1-3, wherein, The chip is in a multi-chip module package, and the interconnection layer is a substrate.

8. The chip of any one of claims 1-3, wherein, Each die of the plurality of dies comprises micro-bumps, and the plurality of dies are interconnected by routing through the micro-bumps.

9. An integrated chip, characterized by The chip comprises a first chip and a second chip, the first chip being as claimed in any one of claims 1-8, and the first chip and the second chip being packaged together.

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