Printed circuit board and memory system comprising a printed circuit board

Abstract

A printed circuit board (PCB) comprising: a negative thermal coefficient (NTC) thermistor providing an electrical signal received from outside the PCB, wherein the electrical resistance of the NTC thermistor varies according to a negative thermal coefficient; and a heating pattern receiving the electrical signal from the NTC thermistor, wherein the heating pattern comprises a positive thermal coefficient (PTC) thermistor having an electrical resistance that varies according to a positive thermal coefficient, wherein the PTC thermistor has a first thermal resistance coefficient at or below a first critical temperature and changes to a second thermal resistance coefficient above the first critical temperature, and the NTC thermistor has a third thermal resistance coefficient at or below a second critical temperature and changes to a fourth thermal resistance coefficient above the second critical temperature.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0021189, filed on February 17, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board (PCB) and a storage system including the printed circuit board. Background Technology

[0003] Currently, automotive infotainment systems and autonomous driving systems are under development for controlling vehicles. Various applications can run on these systems. The various electronic devices within these systems can include semiconductor devices (e.g., non-volatile memory, working memory (e.g., dynamic random access memory (DRAM)), and application processors) to drive the applications.

[0004] Sudden rises or falls in temperature of semiconductor devices can significantly impact their performance and reliability. For example, vehicles are highly likely to create environments exceeding the standard temperatures for semiconductor devices. Therefore, if a semiconductor device is operated in such an environment for an extended period, it may malfunction, potentially posing a serious danger to vehicle operation. Summary of the Invention

[0005] Embodiments of this disclosure provide a printed circuit board (PCB) that rapidly and efficiently raises the temperature to the drive temperature and ensures the operational reliability of the storage device.

[0006] Embodiments of this disclosure also provide a storage system that rapidly and efficiently raises the temperature to the driving temperature while ensuring the operational reliability of the storage device.

[0007] According to embodiments of this disclosure, a PCB is provided, the PCB comprising: a negative thermal coefficient (NTC) thermistor, the NTC thermistor providing an electrical signal received from outside the PCB, wherein the resistance of the NTC thermistor varies according to the negative thermal coefficient; and a heating pattern receiving the electrical signal from the NTC thermistor, wherein the heating pattern includes a positive thermal coefficient (PTC) thermistor, the PTC thermistor having a resistance varying according to the positive thermal coefficient, wherein the PTC thermistor has a first thermal resistance coefficient at or below a first critical temperature and changes to a second thermal resistance coefficient above the first critical temperature, and the NTC thermistor has a third thermal resistance coefficient at or below a second critical temperature and changes to a fourth thermal resistance coefficient above the second critical temperature.

[0008] According to embodiments of this disclosure, a PCB is provided, the PCB comprising: a connector providing an electrical signal received from outside the PCB; and a heating pattern receiving the electrical signal from the connector, wherein the heating pattern includes a PTC thermistor having a resistance varying according to a positive thermal coefficient, wherein the PTC thermistor has a first thermal resistance coefficient at or below a first critical temperature and changes to a second thermal resistance coefficient above the first critical temperature, and the first critical temperature is in the range of -5°C to 25°C.

[0009] According to embodiments of this disclosure, a storage system is provided, the storage system comprising: a storage device for storing data; a storage controller for requesting the storage device to program the data; and a PCB having the storage device and the storage controller disposed thereon, and the PCB providing electrical signals to the storage controller, wherein the PCB includes: an NTC thermistor for providing electrical signals received from outside the PCB, wherein the resistance of the NTC thermistor varies according to a negative thermal coefficient; and a heating pattern for receiving electrical signals from the NTC thermistor, and including a PTC thermistor, wherein the resistance of the PTC thermistor varies according to a positive thermal coefficient, wherein the PTC thermistor has a first thermal resistance coefficient at or below a first critical temperature and changes to a second thermal resistance coefficient above the first critical temperature, and the NTC thermistor has a third thermal resistance coefficient at or below a second critical temperature and changes to a fourth thermal resistance coefficient above the second critical temperature. Attached Figure Description

[0010] Figure 1 This is a block diagram of a storage system that applies an embodiment of the present disclosure;

[0011] Figure 2 This is a block diagram of a storage system according to an embodiment of the present disclosure;

[0012] Figure 3 It shows Figure 2 Non-volatile storage devices;

[0013] Figure 4 A three-dimensional (3D) vertical NAND (V-NAND) structure that may be included in a non-volatile memory device according to an embodiment of the present disclosure is shown;

[0014] Figure 5 A BVNAND structure suitable for non-volatile memory devices according to an embodiment of the present disclosure is shown;

[0015] Figure 6 This is a perspective view of a storage system according to an embodiment of the present disclosure;

[0016] Figure 7 yes Figure 6 A cross-sectional view of a printed circuit board (PCB) taken along line A-A';

[0017] Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a plan view illustrating various arrangements of heating patterns according to embodiments of the present disclosure;

[0018] Figure 13 This is a flowchart illustrating the operation of a storage system according to an embodiment of the present disclosure;

[0019] Figure 14 It is a graph used to illustrate the operation of the storage system according to embodiments of the present disclosure;

[0020] Figure 15 This is a diagram illustrating the operation of a storage system according to embodiments of the present disclosure;

[0021] Figure 16 It is a graph used to illustrate the operation of the storage system according to embodiments of the present disclosure;

[0022] Figure 17 and Figure 18 A storage system according to an embodiment of the present disclosure is illustrated; and

[0023] Figure 19 It is a graph used to illustrate the effect of the storage system according to embodiments of the present disclosure. Detailed Implementation

[0024] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. Figures 1 to 19 In the description, substantially identical components are identified by the same reference numerals; therefore, any redundant description of said substantially identical components may be omitted. Furthermore, similar components are identified by similar reference numerals throughout the accompanying drawings.

[0025] Figure 1 This is a block diagram of a storage system 1000 that applies an embodiment of the present disclosure.

[0026] Reference Figure 1 , Figure 1 System 1000 can be a mobile system, such as an automotive computer, a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 1The system 1000 is not necessarily limited to mobile systems; it can also be a personal computer, laptop computer, server, media player, automotive equipment such as navigation devices, or autonomous driving system.

[0027] Reference Figure 1 System 1000 may include a main processor 1100, a memory 1020, and a storage device 1010, and may additionally include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480. The components of system 1000 can communicate with each other via a bus.

[0028] The main processor 1100 can control the overall operation of the system 1000. For example, the main processor 1100 can control the operation of other components constituting the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0029] The main processor 1100 may include one or more central processing unit (CPU) cores 1110, and may also include a controller 1120 for controlling memory 1020 and / or storage device 1010. According to embodiments of this disclosure, the main processor 1100 may also include an accelerator block 1130, which is dedicated circuitry for high-speed data processing such as artificial intelligence (AI) data processing. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0030] Memory 1020 can be used as the main storage device of system 1000 and may include volatile memory, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), but may also include non-volatile memory, such as flash memory, phase-change random access memory (PRAM), and / or resistive random access memory (RRAM). Memory 1020 may also be implemented in the same package as the main processor 1100. Although in Figure 1 The memory 1020 is set to a singular number, but this disclosure is not limited thereto; the memory 1020 may also be set to a plural number.

[0031] Storage device 1010 can be used as a non-volatile storage device that stores data regardless of power supply, and can have a relatively larger storage capacity than memory 1020. Although in Figure 1 The storage device 1010 is set to the singular, but this disclosure is not limited thereto, and the storage device 1010 may also be set to the plural.

[0032] Storage device 1010 may include storage controller 200, temperature sensor 120 that provides sensing signal SS to storage controller 200, and non-volatile storage device 300 that stores data under the control of storage controller 200.

[0033] Temperature sensor 120 senses the printed circuit board (PCB) 101a, which will be described later (see below). Figure 6 The temperature sensor 120 provides a sensing signal SS to the storage controller 200 when the temperature of the PCB 101a or the pattern reaches a predetermined temperature. The storage controller 200 can then turn on the non-volatile storage device 300 in response to the sensing signal SS.

[0034] The non-volatile storage device 300 may include vertical NAND (V-NAND) flash memory with a two-dimensional (2D) or three-dimensional (3D) structure, but may also include other types of non-volatile memory, such as phase-change random access memory (PRAM) and / or resistive random access memory (RRAM).

[0035] Storage device 1010 may be included in system 1000 in a physically separate state from main processor 1100, or it may be included in system 1000 in the form of being mounted on PCB 101a. Alternatively, storage device 1010 may be implemented in the same package as main processor 1100 or may be implemented as a memory card, and thus can be detachably coupled to other components of system 1000 via an interface such as connection interface 1480 described later. Storage device 1010 may be, but is not limited to, devices that use standard protocols such as Universal Flash Memory (UFS).

[0036] Image capturing device 1410 can capture still images or moving images, and can be a camera, portable video camera and / or webcam.

[0037] User input device 1420 can receive various types of data from the user of system 1000, and can be a touchpad, keypad, keyboard, mouse and / or microphone.

[0038] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000, and can convert the detected physical quantities into electrical signals. Sensor 1430 may be a temperature sensor, pressure sensor, illuminance sensor, position sensor, acceleration sensor, biosensor, and / or gyroscope.

[0039] Communication device 1440 can send signals to and receive signals from other devices outside system 1000 according to various communication protocols. Communication device 1440 may include an antenna, transceiver, and / or modem.

[0040] The display 1450 and the speaker 1460 can be used as output devices to output visual and audio information to the user of the system 1000, respectively.

[0041] The power supply device 1470 can convert power supplied from a battery embedded in the system 1000 and / or an external power source and supply power to each component of the system 1000.

[0042] Connection interface 1480 provides a connection between system 1000 and external devices that connect to system 1000 to exchange data. Connection interface 1480 can be implemented as various interfaces, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), Non-Volatile Memory (NVM) Fast (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), and Compact Flash Memory (CF) card interfaces. Specifically, the aforementioned PCB 101a can also be adapted to the standard protocols of connection interface 1480.

[0043] Figure 2 This is a block diagram of a storage system according to an embodiment of the present disclosure. Storage system 10 may correspond to... Figure 1 Storage device 1010.

[0044] Reference Figure 2 The storage system 10 may include a storage controller 200 and a non-volatile storage device 300. The storage controller 200 and the non-volatile storage device 300 may respectively correspond to... Figure 1 One of the storage controllers 200 and the non-volatile storage device 300.

[0045] The non-volatile storage device 300 may include a first pin P11, a second pin P12, a third pin P13, a fourth pin P14, a fifth pin P15, a sixth pin P16, a seventh pin P17 and an eighth pin P18, a memory interface circuit 310, a control logic circuit 320, and a memory cell array 330.

[0046] The memory interface circuit 310 can receive the chip enable signal nCE from the memory controller 200 via the first pin P11. The memory interface circuit 310 can send signals to and receive signals from the memory controller 200 via the second pin P12 to the eighth pin P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is enabled (e.g., at a low level), the memory interface circuit 310 can send signals to and receive signals from the memory controller 200 via the second pin P12 to the eighth pin P18.

[0047] The memory interface circuit 310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 200 via pins P12 to P14. The memory interface circuit 310 can receive or send the data signal DQ from the memory controller 200 via pin P17. The data signal DQ can be used to send commands (CMD), addresses (ADDR), and data (DATA). For example, the data signal DQ can be sent via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals.

[0048] The memory interface circuit 310 can acquire the command CMD from the data signal DQ received during the enable cycle (e.g., high level state) of the command latch enable signal CLE based on the trigger timing of the write enable signal nWE. The memory interface circuit 310 can also acquire the address ADDR from the data signal DQ received during the enable cycle (e.g., high level state) of the address latch enable signal ALE based on the trigger timing of the write enable signal nWE.

[0049] In embodiments of this disclosure, the write enable signal nWE can remain static (e.g., high or low) and then switch between high and low levels. For example, the write enable signal nWE can be triggered during the cycle in which the command CMD or address ADDR is sent. Therefore, the memory interface circuit 310 can acquire the command CMD or address ADDR based on the trigger timing of the write enable signal nWE.

[0050] The memory interface circuit 310 can receive the read enable signal nRE from the memory controller 200 via its fifth pin P15. The memory interface circuit 310 can receive the data strobe signal DQS from the memory controller 200 or send the data strobe signal DQS to the memory controller 200 via its sixth pin P16.

[0051] In the data output operation of the non-volatile storage device 300, the memory interface circuit 310 can receive a read enable signal nRE triggered via pin 5 P15 before outputting the data DATA. The memory interface circuit 310 can generate a data strobe signal DQS triggered based on the read enable signal nRE. For example, the memory interface circuit 310 can generate a data strobe signal DQS that begins triggering after a predetermined delay (e.g., tDQSRE) from the trigger start time of the read enable signal nRE. The memory interface circuit 310 can transmit a data signal DQ including the data DATA based on the trigger timing of the data strobe signal DQS. Therefore, the data DATA can be aligned with the trigger timing of the data strobe signal DQS and sent to the memory controller 200.

[0052] In the data input operation of the non-volatile storage device 300, when a data signal DQ including data DATA is received from the storage controller 200, the storage interface circuit 310 can receive a data strobe signal DQS triggered together with the data DATA from the storage controller 200. The storage interface circuit 310 can obtain the data DATA from the data signal DQ based on the trigger timing of the data strobe signal DQS. For example, the storage interface circuit 310 can obtain the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0053] The memory interface circuit 310 can send a ready / busy output signal nR / B to the memory controller 200 via pin 8 P18. The memory interface circuit 310 can also send status information of the non-volatile memory device 300 to the memory controller 200 via the ready / busy output signal nR / B. When the non-volatile memory device 300 is in a busy state (in other words, when the internal operation of the non-volatile memory device 300 is being executed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 200. When the non-volatile memory device 300 is in a ready state (in other words, when the internal operation of the non-volatile memory device 300 has not been executed or completed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 200. For example, when the non-volatile storage device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 200. Similarly, when the non-volatile storage device 300 programs data DATA into the memory cell array 330 in response to a programming command, the memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state to the memory controller 200.

[0054] The control logic circuit 320 can control various operations of the non-volatile memory device 300. The control logic circuit 320 can receive acquired commands / addresses (CMD / ADDR) from the memory interface circuit 310. Based on the received commands / addresses (CMD / ADDR), the control logic circuit 320 can generate control signals for controlling other components of the non-volatile memory device 300. For example, the control logic circuit 320 can generate various control signals for programming data DATA into or reading data DATA from the memory cell array 330.

[0055] The memory cell array 330 can store data DATA obtained from the memory interface circuit 310 under the control of the control logic circuit 320. The memory cell array 330 can also output the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320.

[0056] The storage cell array 330 may include multiple storage cells. For example, a storage cell may be a flash memory cell. However, this disclosure is not limited thereto; the storage cell may also be an RRAM cell, a ferroelectric random access memory (FRAM) cell, a PRAM cell, a thyristor random access memory (TRAM) cell, or a magnetoresistive RAM (MRAM) cell. The embodiments of this disclosure will now be described focusing on embodiments where the storage cell is a NAND flash memory cell.

[0057] The storage controller 200 may include a first pin P21, a second pin P22, a third pin P23, a fourth pin P24, a fifth pin P25, a sixth pin P26, a seventh pin P27, and an eighth pin P28, as well as a controller interface circuit 210. The first pin P21 to the eighth pin P28 may correspond to the first pin P11 to the eighth pin P18 of the non-volatile storage device 300.

[0058] The controller interface circuit 210 can send a chip enable signal nCE to the non-volatile memory device 300 via the first pin P21. The controller interface circuit 210 can send signals to and receive signals from the non-volatile memory device 300 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0059] The controller interface circuit 210 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory device 300 via pins P22 to P24. The controller interface circuit 210 can send the data signal DQ to the non-volatile memory device 300 or receive the data signal DQ from the non-volatile memory device 300 via pin P27.

[0060] The controller interface circuit 210 can send a data signal DQ, including a command CMD or an address ADDR, along with a triggered write enable signal nWE to the non-volatile storage device 300. The controller interface circuit 210 can send the data signal DQ, including a command CMD, to the non-volatile storage device 300 by sending an activated command latch enable signal CLE, and can also send the data signal DQ, including an address ADDR, to the non-volatile storage device 300 by sending an activated address latch enable signal ALE.

[0061] The controller interface circuit 210 can send the read enable signal nRE to the non-volatile memory device 300 via its fifth pin P25. The controller interface circuit 210 can receive the data strobe signal DQS from the non-volatile memory device 300 or send the data strobe signal DQS to the non-volatile memory device 300 via its sixth pin P26.

[0062] In the data output operation of the non-volatile memory device 300, the controller interface circuit 210 can generate a triggered read enable signal nRE and send the read enable signal nRE to the non-volatile memory device 300. For example, the controller interface circuit 210 can generate a read enable signal nRE that changes from a static state (e.g., high or low level) to a triggered state before the data DATA is output. Therefore, a data strobe signal DQS triggered based on the read enable signal nRE can be generated in the non-volatile memory device 300. The controller interface circuit 210 can receive a data signal DQ including the data DATA and the triggered data strobe signal DQS from the non-volatile memory device 300. The controller interface circuit 210 can obtain the data DATA from the data signal DQ based on the trigger timing of the data strobe signal DQS.

[0063] In the data input operation of the non-volatile storage device 300, the controller interface circuit 210 can generate a triggered data strobe signal DQS. For example, the controller interface circuit 210 can generate a data strobe signal DQS that changes from a static state (e.g., high or low) to a triggered state before transmitting data DATA. The controller interface circuit 210 can then send a data signal DQ, including data DATA, to the non-volatile storage device 300 based on the trigger timing of the data strobe signal DQS.

[0064] The controller interface circuit 210 can receive the ready / busy output signal nR / B from the non-volatile memory device 300 via pin 8 P28. The controller interface circuit 210 can determine the status information of the non-volatile memory device 300 based on the ready / busy output signal nR / B.

[0065] Figure 3 It shows Figure 2 300 is a non-volatile storage device.

[0066] Figure 3 yes Figure 2 Example block diagram of non-volatile storage device 300. (Refer to...) Figure 3 The non-volatile memory device 300 may include control logic circuitry 320, a memory cell array 330, a page buffer unit 340, a voltage generator 350, and a line decoder 360. The non-volatile memory device 300 may also include... Figure 2 The memory interface circuit 310 shown may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0067] The control logic circuit 320 can control various operations in the non-volatile memory device 300. The control logic circuit 320 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 310. For example, the control logic circuit 320 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0068] The storage cell array 330 may include multiple storage blocks BLK1 to BLKz (where z is a positive integer), and each of the storage blocks BLK1 to BLKz may include multiple storage cells. The storage cell array 330 can be connected to the page buffer unit 340 via the bit line BL, and can be connected to the line decoder 360 via the word line WL, the string select line SSL, and the ground select line GSL.

[0069] In embodiments of this disclosure, the memory cell array 330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference in their entirety. In embodiments of this disclosure, the memory cell array 330 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0070] Page buffer unit 340 may include multiple page buffers PB1 to PBn (where n is an integer of 3 or greater), and page buffers PB1 to PBn may be connected to memory cells via bit lines BL, respectively. Page buffer unit 340 may select at least one of the bit lines BL in response to column address Y-ADDR. Page buffer unit 340 may operate as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer unit 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 340 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0071] Voltage generator 350 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc., as word line voltage VWL.

[0072] The row decoder 360 can select one of the word lines WL and one of the string select lines SSL in response to the row address X-ADDR. For example, during a programming operation, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line. During a read operation, the row decoder 360 can receive a read enable signal nRE and provide a data signal DQ and a data strobe signal DQS to the memory interface circuit 310 by applying a read voltage to the selected word line.

[0073] Figure 4 A 3D V-NAND structure that may be included in a non-volatile memory device 300 according to an embodiment of the present disclosure is shown. When the non-volatile memory device 300 is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the memory cell array 330 can be represented as follows: Figure 4 The equivalent circuit shown.

[0074] Figure 4 The memory block BLKi shown is a 3D memory block formed in a 3D structure on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0075] Reference Figure 4 The memory block BLKi may include multiple memory NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST. Although in Figure 4 Each of the NAND strings NS11 to NS33 comprises eight memory cells MC1 to MC8, but this disclosure is not limited thereto. For example, each of the NAND strings NS11 to NS33 may include fewer or more than eight memory cells.

[0076] The string select transistor SST can be connected to the corresponding string select line SSL1, SSL2, or SSL3. Memory cells MC1 through MC8 can be connected to the corresponding gate lines GTL1, GTL2, GTL3, GTL4, GTL5, GTL6, GTL7, and GTL8, respectively. Gate lines GTL1 through GTL8 can be word lines, and some of them can be dummy word lines. The ground select transistor GST can be connected to the corresponding ground select line GSL1, GSL2, or GSL3. The string select transistor SST can be connected to the corresponding bit line BL1, BL2, or BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0077] Word lines (e.g., WL1) of the same height (e.g., memory cell (e.g., MC1)) can be connected together (connected to memory cell (e.g., MC1)), and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separate from each other. Although in Figure 4 The memory block BLKi is connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3, but this disclosure is not limited thereto.

[0078] Figure 5 A BVNAND structure suitable for a non-volatile memory device 300 according to an embodiment of the present disclosure is shown. (Refer to...) Figure 5 The non-volatile memory device 300 may have a chip-to-chip (C2C) structure. The C2C structure can be formed by: fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other using a bonding method. For example, the bonding method may refer to a method of electrically connecting bonding metal formed on the topmost metal layer of the upper chip and bonding metal formed on the topmost metal layer of the lower chip. For example, when the bonding metal is made of copper (Cu), the bonding method may be a Cu-Cu bonding method. The bonding metal may also be made of aluminum or tungsten.

[0079] Each of the peripheral circuit area PERI and cell area CELL of the non-volatile memory device 300 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0080] The Peripheral Circuit Area (PERI) may include a first substrate 3210, an interlayer insulating layer 3215, a plurality of circuit elements 3220, 3620, and 3420 formed on the first substrate 3210, first metal layers 3230, 3630, and 3430 respectively connected to the circuit elements 3220, 3620, and 3420, and second metal layers 3240, 3640, and 3440 formed on the first metal layers 3230, 3630, and 3430. In embodiments of this disclosure, the first metal layers 3230, 3630, and 3430 may be made of tungsten, which has relatively high resistance, while the second metal layers 3240, 3640, and 3440 may be made of copper, which has relatively low resistance.

[0081] Although only the first metal layers 3230, 3630, and 3430 and the second metal layers 3240, 3640, and 3440 are shown and described herein, this disclosure is not limited thereto, and one or more metal layers may be further formed on the second metal layers 3240, 3640, and 3440. At least some of the metal layers formed on the second metal layers 3240, 3640, and 3440 may be made of aluminum, which has a lower resistivity than copper, the copper used to form the second metal layers 3240, 3640, and 3440.

[0082] Interlayer insulating layer 3215 may be disposed on first substrate 3210 to cover circuit elements 3220, 3620 and 3420, first metal layers 3230, 3630 and 3430 and second metal layers 3240, 3640 and 3440, and may include insulating materials such as silicon oxide or silicon nitride.

[0083] Lower bonding metals 3671 and 3672 can be formed on the second metal layer 3640 of the word line bonding area (WLBA). In the WLBA, the lower bonding metals 3671 and 3672 of the peripheral circuit area (PERI) can be electrically connected to the upper bonding metals 3371b and 3372b of the cell area (CELL) by bonding method, and the lower bonding metals 3671 and 3672 and the upper bonding metals 3371b and 3372b can be made of aluminum, copper, or tungsten.

[0084] A cell area (CELL) can house at least one memory block. The cell area (CELL) may include a second substrate 3310 and a common source line 3320. Multiple word lines 3331, 3332, 3333, 3334, 3335, 3336, 3337, and 3338 (3330) can be stacked on the second substrate 3310 along a direction perpendicular to the upper surface of the second substrate 3310 (Z-axis direction). Serial select lines and ground select lines can be disposed above and below word lines 3330, respectively, and word lines 3330 can be disposed between serial select lines and ground select lines.

[0085] In the bit line bonding area (BLBA), the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 3310 to penetrate the word line 3330, the serial select line, and the ground select line. Each channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 3350c and the second metal layer 3360c. For example, the first metal layer 3350c may be a bit line contact, and the second metal layer 3360c may be a bit line. In embodiments of this disclosure, the bit line 3360c may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate 3310.

[0086] exist Figure 5 In the illustrated embodiment, the region where the channel structure CH and bit line 3360c are provided can be referred to as the bit line bonding area BLBA. Within the bit line bonding area BLBA, one of the bit lines 3360c can be electrically connected to circuit element 3420, which provides a page buffer 340 in the peripheral circuit area PERI. For example, one of the bit lines 3360c can be connected to upper bonding metals 3371c and 3372c in the cell area CELL, and the upper bonding metals 3371c and 3372c can be connected to lower bonding metals 3471 and 3472 connected to the circuit element 3420 of the page buffer 340.

[0087] In the word line bonding area (WLBA), word lines 3330 can extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate 3310 and can be connected to a plurality of cell contact plugs 3341, 3342, 3343, 3344, 3345, 3346, and 3347 (3340). Word lines 3330 and cell contact plugs 3340 can be connected to each other via pads provided by at least some of the word lines extending along the second direction to different lengths. A first metal layer 3350b and a second metal layer 3360b can be sequentially connected to the cell contact plugs 3340 connected to the word lines 3330. In the word line bonding area (WLBA), cell contact plugs 3340 can be connected to the peripheral circuit area (PERI) via upper bonding metals 3371b and 3372b of the cell area (CELL) and lower bonding metals 3671 and 3672 of the peripheral circuit area (PERI).

[0088] Unit contact plug 3340 can be electrically connected to circuit element 3620, which configures the line decoder 360 in the peripheral circuitry area (PERI). In embodiments of this disclosure, the operating voltage of the circuit element 3620 configuring the line decoder 360 can be different from the operating voltage of the circuit element 3420 configuring the page buffer 340. For example, the operating voltage of the circuit element 3420 configuring the page buffer 340 can be greater than the operating voltage of the circuit element 3620 configuring the line decoder 360.

[0089] A common source line contact plug 3380 can be disposed in the external pad bonding area PA. The common source line contact plug 3380 can be made of a conductive material such as metal, metal compound, or polysilicon and can be electrically connected to the common source line 3320. A first metal layer 3350a and a second metal layer 3360a can be sequentially stacked on the common source line contact plug 3380. For example, the area where the common source line contact plug 3380, the first metal layer 3350a, and the second metal layer 3360a are disposed can be referred to as the external pad bonding area PA.

[0090] Input / output pads 3105 and 3106 can be set in the external pad bonding area PA. (See reference...) Figure 5 A lower insulating layer 3201 can be formed below the first substrate 3210 to cover the lower surface of the first substrate 3210, and a first input / output pad 3105 can be formed on the lower insulating layer 3201. The first input / output pad 3105 can be connected to at least one of the circuit elements 3220, 3620 and 3420 disposed in the peripheral circuit area PERI via a first input / output contact plug 3203, and can be separated from the first substrate 3210 by the lower insulating layer 3201. In addition, a side insulating layer can be provided between the first input / output contact plug 3203 and the first substrate 3210 to electrically isolate the first input / output contact plug 3203 and the first substrate 3210.

[0091] Reference Figure 5 An upper insulating layer 3301 may be formed on the second substrate 3310 to cover the upper surface of the second substrate 3310, and a second input / output pad 3106 may be disposed on the upper insulating layer 3301. The second input / output pad 3106 may be connected to at least one of the circuit elements 3220, 3420 and 3620 disposed in the peripheral circuit area PERI via a second input / output contact plug 3303.

[0092] According to embodiments of this disclosure, the second substrate 3310 and the common source line 3320 may not be provided in the area where the second input / output contact plug 3303 is provided. Furthermore, the second input / output pad 3106 may not overlap with the word line 3330 in the third direction (Z-axis direction). See also... Figure 5 The second input / output contact plug 3303 can be separated from the second substrate 3310 in a direction parallel to the upper surface of the second substrate 3310, and can penetrate the interlayer insulating layer 3215 of the cell area CELL, and can be connected to the second input / output pad 3106.

[0093] According to embodiments of this disclosure, the first input / output pad 3105 and the second input / output pad 3106 can be selectively formed. For example, the non-volatile memory device 300 may include only the first input / output pad 3105 disposed on the first substrate 3210, or it may include only the second input / output pad 3106 disposed on the second substrate 3310. Alternatively, the non-volatile memory device 300 may include the first input / output pad 3105 and the second input / output pad 3106.

[0094] In each of the external pad bonding area PA and bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer may exist as a pseudo pattern, or the uppermost metal layer may be empty.

[0095] In the external pad bonding area PA of the non-volatile memory device 300, a lower metal pattern 3273a with the same shape as the upper metal pattern 3372a of the cell area CELL can be formed in the uppermost metal layer of the peripheral circuit area PERI, corresponding to the upper metal pattern 3372a formed in the uppermost metal layer of the cell area CELL. The lower metal pattern 3273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. In the external pad bonding area PA, an upper metal pattern with the same shape as the lower metal pattern of the peripheral circuit area PERI can be formed in the uppermost metal layer of the cell area CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI.

[0096] Lower bonding metals 3671 and 3672 can be formed on the second metal layer 3640 of the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 3671 and 3672 of the peripheral circuit area (PERI) can be electrically connected to the upper bonding metals 3371b and 3372b of the cell area (CELL) by bonding method.

[0097] Furthermore, in the bit line bonding area BLBA, an upper metal pattern 3392 with the same shape as the lower metal pattern 3452 of the peripheral circuit area PERI can be formed in the uppermost metal layer of the cell area CELL, corresponding to the lower metal pattern 3452 formed in the uppermost metal layer of the peripheral circuit area PERI. No contacts may be formed on the upper metal pattern 3392 formed in the uppermost metal layer of the cell area CELL.

[0098] Figure 6 This is a perspective view of a storage system 10a according to an embodiment of the present disclosure. Figure 7 It is a section taken along line A-A' Figure 6Cross-sectional view of PCB 101a. Figure 6 It shows Figure 1 Storage device 1010 and Figure 2 An embodiment in which the storage system 10 is mounted on PCB 101a.

[0099] Reference Figure 6 and Figure 7 The storage system 10a may include a PCB 101a and a volatile memory 110, a temperature sensor 120, a storage controller 200 and a non-volatile storage device 300 mounted on the PCB 101a.

[0100] PCB 101a can be a rigid printed circuit board (RPCB) or a flexible printed circuit board (FPCB). PCB 101a can receive power from an external power source, receive electrical signals from the outside by exchanging data with an external host, and provide the electrical signals to the storage controller 200.

[0101] PCB 101a may include connector 130, core layer 140, conductive layer 151, via 152, heating pattern 161, insulating adhesive layer 162 and protective layer 163.

[0102] Connector 130 can provide electrical signals received from the outside to other components included in PCB 101a. Connector 130 may include a plurality of pins 131a protruding in a first direction DR1, and each pin 131a may include a core layer 140 protruding along the first direction DR1 and a negative thermal coefficient (NTC) thermistor 132 and a protective layer 133 disposed on a portion of the protruding portion of the core layer 140.

[0103] The resistance of the NTC thermistor 132 varies according to its negative thermal coefficient. In other words, the NTC thermistor 132 has a negative thermal resistance coefficient α, and therefore its resistance decreases as the temperature increases.

[0104] The NTC thermistor 132 according to embodiments of the present disclosure can have a near-zero resistance thermal coefficient α when a certain critical temperature is reached, and can be used as a polyswitch by supplying power to other components with constant resistance included in PCB 101a.

[0105] The critical temperature of the NTC thermistor 132 according to embodiments of the present disclosure can be in the range of -5°C to 25°C, which can be directly related to the driving temperature of the non-volatile storage device 300.

[0106] The NTC thermistor 132 may include, but is not limited to, Mn2O3, NiO, Co2O3, Fe2O3, Cu2O3, Al2O3, or combinations thereof.

[0107] The NTC thermistor 132 can contact the conductive layer 151, which will be described later, and can provide electrical signals received from the outside to the conductive layer 151. Although in Figure 6 and Figure 7 The NTC thermistor 132 is only located in the connector 130, but it can be included as part of the conductive layer 151. External electrical signals can be input to the PCB 101a through the NTC thermistor 132.

[0108] Depending on the type of core structure of PCB 101a, core layer 140 may include one core layer or multiple core layers. Core layer 140 may be referred to as a substrate and may include glass fiber and resin, and may be flame retardant (FR)4, polyimide, epoxy resin, phenolic resin, etc., as an insulator. However, this disclosure is not limited to the above-mentioned materials.

[0109] The protective layer 133 may be disposed on a portion of the protruding portion of the core layer 140 and may cover the protruding portion of the core layer 140 where the NTC thermistor 132 is not disposed. For example, the protective layer 133 may cover the end of the core layer 140 or the bottom of the core layer 140 where the NTC thermistor 132 is not disposed. The protective layer 133 may comprise the same material as the protective layer 163 described later.

[0110] Despite Figure 6 and Figure 7 The connector 130 includes protruding pins, but this disclosure is not limited thereto. PCB 101a can be electrically connected to external chips or modules via connector 130. Conductive layer 151 can be coated on the upper or lower surface of core layer 140, and according to embodiments of this disclosure, conductive layer 151 can be disposed on the upper and lower surfaces of core layer 140 or on one side of core layer 140. Conductive layer 151 can include copper or the same material as NTC thermistor 132, but this disclosure is not limited to the aforementioned materials. Conductive layer 151 can provide electrical signal input or output to other components mounted on or disposed in PCB 101a via connector 130.

[0111] The insulating adhesive layer 162 can contact the core layer 140, the heating pattern 161, and the protective layer 163 coated with the conductive layer 151, and can bond the core layer 140, the heating pattern 161, and the protective layer 163 together.

[0112] The insulating adhesive layer 162 can be a prepreg resin, which is a semi-cured resin prepared by impregnating a thermosetting resin into glass fibers and can be formed in a single layer. The insulating adhesive layer 162 is not limited to prepreg resin and can be made of various other resins.

[0113] The heating pattern 161 can be disposed in the insulating adhesive layer 162, and the specific shape of the heating pattern 161 will be described later. Figures 8 to 12 As described in the description.

[0114] The heating pattern 161 may include a first heating pattern layer 161_1 and a second heating pattern layer 161_2 spaced apart along the third direction DR3, and the second heating pattern layer 161_2 may be configured to be adjacent to the memory controller 200 and the non-volatile storage device 300 on the third direction DR3. At least a portion of the second heating pattern layer 161_2 may overlap with the first heating pattern layer 161_1 on the third direction DR3. The number of layers may vary according to embodiments of the present disclosure.

[0115] The heating pattern 161 according to an embodiment of the present disclosure is a positive thermal coefficient (PTC) thermistor, and the resistance of the heating pattern 161 varies according to the positive thermal coefficient. In other words, the heating pattern 161 has a positive thermal resistance coefficient α, and therefore its resistance increases with increasing temperature.

[0116] Since the thermal resistance coefficient α of the heating pattern 161 according to the embodiments of the present disclosure increases when a certain critical temperature is reached, the heating pattern 161 generates heat before reaching the critical temperature and does not generate heat after reaching the critical temperature because no current flows.

[0117] The critical temperature of the heating pattern 161 according to embodiments of the present disclosure can be in the range of -5°C to 25°C, which can be directly related to the driving temperature of the non-volatile storage device 300.

[0118] The heating pattern 161 may include, but is not limited to, a combination of Sr or Pb and BaTiO3 as dielectric ceramic materials, or may include polymer-based materials.

[0119] The protective layer 163, which may be referred to as a solder mask, may have insulating properties and may be disposed on the conductive layer 151 and the insulating adhesive layer 162 to prevent oxidation and corrosion of the conductive layer 151 and the heat-resistant pattern 161. A portion of the protective layer 163 may be exposed to form solder pads, and the solder pads may be connected to the conductive layer 151 through vias 152, described later, to provide electrical signals to other components mounted on the PCB 101a.

[0120] Each via 152 can penetrate the core layer 140 or the insulating adhesive layer 162 to connect multiple conductive layers 151 or to connect the conductive layer 151 and the heating pattern 161.

[0121] The volatile storage device 110 may be, for example, DRAM. The volatile storage device 110 may be used as a buffer in data exchange between the non-volatile storage device 300 and the storage controller 200.

[0122] Temperature sensor 120 can be mounted on PCB 101a. Temperature sensor 120 can sense the temperature of PCB 101a or the temperature of heating pattern 161, and when the temperature of PCB 101a reaches a predetermined temperature or when the temperature of heating pattern 161 reaches a critical temperature, temperature sensor 120 provides a separate sensing signal SS to storage controller 200 (see [link to storage controller 200]). Figure 1 ).

[0123] According to an embodiment of this disclosure, the temperature sensor 120 can be embedded in the PCB 101a.

[0124] The storage controller 200 can be mounted on the PCB 101a, can receive external electrical signals or power input through the connector 130, and can turn on the non-volatile storage device 300 in response to the sensing signal SS.

[0125] The non-volatile storage device 300 can be configured in multiples. The non-volatile storage device 300 can be arranged along a first direction DR1 and a second direction DR2, and data can be written to or read from the non-volatile storage device 300 upon request from the storage controller 200.

[0126] Figures 8 to 12 This is a plan view illustrating various arrangements of heating patterns according to embodiments of the present disclosure.

[0127] Reference Figure 8 According to embodiments of the present disclosure, the heating pattern 161a may include a plurality of patterns extending in a fourth direction DR4 diagonally opposite to the first direction DR1 and the second direction DR2. The heating pattern 161a may be disposed between insulating adhesive layers 162a extending along the fourth direction DR4.

[0128] Reference Figure 9 According to embodiments of the present disclosure, the heating pattern 161b may include a plurality of patterns extending along a second direction DR2. The heating pattern 161b may be disposed between insulating adhesive layers 162b extending along a fourth direction DR4.

[0129] Reference Figure 10According to an embodiment of the present disclosure, the heating pattern 161c may include a plurality of first heating patterns 161c1 extending in a fourth direction DR4 diagonally opposite to the first direction DR1 and the second direction DR2, and a plurality of second heating patterns 161c2 extending in a fifth direction DR5, the fifth direction DR5 being a diagonal direction different from the fourth direction DR4.

[0130] The first heating pattern 161c1 and the second heating pattern 161c2 may intersect each other, and the insulating adhesive layer 162c may be arranged in a diamond shape between portions of the heating pattern 161c in a plan view. In other words, the insulating adhesive layer 162c may be disposed at the intersection of the first heating pattern 161c1 and the second heating pattern 161c2.

[0131] Reference Figure 11 According to embodiments of the present disclosure, the heating pattern 161d may include a plurality of first heating patterns 161d1 extending along a first direction DR1 and a plurality of second heating patterns 161d2 extending along a second direction DR2.

[0132] The first heating pattern 161d1 and the second heating pattern 161d2 may intersect each other, and the insulating adhesive layer 162d may be arranged in a rectangular shape between portions of the heating pattern 161d in the plan view.

[0133] Reference Figure 12 According to embodiments of the present disclosure, the heating pattern 161e may include a plurality of first heating patterns 161e1 extending in the second direction DR2 and a second heating pattern 161e2 shaped like a square ring and surrounding the first heating patterns 161e1. An insulating adhesive layer 162e may surround the second heating pattern 161e2.

[0134] Reference Figures 8 to 12 The heating pattern 161 can be disposed in the insulating adhesive layer 162 to form various types of patterns. Since the insulating adhesive layer 162 is disposed between portions of the heating pattern 161, the heating pattern 161 can be formed with a pattern, thereby preventing warping due to thermal expansion. According to embodiments of this disclosure, the heating pattern 161 can have, except... Figures 8 to 12 Various types of patterns besides those in the text.

[0135] Figure 13 This is a flowchart illustrating the operation of a storage system according to an embodiment of the present disclosure. Figure 14 It is a graph used to illustrate the operation of a storage system according to an embodiment of the present disclosure. Figure 15 This is a diagram illustrating the operation of a storage system according to embodiments of the present disclosure.

[0136] Figure 15The NTC thermistor 132, heating pattern 161, resistors and / or resistors of the non-volatile memory device 300, and capacitors and / or capacitors of the non-volatile memory device 300 are shown.

[0137] Reference Figure 6 , Figure 7 and Figures 13 to 15 Electrical signals or power are supplied to PCB 101a from an external source via connector 130 (operation S110). The external source can be... Figure 1 Components in system 1000, for example, an external source may be power supply device 1470.

[0138] When an electrical signal or power is provided in operation S110, the temperature of the heating pattern 161 is below the first critical temperature t1, and the temperature of the NTC thermistor 132 is the starting temperature t* below the second critical temperature t2.

[0139] At the initial temperature t*, the resistance of the heating pattern 161 is R1. According to the characteristics of the positive thermal coefficient, R1 is lower than the resistance of the heating pattern 161 at the first critical temperature t1. At the initial temperature t*, the resistance of the NTC thermistor 132 is R2. According to the characteristics of the negative thermal coefficient, R2 is higher than the resistance of the NTC thermistor 132 at the second critical temperature t2.

[0140] Heating operation (operation S120) is performed on heating pattern 161, which acts as a PTC thermistor, using the supplied power. Since the resistance of heating pattern 161 is relatively low at the initial temperature t*, a high current can flow through heating pattern 161. Heating pattern 161 can perform the heating operation according to Equation 1 below, thereby increasing the temperature of PCB 101a. According to Equation 1 below, the heat generated by heating pattern 161 is greatly affected by the current. Therefore, when the same power is input, the lower the resistance, the greater the heat generated by heating pattern 161.

[0141] P = I 2 R (1)

[0142] The resistance value of the heating pattern 161 according to an embodiment of the present disclosure can increase linearly according to a first thermal resistance coefficient α1 during a temperature rise between the initial temperature t* and the first critical temperature t1. The resistance value of the NTC thermistor 132 according to an embodiment of the present disclosure can decrease linearly according to a third thermal resistance coefficient α3 during a temperature rise between the initial temperature t* and the second critical temperature t2.

[0143] According to embodiments of the present disclosure, a first critical temperature t1 can be in the range of -5°C to 25°C, and a second critical temperature t2 according to embodiments of the present disclosure can be in the range of -5°C to 25°C. This critical temperature range T is a value directly related to the appropriate driving temperature of the non-volatile memory device. The first temperature point T1 can correspond to -5°C, while the second temperature point T2 can correspond to 25°C.

[0144] According to embodiments of this disclosure, the first critical temperature t1 and the second critical temperature t2 can be the same.

[0145] As the resistance of the NTC thermistor 132 decreases, the power input to the heating pattern 161 can increase. Therefore, even though the resistance of the heating pattern 161 increases with temperature, the heating operation efficiency of the heating pattern 161 can be maintained. By maintaining the efficiency of the heating operation, the heating pattern 161 can quickly increase the temperature of the PCB 101a.

[0146] As the resistance of the NTC thermistor 132 decreases, the amount of power supplied to the storage controller 200 and the non-volatile storage device 300 can be increased.

[0147] The first critical temperature t1 and the second critical temperature t2 are sensed by the NTC thermistor 132 (operation S130). The NTC thermistor 132 and the heating pattern 161 can sense the first critical temperature t1 and the second critical temperature t2 by the change in resistance value, without the need for the sensing operation of the temperature sensor 120.

[0148] The heating pattern 161 senses whether it has reached the first critical temperature t1 or whether the PCB 101a has reached the predetermined temperature, and the temperature sensor 120 generates a sensing signal SS based on the sensing result (see...). Figure 1 After the heating pattern 161 reaches the first critical temperature t1, the resistance value of the heating pattern 161 increases sharply due to a second thermal resistance coefficient α2 that is greater than the first thermal resistance coefficient α1. For example, the second thermal resistance coefficient α2 has a large value close to infinity.

[0149] The resistance value of the NTC thermistor 132 decreases after the second critical temperature t2 due to a fourth thermal resistance coefficient α4, which is less than the third thermal resistance coefficient α3, and becomes close to the converging resistance Rs. According to embodiments of this disclosure, the converging resistance Rs can be zero.

[0150] After the second critical temperature t2, the memory controller 200 and non-volatile storage device 300 according to embodiments of the present disclosure can be driven and supplied with constant, appropriate power by the resistance value of the NTC thermistor 132. The second critical temperature t2 can be sensed by appropriate power.

[0151] Heating pattern 161 stops heating operation (operation S140). The resistance value of heating pattern 161 changes according to the first critical temperature t1 sensed by operation S130 above, and the heating operation stops according to the change in resistance.

[0152] Temperature sensor 120 provides the generated sensing signal SS to storage controller 200. In addition to sensing the NTC thermistor 132 and heating pattern 161, temperature sensor 120 can sense a first critical temperature t1 and a second critical temperature t2, and send the sensing signal SS to storage controller 200 so that it is driven together with storage system 10.

[0153] Immediately after the first critical temperature t1 is reached, the resistance value of the heating pattern 161 reaches its maximum resistance Rmax according to the magnitude of the second thermal resistance coefficient α2. Since this is close to an open circuit state, the current is blocked. Therefore, the heating pattern 161 stops heating operation because no current flows through the heating pattern 161, and the appropriate temperature for operation of the non-volatile storage device 300 can be maintained.

[0154] The storage controller 200 provides drive power to the non-volatile storage device 300 based on the sensing signal SS and the sensing of the NTC thermistor 132 in operation S130 (operation S150).

[0155] The non-volatile memory device 300 can be driven at temperatures above the first critical temperature t1 and the second critical temperature t2 by sensing the temperature using the NTC thermistor 132 or the temperature sensor 120. Therefore, since the non-volatile memory device 300 can operate at an appropriate driving temperature, the operational reliability of the non-volatile memory device 300 can be increased.

[0156] Figure 16 This is a graph illustrating the operation of a storage system according to embodiments of the present disclosure. Reference will now be made to... Figure 16 The PCB 101a described according to an embodiment of the present disclosure focuses on... Figure 14 The differences shown are those of PCB 101a.

[0157] The first critical temperature t1' of the heating pattern 161 and the second critical temperature t2' of the NTC thermistor 132 are within the critical temperature range T, but the second critical temperature t2' is higher than the first critical temperature t1'.

[0158] Therefore, since the sensing of the second critical temperature t2' of the NTC thermistor 132 occurs after the first critical temperature t1' is reached, drive power can be provided in operation S150 after the second critical temperature t2', and thus, the non-volatile memory device 300 can operate stably after the second critical temperature t2' is reached. This ensures the operational reliability of the non-volatile memory device 300, and the heating operation between the first critical temperature t1' and the second critical temperature t2' is performed using the residual heat of the heating pattern 161.

[0159] Therefore, in embodiments of this disclosure where the first critical temperature t1' is higher than the second critical temperature t2', the storage controller 200 can quickly drive the non-volatile storage device 300.

[0160] Figure 17 and Figure 18 A storage system according to an embodiment of the present disclosure is shown. Reference will now be made to... Figure 17 and Figure 18 The PCB 101b described according to an embodiment of the present disclosure focuses on... Figure 6 and Figure 7 The differences shown are those of PCB 101a.

[0161] PCB 101b can be applied to Figure 1 The memory module 1020. The semiconductor memory module structure of the dual memory module (DIMM) can be adapted to PCB 101b. PCB 101b can correspond to PCB 101a, and pin 131b can correspond to one of pins 131a.

[0162] The front volatile storage device 20a, the rear volatile storage device 20b, and the redrive buffer 21 can be mounted on PCB101b.

[0163] The pre-volatile memory device 20a and the post-volatile memory device 20b are DRAMs. Examples of DRAMs may include synchronous dynamic random access memory (SDRAM) and double data rate dynamic random access memory (DDR DRAM), such as DDR-3 SDRAM, DDR-4 SDRAM, and DDR-5 SDRAM. Additionally, other synchronous DRAMs may include Rambus DRAM. Besides DRAM, various other memories such as SRAM and non-volatile memories can be used as the pre-volatile memory device 20a and the post-volatile memory device 20b.

[0164] The redrive buffer 21 can send the electrical signal received from pin 131b to each of the front volatile memory device 20a and the rear volatile memory device 20b.

[0165] Pin 131b can be inserted into connector insertion portion 1021 attached to motherboard 1001, and pin 131b and connector insertion portion 1021 can electrically connect PCB board 101b and motherboard 1001. NTC thermistor 132 can surround the protruding end of core layer 140.

[0166] Figure 19 It is a graph used to illustrate the effect of the storage system according to embodiments of the present disclosure.

[0167] Without applying the PCB 101a / 101b of this disclosure to a storage device, it takes 600 seconds or more for the temperature to rise from 45°C to 85°C due to the heat generated by the operation of the storage device, and it takes 16 seconds for the temperature of the storage device to rise by 1°C.

[0168] In the storage system 10 using the PCB boards 101a / 101b of this disclosure, when 20 watts of power are supplied through pin 131, it takes 160 seconds to raise the temperature from -40°C to 0°C, and 4 seconds to raise the temperature of the storage device by 1°C.

[0169] In the storage system 10 disclosed herein, when 30 watts of power are supplied via pin 131, it takes 80 seconds to raise the temperature from -40°C to 0°C, and 2 seconds to raise the temperature of the storage device by 1°C.

[0170] For example, in an automotive computer system, the storage system 10 of this disclosure can rapidly and efficiently raise the temperature from -40°C to a suitable drive temperature of 0°C using the heating pattern 161 and the NTC thermistor 132. Furthermore, by means of the aggregated switching operation of the NTC thermistor 132 included in the PCB boards 101a / 101b, the storage device can be driven at the suitable drive temperature, thereby improving the operational reliability of the storage device.

[0171] It should be understood that those skilled in the art will appreciate that many variations and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the embodiments described herein.

Claims

1. A printed circuit board (PCB), comprising: A negative thermal coefficient NTC thermistor, wherein the NTC thermistor provides an electrical signal received from outside the PCB, and the resistance of the NTC thermistor varies according to the negative thermal coefficient; and A heating pattern that receives the electrical signal from the NTC thermistor, wherein the heating pattern includes a PTC thermistor with a positive thermal coefficient, the PTC thermistor having a resistance that varies according to the positive thermal coefficient. The PTC thermistor has a first thermal resistance coefficient at or below the first critical temperature, and changes to a second thermal resistance coefficient at or above the first critical temperature. The NTC thermistor has a third thermal resistance coefficient at or below the second critical temperature, and changes to a fourth thermal resistance coefficient at or above the second critical temperature.

2. The PCB according to claim 1, wherein, The first critical temperature is in the range of -5°C to 25°C.

3. The PCB according to claim 2, wherein, The first critical temperature and the second critical temperature are the same.

4. The PCB according to claim 2, wherein, The second critical temperature is in the range of -5°C to 25°C and is higher than the first critical temperature.

5. The PCB according to claim 1, wherein, The magnitude of the first thermal resistance coefficient is smaller than the magnitude of the second thermal resistance coefficient.

6. The PCB according to claim 1, wherein, The magnitude of the third thermal resistance coefficient is greater than the magnitude of the fourth thermal resistance coefficient.

7. The PCB according to claim 1, wherein, The heating pattern is incorporated into the prepreg layer.

8. The PCB according to claim 7, wherein, The heating pattern includes a first heating pattern extending along a first direction and a second heating pattern extending along a second direction intersecting the first direction.

9. The PCB according to claim 7, wherein, The heating pattern includes a first heating pattern layer and a second heating pattern layer that at least partially overlaps with the first heating pattern layer in a planar view.

10. The PCB according to claim 1, further comprising a temperature sensor that measures the temperature of the heating pattern, wherein, When the heating pattern reaches the first critical temperature, the temperature sensor generates a sensing signal.

11. A printed circuit board (PCB), comprising: A connector that provides electrical signals received from outside the PCB; as well as A heating pattern that receives the electrical signal from the connector, wherein the heating pattern includes a positive thermal coefficient (PTC) thermistor, the PTC thermistor having a resistance that varies according to the positive thermal coefficient. The PTC thermistor has a first thermal resistance coefficient at or below a first critical temperature, and changes to a second thermal resistance coefficient above the first critical temperature, wherein the first critical temperature is in the range of -5°C to 25°C.

12. The PCB according to claim 11, wherein, The connector includes a negative thermal coefficient NTC thermistor, the NTC thermistor having a resistance that varies according to the negative thermal coefficient, and the NTC thermistor having a third thermal resistance coefficient at or below a second critical temperature, and changing to a fourth thermal resistance coefficient above the second critical temperature.

13. The PCB according to claim 12, wherein, The second critical temperature is in the range of -5°C to 25°C and is higher than the first critical temperature.

14. The PCB according to claim 11, wherein, The magnitude of the first thermal resistance coefficient is smaller than the magnitude of the second thermal resistance coefficient.

15. The PCB according to claim 11, wherein, The heating pattern is set in the prepreg layer.

16. A storage system, comprising: Storage device, the storage device storing data; A storage controller that requests the storage device to program the data; as well as A printed circuit board (PCB) has the storage device and the storage controller disposed on it, and the PCB provides electrical signals to the storage controller. The PCB includes: A negative thermal coefficient NTC thermistor, wherein the NTC thermistor provides an electrical signal received from outside the PCB, and the resistance of the NTC thermistor varies according to the negative thermal coefficient; and The heating pattern receives the electrical signal from the NTC thermistor and includes a PTC thermistor with a positive thermal coefficient, wherein the resistance of the PTC thermistor varies according to the positive thermal coefficient. The PTC thermistor has a first thermal resistance coefficient at or below the first critical temperature, and changes to a second thermal resistance coefficient at or above the first critical temperature. The NTC thermistor has a third thermal resistance coefficient at or below the second critical temperature, and changes to a fourth thermal resistance coefficient at or above the second critical temperature.

17. The storage system according to claim 16, wherein, The first critical temperature and the second critical temperature are in the range of -5°C to 25°C, and the second critical temperature is higher than the first critical temperature.

18. The storage system according to claim 16, wherein, The heating pattern is included in the prepreg layer and includes a first heating pattern layer and a second heating pattern layer that is closer to the storage device than the first heating pattern layer.

19. The storage system according to claim 16, wherein, The magnitude of the first thermal resistance coefficient is smaller than the magnitude of the second thermal resistance coefficient.

20. The storage system of claim 16, further comprising a temperature sensor that measures the temperature of the PCB, wherein, When the temperature of the PCB reaches a predetermined temperature, the temperature sensor provides a sensing signal to the storage controller.

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