Solid-state image pickup element and image pickup device

Abstract

Power consumption is reduced in a solid-state imaging device for amplifying voltages of respective columns. The solid-state imaging device includes a pixel circuit, an input transistor, a reference-side current source, and a feedback circuit. The pixel circuit generates an input voltage through photoelectric conversion. The input transistor outputs an output voltage corresponding to a voltage between a source and a gate from a drain, to which the input voltage is input. The reference-side current source is connected to a reference node having a predetermined reference voltage and supplies a predetermined current. The feedback circuit feeds back a portion of the current to the gate of the input transistor.

Description

Technical Field

[0001] This technology relates to solid-state imaging elements. More specifically, this technology relates to solid-state imaging elements and imaging devices that convert analog signals into digital signals for each column. Background Technology

[0002] Typically, in solid-state imaging devices, various ADCs (Analog-to-Digital Converters), such as single-slope type, are used to convert analog signals into digital signals. When such an ADC is set up for each column, a current source is generally connected to a node on the ground side of the vertical signal line arranged along the column, and the analog signal from that node is input to the ADC. For example, to amplify voltage, a solid-state imaging device has been proposed in which an amplifier is inserted between the node between the vertical signal line and the current source and the ADC (see, for example, Patent Document 1).

[0003] List of cited references

[0004] Patent documents

[0005] Patent Document 1: JP 2016-5054 A Summary of the Invention

[0006] Technical issues

[0007] In the aforementioned conventional technique, the voltage of the analog signal is amplified by inserting an amplifier. However, to drive the amplifier, in addition to the current source on the ground side of the vertical signal line, a current source is also needed on the power supply side of the amplifier. Because of the added current source on the power supply side, power consumption may increase compared to the case where the voltage is not amplified.

[0008] Given this situation, the purpose of this technology is to reduce power consumption in solid-state imaging elements that amplify voltage column by column.

[0009] Solution to the problem

[0010] This technology is designed to solve the aforementioned problems, and a first aspect of this technology is a solid-state imaging element comprising: a pixel circuit that generates an input voltage through photoelectric conversion; an input transistor that outputs an output voltage from its drain corresponding to the voltage between its source and gate, the input voltage being input to the source; a reference-side current source connected to a reference node having a predetermined reference voltage and providing a predetermined current; and a feedback circuit that feeds a portion of the current back to the gate of the input transistor. Therefore, the effect of amplifying the input voltage using only the current from the reference-side current source is achieved.

[0011] Furthermore, in the first aspect, the feedback circuit may include: a feedback capacitor inserted between the output node that outputs the output voltage and the gate; a reference-side capacitor inserted between the gate and the reference node having the reference voltage; and an input-side auto-zero switch that opens and closes the path between the gate and the output node. Thus, the effect of obtaining a closed-loop gain determined by the values ​​of the feedback capacitor and the reference-side capacitor is achieved.

[0012] Furthermore, in the first aspect, the solid-state imaging element may further include: a cascaded transistor inserted between the reference-side current source and the drain; and a cascaded capacitor inserted between the source of the input transistor and the gate of the cascaded transistor, and the output node may be a node between the cascaded transistor and the reference-side current source. Therefore, improved linearity is achieved.

[0013] Furthermore, in the first aspect, the solid-state imaging element may further include: a power supply-side current source connected to a power supply node having a predetermined power supply voltage; and a pair of cascaded transistors inserted between the power supply-side current source and the reference-side current source, wherein the output node may be the node between the pair of cascaded transistors. Therefore, an expanded output range is achieved.

[0014] Furthermore, in the first aspect, the solid-state imaging element may further include: an intermediate switch that opens and closes the path between the feedback capacitor and the output node; and a reference switch that opens and closes the path between the feedback capacitor and the node having a predetermined reference voltage. Therefore, the effect of extending the output range according to the reference voltage is achieved.

[0015] Furthermore, in the first aspect, the solid-state imaging element may further include: a cascaded capacitor connected to the power node having the power supply voltage; an output-side auto-zero switch that opens and closes the path between the cascaded capacitor and the output node; and an intermediate switch. The reference-side current source may include a first reference-side current source transistor and a second reference-side current source transistor, the first reference-side current source transistor being inserted between the input transistor and the reference node, the second reference-side current source transistor being inserted between one of the pair of cascaded transistors and the reference node having the reference voltage, and the intermediate switch opening and closing the path between the node between the input transistor and the first reference-side current source transistor and the node between one of the pair of cascaded transistors and the second reference-side current source transistor. Therefore, an expanded output range is achieved.

[0016] Furthermore, in the first aspect, the solid-state imaging element may further include: a boost-side current source connected to a power node having a predetermined power supply voltage; a boost transistor inserted between the boost-side current source and the reference node having the reference voltage, the boost transistor having a gate connected to an output node that outputs the output voltage; and a boost-side capacitor inserted between the node between the boost-side current source and the boost transistor and the source. Therefore, the effect of shortening the stabilization time is achieved.

[0017] Furthermore, a second aspect of this technology is a camera device comprising: a pixel circuit that generates an input voltage via photoelectric conversion; an input transistor that outputs an output voltage from its drain corresponding to the voltage between its source and gate, the input voltage being input to the source; a reference-side current source connected to a reference node having a predetermined reference voltage and providing a predetermined current; a feedback circuit that feeds a portion of the current back to the gate of the input transistor; and an analog-to-digital converter that converts the output voltage into a digital signal. Therefore, the following effect is achieved: the input voltage is amplified solely by the current from the reference-side current source, and the amplified output voltage is converted into a digital signal. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating an example of the construction of a camera device in a first embodiment of the present technology.

[0019] Figure 2 This is a diagram illustrating an example of a stacked structure of a solid-state camera element in a first embodiment of the present technology.

[0020] Figure 3 This is a block diagram illustrating a construction example of a solid-state camera element in a first embodiment of the present technology.

[0021] Figure 4 This is a circuit diagram illustrating an example of the construction of a pixel circuit in a first embodiment of the present technology.

[0022] Figure 5 This is a block diagram illustrating a construction example of a constant current source unit in a first embodiment of the present technology.

[0023] Figure 6 This is a circuit diagram illustrating a construction example of a column amplifier in a first embodiment of the present technology.

[0024] Figure 7 This is a block diagram illustrating an example of the construction of an analog-to-digital conversion unit in a first embodiment of the present technology.

[0025] Figure 8 This is a block diagram illustrating another example of an ADC in a first embodiment of the present technology.

[0026] Figure 9 This is a timing diagram illustrating an example of the operation of the column amplifier in a first embodiment of the present technology.

[0027] Figure 10 This is a circuit diagram illustrating a construction example of the column amplifier in the comparative example.

[0028] Figure 11 This is a circuit diagram illustrating a construction example of a current multiplexed column amplifier in a first embodiment of the present technology.

[0029] Figure 12 This is a graph illustrating an example of the input conversion noise frequency distribution in the first embodiment and comparative example of this technology.

[0030] Figure 13 This is a diagram illustrating examples of noise components in the first embodiment and comparative example of the present technology.

[0031] Figure 14 This is a graph illustrating an example of the input / output voltage waveform in a first embodiment of the present technology.

[0032] Figure 15 This is a graph illustrating an example of the stable output voltage waveform in the first embodiment and comparative example of this technology.

[0033] Figure 16 This is a graph illustrating an example of the error of each output voltage in a first embodiment of the present technology.

[0034] Figure 17 This is a circuit diagram illustrating a construction example of a current multiplexed column amplifier in a second embodiment of the present technology.

[0035] Figure 18 This is a graph illustrating an example of the error of each output voltage in the first and second embodiments of the present technology.

[0036] Figure 19 This is a circuit diagram illustrating a construction example of a current multiplexed column amplifier in a third embodiment of the present technology.

[0037] Figure 20 This is a circuit diagram illustrating a construction example of a current multiplexed amplifier in a variation of the third embodiment of the present technology.

[0038] Figure 21 This is a circuit diagram illustrating a construction example of a current multiplexed column amplifier in a fourth embodiment of the present technology.

[0039] Figure 22 This is a timing diagram illustrating an example of the operation of the column amplifier in a fourth embodiment of the present technology.

[0040] Figure 23 This is a circuit diagram illustrating a construction example of a column amplifier in a fifth embodiment of the present technology.

[0041] Figure 24 This is a graph illustrating an example of the input / output voltage waveform in a fifth embodiment of the present technology.

[0042] Figure 25 This is a circuit diagram illustrating another example of a column amplifier in a fifth embodiment of the present technology.

[0043] Figure 26 This is a diagram illustrating examples of the output range in comparative examples and the first to fifth embodiments of the present technology.

[0044] Figure 27 This is a diagram illustrating examples of the input range in the comparative examples and the first to fifth embodiments of the present technology.

[0045] Figure 28 The figures are examples illustrating the noise characteristics of comparative examples and the first to fifth embodiments of the present technology.

[0046] Figure 29 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0047] Figure 30 This is an explanatory diagram showing an example of the installation location of the camera unit. Detailed Implementation

[0048] The following will describe the methods used to implement this technology (hereinafter also referred to as embodiments). The description will proceed in the following order.

[0049] 1. First embodiment (example with input transistor and feedback circuit)

[0050] 2. Second embodiment (example with cascaded transistors, input transistors and feedback circuit)

[0051] 3. Third embodiment (example with input transistor and feedback circuit and added folding stage)

[0052] 4. Fourth embodiment (an example with an input transistor, feedback circuit, and folding stage, all initialized separately)

[0053] 5. Fifth embodiment (example with input transistor and feedback circuit and added boost circuit)

[0054] 6. Application examples of moving objects

[0055] <1. First Embodiment>

[0056] [Example of camera device construction]

[0057] Figure 1 This is a block diagram illustrating a construction example of a camera device 100 according to a first embodiment of the present technology. The camera device 100 is a means for capturing image data (frames) and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. Furthermore, the camera device 100 also includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As a camera device 100, in addition to digital video cameras such as digital cameras, smartphones, personal computers, or vehicle cameras with video recording capabilities can also be considered.

[0058] Optical unit 110 collects light from the subject and directs the light to solid-state imaging element 200. Solid-state imaging element 200 generates frames synchronously with a vertical synchronization signal via photoelectric conversion. Here, the vertical synchronization signal is a periodic signal with a predetermined frequency representing the timing of image capture. Solid-state imaging element 200 provides the generated image data to DSP circuit 120 via signal line 209.

[0059] The DSP circuit 120 performs predetermined signal processing on the frames from the solid-state imaging element 200. The DSP circuit 120 outputs the processed frames to the frame memory 160, etc., via the bus 150.

[0060] Display unit 130 displays frames. For example, a liquid crystal panel or an organic EL (Electroluminescence) panel can be considered as display unit 130. Operation unit 140 generates operation signals based on user input.

[0061] Bus 150 is a common path through which optical unit 110, solid-state camera element 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170 and power supply unit 180 exchange data with each other.

[0062] Frame memory 160 holds image data. Storage unit 170 stores various types of data, such as frames. Power supply unit 180 supplies power to solid-state imaging element 200, DSP circuit 120, and display unit 130, etc.

[0063] [Example of solid-state camera element construction]

[0064] Figure 2This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and pixel chips 201 stacked on the circuit chip 202. These chips are electrically connected via connections such as vias. In addition to vias, these chips can also be connected via Cu-Cu bonding or bumps.

[0065] Figure 3 This is a block diagram illustrating a construction example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a line selection unit 210, a DAC (Digital to Analog Converter) 220, and a timing control circuit 230. Furthermore, the solid-state imaging element 200 also includes a pixel array section 240, a constant current source unit 300, an analog-to-digital conversion unit 260, a horizontal transmission scanning unit 270, and an image processing unit 280.

[0066] Furthermore, in the pixel array section 240, a plurality of pixel circuits 250 are arranged in a two-dimensional grid pattern. In the following text, the set of pixel circuits 250 arranged in a predetermined horizontal direction is referred to as a "row", and the set of pixel circuits 250 arranged in a direction perpendicular to the horizontal direction is referred to as a "column".

[0067] The timing control circuit 230 controls the operation timing of the row selection unit 210, DAC 220, constant current source unit 300, analog-to-digital conversion unit 260 and horizontal transmission scanning unit 270 synchronously with the vertical synchronization signal Vsync.

[0068] The row selection unit 210 sequentially selects and drives rows, and outputs analog pixel signals to the analog-to-digital conversion unit 260 via the constant current source unit 300.

[0069] Under the control of the row selection unit 210, the pixel circuit 250 generates analog pixel signals through photoelectric conversion. Each pixel circuit 250 outputs the pixel signal to the constant current source unit 300 via the vertical signal line 259.

[0070] In the constant current source unit 300, a constant current is provided to each column. In addition, a column amplifier for amplifying pixel signals is provided for each column.

[0071] DAC 220 generates a reference signal through DA (Digital to Analog) conversion and provides this reference signal to analog-to-digital conversion unit 260. For example, a sawtooth lamp signal can be used as the reference signal.

[0072] The analog-to-digital converter 260 uses a reference signal to convert the analog input signal of each column into a digital signal. Under the control of the horizontal transmission scanning unit 270, the analog-to-digital converter 260 provides the digital signal to the image processing unit 280.

[0073] The horizontal transmission scanning unit 270 controls the analog-to-digital conversion unit 260 to output digital signals sequentially.

[0074] The image processing unit 280 performs predetermined image processing on frames arranged with digital signals. The image processing unit 280 provides the processed frames to the DSP circuit 120.

[0075] Furthermore, the aforementioned circuits in the solid-state imaging element 200 are distributed across the pixel chip 201 and the circuit chip 202. For example, the pixel array section 240 is disposed in the pixel chip 201, and circuits other than the pixel array section 240 (such as the analog-to-digital converter 260) are disposed in the circuit chip 202. The circuits disposed in the pixel chip 201 and the circuit chip 202 are not limited to this combination. For example, the pixel array section 240, the constant current source unit 300, and the comparator in the analog-to-digital converter 260 can be disposed in the pixel chip 201, and other circuits can be disposed in the circuit chip 202.

[0076] [Example of pixel circuit construction]

[0077] Figure 4 This is a circuit diagram illustrating a construction example of the pixel circuit 250 in a first embodiment of the present technology. The pixel circuit 250 includes a photoelectric conversion element 251, a transmission transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256.

[0078] Photoelectric conversion element 251 performs photoelectric conversion on incident light to generate charge. Transmission transistor 252 transfers charge from photoelectric conversion element 251 to floating diffusion layer 254 according to transmission signal TRG from row selection unit 210. Reset transistor 253 initializes the charge amount of floating diffusion layer 254 according to reset signal RST from row selection unit 210.

[0079] The floating diffusion layer 254 accumulates charge and generates a voltage corresponding to the amount of charge. The amplifying transistor 255 amplifies the voltage of the floating diffusion layer 254. The selecting transistor 256 outputs the amplified voltage signal as the pixel signal SIG based on the selection signal SEL from the row selecting unit 210. Assuming the number of columns is N (N is an integer), the pixel signal of the nth column (n is an integer from 1 to N) is transmitted to the constant current source unit 300 via the vertical signal line 259-n.

[0080] The circuit of pixel circuit 250 is not limited to the circuit shown in the attached figure, as long as the circuit can generate pixel signals through photoelectric conversion.

[0081] [Example of constructing a constant current source unit]

[0082] Figure 5 This is a block diagram illustrating a construction example of the constant current source unit 300 in the first embodiment of the present technology. In the constant current source unit 300, a column amplifier 310 is arranged for each column. When the number of columns is N, N column amplifiers 310 are arranged.

[0083] The pixel signal of the corresponding column is input to the nth column amplifier 310 via vertical signal line 259-n. Column amplifier 310 amplifies the voltage of the pixel signal and outputs it to analog-to-digital converter 260 via signal line 309-n. Hereinafter, the voltage of the pixel signal before amplification is referred to as "input voltage Vin," and the voltage after amplification is referred to as "output voltage Vout." Furthermore, column amplifier 310 is initialized by an auto-zero signal AZ from timing control circuit 230.

[0084] [Example of column amplifier construction]

[0085] Figure 6 This is a circuit diagram illustrating a construction example of the column amplifier 310 in the first embodiment of the present technology. The column amplifier 310 is provided with a current-reused column amplifier 320. Hereinafter, the current-reused column amplifier 320 will be referred to as a "CRCA (Current Reuse Column Amp)". The CRCA includes an input transistor 322, a feedback circuit 323, and a reference-side current source transistor 327. The feedback circuit 323 includes an input-side auto-zero switch 324, a feedback capacitor 325, and a reference-side capacitor 326. Additionally, in the figure, the VSL capacitor 400 connected to the vertical signal line 259-n represents the wiring capacitance between the vertical signal line 259-n and the reference voltage (ground voltage, etc.).

[0086] Furthermore, as the input transistor 322, for example, a pMOS (p-channel metal-oxide-semiconductor) transistor can be used. As the reference-side current source transistor 327, for example, an nMOS (n-channel MOS) transistor can be used.

[0087] The source of the input transistor 322 is connected to the vertical signal line 259-n, and its drain is connected to the drain of the reference-side current source transistor 327. Furthermore, the pixel circuit 250 generates a pixel signal through photoelectric conversion and inputs the voltage of the pixel signal as the input voltage Vin to the source of the input transistor 322 via the vertical signal line 259-n.

[0088] Furthermore, the source of the reference-side current source transistor 327 is connected to a reference node with a predetermined reference voltage (such as ground voltage). A predetermined bias voltage nbias is applied to the gate of the reference-side current source transistor 327, and the reference-side current source transistor 327 provides a constant bias current corresponding to the bias voltage nbias. The reference-side current source transistor 327 is an example of the reference-side current source described in the claims.

[0089] In addition, the output voltage Vout is output from the output node 328 between the input transistor 322 and the reference-side current source transistor 327 to the analog-to-digital converter unit 260 via signal line 309-n.

[0090] In the feedback circuit 323, a feedback capacitor 325 is inserted between the output node 328 and the gate of the input transistor 322. Additionally, a reference-side capacitor 326 is inserted between the gate of the input transistor 322 and the reference node of the reference voltage. An input-side auto-zero switch 324 opens and closes the path between the output node 328 and the gate of the input transistor 322 according to the auto-zero signal AZ.

[0091] With the above configuration, the gate-source voltage V of the input transistor 322 is... GS The output voltage Vout, corresponding to the drain current of the input transistor 322, varies depending on the input voltage Vin input to the source of the input transistor 322. The output voltage Vout, corresponding to the drain current, is output from the drain of the input transistor 322 (i.e., output node 328). In this way, the output voltage corresponding to the gate-source voltage of the input transistor 322 is output from the drain. Furthermore, a portion of the constant bias current provided by the reference-side current source transistor 327 is fed back to the gate of the input transistor 322 via the feedback circuit 323.

[0092] [Example of Analog-to-Digital Conversion Unit Construction]

[0093] Figure 7 This is a block diagram illustrating a construction example of the analog-to-digital conversion unit 260 in a first embodiment of the present technology. In the analog-to-digital conversion unit 260, an ADC 261 and a latch circuit 266 are arranged for each column. When the number of columns is N, N ADCs 261 and N latch circuits 266 are arranged.

[0094] The ADC 261 converts analog pixel signals into digital signals. The ADC 261 includes capacitors 262 and 263, a comparator 264, and a counter 265. Furthermore, the ADC 261 performs CDS (Correlated Double Sampling) processing.

[0095] Comparator 264 compares the reference signal from DAC 220 with the pixel signal of the corresponding column. Comparator 264 has a pair of input terminals; the reference signal is input to one input terminal via capacitor 262, and the pixel signal is input to the other input terminal via capacitor 263. Comparator 264 provides the comparison result to counter 265.

[0096] Counter 265, under the control of timing control circuit 230, counts the value during the time period before the comparison result inverts. Counter 265 outputs the signal representing the count value as a digital signal to latch circuit 266.

[0097] The latch circuit 266 holds the digital signal. The latch circuit 266 outputs the digital signal to the image processing unit 280 in sync with the synchronization signal from the horizontal transmission scanning unit 270.

[0098] like Figure 8 As shown, in ADC 261, capacitors 262 and 263 can be connected in parallel to one of the input terminals of comparator 264 (e.g., the inverting input terminal). Therefore, with Figure 7 In comparison, it can reduce the voltage of comparator 264.

[0099] [Example of column amplifier operation]

[0100] Figure 9 This is a timing diagram illustrating an example of the operation of the column amplifier 310 in the first embodiment of the present technology. At the moment T0 when the voltage of the vertical signal line 259-n is initialized, the timing control circuit 230 controls the input-side auto-zero switch 324 such that the input-side auto-zero switch 324 is switched to the off state according to the auto-zero signal AZ. Therefore, the initial voltages accumulated in the feedback capacitor 325 and the reference-side capacitor 326 are determined respectively.

[0101] Then, at time T1 after a predetermined pulse period, the timing control circuit 230 controls the input-side auto-zero switch 324 to switch it to the open state according to the auto-zero signal AZ. When the voltage of the floating diffusion layer generated by photoelectric conversion decreases the gate voltage of the amplifying transistor 255, the current supplied to the vertical signal line 259-n decreases, and the voltage of the vertical signal line 259-n (i.e., the input voltage Vin) also decreases. Due to the decrease in the input voltage Vin, the gate-source voltage V of the input transistor 322 decreases. GS The current is reduced further. Here, since the reference-side current source transistor 327 continues to introduce a constant current, the reduction in current from the vertical signal line 259-n is introduced from the output side. Furthermore, the change in output voltage Vout is negatively fed back to input transistor 322 through feedback capacitor 325 and reference-side capacitor 326. The resulting closed-loop gain g is expressed by the following equation.

[0102] g=(C F +C S ) / C F

[0103] In the above formula, C F This indicates the capacitance value of the feedback capacitor 325, C. S This indicates the capacitance value of the reference side capacitor 326.

[0104] Because the current-multiplexed amplifier 320 uses a relatively large current in the vertical signal line 259-n as bias for amplification, it can amplify effectively, thereby reducing power consumption. Furthermore, compared to the comparative example of the inverting amplifier, which will be described later, the amount of capacitor used can be reduced, thus also reducing the circuit area.

[0105] Figure 10 This is a circuit diagram illustrating a construction example of the column amplifier 500 in the comparative example. In this comparative example's column amplifier 500, a current source 501 and an input transistor 505 are connected in series with a power supply, and an output voltage Vout is output from the node between the current source 501 and the input transistor 505. The gate of the input transistor 505 is connected to the vertical signal line 259-n via a capacitor 503, and a feedback capacitor 504 is inserted between the source and the gate. Furthermore, an auto-zero switch 502 opens and closes the path between the source and the gate of the input transistor 505. The load capacitor 401 connected to the output terminal represents the capacitance of the subsequent circuitry (ADC, etc.) of the column amplifier 500.

[0106] The column amplifier 500 is used to accurately amplify the signal on the vertical signal line 259-n and transmit the amplified signal to the next stage ADC. When the signal on the vertical signal line 259-n is small, the noise requirements of the ADC can be reduced by amplifying the signal. When the signal is large, the amplification factor can be suppressed by switching the size of the capacitor. In this way, a wide range of signals can be processed using a less high-specification ADC. Amplifiers such as the column amplifier 500 suppress noise in subsequent stages, but it should be noted that the amplifier itself generates noise. In this figure, although a general single-ended inverting amplifier is used as the column amplifier 500, sufficient current must flow to ensure the transconductance Gm of the input transistor 505 in order to suppress noise. For example, when a current of the same magnitude as that flowing through the reference-side current source transistor 327 (hereinafter referred to as the "load MOS") flows, the transconductance Gm of the input transistor 505 becomes equal to or greater than the transconductance Gm of the load MOS, thereby obtaining a column amplifier with sufficiently low noise.

[0107] Figure 11 This is a circuit diagram illustrating a construction example of the current-multiplexed column amplifier 320 in the first embodiment of the present technology. To obtain a larger transconductance Gm, the column amplifier 500 of the comparative example consumes the same current as the load MOS (i.e., the reference-side current source transistor 327). On the other hand, in the current-multiplexed column amplifier 320, the column amplifier can be generated using only the current of the load MOS, thus, in principle, the power consumption can be halved compared to the column amplifier 500 of the comparative example.

[0108] To compare the CRCA shown in the figure with the case without column amplifiers and only with load MOS, separate test circuits were fabricated, and their characteristics were studied through simulation. The conditions of the test circuits are as follows.

[0109] Transconductance of the 255 amplifying transistor: 25 micro Siemens (μS)

[0110] Bias current: 4 microamps (μA)

[0111] VSL capacitor: 2 pF

[0112] Reference side capacitance: 1.05 picofarads (pF)

[0113] Feedback capacitor value: 150 finite square feet (fF)

[0114] Load capacitance: 300 fenfalcats (fF)

[0115] Input transistor size: 32u / 1u (LVT: Low Threshold Voltage)

[0116] Figure 12The frequency distribution of input switching noise is shown. In this figure, the vertical axis represents input switching noise, and the horizontal axis represents frequency. The dashed line represents the frequency distribution of the load MOS alone, and the solid line represents the frequency distribution of the CRCA. Input switching noise is the switching noise at the input of the pixel amplifier (i.e., the gate of the amplifying transistor 255), and the noise of the pixel amplifier is not considered. In solid-state imaging elements, low-frequency flicker noise is eliminated through CDS processing, and high-frequency noise is band-limited in the subsequent stages, thus focusing on the noise floor at the intermediate frequency (500kHz). The switching noise of the CRCA at 500kHz is almost twice that of the load MOS alone. This is due to the increased noise of the added pMOS (input transistor 322) and the increased input switching noise of the load MOS. Although the noise may seem to have degraded based on this result alone, by obtaining gain, the noise of the subsequent stage (comparator) can be suppressed to 1 / 8. 2 Furthermore, the total noise will decrease based on the noise of the subsequent stage. In this case, if the noise of the subsequent stage is sufficiently greater than the difference between the noise of the load MOS and the noise of the CRCA, then the CRCA can have lower noise. The comparator in the subsequent stage tends to reduce current and increase noise compared to the pixel amplifier in order to reduce power consumption, and in most cases, this condition can be expected to be met.

[0117] Furthermore, as shown by the solid line (CRCA) in the figure, although the noise appears to increase at high frequencies, this is because the amplifier gain attenuates at high frequencies. Since the input switching noise is obtained by dividing the output noise by the gain, it exhibits extreme increases in the frequency band with lower gain. However, the frequency range in which this signal is cut off is not important at all, and therefore it is not used for noise estimation.

[0118] Figure 13 The details of the input switching noise at 500kHz are shown. Here, the reason for the increase in input switching noise due to the load MOS is considered. When the transconductances of the input transistor and the pixel amplifier are gm... p and gm x When the current noise of the transistor used to convert the pixel amplifier into the input conversion voltage is , the actual resistance value can be expressed by the following formula.

[0119] (1 / gm p )+(1 / gm x Formula 1

[0120] According to the simulation, when gm p It is 93.5 micro Siemens (μS) and gm xAt 25 microsiemens (μS), the first term of Equation 1 is approximately 40 kΩ, and the second term is approximately 10.75 kΩ. With only a load MOS, the second term is 0 ohms (Ω), therefore the resistance of CRCA is approximately 1.27 times that of the case with only a load MOS. Thus, the noise (power) contribution is 1.61 times. In this figure, the thermal noise of the load MOS is 1.67 times, which is almost consistent with the prediction.

[0121] Figure 14 This is the waveform of the output voltage when the input voltage amplitude is scanned in CRCA. In this graph, the vertical axis represents voltage, and the horizontal axis represents time. The dashed line represents the waveform of the voltage (i.e., the input voltage) perpendicular to the signal line, and the solid line represents the waveform of the output voltage. One cycle begins with a 1-microsecond (μs) auto-zeroing period, followed by a 2-microsecond (μs) output of the P-phase voltage, and finally a 2-microsecond (μs) output of the D-phase voltage before ending. Here, the P-phase voltage is the voltage when the floating diffusion layer in the pixel circuit 250 has been initialized, and the D-phase voltage is the voltage when charge is transferred to the floating diffusion layer.

[0122] Furthermore, assume the input voltage (PD) is scanned in 10 mV steps within the range of 0 mV to 100 mV. Because the auto-zero signal AZ causes a gate-drain short circuit at the input transistor 322 and sets the output voltage to zero, the output voltage drops from the voltage on the vertical signal line by the gate-source voltage V. GS The quantity. Although an LVT transistor was used in the test circuit, the output voltage dropped by 335 millivolts (mV), thus limiting the output range.

[0123] Figure 15 The graph shows the steady-state of the output voltage when the voltage (input voltage) on the vertical signal line changes by 100 millivolts (mV). In this graph, the vertical axis represents the output voltage of the column amplifier, and the horizontal axis represents time. The dashed line represents the trajectory of the output voltage with only the load MOS, and the solid line represents the trajectory of the output voltage with the CRCA having an 8x gain. When measured using the time required to reach 63% of the final voltage as the time constant, the steady-state time for only the load MOS is 100 nanoseconds (ns), while the steady-state time for the CRCA increases significantly to 256 nanoseconds (ns). Since the gain in the CRCA is 8x, the charge required to charge the capacitance attached to the output is also 8x. Therefore, the actual load capacitance seen from the pixel amplifier increases, thus degrading stability. In the test circuit, the load capacitance (300 fF) and C... F / / C SMultiplying the sum of (131fF) by 8, the vertical signal line appears to have an added capacitance of 3.45 picofarads (pF). With only the load MOS, the sum of the VSL capacitance and the load capacitance is 2.3 picofarads (pF). Meanwhile, the load capacitance (300fF) and C... F / / C S Eight times the sum of (131fF) equals 5.45 picofarads (pF). In this way, the total capacitance in CRCA increases by a factor of 2.37, which is in excellent agreement with the simulation results.

[0124] Figure 16 The graph represents the error between the stabilized output voltage value after scanning the input voltage and the regression line, illustrating the so-called linearity. In this graph, the vertical axis represents the error, and the horizontal axis represents the output voltage. Although CRCA attempts to suppress the error using negative feedback, sufficient loop gain cannot be achieved due to the inherently low open gain, coupled with the small feedback rate caused by voltage division. As a result, as shown in the figure, the width of the linearity is approximately 0.3%. This is approximately 6 LSB (Least Significant Bit) in the 11-bit (i.e., 2048 grayscale) case, which is not small. Methods to improve this linearity will be explained below.

[0125] As described above, according to the first embodiment of this technology, since an input transistor 322 having an input voltage source and a feedback circuit 323 feeding back a portion of the current from the current source to the gate of the input transistor 322 are provided, amplification can be performed using only the current from the current source. Therefore, compared to the comparative example where the input voltage is input to the gate of the input transistor and the current source is added to its source, power consumption can be reduced.

[0126] <2. Second Embodiment>

[0127] Although negative feedback is formed by feedback circuit 323 in the first embodiment described above, sufficient loop gain cannot be obtained in this configuration due to the low feedback rate, and linearity may deteriorate. The current multiplexed column amplifier 320 of the second embodiment differs from the first embodiment in that it improves linearity by adding cascaded transistors.

[0128] Figure 17 This is a circuit diagram illustrating a construction example of the current multiplexed column amplifier 320 in the second embodiment of the present technology. The current multiplexed column amplifier 320 of the second embodiment differs from that of the first embodiment in that it further includes a cascaded capacitor 331, a cascaded transistor 332, and a cascade-side auto-zero switch 333. For example, a pMOS transistor is used as the cascaded transistor 332.

[0129] A cascaded transistor 332 is inserted between the drain of the input transistor 322 and the drain of the reference-side current source transistor 327 (load MOS). Furthermore, a cascaded capacitor 331 is inserted between the source of the input transistor 322 (i.e., the vertical signal line 259-n) and the gate of the cascaded transistor 332.

[0130] The cascaded-side automatic zeroing switch 333 opens and closes the path between the gate and drain of the cascaded transistor 332 according to the automatic zeroing signal AZ.

[0131] While the gate voltage of a cascaded transistor is biased at a constant voltage in a typical analog circuit, in a CRCA, the source voltage (i.e., the input voltage) of the input transistor 322 varies, thus requiring a voltage bias that varies with the source voltage. Therefore, as shown, a cascaded capacitor 331 is connected between the vertical signal line 259-n and the gate of the cascaded transistor 332, and the cascade-side auto-zero switch 333 is closed during auto-zeroing. Thus, the gate voltage of the cascaded transistor 332 can be linked to the vertical signal line 259-n. The current-multiplexed amplifier 320 shown in the figure is referred to below as a "cascaded (C)-CRCA".

[0132] Figure 18 This is a graph illustrating examples of the error of each output voltage in the first and second embodiments of the present technology. In this graph, the vertical axis represents the error, and the horizontal axis represents the output voltage. Furthermore, the dashed line in this graph represents the linearity of the C-CRCA in the first embodiment without cascaded transistor 332, etc., and the solid line represents the linearity of the C-CRCA in the second embodiment. As shown, in the second embodiment, by adding cascaded transistor 332, the linearity is significantly improved, with a width of 0.06%.

[0133] As described above, according to the second embodiment of the present technology, since a cascaded transistor 332 is inserted to apply a voltage to the gate that depends on the input voltage, the linearity of the output voltage relative to the input voltage can be improved.

[0134] <3. Third Embodiment>

[0135] In the second embodiment described above, a cascaded transistor 332 is inserted between the drain of the input transistor 322 and the reference-side current source transistor 327 (load MOS). However, in this C-CRCA, the output range is reduced, thus becoming a problem. The current multiplexed column amplifier 320 of the third embodiment differs from the second embodiment in that it expands the output range through a folding stage.

[0136] Figure 19This is a circuit diagram illustrating a construction example of the current multiplexed column amplifier 320 according to a third embodiment of the present technology. The current multiplexed column amplifier 320 of the third embodiment includes an input stage 321 and a folding stage 340. An input transistor 322, an input-side auto-zero switch 324, a feedback capacitor 325, a reference-side capacitor 326, and a reference-side current source transistor 327 are arranged in the input stage 321. The connection configuration of the input transistor 322, the reference-side capacitor 326, and the reference-side current source transistor 327 is the same as that of the first embodiment.

[0137] Furthermore, a power-side current source transistor 342 and cascaded transistors 343 and 345 are arranged in the folded stage 340. A pMOS transistor is used as the power-side current source transistor 342 and the cascaded transistor 343, and an nMOS transistor is used as the cascaded transistor 345.

[0138] A power-side current source transistor 342 and a cascaded transistor 343 are connected in series to a power node. Furthermore, a bias voltage pbias is applied to the gate of the power-side current source transistor 342, and a bias voltage pcas is applied to the gate of the cascaded transistor 343. The power-side current source transistor 342 is an example of the power-side current source described in the claims.

[0139] A cascade transistor 345 is inserted between a cascade transistor 343 and a reference-side current source transistor 327. Furthermore, a predetermined bias voltage ncas is applied to the gate of the cascade transistor 345.

[0140] Furthermore, the node between cascaded transistors 343 and 345 is used as output node 328. An input-side auto-zero switch 324 opens and closes the path between input transistor 322 and output node 328, and a feedback capacitor 325 is inserted between input transistor 322 and output node 328.

[0141] In the following text, the current-multiplexed column amplifier 320 shown in the figure is referred to as a "Folded Cascode (FC)-CRCA". Although current flowing through the folding stage 340 is added to this FC-CRCA, this current can be reduced compared to the current of the input stage 321. Since the input switching noise of the power supply side current source transistor 342 also decreases when the current is reduced, reducing the current is desirable. In the FC-CRCA of the third embodiment, the output range can be expanded by 1V compared to the C-CRCA of the second embodiment. GS .

[0142] As described above, according to the third embodiment of the present technology, the output range can be expanded compared to the second embodiment which only has cascaded transistor 332, due to the addition of cascaded transistors 343 and 345.

[0143] [Variation Example]

[0144] Although cascaded transistors 343 and 345 are added in the third embodiment described above, the output range may be insufficient in this configuration. The current-multiplexed column amplifier 320 of this variant of the third embodiment differs from that of the first embodiment in that, during automatic zeroing, the output range is expanded by applying a reference voltage to the feedback capacitor 325.

[0145] Figure 20 This is a circuit diagram illustrating a construction example of the current multiplexed amplifier 320 in a variation of the third embodiment of the present technology. The current multiplexed amplifier 320 in the variation of the third embodiment differs from that of the third embodiment in that it further includes an intermediate switch 330 and a reference switch 330-1. Furthermore, one end of the feedback capacitor 325 is connected to the node between the intermediate switch 330 and the reference switch 330-1, instead of the output node 328.

[0146] Intermediate switch 330 opens and closes the path between output node 328 and one end of feedback capacitor 325 according to the inversion signal xAZ. Here, the inversion signal xAZ is obtained by inverting the auto-zero signal AZ. Reference switch 330-1 opens and closes one end of feedback capacitor 325 and a predetermined reference voltage V according to the auto-zero signal AZ. R The path between nodes.

[0147] According to the configuration shown in the figure, during automatic zeroing, the timing control circuit 230 closes the input-side automatic zeroing switch 324 and the reference switch 330-1, and opens the intermediate switch 330. Therefore, regardless of the vertical signal line, the zero voltage can be determined as the output voltage during automatic zeroing. Reference voltage V R The current source transistor 342 and the cascaded transistor 343 on the power supply side are configured to prevent them from entering the high voltage region of the linear region. Therefore, the output range can be fully utilized.

[0148] As described above, in a variation of the third embodiment of this technology, since the reference voltage V will be used to connect during automatic zeroing... R The reference switch 330-1 of the node is added to one end of the feedback capacitor 325, so that the zero voltage can be set to depend on the reference voltage V. R The voltage is used to extend the output range.

[0149] <4. Fourth Embodiment>

[0150] Although in the third embodiment described above, the input-side auto-zero switch 324 opens and closes the path between the input transistor 322 and the output node 328, in this configuration, during auto-zeroing, the output zero voltage drops by 1V from the zero voltage of the vertical signal line.GS The current multiplexed amplifier 320 of the fourth embodiment differs from that of the third embodiment in that automatic zeroing is performed in the input stage 321 and the folding stage 340 respectively, and a switch is inserted between the input stage 321 and the folding stage 340 to suppress the drop in zero voltage.

[0151] Figure 21 This is a circuit diagram illustrating a construction example of the current multiplexed column amplifier 320 in the fourth embodiment of the present technology. The current multiplexed column amplifier 320 of the fourth embodiment differs from that of the third embodiment in that it further includes a cascaded capacitor 341, an output-side auto-zero switch 344, an intermediate switch 346, and a reference-side current source transistor 347. An nMOS transistor is used as the reference-side current source transistor 347. Furthermore, the connection configuration of the components in the input stage 321 of the fourth embodiment is the same as that of the first embodiment.

[0152] Furthermore, a cascaded capacitor 341 is inserted between a power supply node having a predetermined power supply voltage and an output-side auto-zero switch 344. The gate of the power supply-side current source transistor 342 is connected to the node between the cascaded capacitor 341 and the output-side auto-zero switch 344.

[0153] Furthermore, a reference-side current source transistor 347 is inserted between the cascaded transistor 345 and the reference node. A bias voltage nbias, the same as the bias voltage of the reference-side current source transistor 327, is applied to the gate of the reference-side current source transistor 347. The reference-side current source transistor 327 is an example of the first reference-side current source transistor described in the claims, and the reference-side current source transistor 347 is an example of the second reference-side current source transistor described in the claims.

[0154] Intermediate switch 346 opens and closes the path between the node between input transistor 322 and reference-side current source transistor 327 and the node between cascade transistor 345 and reference-side current source transistor 347 according to the inversion signal xAZ.

[0155] In addition, the output-side auto-zero switch 344 opens and closes the path between the cascade capacitor 341 and the output node 328 according to the auto-zero signal AZ.

[0156] In the following text, the current multiplexed column amplifier 320 shown in the figure is referred to as “Modified Folded Cascode (MFC)-CRCA”.

[0157] According to the configuration shown in the figure, during automatic zeroing, the input stage 321 and the folding stage 340 can be separated by the intermediate switch 346, and automatic zeroing can be performed separately in the input stage 321 and the folding stage 340. In the input stage 321, the input-side automatic zeroing switch 324 performs automatic zeroing using the intermediate node. On the other hand, the output-side automatic zeroing switch 344 in the folding stage 340 short-circuits the gate of the power supply-side current source transistor 342 and the output node 328. In this way, the zero voltage of the output becomes a 1V drop from the power supply of the folding stage 340. GS The voltage is such that a voltage higher than the FC-CRCA voltage in the third embodiment can be set to zero. This expands the output range. In the fourth embodiment, since the single current source in the third embodiment is divided into two current sources (reference-side current source transistors 327 and 347), the effect of auto-zeroing is weakened, thus requiring attention to the generation of offset. Specifically, the drain voltage of the input transistor 322 decreases during normal operation compared to the auto-zeroing period, thus offsetting in the direction of increased output voltage. This offset is particularly amplified when the current in the folded stage 340 decreases compared to the current in the input stage 321.

[0158] Furthermore, while the output range is greatly expanded, the maximum value of the input range is reduced by the amount of saturation voltage of the input transistor 322 compared to the case where only the load MOS is set. When used at 1x gain, the input range becomes narrower and noise increases compared to the case where only the load MOS is set. Therefore, it is possible to lose the noise suppression effect in subsequent stages.

[0159] Figure 22 This is a timing diagram illustrating an example of the operation of the column amplifier 310 in the fourth embodiment of the present technology. At the moment T0 when the voltage of the vertical signal line 259-n is initialized, the timing control circuit 230 controls the input-side auto-zero switch 324 and the output-side auto-zero switch 344, such that the input-side auto-zero switch 324 and the output-side auto-zero switch 344 are switched to the off state according to the auto-zero signal AZ. Furthermore, the timing control circuit 230 controls the intermediate switch 346, such that the intermediate switch 346 is switched to the on state according to the inversion signal xAZ.

[0160] Then, at time T1 after a predetermined pulse period, the timing control circuit 230 controls the input-side auto-zero switch 324 and the output-side auto-zero switch 344, causing them to switch to the open state according to the auto-zero signal AZ. Furthermore, the timing control circuit 230 controls the intermediate switch 346, causing it to switch to the closed state according to the inversion signal xAZ.

[0161] When the voltage of the floating diffusion layer generated by photoelectric conversion reduces the gate voltage of the amplifying transistor 255, the current supplied to the vertical signal line 259-n decreases, and the voltage of the vertical signal line 259-n (input voltage Vin) also decreases. Due to the decrease in input voltage Vin, the gate-source voltage V of the input transistor 322 decreases. GS The current is further reduced. Here, since the reference-side current source transistors 327 and 347 continue to introduce a constant current, the reduction in current from the vertical signal line 259-n is introduced from the output side. The output node 328 has high impedance due to the cascaded transistors 343 and 345, resulting in a large voltage drop. In addition, the change in output voltage Vout is negatively fed back to the input transistor 322 through the feedback capacitor 325 and the reference-side capacitor 326.

[0162] As described above, according to the fourth embodiment of the present technology, since the intermediate switch 346 separates the input stage 321 and the folding stage 340 during automatic zeroing, thereby performing automatic zeroing separately, the zero voltage can be increased to expand the output range compared to the case where the input stage 321 and the folding stage 340 are not separated.

[0163] <5. Fifth Embodiment>

[0164] In the first embodiment described above, the gain is higher compared to the case with only a load MOS, thus increasing the actual load capacitance seen from the pixel amplifier and deteriorating stability. The column amplifier 310 of this fifth embodiment differs from the first embodiment in that a boost circuit 350 is added to reduce the load capacitance.

[0165] Figure 23 This is a circuit diagram illustrating a construction example of the column amplifier 310 in the fifth embodiment of the present technology. The column amplifier 310 of the fifth embodiment differs from that of the first embodiment in that, in addition to the current-multiplexed column amplifier 320, it also includes a boost circuit 350. The boost circuit 350 includes a boost-side capacitor 351, a boost-side current source transistor 352, a cascaded transistor 353, and a boost transistor 354. pMOS transistors are used as the boost-side current source transistor 352, the cascaded transistor 353, and the boost transistor 354.

[0166] A boost-side current source transistor 352, a cascaded transistor 353, and a boost transistor 354 are connected in series between the power supply node and the reference node. A predetermined bias voltage pbias is applied to the gate of the boost-side current source transistor 352, and a predetermined bias voltage pcas is applied to the gate of the cascaded transistor 353. The gate of the boost transistor 354 is connected to the output node 328. The boost-side current source transistor 352 and the cascaded transistor 353 are examples of the boost-side current sources described in the claims.

[0167] In addition, the boost-side capacitor 351 is inserted between the vertical signal line 259-n and the node between the cascaded transistor 353 and the boost transistor 354.

[0168] According to the configuration shown in the figure, the output voltage Vout can be buffered by using the source follower of the boost transistor 354, and the output voltage Vout can be connected to the vertical signal line 259-n via a capacitor. For example, when the gain is 8x, the voltage drop of the output voltage Vout is 8 times that of the voltage drop of the vertical signal line 259-n, thus generating a voltage fluctuation in the boost-side capacitor 351 that is 7 times the difference between the two. A current can then be introduced from the vertical signal line 259-n to charge the boost-side capacitor 351 to assist in stabilization. This operation can be viewed as attaching a negative capacitance to ground of 7 times the size of the vertical signal line 259-n to the vertical signal line 259-n, effectively reducing the load capacitance.

[0169] Here, the load capacity on the output side is expressed by the following formula.

[0170] C L +C S / / C F Formula 2

[0171] When the capacitance value of the boost-side capacitor 351 is set to the same level as in Equation 2, it can be expected that the virtual capacitance that increases with the gain will be completely eliminated. However, when the gain is 1, it should be noted that the voltage of the boost-side capacitor 351 does not change and it does not work at all.

[0172] Although an additional branch current is required for the boost circuit 350 in the fifth embodiment, this current can be relatively small. When gain is present, this is achieved by applying the gate-source voltage Vboost of the boost transistor 354. GS This allows a large current to flow to the reference node. Furthermore, noise from the additional boost circuit 350 is filtered out of the output by the VSL capacitor 400.

[0173] Figure 24 This is a graph illustrating an example of the input / output voltage waveforms in the fifth embodiment of the present technology. In this graph, the vertical axis represents voltage, and the horizontal axis represents time. The dotted-dashed line represents the waveform of the input voltage, the solid line represents the waveform of the output voltage with the boost circuit 350 added, and the dashed line represents the waveform of the output voltage without the boost circuit 350 added.

[0174] Assuming the boost transistor 354 has dimensions of 8µm / 1µm, a current of 1µA, and a boost-side capacitor 351 with a capacitance of 431 finite square feet (fF), the waveform shown in the figure is obtained. The time constant of 256 nanoseconds (ns) for CRCA alone is improved to 167 nanoseconds (ns) by adding the boost circuit 350.

[0175] Although the boost circuit 350 is added to the CRCA of the first embodiment, it is also possible to add the boost circuit 350 to the second to fourth embodiments. For example, as Figure 25 As shown, a boost circuit 350 can be added to the MFC-CRCA of the fourth embodiment.

[0176] As described above, according to the fifth embodiment of the present technology, since the load capacity is reduced by adding the boost circuit 350, the time required for stabilization can be shortened.

[0177] Subsequently, a comparative example with only a load MOS and the first to fifth embodiments will be compared. Figure 26 Comparative examples with only the load MOS set and examples of the output range in the first to fifth embodiments are shown. Figure 27 A comparative example with only the load MOS set and examples of the input range in the first to fifth embodiments are shown.

[0178] The zero voltage of the input signal is set to 2 volts (V), the voltage range from which it can drop below zero is set as the input range, and the voltage range from which it can output at any gain is set as the output range. First, with only the load MOS of the comparative example, only 300 millivolts (mV) are needed to saturate the reference-side current source. However, when ensuring 900 millivolts (mV) as a margin for absorbing variations and IR drop, the remaining 800 millivolts (mV) obtained by subtracting these from 2 volts (V) becomes the net output range.

[0179] Next, in the first embodiment of the CRCA, the output range is reduced by the amount of the 335 millivolt (mV) voltage drop generated by the auto-zeroing operation of the input transistor 322. Furthermore, in the second embodiment of the C-CRCA, the auto-zeroing voltage drop is doubled, resulting in an output range of only 130 millivolt (mV). Meanwhile, in the comparative example, CRCA, and C-CRCA where only the load MOS is set, the input and output ranges are the same.

[0180] In the third embodiment of FC-CRCA, although the voltage drop of automatic zeroing is only one step, due to the addition of nMOS cascade transistor 345, it is necessary to ensure a saturation voltage of approximately 100 millivolts (mV).

[0181] In the fourth embodiment of MFC-CRCA, due to the different auto-zeroing method, subtraction can begin from the power supply voltage (2.8 volts in this case) instead of from the 2 volt (V) input signal. The voltage drop during auto-zeroing is 600 millivolts (mV). Furthermore, even after subtracting 100 millivolts (mV) as the saturation voltage of the nMOS cascade transistor 345, the output range is 900 millivolts (mV), which is higher than any other method. Regarding the input range, the voltage drop caused by auto-zeroing disappears, but since only the saturation voltage of the input transistor 322, 100 millivolts (mV), is required, the input range is 700 millivolts (mV), slightly less than the case where only the load MOS is set.

[0182] Subsequently, Figure 28 The diagram shows predictions for input switching noise and signal-noise ratio (SNR) when considering the noise of the comparators in the subsequent stage. Comparator A is a comparator that operates at a lower voltage than comparator B. Comparator A consumes less power than comparator B, but has higher noise.

[0183] The effect is significant when using CRCA in a noisy comparator such as comparator A. Therefore, the noise of both the CRCA of the first embodiment and the MFC-CRCA of the fourth embodiment, when combined with A, was predicted. When comparator A is combined with CRCA, the input switching noise is suppressed to about one-third of the noise of comparator A at a gain of 8x. However, the input / output range is reduced, so the SNR is not very good. When the gain is 1x, the SNR deteriorates significantly.

[0184] When comparator A is combined with an MFC-CRCA, the input / output range is not reduced. Therefore, the SNR improves by more than 3 dB at a gain of 8x, and there is no SNR degradation at a gain of 1x. Compared to comparator B, the SNR is the same at a gain of 8x, but the SNR is lower at a gain of 1x. Although there is a several-fold difference in power consumption between comparators A and B, if comparator A uses an MFC-CRCA at a gain of 8x, it can achieve comparable noise performance to comparator B with significantly less power.

[0185] <6. Application Examples of Moving Bodies>

[0186] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0187] Figure 29This is a block diagram illustrating a schematic construction example of a vehicle control system that is an example of a mobile body control system capable of applying the technology according to this disclosure.

[0188] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 29 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0189] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: drive force generating devices such as internal combustion engines or drive motors for generating drive force for the vehicle; drive force transmission mechanisms for transmitting drive force to the wheels; steering mechanisms for adjusting the vehicle's steering angle; and braking devices for generating braking force for the vehicle.

[0190] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for devices such as keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various switches transmitted from a portable device that replaces the key can be input to the body system control unit 12020. The body system control unit 12020 receives these radio wave or signal inputs and controls the vehicle's door locking devices, power windows, and lights, etc.

[0191] The exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing for pedestrians, vehicles, obstacles, signs, and letters on the road surface.

[0192] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the intensity of the received light. The camera unit 12031 can output this electrical signal as an image or as distance measurement information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0193] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera for capturing images of the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0194] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information obtained from the vehicle's internal or external environment by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an Advanced Driver Assistance System (ADAS), including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, or lane departure warning.

[0195] Furthermore, based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control, such as autonomous driving, which aims to drive autonomously without relying on the driver's operation, by controlling the drive force generator, steering mechanism, and braking device.

[0196] Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on information about the exterior of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or oncoming vehicles detected by the external information detection unit 12030, thereby performing anti-glare coordinated control such as switching the high beams to the low beams.

[0197] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying passengers of the vehicle or the outside world. Figure 29 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as such output devices. The display unit 12062 may include at least one of, for example, an onboard display and a head-up display.

[0198] Figure 30 This is a diagram showing an example of the mounting location of the camera unit 12031.

[0199] exist Figure 30 In the middle, as a camera unit 12031, camera units 12101, 12102, 12103, 12104 and 12105 are provided.

[0200] For example, camera units 12101, 12102, 12103, 12104, and 12105 can be positioned at locations such as the front nose, rearview mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle 12100. Camera unit 12101 at the front nose and camera unit 12105 at the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Camera units 12102 and 12103 at the rearview mirrors primarily acquire images of the sides of the vehicle 12100. Camera unit 12104 at the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Camera unit 12105 at the upper part of the windshield inside the vehicle is primarily used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes ahead.

[0201] Here, Figure 30 An example of the camera range of camera units 12101 to 12104 is shown. Camera range 12111 represents the camera range of camera unit 12101 located at the front nose; camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the rearview mirrors, respectively; and camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or rear door. For example, by overlaying the image data captured by camera units 12101 to 12104, a bird's-eye view of the vehicle 12100 as seen from above can be obtained.

[0202] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple camera elements, or may be a camera element having pixels for phase difference detection.

[0203] For example, the microcomputer 12051 can, based on distance information obtained from camera units 12101 to 12104, determine the vehicle ahead by acquiring the distance to each three-dimensional object within the camera range 12111 to 12114 and the change of that distance over time (relative speed to the vehicle 12100). Specifically, it can identify the three-dimensional object closest to the vehicle 12100 on its travel path and traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. Furthermore, the microcomputer 12051 can pre-set the distance to be maintained in front of the vehicle ahead and can perform automatic braking control (including follow-stop control) and automatic acceleration control (including follow-start control), etc. In this way, cooperative control for autonomous driving, etc., can be performed.

[0204] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles based on distance information obtained from camera units 12101 to 12104, extract the three-dimensional object data, and use the three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles near vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 can determine the collision risk, which represents the degree of danger of colliding with each obstacle, and when the collision risk value is equal to or greater than a set value and there is a possibility of collision, the microcomputer 12051 can output a warning to the driver through audio speaker 12061 or display unit 12062, and execute forced deceleration or evasive steering through drive system control unit 12010, thereby performing collision avoidance driving assistance.

[0205] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object, and determining whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to overlay and display a square outline for emphasis on the identified pedestrian. Furthermore, the sound / image output unit 12052 can control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0206] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. For example, the technology according to this disclosure can be applied to the camera unit 12031 in the above-described configuration. Specifically, Figure 1 The camera device 100 can be applied to the camera unit 12031. By applying the technology according to this disclosure to the camera unit 12031, the power consumption of the column amplifier can be suppressed, thereby reducing the power consumption of the entire vehicle system.

[0207] Furthermore, the above embodiments illustrate examples for implementing this technology, and the matters in the embodiments correspond to the matters of the invention defined in the claims. Similarly, the matters of the invention defined in the claims also correspond to the matters in the embodiments of this technology with the same name. However, this technology is not limited to these embodiments, and various modifications can be made to these embodiments without departing from the spirit of this technology.

[0208] The effects described in this manual are for illustrative purposes only and are not intended to be limiting; other effects may be achieved.

[0209] This technology can also have the following structure.

[0210] (1) A solid-state imaging element, comprising:

[0211] Pixel circuitry generates input voltage through photoelectric conversion;

[0212] An input transistor that outputs an output voltage from its drain corresponding to the voltage between its source and gate, the input voltage being input to the source;

[0213] A reference-side current source, connected to a reference node having a predetermined reference voltage, and providing a predetermined current; and

[0214] A feedback circuit that feeds a portion of the current back to the gate of the input transistor.

[0215] (2) The solid-state imaging element according to (1), wherein the feedback circuit comprises:

[0216] A feedback capacitor is inserted between the output node that outputs the output voltage and the gate.

[0217] A reference-side capacitor, inserted between the gate and the reference node having the reference voltage; and

[0218] An input-side automatic zero-adjustment switch opens and closes the path between the gate and the output node.

[0219] (3) The solid-state imaging element according to (2) further includes:

[0220] A cascaded transistor is inserted between the reference-side current source and the drain; and

[0221] A cascaded capacitor is inserted between the source of the input transistor and the gate of the cascaded transistor.

[0222] The output node is the node between the cascaded transistor and the reference-side current source.

[0223] (4) The solid-state imaging element according to (2) further includes:

[0224] A power supply-side current source, connected to a power node having a predetermined power supply voltage; and

[0225] A pair of cascaded transistors are inserted between the power supply-side current source and the reference-side current source.

[0226] The output node is the node between the pair of cascaded transistors.

[0227] (5) The solid-state imaging element according to (4) further includes:

[0228] An intermediate switch that opens and closes the path between the feedback capacitor and the output node; and

[0229] A reference switch that opens and closes the path between the feedback capacitor and the node having a predetermined reference voltage.

[0230] (6) The solid-state imaging element according to (4) further includes:

[0231] Cascaded capacitors are connected to the power node having the power supply voltage;

[0232] The output-side automatic zero-adjustment switch opens and closes the path between the cascaded capacitor and the output node; and

[0233] Intermediate switch

[0234] The reference-side current source includes a first reference-side current source transistor and a second reference-side current source transistor.

[0235] The first reference-side current source transistor is inserted between the input transistor and the reference node.

[0236] The second reference-side current source transistor is inserted between one of the pair of cascaded transistors and the reference node having the reference voltage, and

[0237] The intermediate switch opens and closes the path between the node between the input transistor and the first reference-side current source transistor and the node between one of the pair of cascaded transistors and the second reference-side current source transistor.

[0238] (7) The solid-state imaging element according to any one of (1) to (6), further comprising:

[0239] A boost-side current source is connected to a power node having a predetermined power supply voltage;

[0240] A boost transistor is inserted between the boost-side current source and the reference node having the reference voltage, and the boost transistor has a gate connected to an output node that outputs the output voltage; and

[0241] A boost-side capacitor is inserted between the node between the boost-side current source and the boost transistor and the source.

[0242] (8) A camera device comprising:

[0243] Pixel circuitry generates input voltage through photoelectric conversion;

[0244] An input transistor that outputs an output voltage from its drain corresponding to the voltage between its source and gate, the input voltage being input to the source;

[0245] A reference-side current source is connected to a reference node having a predetermined reference voltage and provides a predetermined current;

[0246] A feedback circuit that feeds a portion of the current back to the gate of the input transistor; and

[0247] An analog-to-digital converter that converts the output voltage into a digital signal.

[0248] List of reference numerals

[0249] 100 camera devices

[0250] 110 optical units

[0251] 120 DSP circuit

[0252] 130 display units

[0253] 140 operating units

[0254] 150 bus

[0255] 160-frame memory

[0256] 170 storage units

[0257] 180 power supply unit

[0258] 200 solid-state camera elements

[0259] 201 pixel chip

[0260] 202 Circuit Chip

[0261] 210 rows of selection cells

[0262] 220 DAC

[0263] 230 Timing Control Circuit

[0264] 240 pixel array

[0265] 250 pixel circuit

[0266] 251 Photoelectric conversion element

[0267] 252 Transmission Transistors

[0268] 253 Reset Transistor

[0269] 254 Floating Diffusion Layer

[0270] 255 Amplifying Transistor

[0271] 256 Select Transistors

[0272] 260 Analog-to-Digital Conversion Unit

[0273] 261 ADC

[0274] Capacitors 262, 263, and 503

[0275] 264 comparators

[0276] 265 counter

[0277] 266 Latch Circuit

[0278] 270 Horizontal Transmission Scanning Unit

[0279] 280 Image Processing Units

[0280] 300 constant current source unit

[0281] 310, 500 column amplifiers

[0282] 320 Current Multiplexed Column Amplifier

[0283] 321 Input Level

[0284] 322 and 505 input transistors

[0285] 323 Feedback Circuit

[0286] 324 Input-side automatic zeroing switch

[0287] 325 and 504 feedback capacitors

[0288] 326 Reference-side capacitor

[0289] 327, 347 Reference-side current source transistors

[0290] 330, 346 Intermediate Switch

[0291] 330-1 Reference Switch

[0292] Cascaded capacitors 331 and 341

[0293] Cascaded transistors 332, 343, 345, and 353

[0294] 333 Cascade Side Automatic Zeroing Switch

[0295] 340 Folding Class

[0296] 342 Power supply side current source transistor

[0297] 344 Output side automatic zeroing switch

[0298] 350 boost circuit

[0299] 351 Boost-side capacitor

[0300] 352 Boost-side current source transistor

[0301] 354 boost transistor

[0302] 400 VSL capacitor

[0303] 401 Load Capacitor

[0304] 501 Current Source

[0305] 502 Automatic Zero Adjustment Switch

[0306] 12031 Camera Unit

Claims

1. A solid-state imaging element, comprising: Pixel circuitry generates input voltage through photoelectric conversion; An input transistor that outputs a voltage from its drain that corresponds to the voltage between its source and gate; A reference-side current source is connected to a reference node having a predetermined reference voltage and provides a predetermined current; and A feedback circuit that feeds a portion of the current back to the gate of the input transistor. The input transistor has its source connected to a vertical signal line, the input voltage is input to the source of the input transistor through the vertical signal line, the drain of the input transistor is connected to the reference-side current source, and the feedback circuit is connected between the drain and gate of the input transistor. The feedback circuit includes: A feedback capacitor is inserted between the output node that outputs the output voltage and the gate of the input transistor; A reference-side capacitor, inserted between the gate of the input transistor and the reference node having the reference voltage; and An input-side automatic zeroing switch opens and closes the path between the gate of the input transistor and the output node.

2. The solid-state imaging element according to claim 1, further comprising: A cascaded transistor is inserted between the reference-side current source and the drain. and A cascaded capacitor is inserted between the source of the input transistor and the gate of the cascaded transistor. The output node is the node between the cascaded transistor and the reference-side current source.

3. The solid-state imaging element according to claim 1, further comprising: A power supply side current source, which is connected to a power node having a predetermined power supply voltage; and A pair of cascaded transistors are inserted between the power supply-side current source and the reference-side current source. The output node is the node between the pair of cascaded transistors.

4. The solid-state imaging element according to claim 3, further comprising: An intermediate switch that opens and closes the path between the feedback capacitor and the output node; and A reference switch that opens and closes the path between the feedback capacitor and the node having a predetermined reference voltage.

5. The solid-state imaging element according to claim 3, further comprising: Cascaded capacitors are connected to the power node having the power supply voltage; An automatic zero-adjustment switch on the output side opens and closes the path between the cascaded capacitor and the output node; and Intermediate switch The reference-side current source includes a first reference-side current source transistor and a second reference-side current source transistor. The first reference-side current source transistor is inserted between the input transistor and the reference node. The second reference-side current source transistor is inserted between one of the pair of cascaded transistors and the reference node having the reference voltage, and The intermediate switch opens and closes the path between the node between the input transistor and the first reference-side current source transistor and the node between one of the pair of cascaded transistors and the second reference-side current source transistor.

6. The solid-state imaging element according to any one of claims 1 and 5, further comprising: A boost-side current source is connected to a power node having a predetermined power supply voltage; A boost transistor is inserted between the boost-side current source and the reference node having the reference voltage, and the boost transistor has a gate connected to an output node that outputs the output voltage; and A boost-side capacitor is inserted between the node between the boost-side current source and the boost transistor and the source.

7. A camera device comprising: Solid-state imaging element according to any one of claims 1 to 6; and An analog-to-digital converter that converts the output voltage into a digital signal.

Images