A Multi-channel Parallel De-skewing Method for Wideband Linear Frequency Modulation Signals

Abstract

The present invention discloses a multi-channel parallel de-skewing method for broadband linear frequency modulation signals, the method comprising: using a high sampling rate ADC device to perform high-quality bandpass sampling on a wide bandwidth intermediate frequency echo signal, and performing parallel decomposition into M digital signals according to an FPGA clock rate; performing multi-channel parallel digital down-conversion and low-pass filtering on the M echo signals to obtain M zero intermediate frequency IQ signals; based on the principle of direct digital frequency synthesis, generating linear frequency modulation signals with the same bandwidth, time width and opposite slope in M ​​parallel channels as de-skewing reference signals; multiplying the M zero intermediate frequency echo signals with the M de-skewing reference signals, and then performing M times multi-phase extraction filtering and FFT processing to obtain a single frequency echo signal with target distance information after de-skewing. The present invention converts the digital de-skewing process of a high-speed, wide bandwidth echo signal into multi-channel parallel processing, which is simple to implement, has high resource utilization and small calculation delay.

Description

Technical Field

[0001] The invention belongs to the technical field of radar signal processing, and in particular relates to a multi-channel parallel de-skewing method for broadband linear frequency modulation signals. Background Art

[0002] With the continuous development of science and technology, in order to make the radar system have high distance resolution, the radar transmission signal waveform is often required to have a wide signal bandwidth. The reason is that the radar's distance resolution is inversely proportional to the radar transmission signal bandwidth. Under this premise, radar signal designers generally modulate the radar signal to increase the signal bandwidth. Common modulation methods include frequency modulation and phase modulation. In the frequency modulation method, there are mainly two signal styles: linear frequency modulation signal and nonlinear frequency modulation signal. Compared with nonlinear frequency modulation signal, linear frequency modulation signal has a wide working bandwidth and is easy to implement in hardware. Therefore, linear frequency modulation signal is one of the commonly used signal styles in high-performance radar systems at this stage. For the principle of linear frequency modulation signal, please refer to non-patent literature 1-3.

[0003] However, as the bandwidth of radar transmission signals continues to increase, higher requirements are also placed on the hardware performance of radar systems, such as higher signal sampling frequencies, higher data processing rates, and higher data transmission rates. In order to cope with the challenges of high-speed signal acquisition and data processing to the system, the echo signal bandwidth is generally reduced by de-skewing the broadband linear frequency modulation signal, that is, reducing the sampling rate of the signal while retaining complete target information. There are two common de-skewing methods, namely analog de-skewing and digital de-skewing. For details, see non-patent literature 4-10. The following briefly introduces these two de-skewing methods.

[0004] Analog deskewing is to multiply the simulated target echo signal received by the radar with the analog reference signal, and then obtain the echo signal in the form of a single-frequency sine wave after filtering, amplification, ADC sampling, and fast Fourier transform (FFT), such as Figure 1 At this time, the frequency of the single-frequency signal is associated with information such as the distance to the target, and the expression is as follows:

[0005]

[0006] Where K is the slope of the FM signal, R is the target distance, and R 0 is the target reference center distance, and c is the speed of light in vacuum. After analog de-skewing, a single-frequency signal containing target information is obtained, which reduces the bandwidth of the echo signal, thereby reducing the radar system's demand for sampling rate. However, the analog de-skewing method requires the generation of an analog de-skewing reference signal, which increases the complexity and implementation difficulty of the system. In order to more conveniently implement the de-skewing of large-bandwidth linear frequency modulation signals, the echo signal can be de-skewed in the digital domain, that is, the digital de-skewing method. The processing flow is as follows: Figure 2 As shown in the figure, the intermediate frequency echo signal is first sampled by AD and converted into a digital signal, then the baseband echo signal is obtained by digital down-conversion and low-pass filtering, and then the baseband echo signal is multiplied with the digitally generated de-skew reference signal, and finally the single-frequency signal is obtained by fast Fourier transform (FFT). Digital de-skew can also transform the echo signal into a single-frequency signal with target information. At the same time, the digital de-skew reference signal is easier to generate and the parameter adjustment is more convenient.

[0007] The digital de-skewing method requires the signal processing system to sample the analog intermediate frequency signal at a higher sampling rate, but as the sampling rate of AD chips becomes higher and higher, the sampling rate will no longer limit the application and development of the digital de-skewing method. At the same time, non-patent document 11 proposes that based on FPGA high-speed programmable logic devices, extremely complex high-speed and high-density digital circuit designs can be completed, thereby realizing complex digital signal processing functions. Although the current FPGA chip operation rate has reached hundreds of megahertz, in order to adapt to the signal sampling rate of several gigahertz of AD chips, the multi-channel parallel implementation method of signal processing algorithms is widely used in various digital signal processing fields.

[0008] Prior Literature

[0009] Non-patent literature

[0010] 1. Ding Lufei, Geng Fulu, Chen Jianchun. Radar Principles (4th Edition)[M]. Publishing House of Electronics Industry, 2009.

[0011] 2. Richards, Xing Mengdao, Wang Tong, et al. Fundamentals of radar signal processing [M]. Publishing House of Electronics Industry, 2008.

[0012] 3. Wan Yonglun. Research on broadband radar signal generation and processing technology[D], 2006. University of Electronic Science and Technology of China.

[0013] 4. Li Heping, Wang Yanfei, Zhang Chi, et al. De-skewing receiving method for radar echo signal, 2016.

[0014] 5. Luo Fei, Wang Yanfei, Niu Xiaoli, et al. Research on an efficient digital de-skewing method for SAR[J]. Electronic Measurement Technology, 2016, 39(9): 165-171.

[0015] 6. Wan Yonglun, Si Qiang, Lü Youxin. Research on de-skew pulse compression processing method for broadband signals[J]. Acta Aeronautica Sinica, 2006, 27(5): 917-921.

[0016] 7. Pollock B, Goodman N A. Structured de-chirp for compressive sampling of LFM waveforms[J]. 7th Sensor Array and Multichannel Signal Processing Workshop (SAM), 2012: 37-40.

[0017] 8. Luo Fei, Wang Yanfei, Niu Xiaoli, et al. A method for deskewing SAR echo signals[P], Institute of Electronics, Chinese Academy of Sciences, 2016-07-26.

[0018] 9. Wang Xin, Chen Haihong. Research on full digital de-skew and pulse compression method for broadband signals[J]. Modern Radar, 2011, 33(9): 34-37.

[0019] 10. Qian-Qiang L, Peng-Fei T, Bin Y, et al. A new dechirp method for wideband radar direct IF sampling signal [C], Signal Processing (ICSP), 2012 IEEE11th International Conference on. 2012: 1920-1924.

[0020] 11. Gao Yajun. Digital Signal Processing Based on FPGA. 2nd Edition[M]. Publishing House of Electronics Industry, 2015. Summary of the invention

[0021] The present invention discloses a broadband linear frequency modulation signal multi-channel parallel de-skewing method, which can complete the de-skewing processing of high sampling rate and large bandwidth linear frequency modulation signals in the digital domain within the range of FPGA operation rate requirements, and has the characteristics of simple implementation, high resource utilization and small calculation delay.

[0022] The invention provides a broadband linear frequency modulation signal multi-channel parallel de-skewing method, comprising the following steps:

[0023] Use high sampling rate ADC devices to perform high-quality bandpass sampling on the large-bandwidth intermediate frequency echo signal, and decompose it into M digital signals in parallel according to the FPGA clock rate;

[0024] Perform multi-channel parallel digital down-conversion and low-pass filtering on the M-channel echo signals to obtain M-channel zero intermediate frequency IQ signals;

[0025] Based on the principle of direct digital frequency synthesis, M channels are used to generate linear frequency modulation signals with the same bandwidth, time width and opposite slope in parallel as de-skewing reference signals.

[0026] The M-channel zero-IF echo signal is multiplied by the M-channel de-skewed reference signal, and then subjected to M-fold multiphase extraction filtering and FFT processing to obtain a de-skewed sampling rate of f s / M and a single-frequency echo signal with target distance information, completing the multi-channel parallel implementation of digital de-skewing processing of the entire large-bandwidth linear frequency modulation signal.

[0027] Furthermore, based on the bandpass sampling theorem, the ADC sampling frequency satisfies the following formula:

[0028]

[0029] Where f 0 is the signal center frequency, B is the signal bandwidth, and n is f s The largest positive integer ≥ 2B;

[0030] Using the ADC sampling frequency f that satisfies the above formula s The echo signal is sampled at the intermediate frequency to obtain the digital echo signal x[n], and x[n] is converted according to the FPGA clock operating frequency f clock Parallel decomposition into M echo signals, at this time, satisfies f s =M*f clock Then, the M-channel signals are digitally down-converted and multi-channel parallel low-pass filtered. The digital down-conversion process converts the M-channel signals to f 0 The calculation process of converting the intermediate frequency signal with the center frequency into a zero intermediate frequency baseband signal is as follows:

[0031]

[0032] In the formula, cos(2πf 0 nT s ) and sin(2πf 0 nT s ) are generated in parallel by M-channel DDS;

[0033] After digital down-conversion, M-channel I signals and M-channel Q signals with zero intermediate frequency are obtained, and the IQ signals are filtered through a multi-channel parallel low-pass filter to filter out high-frequency components and obtain zero intermediate frequency echo signals.

[0034] Further, for two parallel 4th-order FIR filters, the filtering process of the low-pass filter includes:

[0035] The filter output y[n] is expressed as:

[0036]

[0037] Where h(m) is the filter coefficient, which is divided into the even number y e [n] and odd number y o [n] The sum of two parts:

[0038]

[0039] y e (n) = h(0)x(n) + h(2)x(n-2)

[0040] y o (n) = h(1)x(n-1) + h(3)x(n-3)

[0041] Similarly, y(n+1) is divided into:

[0042]

[0043] y e (n+1)=h(0)x(n+1)+h(2)x(n-1)

[0044] y o (n+1)=h(1)x(n)+h(3)x(n-2)

[0045] y e (n+1) and y o (n) The input data is the same, and y o (n+1) and y e (n) The input data differ by two clock cycles and are therefore filtered in parallel using FIR filters.

[0046] Furthermore, the FIR filter performs parallel filtering including: at time n, the first filtering output result is the sum of the even part of the first filtering result of the data at time n and the odd part of the second filtering result of the data at time n-1 after a delay of one clock cycle; the second filtering output result is the sum of the even part of the second filtering result of the data at time n and the odd part of the first filtering result of the data at time n, and so on, expanding the parallel implementation structure of this filter to n-order M paths.

[0047] Further, using DDS to generate M-channel large bandwidth digital de-skew reference signals in parallel includes:

[0048] The linear frequency modulation signal expression is as follows:

[0049] S r [n] = A cos[2πf 0 nT s +πk(nT s ) 2 ]

[0050] Where n∈[0,N], T s =1 / f s ,

[0051] The expression at time n+1 is as follows:

[0052] S r [n+1]=A cos[2πf 0 (n+1)T s +πk(n+1) 2 T s 2 ]

[0053] When M paths are generated in parallel, n = Mi + j, where j∈[0,M], the phase part in the above two equations is transformed into:

[0054]

[0055]

[0056] Where K = kT s / 2=k / 2f s ,therefore:

[0057]

[0058] Among them, Based on the principle of direct digital frequency synthesis, M different phase step values ​​are obtained, so that a large-bandwidth linear frequency modulation de-skew reference signal is generated in M ​​parallel paths.

[0059] Furthermore, the M-channel linear frequency modulation de-skew reference signal I generated in parallel is rm -j*Q rm and the processed M-channel zero intermediate frequency echo signal Ix+j*Q m Multiply them to get the de-sloped I dm With Q dm The two-way echo signal is shown in the following formula:

[0060] (I m +jQ m )·(I rm -jQ rm )=-I m Q rm +Q m I rm +j(I m I rm +Q m Q rm ), m=0,1,…M

[0061] Among them, I rm is the I signal in the M-channel linear frequency modulation de-skew reference signal, Q rm is the Q channel signal of the M channel linear frequency modulation de-skew reference signal, I m is the I-channel signal among the M-channel zero-IF echo signals, Q m is the Q-channel signal of the M-channel zero intermediate frequency echo signal;

[0062] After the two echo signals after the above de-skewing are subjected to M-fold multiphase extraction filtering and FFT transformation, the sampling rate is obtained. s / M and a single-frequency echo signal with information such as target distance.

[0063] Furthermore, when processing the echo signal, it is first decomposed into 16 channels in parallel, and the 16 channels of linear frequency modulation echo signals are subjected to multi-channel parallel mixing and filtering, and the process is as follows:

[0064] Generate M mixing reference signals:

[0065]

[0066] Similarly:

[0067]

[0068] Therefore, the 16 echo signals are multiplied one by one with the above 16 mixing reference signals, and only one multiplication operation is required in this process;

[0069] The mixed signal is then processed by multi-channel parallel filtering. After the mixing and filtering, the 16-channel zero intermediate frequency I signal and the 16-channel zero intermediate frequency Q signal are multiplied with the 16-channel parallel generated de-skew reference signal. When performing complex multiplication, each channel only needs two multiplication operations and one addition operation to complete the de-skew processing process.

[0070] The beneficial effect of the present invention is to adapt to the clock calculation rate of hardware such as FGPA, convert the digital de-skewing processing of high-speed and large-bandwidth echo signals into multi-channel parallel processing, which is simple to implement, has high resource utilization and low calculation delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 Simulate the de-skewing process for radar echo signals;

[0072] Figure 2 Digital de-skewing process for radar echo signal;

[0073] Figure 3 A multi-channel parallel implementation process of digital de-skewing of radar echo signals of the present invention;

[0074] Figure 4The present invention uses a 2-way 4th-order FIR low-pass filter multi-way parallel decomposition structure.

[0075] Figure 5 This is an example of a signal in the multi-channel parallel digital de-skewing process of the present invention. DETAILED DESCRIPTION

[0076] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0077] The terms "first", "second", "third", "fourth", etc. (if any) or "left", "right", "front", "back", "top", "bottom" in the specification and claims of the present invention are used to distinguish similar objects or facilitate the structural description of the present invention, and are not necessarily used to describe a specific order or sequence and to limit the structural and technical features of the present invention. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein, for example, can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0078] Example

[0079] In order to enable the high-speed echo signal after ADC sampling to be processed quickly and with low latency in hardware systems such as FPGA, the present invention proposes a method for implementing zero-IF digital de-skewing of multi-channel parallel large-bandwidth linear frequency modulation signals based on FPGA. The processing flow is as follows: Figure 3 shown.

[0080] Based on the bandpass sampling theorem, the ADC sampling frequency should satisfy the following formula:

[0081]

[0082] Where f 0 is the signal center frequency, B is the signal bandwidth, and n is f s The largest positive integer ≥ 2B.

[0083] Using the ADC sampling frequency f that meets the above conditions sThe echo signal is sampled at the intermediate frequency to obtain the digital echo signal x[n], and x[n] is converted according to the FPGA clock operating frequency f clock Parallel decomposition into M echo signals, at this time, satisfies f s =M*f clock Then, the M-channel signals are subjected to digital down-conversion (DDC) and multi-channel parallel low-pass filtering. The digital low-pass filter uses the commonly used FIR filter. 0 The intermediate frequency signal with the center frequency becomes a zero intermediate frequency baseband signal. The calculation process is as follows:

[0084]

[0085] In the formula, cos(2πf 0 nT s ) and sin(2πf 0 nT s ) are generated in parallel by M-way DDS.

[0086] After DDC, we can get zero intermediate frequency M-channel I signal and M-channel Q signal. The IQ signal is filtered through a multi-channel parallel low-pass filter to filter out the high-frequency component. The parallel filtering process is as follows. Taking a 2-channel parallel 4th-order FIR filter as an example, the filter output y[n] can be expressed as:

[0087]

[0088] Where h(m) is the filter coefficient, which is divided into the even number y e [n] and odd number y o [n] The sum of two parts:

[0089]

[0090] y e (n) = h(0)x(n) + h(2)x(n-2)

[0091] y o (n) = h(1)x(n-1) + h(3)x(n-3)

[0092] Similarly, y(n+1) is divided into:

[0093]

[0094] y e (n+1)=h(0)x(n+1)+h(2)x(n-1)

[0095] y o (n+1)=h(1)x(n)+h(3)x(n-2)

[0096] From the decomposition of y(n) and y(n+1), we can see that y e (n+1) and y o (n) The input data is the same, and y o (n+1) and y e (n) The input data differs by two clock cycles, so it can be used Figure 4 The FIR filter structure of the form is used for parallel filtering. At time n, the output result of the first filtering is the sum of the even part of the first filtering result of the data at time n and the odd part of the second filtering result of the data at time n-1 after a delay of one clock cycle; the output result of the second filtering is the sum of the even part of the second filtering result of the data at time n and the odd part of the first filtering result of the data at time n. By analogy, this filter parallel implementation structure can be extended to n-order M channels. After multi-channel parallel low-pass filtering, a zero intermediate frequency echo signal is obtained. This embodiment takes a 2-channel 4-order FIR filter structure as an example, and other forms of FIR filter structures are not limited here.

[0097] The next step is to use DDS to generate M-channel large-bandwidth digital de-skew reference signals in parallel. The linear frequency modulation signal expression is as follows:

[0098] S r [n] = A cos[2πf 0 nT s +πk(nT s ) 2 ]

[0099] Where n∈[0,N], T s =1 / f s The expression at time n+1 is as follows:

[0100] S r [n+1]=A cos[2πf 0 (n+1)T s +πk(n+1) 2 T s 2 ]

[0101] When M paths are generated in parallel, n = Mi + j, where j∈[0,M], the phase part in the above two equations can be transformed into:

[0102]

[0103]

[0104] Where K = kT s / 2=k / 2f s .therefore:

[0105]

[0106] Where ΔX f0 (n) = Mf 0 T s ,ΔX k (n) = K[M(Mi+j)+M(Mi+j+1)+M 2 ]T s Based on the DDS principle, M different phase step values ​​can be obtained according to the designed accumulated value, so that the large-bandwidth linear frequency modulation de-skew reference signal can be generated in M ​​parallel paths.

[0107] The M-channel linear frequency modulation de-skew reference signal (I rm -j*Q rm ) and the processed M-channel zero intermediate frequency echo signal (I m +j*Q m ) and we can get the de-sloped I dm With Q dm The two-way echo signal is shown in the following formula:

[0108] (I m +jQ m )·(I rm -jQ rm )=-I m Q rm +Q m I rm +j(I m I rm +Q m Q rm ), m = 0, 1, ... M After the above de-skewing echo signal is subjected to M times multiphase extraction filtering and FFT transformation, we

[0109] The sampling rate can be obtained as f s / M and a single-frequency echo signal with information such as target distance.

[0110] So far, the multi-channel parallel implementation of digital de-skewing of large-bandwidth linear frequency modulation signals has been completed. The method is summarized as follows:

[0111] (1) High sampling rate ADC devices are used to perform high-quality bandpass sampling on the large-bandwidth intermediate frequency echo signal, and the FPGA clock rate is comprehensively considered to perform parallel decomposition into M digital signals.

[0112] (2) Perform multi-channel parallel digital down conversion (DDC) and low-pass filtering on the M-channel echo signals to obtain M-channel zero intermediate frequency IQ signals.

[0113] (3) Based on the DDS principle, M channels are used to generate linear frequency modulation signals with the same bandwidth, time width and opposite slope in parallel as de-skew reference signals.

[0114] (4) Multiply the M zero-IF echo signals with the M de-skewed reference signals, and then process them through M-fold multiphase decimation filtering and FFT processing to obtain a de-skewed sampling rate of f s / M and a single-frequency echo signal with information such as target distance, thereby completing the multi-channel parallel implementation of digital de-skewing processing of the entire large-bandwidth linear frequency modulation signal.

[0115] Next, in combination with actual engineering data, digital de-skewing of a large-bandwidth linear frequency modulation signal is performed according to the above method.

[0116] The system operating center frequency is set to 2.4GHz, the signal bandwidth is 1.3G, and based on the bandpass sampling theorem, the ADC sampling frequency is determined to be 3.2GHz (n=1), and the FPGA operating clock is 200MHz. It can be obtained that:

[0117] M=f s / f clock =16

[0118] At the same time, three target linear frequency modulation echo signals are generated according to the above parameters, and the target center reference distances are 2000m, 2025m, and 2045m respectively.

[0119] When processing the echo signal, it is first decomposed into 16 channels in parallel, and the 16 channels of linear frequency modulation echo signals are subjected to multi-channel parallel mixing and filtering. The process is as follows:

[0120] Generate M mixing reference signals:

[0121]

[0122] Similarly:

[0123]

[0124] Therefore, the 16 echo signals are multiplied one by one with the above 16 mixing reference signals, and only one multiplication operation is required in this process. The mixed signal is then processed by multi-channel parallel filtering. The filter passband cutoff frequency can be set to 650MHz, the stopband cutoff frequency to 800MHz, the order to 32, and it is decomposed into 16 channels in parallel, 2 orders per channel. The filter order, passband cutoff frequency and stopband cutoff frequency can be flexibly set according to the signal bandwidth and the signal quality required after filtering. After the mixing and filtering process, the 16 zero intermediate frequency I signals and the 16 zero intermediate frequency Q signals are multiplied with the 16 parallel generated de-skewing reference signals. When performing complex multiplication, each channel only needs two multiplication operations and one addition operation to complete the de-skewing process.

[0125] After de-skewing, the 16-channel I signal and the 16-channel Q signal are subjected to 16 times multi-phase extraction filtering, the filter order is 64, and they are decomposed into 16 channels in parallel, each with 4 orders. At the same time, the filter passband cutoff frequency and stopband cutoff frequency are still 650MHz and 800MHz. Thus, the IQ two-channel signal with a sampling frequency of 200M is obtained after de-skewing. The FFT operation of this signal can obtain a single-frequency signal with target distance information. The signal processing process is as follows: Figure 5 As shown, Figure 5 (a) is the structure after FFT processing of the echo signal. Figure 5 (b) is the FFT result of the echo signal after mixing and filtering. Figure 5 (c) is the FFT result after de-skewing the echo signal. Figure 5 (d) is the result of the decimation filter FFT after the echo signal is de-skewed.

[0126] So far, this embodiment has completed the de-skewing of the large bandwidth echo signal with 3 target distance information, and the theoretical calculation results are consistent with the FPGA hardware operation results. This embodiment also shows that the present invention converts the digital de-skewing of the high-speed large bandwidth echo signal into multi-channel parallel processing to adapt to the clock calculation rate of hardware such as FGPA, which has the characteristics of simple implementation, high resource utilization, and small calculation delay. At a clock frequency of 200MHz, the overall delay of the above de-skewing process does not exceed 100 clock cycles, i.e., 500ns, and the sampling rate of the signal is reduced by a multi-phase extraction filter.

[0127] The above are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Although the present invention has been disclosed as above in terms of preferred embodiments, they are not intended to limit the present invention. Any technician familiar with the art can use the above disclosed technical content to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention, which does not depart from the content of the technical solution of the present invention, should fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for parallel de-skewing of broadband linear frequency modulation signals through multiple channels, characterized in that: The method comprises the following steps: Use high sampling rate ADC devices to perform high-quality bandpass sampling on the large-bandwidth intermediate frequency echo signal, and decompose it into M digital signals in parallel according to the FPGA clock rate; Perform multi-channel parallel digital down-conversion and low-pass filtering on the M-channel echo signals to obtain M-channel zero intermediate frequency IQ signals; Based on the principle of direct digital frequency synthesis, M channels are used to generate linear frequency modulation signals with the same bandwidth, time width and opposite slope in parallel as de-skewing reference signals. The M-channel zero-IF echo signal is multiplied by the M-channel de-skewed reference signal, and then subjected to M-fold multiphase extraction filtering and FFT processing to obtain a de-skewed sampling rate of f s / M and a single frequency echo signal with target distance information, completing the multi-channel parallel implementation of digital de-skewing of the entire large bandwidth linear frequency modulation signal, where f s is the sampling rate of the signal.

2. The broadband linear frequency modulation signal multi-channel parallel de-skewing method according to claim 1, characterized in that: Based on the bandpass sampling theorem, the ADC sampling frequency satisfies the following formula: Where f0 is the signal center frequency, B is the signal bandwidth, and n is f s The largest positive integer ≥ 2B; Using the ADC sampling frequency f that satisfies the above formula s The echo signal is sampled at the intermediate frequency to obtain the digital echo signal x[n], and x[n] is converted according to the FPGA clock operating frequency f clock Parallel decomposition into M echo signals, at this time, satisfies f s =M*f clock , and then perform digital down-conversion and multi-channel parallel low-pass filtering on the M-channel signals. The digital down-conversion process converts the M-channel intermediate frequency signals with f0 as the center frequency into zero intermediate frequency baseband signals. The calculation process is as follows: In the formula, cos(2πf0nT s ) and sin(2πf0nT s ) are generated in parallel by M-channel DDS; After digital down-conversion, M-channel I signals and M-channel Q signals with zero intermediate frequency are obtained, and the IQ signals are filtered through a multi-channel parallel low-pass filter to filter out high-frequency components and obtain zero intermediate frequency echo signals.

3. The broadband linear frequency modulation signal multi-channel parallel de-skewing method according to claim 1, characterized in that: For a 2-way parallel 4th-order FIR filter, the filtering process of the low-pass filter includes: The filter output y[n] is expressed as: Where h(m) is the filter coefficient, which is divided into the even number y e [n] and odd number y o [n] The sum of two parts: y e (n)=h(0)x(n)+h(2)x(n-2) y o (n)=h(1)x(n-1)+h(3)x(n-3) Similarly, y(n+1) is divided into: y e (n+1)=h(0)x(n+1)+h(2)x(n-1) y o (n+1)=h(1)x(n)+h(3)x(n-2) y e (n+1) and y o (n) The input data is the same, and y o (n+1) and y e (n) The input data differ by two clock cycles and are therefore filtered in parallel using FIR filters.

4. The method for parallel de-skewing of broadband linear frequency modulation signals through multiple channels according to claim 3, characterized in that: The parallel filtering of the FIR filter includes: at time n, the first filtering output result is the sum of the even part of the first filtering result of the data at time n and the odd part of the second filtering result of the data at time n-1 after a delay of one clock cycle; the second filtering output result is the sum of the even part of the second filtering result of the data at time n and the odd part of the first filtering result of the data at time n, and so on, expanding the parallel implementation structure of this filter to n-order M paths.

5. The method for parallel de-skewing of broadband linear frequency modulation signals through multiple channels according to claim 4, characterized in that: The method of using DDS to generate M-channel high-bandwidth digital de-skew reference signals in parallel includes: The linear frequency modulation signal expression is as follows: S r [n]=Acos[2πf0nT s +πk(nT s ) 2 ] Where n∈[0,N],T s =1 / f s , The expression at time n+1 is as follows: S r [n+1]=Acos[2πf0(n+1)T s +πk(n+1) 2 T s 2 ] When M paths are generated in parallel, n = Mi + j, where j∈[0,M], the phase part in the above two equations is transformed into: Where K = kT s / 2=k / 2f s ,therefore: Where ΔX f0 (n) = Mf0T s ,ΔX k (n) = K[M(Mi+j)+M(Mi+j+1)+M 2 ]T s Based on the principle of direct digital frequency synthesis, M different phase step values ​​are obtained, so that the large-bandwidth linear frequency modulation de-skew reference signal is generated in M ​​parallel paths, where f0 is the signal center frequency.

6. The broadband linear frequency modulation signal multi-channel parallel de-skewing method according to claim 5, characterized in that: The M-channel linear frequency modulation de-skew reference signal I generated in parallel rm -j*Q rm and the processed M-channel zero intermediate frequency echo signal I m +j*Q m Multiply them to get the de-sloped I dm With Q dm The two-way echo signal is shown in the following formula: (I m +jQ m )·(I rm -jQ rm )=-I m ·Q rm +Q m ·I rm +j(I m ·I rm +Q m ·Q rm ),m=0,1,…M Among them, I rm is the I signal in the M-channel linear frequency modulation de-skew reference signal, Q rm is the Q channel signal of the M channel linear frequency modulation de-skew reference signal, I m is the I-channel signal among the M-channel zero-IF echo signals, Q m is the Q-channel signal of the M-channel zero intermediate frequency echo signal; After the two echo signals after the above de-skewing are subjected to M-fold multiphase extraction filtering and FFT transformation, the sampling rate is obtained. s / M and a single-frequency echo signal with target distance information.

7. The broadband linear frequency modulation signal multi-channel parallel de-skewing method according to claim 1, characterized in that: When processing the echo signal, it is first decomposed into 16 channels in parallel, and the 16 channels of linear frequency modulation echo signals are subjected to multi-channel parallel mixing and filtering. The process is as follows: Generate M mixing reference signals: Similarly: Where f0 is the signal center frequency, so the 16 echo signals are multiplied with the above 16 mixing reference signals one by one, and only one multiplication operation is required in this process; The mixed signal is then processed by multi-channel parallel filtering. After the mixing and filtering, the 16-channel zero intermediate frequency I signal and the 16-channel zero intermediate frequency Q signal are multiplied with the 16-channel parallel generated de-skew reference signal. When performing complex multiplication, each channel only needs two multiplication operations and one addition operation to complete the de-skew processing process.

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