Data storage device and non-volatile memory control method

Abstract

The present invention relates to multi-channel non-volatile memory control technology, and more specifically, to a data storage device and a non-volatile memory control method. When a controller reads a read target on a non-volatile memory, it increases a read count of a counting unit to which the read target belongs and, based on the read count, determines whether to move the data in the counting unit to handle read disturbance. The counting unit is smaller than a cross-channel management unit; the controller sets the space allowed for parallel access to the non-volatile memory through the channels based on the cross-channel management unit.

Description

Technical Field

[0001] The present invention relates to a read disturbance solution for a data storage device. Background Art

[0002] Non-volatile memory comes in various forms, such as flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM, and spin transfer torque RAM (STT-RAM). These types of non-volatile memory are used for long-term data storage and can be used as storage media to implement a data storage device.

[0003] Non-volatile memory typically has unique storage characteristics. This technical field requires the development of control technologies tailored to these characteristics. For example, data stored in non-volatile memory can become corrupted by repeated reads, a phenomenon known as read disturb. Non-volatile memory control technologies must address this read disturb issue. Summary of the Invention

[0004] The present invention proposes a multi-channel non-volatile memory control technology to cope with read disturbance in an optimized manner.

[0005] According to one embodiment of the present invention, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory via multiple channels. When the controller reads a read target from the non-volatile memory, it increments a read count of a counting unit to which the read target belongs and, based on the read count, determines whether to move the data in the counting unit to mitigate read disturb. The counting unit is smaller than a cross-channel management unit, and the controller uses the cross-channel management unit to determine the amount of space allowed for parallel access to the non-volatile memory across the channels.

[0006] In one embodiment, the controller moves the data of the counting statistical unit when the read count exceeds a first threshold. If the read count is not higher than the first threshold but higher than a second threshold lower than the first threshold, the controller may further refer to a bit error rate of the read target and move the data of the counting statistical unit when the bit error rate exceeds a stability threshold.

[0007] In one embodiment, the non-volatile memory includes a pseudo-low-order storage cell region and a high-order storage cell region. When the read target falls within the pseudo-low-order storage cell region, the controller moves the data of the counting statistical unit when the read count exceeds a third threshold. When the read target falls within the high-order storage cell region, the controller moves the data of the counting statistical unit when the read count exceeds a fourth threshold. The third threshold is higher than the fourth threshold.

[0008] When the read target falls within the pseudo low-level storage cell region, if the read count is not higher than the third threshold but higher than a fifth threshold lower than the third threshold, the controller may further refer to a bit error rate of the read target and move the data of the counting statistical unit when the bit error rate is higher than a stability threshold.

[0009] When the read target is located in the high-order storage cell region, if the read count is not higher than the fourth threshold but higher than a sixth threshold lower than the fourth threshold, the controller further refers to the bit error rate of the read target and moves the data of the counting statistical unit when the bit error rate is higher than the stability threshold. The fifth threshold may be higher than the sixth threshold.

[0010] In one embodiment, the non-volatile memory is a flash memory having NxM dies, which are accessed in parallel by the controller via N channels. Each channel is shared by M dies, where N and M are the number of dies. Each cross-channel management unit comprises a block of NxM dies, each of which is a super block. A block includes multiple pages, and each read target is a page in size.

[0011] Each counting and statistical unit can be composed of M blocks, each provided by one block from M dies in the same channel. The controller moves the data of the M blocks determined to be affected by read disturb to a spare counting and statistical unit in the same channel, so that the data of the remaining (N-1)xM blocks of the super block that did not move can continue to form a super block with the M blocks of the spare counting and statistical unit.

[0012] The size of each counting unit is a block. The controller moves the data of a block determined to be read disturbed to a spare block in the same die, so that the data of the other (NxM-1) blocks of the super block that are not moved and the spare block continue to form a super block.

[0013] Each counting and statistical unit can be composed of a block provided by each of the KxM dies accessed by K channels, resulting in a size of KxM blocks. N is an integer multiple of K. The controller moves the data of the KxM blocks determined to have been read disturbed to a spare counting and statistical unit with the same K channels, allowing the data of the remaining (NK)xM blocks of the super block that were not moved to continue to form a super block with the KxM blocks of the spare counting and statistical unit.

[0014] The controller for controlling the non-volatile memory can also be implemented by other architectures. The present invention can also implement a control method for the non-volatile memory based on the above concept.

[0015] The following describes the present invention in detail with reference to the following embodiments and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Illustrate the structure of block Blk in flash memory;

[0017] Figure 2 A multi-channel access architecture according to an embodiment of the present invention is illustrated;

[0018] Figure 3 is a flow chart illustrating a process for resolving read disturbance according to an embodiment of the present invention; and

[0019] Figure 4 A space planning of a flash memory 400 is illustrated according to one embodiment of the present invention.

[0020] Explanation of symbols

[0021] Blk~block;

[0022] 202~Host;

[0023] 204~data storage device;

[0024] 206~controller;

[0025] 208~Super Page;

[0026] 210~Super Block;

[0027] 212 ~ Super Block - Flash Memory Mapping Table;

[0028] Blocks 214, 216, 218, 220, 222, 224, 226, 228, 234, and 236~;

[0029] 230~Read the counter table;

[0030] Page 232~

[0031] 400~Flash memory;

[0032] CH0, CH1, CH2, CH3~ channels;

[0033] CE0, CE1~chip enable signal;

[0034] Step S302: adjusting the read count RdCnt of the count statistical unit to which the read target belongs along with the read operation;

[0035] S304~Step, determine whether RdCnt is greater than TH1;

[0036] In step S306, the data of the counting unit is completely moved to the idle space of the same channel, and the mapping table 212 is updated accordingly;

[0037] S308~Step, determine whether RdCnt is greater than TH2;

[0038] In step S310, it is determined whether Err_Bit is greater than TH_EB. DETAILED DESCRIPTION

[0039] The following description lists various embodiments of the present invention. The following description introduces the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined according to the scope of the patent application.

[0040] Non-volatile memory can be flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM (RRAM), spin transfer torque RAM (STT-RAM), and other storage media that provide long-term data retention. The following discussion uses flash memory as an example, but the technology described can also be applied to other types of non-volatile memory.

[0041] Flash memory is commonly used as the storage medium for data storage devices today, including memory cards, USB flash devices, solid-state drives (SSDs), and more. One application involves packaging the flash memory and its controller together in a multi-chip package, known as an embedded flash memory module (eMMC).

[0042] Data storage devices using flash memory as storage media are used in a variety of electronic devices, including smartphones, wearable devices, tablet computers, and virtual reality devices. The computing module of the electronic device can be considered the host, operating the data storage device to access the flash memory therein.

[0043] Data storage devices using flash memory as storage media can also be used to build data centers. For example, servers can operate solid-state drive (SSD) arrays to form a data center. The server can be regarded as a host, operating the connected SSDs to access the flash memory stored therein.

[0044] Flash memory has its own special storage characteristics, which are described below.

[0045] The host uses logical addresses (e.g., logical block addresses (LBA) or global host pages (GHP)) to distinguish data. Where the data is actually stored in the flash memory is managed in a mapping manner.

[0046] The physical space of the flash memory is divided into multiple blocks for configuration and use. Figure 1 Illustrate the structure of block Blk in flash memory.

[0047] Block Blk includes multiple pages, for example, page 0 to page 255. Each page includes multiple sectors, for example, 32 sectors. Each sector can store 512 bytes of user data; a page provides 16KB of storage space.

[0048] However, to improve data throughput, the present invention utilizes a multi-channel access technology, using multiple channels to access multiple spaces. A flash memory can be composed of multiple dies. These dies can be divided into multiple groups, with each group of dies sharing a single channel for access. One implementation method is to have dies in the same group interleave to use the shared channel.

[0049] Figure 2The diagram illustrates a multi-channel access architecture implemented according to one embodiment of the present invention. A host 202 is coupled to a data storage device 204, which uses a controller 206 therein to access the flash memory in parallel using multiple channels CH0...CH3. As shown in the figure, each channel is shared by two dies (referred to as die 0 and die 1). The chip enable signal CE0 enables die 0 on all channels CH0...CH3. The chip enable signal CE1 enables die 1 on all channels CH0...CH3. The chip enable signal CE0 and the chip enable signal CE1 are enabled in an interleaving manner. The space accessed through channels CH0...CH3 is considered to be accessed in parallel by enabling the chip enable signals CE0 and CE1 in an interleaving manner. For example, all dies can have one page accessed in parallel at a time, which is called a super page. The frame line 208 indicates a super page. The frame line 210 indicates a super block. Multi-channel technology allows for sequential use of a superblock's storage space based on superpage numbers—from lowest to highest. A superblock is a cross-channel management unit. Based on this cross-channel management unit, controller 206 sets the space allowed for parallel access to die 0 through die 3 via channels CH0 through CH3.

[0050] In one embodiment, controller 206 dynamically manages a mapping table 212 between super blocks and flash memory. Initially, super blocks are assigned based on the block numbers of each die. For example, on each die, blocks numbered 0 form super blocks numbered 0, blocks numbered 1 form super blocks numbered 1, and so on. The initial mapping table 212 records this sequential mapping relationship.

[0051] The data stored in the flash memory will become unstable due to repeated reading, and this phenomenon is called read interference. In order to deal with read interference, the present invention proposes a read counting scheme to monitor which areas are frequently read (for example, the read count is greater than a critical value) and copy the data in the area to an idle area in time before it is damaged. In particular, the read counting proposed by the present invention is not based on the super block as the counting statistical unit, but on the space smaller than the super block as the counting statistical unit. In this way, data migration does not need to be performed on the entire super block. Simply moving the content of the counting statistical unit can reduce unnecessary data movement in other spaces in the same super block. In particular, data movement will cause the original space to be erased to release it. The life of the flash memory is related to the number of times the storage space is erased. Too high an erase count can cause physical damage. The special counting statistical unit design of the present invention can effectively reduce unnecessary data movement and extend the life of the flash memory.

[0052] In one embodiment, the counting unit is distinguished by channel—the space within the same channel within a superblock. The following uses superblock 210 as an example. On channel 0, two blocks 214 and 216 provided by die 0 and die 1 are assigned a read count of number 0. A read on any page of blocks 214 and 216 will increment this read count by 1. On channel 1, two blocks 218 and 220 provided by die 0 and die 1 are assigned a read count of number 1. A read on any page of blocks 218 and 220 will increment this read count by 1. On channel 2, two blocks 222 and 224 provided by die 0 and die 1 are assigned a read count of number 2. A read on any page of blocks 222 and 224 will increment this read count by 1. A read count of 3 is assigned to the two blocks 226 and 228 provided by die 0 and die 1 on channel 3. A read on any page of blocks 226 and 228 increments the read count by 1. Read counts are assigned to other superblocks in a similar manner. Controller 206 dynamically updates the read counts of all statistical units in a read count table 230 to monitor which spaces are frequently read. Statistical units can also be of other sizes, as discussed later.

[0053] Regarding the interpretation of the read count, one implementation method is to set two thresholds, which are described below.

[0054] Figure 3 FIG. 1 is a flow chart illustrating a read disturbance resolution process according to an embodiment of the present invention, wherein thresholds TH1 and TH2 are used. The threshold TH1 is higher than the threshold TH2.

[0055] In step S302 , following the read operation, the controller 206 adjusts the read count RdCnt of the count statistics unit to which the read target belongs.

[0056] In step S304, controller 206 determines whether the adjusted read count RdCnt is greater than threshold TH1. If so, the process proceeds to step S306, where controller 206 completely moves the data in the corresponding counting unit to an unused space on the same channel. In step S306, controller 206 updates mapping table 212 as the data is moved, ensuring that the corresponding super block correctly corresponds to the physical space in the flash memory.

[0057] If step S304 determines that the read count RdCnt is not greater than the threshold TH1, the process proceeds to step S308, where the controller 206 compares the read count RdCnt with the lower threshold TH2. If the read count RdCnt does not exceed the threshold TH2, the process returns to step S302.

[0058] If step S308 determines that the read count RdCnt is greater than the threshold TH2, the process proceeds to step S310, where the controller 206 determines whether the error bit rate of the read target is greater than a threshold TH_EB. If so, the process proceeds to step S306, completing the data transfer and updating the mapping table 212. If not, the process returns to step S302.

[0059] The following references Figure 2 , for example Figure 3 When controller 206 reads page 232 of block 214 via channel 0, it increments read count RdCnt#0 for monitoring blocks 214 and 216 by 1 (step S302). If read count RdCnt#0 is greater than threshold TH1 after comparison in step S304, controller 206 completely moves the contents of blocks 214 and 216 to blocks 234 and 236, and adjusts mapping table 212 so that the super blocks originally corresponding to blocks 214, 216, 218, 220, 222, 224, 226, and 228 are now mapped to blocks 234, 236, 218, 220, 222, 224, 226, and 228 (step S306). If read count RdCnt#0 is not greater than threshold TH1, comparison in step S308 is performed. If the read count RdCnt#0 for page 0 is not greater than the threshold TH1 but exceeds the threshold TH2, the controller 206 further checks the bit error rate Err_Bit calculated when reading page 232 (step S310). One implementation utilizes the bit error rate generated by error correction (ECC) technology. If the bit error rate of page 232 is greater than the threshold TH_EB, the controller 206 also moves the contents of blocks 214 and 216 to the safe area and updates the contents of the mapping table 212 (step S306).

[0060] In summary, by establishing two thresholds, TH1 and TH2, for the read count RdCnt, the present invention enables early detection of data instability. Even if the read count RdCnt of the statistical unit containing the read target has not yet exceeded the threshold TH1, as soon as it exceeds the threshold TH2, the controller 206 triggers a check of the bit error rate of the read target, identifies unstable data, and performs data migration for the entire statistical unit.

[0061] The design of the threshold values TH1 and TH2 may also have other variations.

[0062] Flash memory can be divided into multiple types according to its cell storage capacity. In SLC (Single Level Cell) flash memory, each storage cell corresponds to one bit of data. In MLC (Multiple Level Cell) flash memory, each storage cell corresponds to two bits of data. In TLC (Triple Level Cell) flash memory, each storage cell corresponds to three bits of data. In QLC (Quad Level Cell) flash memory, each storage cell corresponds to four bits of data. The logical boundaries of single-level storage cells (SLC) are clearer than those of multi-level storage cells (MLC / TLC / QLC); not only is it more reliable, but it also has faster write speeds. Multi-level storage cells (MLC / TLC / QLC) have their advantages in storage capacity.

[0063] However, due to cost considerations, the mainstream flash memory currently used on the market is multi-level cell (MLC / TLC / QLC). Single-level cell (SLC) flash memory is quite expensive. To meet the demand for high accuracy and high speed, multi-level cell (MLC / TLC / QLC) flash memory offers a pseudo-single-level cell (pseudo-SLC, or p-SLC) operating mode, which also provides high accuracy and high speed without the cost of true single-level cell flash memory.

[0064] Figure 4 According to one embodiment of the present invention, the space planning of a flash memory 400 is illustrated. The flash memory 400 adopts a three-level cell (TLC) process. A portion of each die is fixedly used as a pseudo single-level cell (p-SLC), while the rest remains as a three-level cell (TLC). The aforementioned threshold values TH1 and TH2 are adjusted according to different storage characteristics. For example, the aforementioned threshold values TH1 and TH2 are set as TH1_pSLC and TH2_pSLC in the pseudo single-level cell (p-SLC) region, and as TH1_TLC and TH2_TLC in the three-level cell (TLC) region. Because the pseudo single-level cell (p-SLC) is more stable than the three-level cell (TLC), the threshold value TH1_pSLC is higher than the threshold value TH1_TLC, and the threshold value TH2_pSLC is higher than the threshold value TH2_TLC. In one embodiment, the threshold value TH1_pSLC is 2 million times, which is higher than the threshold value TH1_TLC set to 1.5 million times; the threshold value TH2_pSLC is 1.5 million times, which is higher than the threshold value TH2_TLC set to 1 million times.

[0065] Other sizes of count statistical units are discussed below.

[0066] In one embodiment, the unit of count statistics is a single block of a single die in a single channel. For example, for super block 210, each of the eight blocks 214, 216, 218, 220, 222, 224, 226, and 228 corresponds to a read count. The amount of data movement caused by unstable data, as determined by the read count, is referred to as a "block." Blocks without unstable pages do not require movement.

[0067] In one embodiment, the unit of count statistics is multiple blocks provided by the die controlled by a portion of the channels. For example, for super block 210, the four blocks 214, 216, 218, and 220 of channels 0 and 1 correspond to read count number 0, while the four blocks 222, 224, 226, and 228 of channels 2 and 3 correspond to read count number 1. The amount of data to be moved due to unstable data, as determined by the read counts, is "four blocks," and it is not necessary to move all the contents of the super block.

[0068] Other implementations that do not use "super blocks" as the counting unit also fall within the technical scope of the present invention. The number of channels is not limited to 4. Each channel is not limited to being shared by two dies.

[0069] In one embodiment, a flash memory comprises NxM dies, accessed in parallel by a controller via N channels. Each channel is shared by M dies. N and M are the number of dies. Each cross-channel management unit provides a block for each of the NxM dies, each of which is a superblock in size. A block includes multiple pages, and each read target is a page in size.

[0070] In one embodiment, each counting and statistical unit can be composed of M blocks, each provided by one block from M dies in the same channel. The controller moves the data of the M blocks determined to be affected by read disturb to a spare counting and statistical unit in the same channel, allowing the data of the remaining (N-1)xM blocks of the super block, which remain unchanged, to continue forming a super block with the M blocks of the spare counting and statistical unit.

[0071] In one embodiment, the size of each counting unit can be a block. The controller moves the data of a block determined to be read disturbed to a spare block on the same die, so that the data of the remaining (NxM-1) blocks of the super block that were not moved can continue to form a super block together with the spare block.

[0072] In one embodiment, each counting and statistical unit may be composed of a block provided by each of the KxM dies accessed by K channels, resulting in a size of KxM blocks. N is an integer multiple of K. The controller moves the data of the KxM blocks determined to be read disturbed to a spare counting and statistical unit with the same K channels, allowing the data of the remaining (NK)xM blocks of the super block that remain unchanged to form a super block together with the KxM blocks of the spare counting and statistical unit.

[0073] The aforementioned technology can be applied to other types of non-volatile memories (eg, magnetoresistive random access memory, ferroelectric random access memory, resistive random access memory, spin transfer torque random access memory, etc.).

[0074] A data storage device implemented according to the present invention includes a non-volatile memory and a controller coupled to the non-volatile memory via multiple channels. When the controller reads a read target from the non-volatile memory, it increments a read count of a counting unit to which the read target belongs and, based on the read count, determines whether to move the data in the counting unit to mitigate read disturb. The counting unit is smaller than a cross-channel management unit, and the controller uses the cross-channel management unit to determine the amount of space allowed for parallel access to the non-volatile memory across the channels.

[0075] The above controller's operation design for non-volatile memory can also be implemented using other structures. Any design based on the aforementioned concepts for reading operation counting and statistical units falls within the scope of protection of the present invention. The present invention can also implement a control method for non-volatile memory using the aforementioned concepts.

[0076] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone familiar with the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A data storage device, comprising: a non-volatile memory; as well as a controller coupled to the non-volatile memory via a plurality of channels; in: When the controller reads a read target on the non-volatile memory, it increases a read count of a counting unit to which the read target belongs, and determines whether to move data of the counting unit according to the read count to handle read disturbance; The counting unit is smaller than a cross-channel management unit, and the controller sets a space allowed to be accessed in parallel to the non-volatile memory through the channels according to the cross-channel management unit; The non-volatile memory includes a pseudo low-level storage unit area and a high-level storage unit area; When the read target falls in the pseudo low-level storage cell area, the controller moves the data of the counting unit when the read count is higher than a third threshold; When the read target falls on the high-level storage unit area, the controller moves the data of the counting unit when the read count is higher than a fourth threshold; and The third threshold value is higher than the fourth threshold value.

2. The data storage device according to claim 1, wherein: When the read target falls within the pseudo low-level storage cell region, if the read count is not higher than the third threshold but higher than a fifth threshold lower than the third threshold, the controller further refers to a bit error rate of the read target and moves the data of the counting statistical unit when the bit error rate is higher than a stability threshold.

3. The data storage device according to claim 2, wherein: When the read target falls within the high-order storage cell region, if the read count is not higher than the fourth threshold but higher than a sixth threshold lower than the fourth threshold, the controller further refers to the bit error rate of the read target and moves the data of the counting statistical unit when the bit error rate is higher than the stability threshold.

4. The data storage device according to claim 3, wherein: The fifth threshold value is higher than the sixth threshold value.

5. The data storage device according to claim 1, wherein: The non-volatile memory is a flash memory having NxM dies, and is accessed in parallel by the controller via N channels, each channel being shared by M dies, where N is an integer greater than 1, and M is an integer greater than or equal to 1; The cross-channel management unit provides a block for each of the NxM dies, with a size of a super block having NxM blocks; and Each block includes a plurality of pages, and the read target size is one page.

6. The data storage device according to claim 5, wherein: The counting unit is composed of M dies in the same channel, each providing a block, and the size is M blocks; and The controller moves the data of the M blocks determined to be read disturbed to a spare counting and statistical unit in the same channel, so that the data of the other (N-1)xM blocks of the super block that are not moved continue to form a super block with the M blocks of the spare counting and statistical unit.

7. The data storage device according to claim 5, wherein: The counting statistics unit size is a block; and The controller moves the data of a block determined to be read disturbed to a spare block in the same die, so that the data of the other (NxM-1) blocks of the super block that are not moved continue to form a super block with the spare block.

8. The data storage device according to claim 5, wherein: The counting unit is composed of KxM dies accessed by K channels, each providing a block, with a size of KxM blocks, where N is an integer multiple of K; and The controller moves the data of the KxM blocks determined to be read disturbed to a spare counting and statistical unit with the same K channels, so that the data of the other (NK)xM blocks of the super block that are not moved continue to form a super block with the KxM blocks of the spare counting and statistical unit.

9. A non-volatile memory control method, comprising: Providing a plurality of channels coupled to the non-volatile memory; When reading a read target on the non-volatile memory, increasing a read count of a counting statistical unit to which the read target belongs; Determining whether to move data of the counting unit according to the read count to handle read disturbance; When the read target falls on a pseudo low-level storage unit area of the non-volatile memory, the read count is compared with a third threshold value, and when the read count is higher than the third threshold value, the data of the counting unit is moved; and When the read target falls on a high-order storage unit area of the non-volatile memory, comparing the read count with a fourth threshold value, and moving data of the counting statistical unit when the read count is higher than the fourth threshold value, wherein the third threshold value is higher than the fourth threshold value; The counting unit is smaller than a cross-channel management unit, and the cross-channel management unit is used to set a space allowed to perform parallel access to the non-volatile memory through the channels.

10. The non-volatile memory control method according to claim 9, wherein: Also includes: When the read target falls within the pseudo low-level storage cell region, if the read count is not higher than the third threshold but higher than a fifth threshold that is lower than the third threshold, referencing a bit error rate of the read target, and when the bit error rate is higher than a stability threshold, move the data of the counting statistical unit.

11. The non-volatile memory control method according to claim 10, wherein: Also includes: When the read target falls within the high-order storage cell region, if the read count is not higher than the fourth threshold but higher than a sixth threshold lower than the fourth threshold, the bit error rate of the read target is referenced, and when the bit error rate is higher than the stability threshold, the data of the counting statistical unit is moved.

12. The non-volatile memory control method according to claim 11, wherein: The fifth threshold value is higher than the sixth threshold value.

13. The non-volatile memory control method according to claim 9, wherein: The non-volatile memory is a flash memory having NxM dies, accessed in parallel via N channels, each channel being shared by M dies, where N is an integer greater than 1, and M is an integer greater than or equal to 1; The cross-channel management unit provides a block for each of the NxM dies, with a size of a super block having NxM blocks; and Each block includes a plurality of pages, and the read target size is one page.

14. The non-volatile memory control method according to claim 13, wherein: The counting unit is composed of M dies in the same channel, each providing a block, and the size is M blocks; and The data of the M blocks determined to be read disturbed are moved to a spare counting unit in the same channel, so that the data of the other (N-1)xM blocks of the super block that are not moved continue to form a super block with the M blocks of the spare counting unit.

15. The non-volatile memory control method according to claim 13, wherein: The counting statistics unit size is a block; and The data of a block determined to be read disturbed is moved to a spare block in the same die, so that the data of the other (NxM-1) blocks of the super block that are not moved continue to form a super block with the spare block.

16. The non-volatile memory control method according to claim 13, wherein: The counting unit is composed of KxM dies accessed by K channels, each providing a block, with a size of KxM blocks, where N is an integer multiple of K; and The data of the KxM blocks determined to be read disturbed are moved to a spare counting unit of the same K channels, so that the data of the other (NK)xM blocks of the corresponding super block that are not moved continue to form a super block with the KxM blocks of the spare counting unit.

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